1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2021-2022 Intel Corporation. All rights reserved. 4 * 5 * Authors: Cezary Rojewski <cezary.rojewski@intel.com> 6 * Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> 7 */ 8 9 #ifndef __SOUND_SOC_INTEL_AVS_REGS_H 10 #define __SOUND_SOC_INTEL_AVS_REGS_H 11 12 #define AZX_PCIREG_PGCTL 0x44 13 #define AZX_PCIREG_CGCTL 0x48 14 #define AZX_PGCTL_LSRMD_MASK BIT(4) 15 #define AZX_CGCTL_MISCBDCGE_MASK BIT(6) 16 #define AZX_VS_EM2_L1SEN BIT(13) 17 18 /* Intel HD Audio General DSP Registers */ 19 #define AVS_ADSP_GEN_BASE 0x0 20 #define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04) 21 #define AVS_ADSP_REG_ADSPIC (AVS_ADSP_GEN_BASE + 0x08) 22 #define AVS_ADSP_REG_ADSPIS (AVS_ADSP_GEN_BASE + 0x0C) 23 24 #define AVS_ADSP_ADSPIC_IPC BIT(0) 25 #define AVS_ADSP_ADSPIC_CLDMA BIT(1) 26 #define AVS_ADSP_ADSPIS_IPC BIT(0) 27 #define AVS_ADSP_ADSPIS_CLDMA BIT(1) 28 29 #define AVS_ADSPCS_CRST_MASK(cm) (cm) 30 #define AVS_ADSPCS_CSTALL_MASK(cm) ((cm) << 8) 31 #define AVS_ADSPCS_SPA_MASK(cm) ((cm) << 16) 32 #define AVS_ADSPCS_CPA_MASK(cm) ((cm) << 24) 33 #define AVS_MAIN_CORE_MASK BIT(0) 34 35 #define AVS_ADSP_HIPCCTL_BUSY BIT(0) 36 #define AVS_ADSP_HIPCCTL_DONE BIT(1) 37 38 /* SKL Intel HD Audio Inter-Processor Communication Registers */ 39 #define SKL_ADSP_IPC_BASE 0x40 40 #define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00) 41 #define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04) 42 #define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08) 43 #define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C) 44 #define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10) 45 46 #define SKL_ADSP_HIPCI_BUSY BIT(31) 47 #define SKL_ADSP_HIPCIE_DONE BIT(30) 48 #define SKL_ADSP_HIPCT_BUSY BIT(31) 49 50 /* Constants used when accessing SRAM, space shared with firmware */ 51 #define AVS_FW_REG_BASE(adev) ((adev)->spec->sram_base_offset) 52 #define AVS_FW_REG_STATUS(adev) (AVS_FW_REG_BASE(adev) + 0x0) 53 #define AVS_FW_REG_ERROR_CODE(adev) (AVS_FW_REG_BASE(adev) + 0x4) 54 55 #define AVS_FW_REGS_SIZE PAGE_SIZE 56 #define AVS_FW_REGS_WINDOW 0 57 /* DSP -> HOST communication window */ 58 #define AVS_UPLINK_WINDOW AVS_FW_REGS_WINDOW 59 /* HOST -> DSP communication window */ 60 #define AVS_DOWNLINK_WINDOW 1 61 62 /* registry I/O helpers */ 63 #define avs_sram_offset(adev, window_idx) \ 64 ((adev)->spec->sram_base_offset + \ 65 (adev)->spec->sram_window_size * (window_idx)) 66 67 #define avs_sram_addr(adev, window_idx) \ 68 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx)) 69 70 #define avs_uplink_addr(adev) \ 71 (avs_sram_addr(adev, AVS_UPLINK_WINDOW) + AVS_FW_REGS_SIZE) 72 #define avs_downlink_addr(adev) \ 73 avs_sram_addr(adev, AVS_DOWNLINK_WINDOW) 74 75 #endif /* __SOUND_SOC_INTEL_AVS_REGS_H */ 76