1 /* 2 * wm8350.c -- WM8350 ALSA SoC audio driver 3 * 4 * Copyright (C) 2007-12 Wolfson Microelectronics PLC. 5 * 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/platform_device.h> 20 #include <linux/mfd/wm8350/audio.h> 21 #include <linux/mfd/wm8350/core.h> 22 #include <linux/regulator/consumer.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/initval.h> 28 #include <sound/tlv.h> 29 #include <trace/events/asoc.h> 30 31 #include "wm8350.h" 32 33 #define WM8350_OUTn_0dB 0x39 34 35 #define WM8350_RAMP_NONE 0 36 #define WM8350_RAMP_UP 1 37 #define WM8350_RAMP_DOWN 2 38 39 /* We only include the analogue supplies here; the digital supplies 40 * need to be available well before this driver can be probed. 41 */ 42 static const char *supply_names[] = { 43 "AVDD", 44 "HPVDD", 45 }; 46 47 struct wm8350_output { 48 u16 active; 49 u16 left_vol; 50 u16 right_vol; 51 u16 ramp; 52 u16 mute; 53 }; 54 55 struct wm8350_jack_data { 56 struct snd_soc_jack *jack; 57 struct delayed_work work; 58 int report; 59 int short_report; 60 }; 61 62 struct wm8350_data { 63 struct wm8350 *wm8350; 64 struct wm8350_output out1; 65 struct wm8350_output out2; 66 struct wm8350_jack_data hpl; 67 struct wm8350_jack_data hpr; 68 struct wm8350_jack_data mic; 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 70 int fll_freq_out; 71 int fll_freq_in; 72 }; 73 74 /* 75 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. 76 */ 77 static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) 78 { 79 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 80 struct wm8350_output *out1 = &wm8350_data->out1; 81 struct wm8350 *wm8350 = wm8350_data->wm8350; 82 int left_complete = 0, right_complete = 0; 83 u16 reg, val; 84 85 /* left channel */ 86 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); 87 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 88 89 if (out1->ramp == WM8350_RAMP_UP) { 90 /* ramp step up */ 91 if (val < out1->left_vol) { 92 val++; 93 reg &= ~WM8350_OUT1L_VOL_MASK; 94 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 95 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 96 } else 97 left_complete = 1; 98 } else if (out1->ramp == WM8350_RAMP_DOWN) { 99 /* ramp step down */ 100 if (val > 0) { 101 val--; 102 reg &= ~WM8350_OUT1L_VOL_MASK; 103 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 104 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 105 } else 106 left_complete = 1; 107 } else 108 return 1; 109 110 /* right channel */ 111 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); 112 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 113 if (out1->ramp == WM8350_RAMP_UP) { 114 /* ramp step up */ 115 if (val < out1->right_vol) { 116 val++; 117 reg &= ~WM8350_OUT1R_VOL_MASK; 118 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 119 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 120 } else 121 right_complete = 1; 122 } else if (out1->ramp == WM8350_RAMP_DOWN) { 123 /* ramp step down */ 124 if (val > 0) { 125 val--; 126 reg &= ~WM8350_OUT1R_VOL_MASK; 127 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 128 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 129 } else 130 right_complete = 1; 131 } 132 133 /* only hit the update bit if either volume has changed this step */ 134 if (!left_complete || !right_complete) 135 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); 136 137 return left_complete & right_complete; 138 } 139 140 /* 141 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. 142 */ 143 static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) 144 { 145 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 146 struct wm8350_output *out2 = &wm8350_data->out2; 147 struct wm8350 *wm8350 = wm8350_data->wm8350; 148 int left_complete = 0, right_complete = 0; 149 u16 reg, val; 150 151 /* left channel */ 152 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); 153 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 154 if (out2->ramp == WM8350_RAMP_UP) { 155 /* ramp step up */ 156 if (val < out2->left_vol) { 157 val++; 158 reg &= ~WM8350_OUT2L_VOL_MASK; 159 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 160 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 161 } else 162 left_complete = 1; 163 } else if (out2->ramp == WM8350_RAMP_DOWN) { 164 /* ramp step down */ 165 if (val > 0) { 166 val--; 167 reg &= ~WM8350_OUT2L_VOL_MASK; 168 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 169 reg | (val << WM8350_OUT1L_VOL_SHIFT)); 170 } else 171 left_complete = 1; 172 } else 173 return 1; 174 175 /* right channel */ 176 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); 177 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 178 if (out2->ramp == WM8350_RAMP_UP) { 179 /* ramp step up */ 180 if (val < out2->right_vol) { 181 val++; 182 reg &= ~WM8350_OUT2R_VOL_MASK; 183 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 184 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 185 } else 186 right_complete = 1; 187 } else if (out2->ramp == WM8350_RAMP_DOWN) { 188 /* ramp step down */ 189 if (val > 0) { 190 val--; 191 reg &= ~WM8350_OUT2R_VOL_MASK; 192 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 193 reg | (val << WM8350_OUT1R_VOL_SHIFT)); 194 } else 195 right_complete = 1; 196 } 197 198 /* only hit the update bit if either volume has changed this step */ 199 if (!left_complete || !right_complete) 200 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); 201 202 return left_complete & right_complete; 203 } 204 205 /* 206 * This work ramps both output PGAs at stream start/stop time to 207 * minimise pop associated with DAPM power switching. 208 * It's best to enable Zero Cross when ramping occurs to minimise any 209 * zipper noises. 210 */ 211 static void wm8350_pga_work(struct work_struct *work) 212 { 213 struct snd_soc_dapm_context *dapm = 214 container_of(work, struct snd_soc_dapm_context, delayed_work.work); 215 struct snd_soc_codec *codec = dapm->codec; 216 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 217 struct wm8350_output *out1 = &wm8350_data->out1, 218 *out2 = &wm8350_data->out2; 219 int i, out1_complete, out2_complete; 220 221 /* do we need to ramp at all ? */ 222 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) 223 return; 224 225 /* PGA volumes have 6 bits of resolution to ramp */ 226 for (i = 0; i <= 63; i++) { 227 out1_complete = 1, out2_complete = 1; 228 if (out1->ramp != WM8350_RAMP_NONE) 229 out1_complete = wm8350_out1_ramp_step(codec); 230 if (out2->ramp != WM8350_RAMP_NONE) 231 out2_complete = wm8350_out2_ramp_step(codec); 232 233 /* ramp finished ? */ 234 if (out1_complete && out2_complete) 235 break; 236 237 /* we need to delay longer on the up ramp */ 238 if (out1->ramp == WM8350_RAMP_UP || 239 out2->ramp == WM8350_RAMP_UP) { 240 /* delay is longer over 0dB as increases are larger */ 241 if (i >= WM8350_OUTn_0dB) 242 schedule_timeout_interruptible(msecs_to_jiffies 243 (2)); 244 else 245 schedule_timeout_interruptible(msecs_to_jiffies 246 (1)); 247 } else 248 udelay(50); /* doesn't matter if we delay longer */ 249 } 250 251 out1->ramp = WM8350_RAMP_NONE; 252 out2->ramp = WM8350_RAMP_NONE; 253 } 254 255 /* 256 * WM8350 Controls 257 */ 258 259 static int pga_event(struct snd_soc_dapm_widget *w, 260 struct snd_kcontrol *kcontrol, int event) 261 { 262 struct snd_soc_codec *codec = w->codec; 263 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 264 struct wm8350_output *out; 265 266 switch (w->shift) { 267 case 0: 268 case 1: 269 out = &wm8350_data->out1; 270 break; 271 case 2: 272 case 3: 273 out = &wm8350_data->out2; 274 break; 275 276 default: 277 BUG(); 278 return -1; 279 } 280 281 switch (event) { 282 case SND_SOC_DAPM_POST_PMU: 283 out->ramp = WM8350_RAMP_UP; 284 out->active = 1; 285 286 if (!delayed_work_pending(&codec->dapm.delayed_work)) 287 schedule_delayed_work(&codec->dapm.delayed_work, 288 msecs_to_jiffies(1)); 289 break; 290 291 case SND_SOC_DAPM_PRE_PMD: 292 out->ramp = WM8350_RAMP_DOWN; 293 out->active = 0; 294 295 if (!delayed_work_pending(&codec->dapm.delayed_work)) 296 schedule_delayed_work(&codec->dapm.delayed_work, 297 msecs_to_jiffies(1)); 298 break; 299 } 300 301 return 0; 302 } 303 304 static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, 305 struct snd_ctl_elem_value *ucontrol) 306 { 307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 308 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 309 struct wm8350_output *out = NULL; 310 struct soc_mixer_control *mc = 311 (struct soc_mixer_control *)kcontrol->private_value; 312 int ret; 313 unsigned int reg = mc->reg; 314 u16 val; 315 316 /* For OUT1 and OUT2 we shadow the values and only actually write 317 * them out when active in order to ensure the amplifier comes on 318 * as quietly as possible. */ 319 switch (reg) { 320 case WM8350_LOUT1_VOLUME: 321 out = &wm8350_priv->out1; 322 break; 323 case WM8350_LOUT2_VOLUME: 324 out = &wm8350_priv->out2; 325 break; 326 default: 327 break; 328 } 329 330 if (out) { 331 out->left_vol = ucontrol->value.integer.value[0]; 332 out->right_vol = ucontrol->value.integer.value[1]; 333 if (!out->active) 334 return 1; 335 } 336 337 ret = snd_soc_put_volsw(kcontrol, ucontrol); 338 if (ret < 0) 339 return ret; 340 341 /* now hit the volume update bits (always bit 8) */ 342 val = snd_soc_read(codec, reg); 343 snd_soc_write(codec, reg, val | WM8350_OUT1_VU); 344 return 1; 345 } 346 347 static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, 348 struct snd_ctl_elem_value *ucontrol) 349 { 350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 351 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 352 struct wm8350_output *out1 = &wm8350_priv->out1; 353 struct wm8350_output *out2 = &wm8350_priv->out2; 354 struct soc_mixer_control *mc = 355 (struct soc_mixer_control *)kcontrol->private_value; 356 unsigned int reg = mc->reg; 357 358 /* If these are cached registers use the cache */ 359 switch (reg) { 360 case WM8350_LOUT1_VOLUME: 361 ucontrol->value.integer.value[0] = out1->left_vol; 362 ucontrol->value.integer.value[1] = out1->right_vol; 363 return 0; 364 365 case WM8350_LOUT2_VOLUME: 366 ucontrol->value.integer.value[0] = out2->left_vol; 367 ucontrol->value.integer.value[1] = out2->right_vol; 368 return 0; 369 370 default: 371 break; 372 } 373 374 return snd_soc_get_volsw(kcontrol, ucontrol); 375 } 376 377 static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; 378 static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; 379 static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; 380 static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; 381 static const char *wm8350_adcfilter[] = { "None", "High Pass" }; 382 static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; 383 static const char *wm8350_lr[] = { "Left", "Right" }; 384 385 static const struct soc_enum wm8350_enum[] = { 386 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), 387 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), 388 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), 389 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), 390 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), 391 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), 392 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), 393 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), 394 }; 395 396 static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0); 397 static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0); 398 static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); 399 static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); 400 static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); 401 402 static const unsigned int capture_sd_tlv[] = { 403 TLV_DB_RANGE_HEAD(2), 404 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), 405 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), 406 }; 407 408 static const struct snd_kcontrol_new wm8350_snd_controls[] = { 409 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), 410 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), 411 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume", 412 WM8350_DAC_DIGITAL_VOLUME_L, 413 WM8350_DAC_DIGITAL_VOLUME_R, 414 0, 255, 0, wm8350_get_volsw_2r, 415 wm8350_put_volsw_2r_vu, dac_pcm_tlv), 416 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), 417 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), 418 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]), 419 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]), 420 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]), 421 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume", 422 WM8350_ADC_DIGITAL_VOLUME_L, 423 WM8350_ADC_DIGITAL_VOLUME_R, 424 0, 255, 0, wm8350_get_volsw_2r, 425 wm8350_put_volsw_2r_vu, adc_pcm_tlv), 426 SOC_DOUBLE_TLV("Capture Sidetone Volume", 427 WM8350_ADC_DIVIDER, 428 8, 4, 15, 1, capture_sd_tlv), 429 SOC_DOUBLE_R_EXT_TLV("Capture Volume", 430 WM8350_LEFT_INPUT_VOLUME, 431 WM8350_RIGHT_INPUT_VOLUME, 432 2, 63, 0, wm8350_get_volsw_2r, 433 wm8350_put_volsw_2r_vu, pre_amp_tlv), 434 SOC_DOUBLE_R("Capture ZC Switch", 435 WM8350_LEFT_INPUT_VOLUME, 436 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), 437 SOC_SINGLE_TLV("Left Input Left Sidetone Volume", 438 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), 439 SOC_SINGLE_TLV("Left Input Right Sidetone Volume", 440 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 441 5, 7, 0, out_mix_tlv), 442 SOC_SINGLE_TLV("Left Input Bypass Volume", 443 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 444 9, 7, 0, out_mix_tlv), 445 SOC_SINGLE_TLV("Right Input Left Sidetone Volume", 446 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 447 1, 7, 0, out_mix_tlv), 448 SOC_SINGLE_TLV("Right Input Right Sidetone Volume", 449 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 450 5, 7, 0, out_mix_tlv), 451 SOC_SINGLE_TLV("Right Input Bypass Volume", 452 WM8350_OUTPUT_RIGHT_MIXER_VOLUME, 453 13, 7, 0, out_mix_tlv), 454 SOC_SINGLE("Left Input Mixer +20dB Switch", 455 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), 456 SOC_SINGLE("Right Input Mixer +20dB Switch", 457 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), 458 SOC_SINGLE_TLV("Out4 Capture Volume", 459 WM8350_INPUT_MIXER_VOLUME, 460 1, 7, 0, out_mix_tlv), 461 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume", 462 WM8350_LOUT1_VOLUME, 463 WM8350_ROUT1_VOLUME, 464 2, 63, 0, wm8350_get_volsw_2r, 465 wm8350_put_volsw_2r_vu, out_pga_tlv), 466 SOC_DOUBLE_R("Out1 Playback ZC Switch", 467 WM8350_LOUT1_VOLUME, 468 WM8350_ROUT1_VOLUME, 13, 1, 0), 469 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume", 470 WM8350_LOUT2_VOLUME, 471 WM8350_ROUT2_VOLUME, 472 2, 63, 0, wm8350_get_volsw_2r, 473 wm8350_put_volsw_2r_vu, out_pga_tlv), 474 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, 475 WM8350_ROUT2_VOLUME, 13, 1, 0), 476 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), 477 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, 478 5, 7, 0, out_mix_tlv), 479 480 SOC_DOUBLE_R("Out1 Playback Switch", 481 WM8350_LOUT1_VOLUME, 482 WM8350_ROUT1_VOLUME, 483 14, 1, 1), 484 SOC_DOUBLE_R("Out2 Playback Switch", 485 WM8350_LOUT2_VOLUME, 486 WM8350_ROUT2_VOLUME, 487 14, 1, 1), 488 }; 489 490 /* 491 * DAPM Controls 492 */ 493 494 /* Left Playback Mixer */ 495 static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { 496 SOC_DAPM_SINGLE("Playback Switch", 497 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), 498 SOC_DAPM_SINGLE("Left Bypass Switch", 499 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), 500 SOC_DAPM_SINGLE("Right Playback Switch", 501 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), 502 SOC_DAPM_SINGLE("Left Sidetone Switch", 503 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), 504 SOC_DAPM_SINGLE("Right Sidetone Switch", 505 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), 506 }; 507 508 /* Right Playback Mixer */ 509 static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { 510 SOC_DAPM_SINGLE("Playback Switch", 511 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), 512 SOC_DAPM_SINGLE("Right Bypass Switch", 513 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), 514 SOC_DAPM_SINGLE("Left Playback Switch", 515 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), 516 SOC_DAPM_SINGLE("Left Sidetone Switch", 517 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), 518 SOC_DAPM_SINGLE("Right Sidetone Switch", 519 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), 520 }; 521 522 /* Out4 Mixer */ 523 static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { 524 SOC_DAPM_SINGLE("Right Playback Switch", 525 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), 526 SOC_DAPM_SINGLE("Left Playback Switch", 527 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), 528 SOC_DAPM_SINGLE("Right Capture Switch", 529 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), 530 SOC_DAPM_SINGLE("Out3 Playback Switch", 531 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), 532 SOC_DAPM_SINGLE("Right Mixer Switch", 533 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), 534 SOC_DAPM_SINGLE("Left Mixer Switch", 535 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), 536 }; 537 538 /* Out3 Mixer */ 539 static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { 540 SOC_DAPM_SINGLE("Left Playback Switch", 541 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), 542 SOC_DAPM_SINGLE("Left Capture Switch", 543 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), 544 SOC_DAPM_SINGLE("Out4 Playback Switch", 545 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), 546 SOC_DAPM_SINGLE("Left Mixer Switch", 547 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), 548 }; 549 550 /* Left Input Mixer */ 551 static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { 552 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 553 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), 554 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 555 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), 556 SOC_DAPM_SINGLE("PGA Capture Switch", 557 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1), 558 }; 559 560 /* Right Input Mixer */ 561 static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { 562 SOC_DAPM_SINGLE_TLV("L2 Capture Volume", 563 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), 564 SOC_DAPM_SINGLE_TLV("L3 Capture Volume", 565 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), 566 SOC_DAPM_SINGLE("PGA Capture Switch", 567 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1), 568 }; 569 570 /* Left Mic Mixer */ 571 static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { 572 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), 573 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), 574 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), 575 }; 576 577 /* Right Mic Mixer */ 578 static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { 579 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), 580 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), 581 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), 582 }; 583 584 /* Beep Switch */ 585 static const struct snd_kcontrol_new wm8350_beep_switch_controls = 586 SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); 587 588 /* Out4 Capture Mux */ 589 static const struct snd_kcontrol_new wm8350_out4_capture_controls = 590 SOC_DAPM_ENUM("Route", wm8350_enum[7]); 591 592 static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { 593 594 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), 595 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), 596 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, 597 0, pga_event, 598 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 599 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, 600 pga_event, 601 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 602 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, 603 0, pga_event, 604 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 605 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, 606 pga_event, 607 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 608 609 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, 610 7, 0, &wm8350_right_capt_mixer_controls[0], 611 ARRAY_SIZE(wm8350_right_capt_mixer_controls)), 612 613 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, 614 6, 0, &wm8350_left_capt_mixer_controls[0], 615 ARRAY_SIZE(wm8350_left_capt_mixer_controls)), 616 617 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, 618 &wm8350_out4_mixer_controls[0], 619 ARRAY_SIZE(wm8350_out4_mixer_controls)), 620 621 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, 622 &wm8350_out3_mixer_controls[0], 623 ARRAY_SIZE(wm8350_out3_mixer_controls)), 624 625 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, 626 &wm8350_right_play_mixer_controls[0], 627 ARRAY_SIZE(wm8350_right_play_mixer_controls)), 628 629 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, 630 &wm8350_left_play_mixer_controls[0], 631 ARRAY_SIZE(wm8350_left_play_mixer_controls)), 632 633 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, 634 &wm8350_left_mic_mixer_controls[0], 635 ARRAY_SIZE(wm8350_left_mic_mixer_controls)), 636 637 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, 638 &wm8350_right_mic_mixer_controls[0], 639 ARRAY_SIZE(wm8350_right_mic_mixer_controls)), 640 641 /* virtual mixer for Beep and Out2R */ 642 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 643 644 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, 645 &wm8350_beep_switch_controls), 646 647 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 648 WM8350_POWER_MGMT_4, 3, 0), 649 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", 650 WM8350_POWER_MGMT_4, 2, 0), 651 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", 652 WM8350_POWER_MGMT_4, 5, 0), 653 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", 654 WM8350_POWER_MGMT_4, 4, 0), 655 656 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), 657 658 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, 659 &wm8350_out4_capture_controls), 660 661 SND_SOC_DAPM_OUTPUT("OUT1R"), 662 SND_SOC_DAPM_OUTPUT("OUT1L"), 663 SND_SOC_DAPM_OUTPUT("OUT2R"), 664 SND_SOC_DAPM_OUTPUT("OUT2L"), 665 SND_SOC_DAPM_OUTPUT("OUT3"), 666 SND_SOC_DAPM_OUTPUT("OUT4"), 667 668 SND_SOC_DAPM_INPUT("IN1RN"), 669 SND_SOC_DAPM_INPUT("IN1RP"), 670 SND_SOC_DAPM_INPUT("IN2R"), 671 SND_SOC_DAPM_INPUT("IN1LP"), 672 SND_SOC_DAPM_INPUT("IN1LN"), 673 SND_SOC_DAPM_INPUT("IN2L"), 674 SND_SOC_DAPM_INPUT("IN3R"), 675 SND_SOC_DAPM_INPUT("IN3L"), 676 }; 677 678 static const struct snd_soc_dapm_route wm8350_dapm_routes[] = { 679 680 /* left playback mixer */ 681 {"Left Playback Mixer", "Playback Switch", "Left DAC"}, 682 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, 683 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, 684 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 685 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 686 687 /* right playback mixer */ 688 {"Right Playback Mixer", "Playback Switch", "Right DAC"}, 689 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, 690 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, 691 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, 692 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, 693 694 /* out4 playback mixer */ 695 {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, 696 {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, 697 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, 698 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, 699 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, 700 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 701 {"OUT4", NULL, "Out4 Mixer"}, 702 703 /* out3 playback mixer */ 704 {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, 705 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, 706 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, 707 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, 708 {"OUT3", NULL, "Out3 Mixer"}, 709 710 /* out2 */ 711 {"Right Out2 PGA", NULL, "Right Playback Mixer"}, 712 {"Left Out2 PGA", NULL, "Left Playback Mixer"}, 713 {"OUT2L", NULL, "Left Out2 PGA"}, 714 {"OUT2R", NULL, "Right Out2 PGA"}, 715 716 /* out1 */ 717 {"Right Out1 PGA", NULL, "Right Playback Mixer"}, 718 {"Left Out1 PGA", NULL, "Left Playback Mixer"}, 719 {"OUT1L", NULL, "Left Out1 PGA"}, 720 {"OUT1R", NULL, "Right Out1 PGA"}, 721 722 /* ADCs */ 723 {"Left ADC", NULL, "Left Capture Mixer"}, 724 {"Right ADC", NULL, "Right Capture Mixer"}, 725 726 /* Left capture mixer */ 727 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, 728 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, 729 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, 730 {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, 731 732 /* Right capture mixer */ 733 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, 734 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, 735 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, 736 {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, 737 738 /* L3 Inputs */ 739 {"IN3L PGA", NULL, "IN3L"}, 740 {"IN3R PGA", NULL, "IN3R"}, 741 742 /* Left Mic mixer */ 743 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, 744 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, 745 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, 746 747 /* Right Mic mixer */ 748 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, 749 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, 750 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, 751 752 /* out 4 capture */ 753 {"Out4 Capture Channel", NULL, "Out4 Mixer"}, 754 755 /* Beep */ 756 {"Beep", NULL, "IN3R PGA"}, 757 }; 758 759 static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, 760 int clk_id, unsigned int freq, int dir) 761 { 762 struct snd_soc_codec *codec = codec_dai->codec; 763 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 764 struct wm8350 *wm8350 = wm8350_data->wm8350; 765 u16 fll_4; 766 767 switch (clk_id) { 768 case WM8350_MCLK_SEL_MCLK: 769 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, 770 WM8350_MCLK_SEL); 771 break; 772 case WM8350_MCLK_SEL_PLL_MCLK: 773 case WM8350_MCLK_SEL_PLL_DAC: 774 case WM8350_MCLK_SEL_PLL_ADC: 775 case WM8350_MCLK_SEL_PLL_32K: 776 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, 777 WM8350_MCLK_SEL); 778 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) & 779 ~WM8350_FLL_CLK_SRC_MASK; 780 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); 781 break; 782 } 783 784 /* MCLK direction */ 785 if (dir == SND_SOC_CLOCK_OUT) 786 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, 787 WM8350_MCLK_DIR); 788 else 789 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, 790 WM8350_MCLK_DIR); 791 792 return 0; 793 } 794 795 static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) 796 { 797 struct snd_soc_codec *codec = codec_dai->codec; 798 u16 val; 799 800 switch (div_id) { 801 case WM8350_ADC_CLKDIV: 802 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) & 803 ~WM8350_ADC_CLKDIV_MASK; 804 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div); 805 break; 806 case WM8350_DAC_CLKDIV: 807 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) & 808 ~WM8350_DAC_CLKDIV_MASK; 809 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); 810 break; 811 case WM8350_BCLK_CLKDIV: 812 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 813 ~WM8350_BCLK_DIV_MASK; 814 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 815 break; 816 case WM8350_OPCLK_CLKDIV: 817 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 818 ~WM8350_OPCLK_DIV_MASK; 819 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 820 break; 821 case WM8350_SYS_CLKDIV: 822 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) & 823 ~WM8350_MCLK_DIV_MASK; 824 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 825 break; 826 case WM8350_DACLR_CLKDIV: 827 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) & 828 ~WM8350_DACLRC_RATE_MASK; 829 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div); 830 break; 831 case WM8350_ADCLR_CLKDIV: 832 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) & 833 ~WM8350_ADCLRC_RATE_MASK; 834 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div); 835 break; 836 default: 837 return -EINVAL; 838 } 839 840 return 0; 841 } 842 843 static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 844 { 845 struct snd_soc_codec *codec = codec_dai->codec; 846 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) & 847 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); 848 u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) & 849 ~WM8350_BCLK_MSTR; 850 u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) & 851 ~WM8350_DACLRC_ENA; 852 u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) & 853 ~WM8350_ADCLRC_ENA; 854 855 /* set master/slave audio interface */ 856 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 857 case SND_SOC_DAIFMT_CBM_CFM: 858 master |= WM8350_BCLK_MSTR; 859 dac_lrc |= WM8350_DACLRC_ENA; 860 adc_lrc |= WM8350_ADCLRC_ENA; 861 break; 862 case SND_SOC_DAIFMT_CBS_CFS: 863 break; 864 default: 865 return -EINVAL; 866 } 867 868 /* interface format */ 869 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 870 case SND_SOC_DAIFMT_I2S: 871 iface |= 0x2 << 8; 872 break; 873 case SND_SOC_DAIFMT_RIGHT_J: 874 break; 875 case SND_SOC_DAIFMT_LEFT_J: 876 iface |= 0x1 << 8; 877 break; 878 case SND_SOC_DAIFMT_DSP_A: 879 iface |= 0x3 << 8; 880 break; 881 case SND_SOC_DAIFMT_DSP_B: 882 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV; 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 /* clock inversion */ 889 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 890 case SND_SOC_DAIFMT_NB_NF: 891 break; 892 case SND_SOC_DAIFMT_IB_IF: 893 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; 894 break; 895 case SND_SOC_DAIFMT_IB_NF: 896 iface |= WM8350_AIF_BCLK_INV; 897 break; 898 case SND_SOC_DAIFMT_NB_IF: 899 iface |= WM8350_AIF_LRCLK_INV; 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 snd_soc_write(codec, WM8350_AI_FORMATING, iface); 906 snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master); 907 snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc); 908 snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc); 909 return 0; 910 } 911 912 static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, 913 struct snd_pcm_hw_params *params, 914 struct snd_soc_dai *codec_dai) 915 { 916 struct snd_soc_codec *codec = codec_dai->codec; 917 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 918 struct wm8350 *wm8350 = wm8350_data->wm8350; 919 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) & 920 ~WM8350_AIF_WL_MASK; 921 922 /* bit size */ 923 switch (params_format(params)) { 924 case SNDRV_PCM_FORMAT_S16_LE: 925 break; 926 case SNDRV_PCM_FORMAT_S20_3LE: 927 iface |= 0x1 << 10; 928 break; 929 case SNDRV_PCM_FORMAT_S24_LE: 930 iface |= 0x2 << 10; 931 break; 932 case SNDRV_PCM_FORMAT_S32_LE: 933 iface |= 0x3 << 10; 934 break; 935 } 936 937 snd_soc_write(codec, WM8350_AI_FORMATING, iface); 938 939 /* The sloping stopband filter is recommended for use with 940 * lower sample rates to improve performance. 941 */ 942 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 943 if (params_rate(params) < 24000) 944 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 945 WM8350_DAC_SB_FILT); 946 else 947 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME, 948 WM8350_DAC_SB_FILT); 949 } 950 951 return 0; 952 } 953 954 static int wm8350_mute(struct snd_soc_dai *dai, int mute) 955 { 956 struct snd_soc_codec *codec = dai->codec; 957 unsigned int val; 958 959 if (mute) 960 val = WM8350_DAC_MUTE_ENA; 961 else 962 val = 0; 963 964 snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val); 965 966 return 0; 967 } 968 969 /* FLL divisors */ 970 struct _fll_div { 971 int div; /* FLL_OUTDIV */ 972 int n; 973 int k; 974 int ratio; /* FLL_FRATIO */ 975 }; 976 977 /* The size in bits of the fll divide multiplied by 10 978 * to allow rounding later */ 979 #define FIXED_FLL_SIZE ((1 << 16) * 10) 980 981 static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, 982 unsigned int output) 983 { 984 u64 Kpart; 985 unsigned int t1, t2, K, Nmod; 986 987 if (output >= 2815250 && output <= 3125000) 988 fll_div->div = 0x4; 989 else if (output >= 5625000 && output <= 6250000) 990 fll_div->div = 0x3; 991 else if (output >= 11250000 && output <= 12500000) 992 fll_div->div = 0x2; 993 else if (output >= 22500000 && output <= 25000000) 994 fll_div->div = 0x1; 995 else { 996 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); 997 return -EINVAL; 998 } 999 1000 if (input > 48000) 1001 fll_div->ratio = 1; 1002 else 1003 fll_div->ratio = 8; 1004 1005 t1 = output * (1 << (fll_div->div + 1)); 1006 t2 = input * fll_div->ratio; 1007 1008 fll_div->n = t1 / t2; 1009 Nmod = t1 % t2; 1010 1011 if (Nmod) { 1012 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1013 do_div(Kpart, t2); 1014 K = Kpart & 0xFFFFFFFF; 1015 1016 /* Check if we need to round */ 1017 if ((K % 10) >= 5) 1018 K += 5; 1019 1020 /* Move down to proper range now rounding is done */ 1021 K /= 10; 1022 fll_div->k = K; 1023 } else 1024 fll_div->k = 0; 1025 1026 return 0; 1027 } 1028 1029 static int wm8350_set_fll(struct snd_soc_dai *codec_dai, 1030 int pll_id, int source, unsigned int freq_in, 1031 unsigned int freq_out) 1032 { 1033 struct snd_soc_codec *codec = codec_dai->codec; 1034 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1035 struct wm8350 *wm8350 = priv->wm8350; 1036 struct _fll_div fll_div; 1037 int ret = 0; 1038 u16 fll_1, fll_4; 1039 1040 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out) 1041 return 0; 1042 1043 /* power down FLL - we need to do this for reconfiguration */ 1044 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1045 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); 1046 1047 if (freq_out == 0 || freq_in == 0) 1048 return ret; 1049 1050 ret = fll_factors(&fll_div, freq_in, freq_out); 1051 if (ret < 0) 1052 return ret; 1053 dev_dbg(wm8350->dev, 1054 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d", 1055 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, 1056 fll_div.ratio); 1057 1058 /* set up N.K & dividers */ 1059 fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) & 1060 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); 1061 snd_soc_write(codec, WM8350_FLL_CONTROL_1, 1062 fll_1 | (fll_div.div << 8) | 0x50); 1063 snd_soc_write(codec, WM8350_FLL_CONTROL_2, 1064 (fll_div.ratio << 11) | (fll_div. 1065 n & WM8350_FLL_N_MASK)); 1066 snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); 1067 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) & 1068 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); 1069 snd_soc_write(codec, WM8350_FLL_CONTROL_4, 1070 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | 1071 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); 1072 1073 /* power FLL on */ 1074 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); 1075 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); 1076 1077 priv->fll_freq_out = freq_out; 1078 priv->fll_freq_in = freq_in; 1079 1080 return 0; 1081 } 1082 1083 static int wm8350_set_bias_level(struct snd_soc_codec *codec, 1084 enum snd_soc_bias_level level) 1085 { 1086 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1087 struct wm8350 *wm8350 = priv->wm8350; 1088 struct wm8350_audio_platform_data *platform = 1089 wm8350->codec.platform_data; 1090 u16 pm1; 1091 int ret; 1092 1093 switch (level) { 1094 case SND_SOC_BIAS_ON: 1095 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1096 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1097 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1098 pm1 | WM8350_VMID_50K | 1099 platform->codec_current_on << 14); 1100 break; 1101 1102 case SND_SOC_BIAS_PREPARE: 1103 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); 1104 pm1 &= ~WM8350_VMID_MASK; 1105 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1106 pm1 | WM8350_VMID_50K); 1107 break; 1108 1109 case SND_SOC_BIAS_STANDBY: 1110 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1111 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), 1112 priv->supplies); 1113 if (ret != 0) 1114 return ret; 1115 1116 /* Enable the system clock */ 1117 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, 1118 WM8350_SYSCLK_ENA); 1119 1120 /* mute DAC & outputs */ 1121 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, 1122 WM8350_DAC_MUTE_ENA); 1123 1124 /* discharge cap memory */ 1125 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1126 platform->dis_out1 | 1127 (platform->dis_out2 << 2) | 1128 (platform->dis_out3 << 4) | 1129 (platform->dis_out4 << 6)); 1130 1131 /* wait for discharge */ 1132 schedule_timeout_interruptible(msecs_to_jiffies 1133 (platform-> 1134 cap_discharge_msecs)); 1135 1136 /* enable antipop */ 1137 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1138 (platform->vmid_s_curve << 8)); 1139 1140 /* ramp up vmid */ 1141 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1142 (platform-> 1143 codec_current_charge << 14) | 1144 WM8350_VMID_5K | WM8350_VMIDEN | 1145 WM8350_VBUFEN); 1146 1147 /* wait for vmid */ 1148 schedule_timeout_interruptible(msecs_to_jiffies 1149 (platform-> 1150 vmid_charge_msecs)); 1151 1152 /* turn on vmid 300k */ 1153 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1154 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1155 pm1 |= WM8350_VMID_300K | 1156 (platform->codec_current_standby << 14); 1157 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1158 pm1); 1159 1160 1161 /* enable analogue bias */ 1162 pm1 |= WM8350_BIASEN; 1163 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1164 1165 /* disable antipop */ 1166 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1167 1168 } else { 1169 /* turn on vmid 300k and reduce current */ 1170 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1171 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); 1172 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1173 pm1 | WM8350_VMID_300K | 1174 (platform-> 1175 codec_current_standby << 14)); 1176 1177 } 1178 break; 1179 1180 case SND_SOC_BIAS_OFF: 1181 1182 /* mute DAC & enable outputs */ 1183 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 1184 1185 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, 1186 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | 1187 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); 1188 1189 /* enable anti pop S curve */ 1190 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1191 (platform->vmid_s_curve << 8)); 1192 1193 /* turn off vmid */ 1194 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1195 ~WM8350_VMIDEN; 1196 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1197 1198 /* wait */ 1199 schedule_timeout_interruptible(msecs_to_jiffies 1200 (platform-> 1201 vmid_discharge_msecs)); 1202 1203 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 1204 (platform->vmid_s_curve << 8) | 1205 platform->dis_out1 | 1206 (platform->dis_out2 << 2) | 1207 (platform->dis_out3 << 4) | 1208 (platform->dis_out4 << 6)); 1209 1210 /* turn off VBuf and drain */ 1211 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & 1212 ~(WM8350_VBUFEN | WM8350_VMID_MASK); 1213 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, 1214 pm1 | WM8350_OUTPUT_DRAIN_EN); 1215 1216 /* wait */ 1217 schedule_timeout_interruptible(msecs_to_jiffies 1218 (platform->drain_msecs)); 1219 1220 pm1 &= ~WM8350_BIASEN; 1221 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); 1222 1223 /* disable anti-pop */ 1224 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); 1225 1226 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, 1227 WM8350_OUT1L_ENA); 1228 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, 1229 WM8350_OUT1R_ENA); 1230 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, 1231 WM8350_OUT2L_ENA); 1232 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, 1233 WM8350_OUT2R_ENA); 1234 1235 /* disable clock gen */ 1236 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, 1237 WM8350_SYSCLK_ENA); 1238 1239 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 1240 priv->supplies); 1241 break; 1242 } 1243 codec->dapm.bias_level = level; 1244 return 0; 1245 } 1246 1247 static int wm8350_suspend(struct snd_soc_codec *codec) 1248 { 1249 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1250 return 0; 1251 } 1252 1253 static int wm8350_resume(struct snd_soc_codec *codec) 1254 { 1255 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1256 1257 return 0; 1258 } 1259 1260 static void wm8350_hp_work(struct wm8350_data *priv, 1261 struct wm8350_jack_data *jack, 1262 u16 mask) 1263 { 1264 struct wm8350 *wm8350 = priv->wm8350; 1265 u16 reg; 1266 int report; 1267 1268 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1269 if (reg & mask) 1270 report = jack->report; 1271 else 1272 report = 0; 1273 1274 snd_soc_jack_report(jack->jack, report, jack->report); 1275 1276 } 1277 1278 static void wm8350_hpl_work(struct work_struct *work) 1279 { 1280 struct wm8350_data *priv = 1281 container_of(work, struct wm8350_data, hpl.work.work); 1282 1283 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL); 1284 } 1285 1286 static void wm8350_hpr_work(struct work_struct *work) 1287 { 1288 struct wm8350_data *priv = 1289 container_of(work, struct wm8350_data, hpr.work.work); 1290 1291 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); 1292 } 1293 1294 static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data) 1295 { 1296 struct wm8350_data *priv = data; 1297 struct wm8350 *wm8350 = priv->wm8350; 1298 1299 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1300 trace_snd_soc_jack_irq("WM8350 HPL"); 1301 #endif 1302 1303 if (device_may_wakeup(wm8350->dev)) 1304 pm_wakeup_event(wm8350->dev, 250); 1305 1306 schedule_delayed_work(&priv->hpl.work, 200); 1307 1308 return IRQ_HANDLED; 1309 } 1310 1311 static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data) 1312 { 1313 struct wm8350_data *priv = data; 1314 struct wm8350 *wm8350 = priv->wm8350; 1315 1316 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1317 trace_snd_soc_jack_irq("WM8350 HPR"); 1318 #endif 1319 1320 if (device_may_wakeup(wm8350->dev)) 1321 pm_wakeup_event(wm8350->dev, 250); 1322 1323 schedule_delayed_work(&priv->hpr.work, 200); 1324 1325 return IRQ_HANDLED; 1326 } 1327 1328 /** 1329 * wm8350_hp_jack_detect - Enable headphone jack detection. 1330 * 1331 * @codec: WM8350 codec 1332 * @which: left or right jack detect signal 1333 * @jack: jack to report detection events on 1334 * @report: value to report 1335 * 1336 * Enables the headphone jack detection of the WM8350. If no report 1337 * is specified then detection is disabled. 1338 */ 1339 int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, 1340 struct snd_soc_jack *jack, int report) 1341 { 1342 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1343 struct wm8350 *wm8350 = priv->wm8350; 1344 int irq; 1345 int ena; 1346 1347 switch (which) { 1348 case WM8350_JDL: 1349 priv->hpl.jack = jack; 1350 priv->hpl.report = report; 1351 irq = WM8350_IRQ_CODEC_JCK_DET_L; 1352 ena = WM8350_JDL_ENA; 1353 break; 1354 1355 case WM8350_JDR: 1356 priv->hpr.jack = jack; 1357 priv->hpr.report = report; 1358 irq = WM8350_IRQ_CODEC_JCK_DET_R; 1359 ena = WM8350_JDR_ENA; 1360 break; 1361 1362 default: 1363 return -EINVAL; 1364 } 1365 1366 if (report) { 1367 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1368 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); 1369 } else { 1370 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena); 1371 } 1372 1373 /* Sync status */ 1374 switch (which) { 1375 case WM8350_JDL: 1376 wm8350_hpl_jack_handler(0, priv); 1377 break; 1378 case WM8350_JDR: 1379 wm8350_hpr_jack_handler(0, priv); 1380 break; 1381 } 1382 1383 return 0; 1384 } 1385 EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); 1386 1387 static irqreturn_t wm8350_mic_handler(int irq, void *data) 1388 { 1389 struct wm8350_data *priv = data; 1390 struct wm8350 *wm8350 = priv->wm8350; 1391 u16 reg; 1392 int report = 0; 1393 1394 #ifndef CONFIG_SND_SOC_WM8350_MODULE 1395 trace_snd_soc_jack_irq("WM8350 mic"); 1396 #endif 1397 1398 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1399 if (reg & WM8350_JACK_MICSCD_LVL) 1400 report |= priv->mic.short_report; 1401 if (reg & WM8350_JACK_MICSD_LVL) 1402 report |= priv->mic.report; 1403 1404 snd_soc_jack_report(priv->mic.jack, report, 1405 priv->mic.report | priv->mic.short_report); 1406 1407 return IRQ_HANDLED; 1408 } 1409 1410 /** 1411 * wm8350_mic_jack_detect - Enable microphone jack detection. 1412 * 1413 * @codec: WM8350 codec 1414 * @jack: jack to report detection events on 1415 * @detect_report: value to report when presence detected 1416 * @short_report: value to report when microphone short detected 1417 * 1418 * Enables the microphone jack detection of the WM8350. If both reports 1419 * are specified as zero then detection is disabled. 1420 */ 1421 int wm8350_mic_jack_detect(struct snd_soc_codec *codec, 1422 struct snd_soc_jack *jack, 1423 int detect_report, int short_report) 1424 { 1425 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1426 struct wm8350 *wm8350 = priv->wm8350; 1427 1428 priv->mic.jack = jack; 1429 priv->mic.report = detect_report; 1430 priv->mic.short_report = short_report; 1431 1432 if (detect_report || short_report) { 1433 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1434 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1, 1435 WM8350_MIC_DET_ENA); 1436 } else { 1437 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1, 1438 WM8350_MIC_DET_ENA); 1439 } 1440 1441 return 0; 1442 } 1443 EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect); 1444 1445 #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) 1446 1447 #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1448 SNDRV_PCM_FMTBIT_S20_3LE |\ 1449 SNDRV_PCM_FMTBIT_S24_LE) 1450 1451 static const struct snd_soc_dai_ops wm8350_dai_ops = { 1452 .hw_params = wm8350_pcm_hw_params, 1453 .digital_mute = wm8350_mute, 1454 .set_fmt = wm8350_set_dai_fmt, 1455 .set_sysclk = wm8350_set_dai_sysclk, 1456 .set_pll = wm8350_set_fll, 1457 .set_clkdiv = wm8350_set_clkdiv, 1458 }; 1459 1460 static struct snd_soc_dai_driver wm8350_dai = { 1461 .name = "wm8350-hifi", 1462 .playback = { 1463 .stream_name = "Playback", 1464 .channels_min = 1, 1465 .channels_max = 2, 1466 .rates = WM8350_RATES, 1467 .formats = WM8350_FORMATS, 1468 }, 1469 .capture = { 1470 .stream_name = "Capture", 1471 .channels_min = 1, 1472 .channels_max = 2, 1473 .rates = WM8350_RATES, 1474 .formats = WM8350_FORMATS, 1475 }, 1476 .ops = &wm8350_dai_ops, 1477 }; 1478 1479 static int wm8350_codec_probe(struct snd_soc_codec *codec) 1480 { 1481 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1482 struct wm8350_data *priv; 1483 struct wm8350_output *out1; 1484 struct wm8350_output *out2; 1485 int ret, i; 1486 1487 if (wm8350->codec.platform_data == NULL) { 1488 dev_err(codec->dev, "No audio platform data supplied\n"); 1489 return -EINVAL; 1490 } 1491 1492 priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data), 1493 GFP_KERNEL); 1494 if (priv == NULL) 1495 return -ENOMEM; 1496 snd_soc_codec_set_drvdata(codec, priv); 1497 1498 priv->wm8350 = wm8350; 1499 1500 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1501 priv->supplies[i].supply = supply_names[i]; 1502 1503 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), 1504 priv->supplies); 1505 if (ret != 0) 1506 return ret; 1507 1508 codec->control_data = wm8350->regmap; 1509 1510 snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); 1511 1512 /* Put the codec into reset if it wasn't already */ 1513 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1514 1515 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); 1516 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work); 1517 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work); 1518 1519 /* Enable the codec */ 1520 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1521 1522 /* Enable robust clocking mode in ADC */ 1523 snd_soc_write(codec, WM8350_SECURITY, 0xa7); 1524 snd_soc_write(codec, 0xde, 0x13); 1525 snd_soc_write(codec, WM8350_SECURITY, 0); 1526 1527 /* read OUT1 & OUT2 volumes */ 1528 out1 = &priv->out1; 1529 out2 = &priv->out2; 1530 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & 1531 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1532 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & 1533 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1534 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & 1535 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; 1536 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & 1537 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; 1538 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); 1539 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); 1540 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); 1541 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); 1542 1543 /* Latch VU bits & mute */ 1544 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, 1545 WM8350_OUT1_VU | WM8350_OUT1L_MUTE); 1546 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, 1547 WM8350_OUT2_VU | WM8350_OUT2L_MUTE); 1548 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, 1549 WM8350_OUT1_VU | WM8350_OUT1R_MUTE); 1550 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, 1551 WM8350_OUT2_VU | WM8350_OUT2R_MUTE); 1552 1553 /* Make sure AIF tristating is disabled by default */ 1554 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI); 1555 1556 /* Make sure we've got a sane companding setup too */ 1557 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP, 1558 WM8350_DAC_COMP | WM8350_LOOPBACK); 1559 1560 /* Make sure jack detect is disabled to start off with */ 1561 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1562 WM8350_JDL_ENA | WM8350_JDR_ENA); 1563 1564 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, 1565 wm8350_hpl_jack_handler, 0, "Left jack detect", 1566 priv); 1567 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, 1568 wm8350_hpr_jack_handler, 0, "Right jack detect", 1569 priv); 1570 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, 1571 wm8350_mic_handler, 0, "Microphone short", priv); 1572 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD, 1573 wm8350_mic_handler, 0, "Microphone detect", priv); 1574 1575 1576 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1577 1578 return 0; 1579 } 1580 1581 static int wm8350_codec_remove(struct snd_soc_codec *codec) 1582 { 1583 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1584 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1585 1586 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1587 WM8350_JDL_ENA | WM8350_JDR_ENA); 1588 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); 1589 1590 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv); 1591 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv); 1592 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv); 1593 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv); 1594 1595 priv->hpl.jack = NULL; 1596 priv->hpr.jack = NULL; 1597 priv->mic.jack = NULL; 1598 1599 cancel_delayed_work_sync(&priv->hpl.work); 1600 cancel_delayed_work_sync(&priv->hpr.work); 1601 1602 /* if there was any work waiting then we run it now and 1603 * wait for its completion */ 1604 flush_delayed_work_sync(&codec->dapm.delayed_work); 1605 1606 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1607 1608 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1609 1610 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); 1611 1612 return 0; 1613 } 1614 1615 static struct snd_soc_codec_driver soc_codec_dev_wm8350 = { 1616 .probe = wm8350_codec_probe, 1617 .remove = wm8350_codec_remove, 1618 .suspend = wm8350_suspend, 1619 .resume = wm8350_resume, 1620 .set_bias_level = wm8350_set_bias_level, 1621 1622 .controls = wm8350_snd_controls, 1623 .num_controls = ARRAY_SIZE(wm8350_snd_controls), 1624 .dapm_widgets = wm8350_dapm_widgets, 1625 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets), 1626 .dapm_routes = wm8350_dapm_routes, 1627 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes), 1628 }; 1629 1630 static int __devinit wm8350_probe(struct platform_device *pdev) 1631 { 1632 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350, 1633 &wm8350_dai, 1); 1634 } 1635 1636 static int __devexit wm8350_remove(struct platform_device *pdev) 1637 { 1638 snd_soc_unregister_codec(&pdev->dev); 1639 return 0; 1640 } 1641 1642 static struct platform_driver wm8350_codec_driver = { 1643 .driver = { 1644 .name = "wm8350-codec", 1645 .owner = THIS_MODULE, 1646 }, 1647 .probe = wm8350_probe, 1648 .remove = __devexit_p(wm8350_remove), 1649 }; 1650 1651 module_platform_driver(wm8350_codec_driver); 1652 1653 MODULE_DESCRIPTION("ASoC WM8350 driver"); 1654 MODULE_AUTHOR("Liam Girdwood"); 1655 MODULE_LICENSE("GPL"); 1656 MODULE_ALIAS("platform:wm8350-codec"); 1657