1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // CS42L43 CODEC driver 4 // 5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 // Cirrus Logic International Semiconductor Ltd. 7 8 #include <linux/bitops.h> 9 #include <linux/err.h> 10 #include <linux/errno.h> 11 #include <linux/gcd.h> 12 #include <linux/irq.h> 13 #include <linux/jiffies.h> 14 #include <linux/mfd/cs42l43.h> 15 #include <linux/mfd/cs42l43-regs.h> 16 #include <linux/module.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/string.h> 19 #include <sound/control.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc-component.h> 23 #include <sound/soc-dapm.h> 24 #include <sound/soc-dai.h> 25 #include <sound/soc.h> 26 #include <sound/tlv.h> 27 28 #include "cs42l43.h" 29 30 #define CS42L43_DECL_MUX(name, reg) \ 31 static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ 32 0, CS42L43_MIXER_SRC_MASK, \ 33 cs42l43_mixer_texts, cs42l43_mixer_values); \ 34 static const struct snd_kcontrol_new cs42l43_##name##_mux = \ 35 SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) 36 37 #define CS42L43_DECL_MIXER(name, reg) \ 38 CS42L43_DECL_MUX(name##_in1, reg); \ 39 CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ 40 CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ 41 CS42L43_DECL_MUX(name##_in4, reg + 0xC) 42 43 #define CS42L43_DAPM_MUX(name_str, name) \ 44 SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) 45 46 #define CS42L43_DAPM_MIXER(name_str, name) \ 47 SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \ 48 SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \ 49 SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \ 50 SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \ 51 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) 52 53 #define CS42L43_BASE_ROUTES(name_str) \ 54 { name_str, "Tone Generator 1", "Tone 1" }, \ 55 { name_str, "Tone Generator 2", "Tone 2" }, \ 56 { name_str, "Decimator 1", "Decimator 1" }, \ 57 { name_str, "Decimator 2", "Decimator 2" }, \ 58 { name_str, "Decimator 3", "Decimator 3" }, \ 59 { name_str, "Decimator 4", "Decimator 4" }, \ 60 { name_str, "ASPRX1", "ASPRX1" }, \ 61 { name_str, "ASPRX2", "ASPRX2" }, \ 62 { name_str, "ASPRX3", "ASPRX3" }, \ 63 { name_str, "ASPRX4", "ASPRX4" }, \ 64 { name_str, "ASPRX5", "ASPRX5" }, \ 65 { name_str, "ASPRX6", "ASPRX6" }, \ 66 { name_str, "DP5RX1", "DP5RX1" }, \ 67 { name_str, "DP5RX2", "DP5RX2" }, \ 68 { name_str, "DP6RX1", "DP6RX1" }, \ 69 { name_str, "DP6RX2", "DP6RX2" }, \ 70 { name_str, "DP7RX1", "DP7RX1" }, \ 71 { name_str, "DP7RX2", "DP7RX2" }, \ 72 { name_str, "ASRC INT1", "ASRC_INT1" }, \ 73 { name_str, "ASRC INT2", "ASRC_INT2" }, \ 74 { name_str, "ASRC INT3", "ASRC_INT3" }, \ 75 { name_str, "ASRC INT4", "ASRC_INT4" }, \ 76 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \ 77 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \ 78 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \ 79 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \ 80 { name_str, "ISRC1 INT1", "ISRC1INT1" }, \ 81 { name_str, "ISRC1 INT2", "ISRC1INT2" }, \ 82 { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \ 83 { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \ 84 { name_str, "ISRC2 INT1", "ISRC2INT1" }, \ 85 { name_str, "ISRC2 INT2", "ISRC2INT2" }, \ 86 { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \ 87 { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \ 88 { name_str, "EQ1", "EQ" }, \ 89 { name_str, "EQ2", "EQ" } 90 91 #define CS42L43_MUX_ROUTES(name_str, widget) \ 92 { widget, NULL, name_str " Input" }, \ 93 { name_str " Input", NULL, "Mixer Core" }, \ 94 CS42L43_BASE_ROUTES(name_str " Input") 95 96 #define CS42L43_MIXER_ROUTES(name_str, widget) \ 97 { name_str " Mixer", NULL, name_str " Input 1" }, \ 98 { name_str " Mixer", NULL, name_str " Input 2" }, \ 99 { name_str " Mixer", NULL, name_str " Input 3" }, \ 100 { name_str " Mixer", NULL, name_str " Input 4" }, \ 101 { widget, NULL, name_str " Mixer" }, \ 102 { name_str " Mixer", NULL, "Mixer Core" }, \ 103 CS42L43_BASE_ROUTES(name_str " Input 1"), \ 104 CS42L43_BASE_ROUTES(name_str " Input 2"), \ 105 CS42L43_BASE_ROUTES(name_str " Input 3"), \ 106 CS42L43_BASE_ROUTES(name_str " Input 4") 107 108 #define CS42L43_MIXER_VOLUMES(name_str, base) \ 109 SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ 110 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 111 cs42l43_mixer_tlv), \ 112 SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \ 113 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 114 cs42l43_mixer_tlv), \ 115 SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \ 116 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 117 cs42l43_mixer_tlv), \ 118 SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \ 119 CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ 120 cs42l43_mixer_tlv) 121 122 #define CS42L43_IRQ_ERROR(name) \ 123 static irqreturn_t cs42l43_##name(int irq, void *data) \ 124 { \ 125 struct cs42l43_codec *priv = data; \ 126 dev_err(priv->dev, "Error " #name " IRQ\n"); \ 127 return IRQ_HANDLED; \ 128 } 129 130 CS42L43_IRQ_ERROR(pll_lost_lock) 131 CS42L43_IRQ_ERROR(spkr_clock_stop) 132 CS42L43_IRQ_ERROR(spkl_clock_stop) 133 CS42L43_IRQ_ERROR(spkr_brown_out) 134 CS42L43_IRQ_ERROR(spkl_brown_out) 135 CS42L43_IRQ_ERROR(spkr_therm_shutdown) 136 CS42L43_IRQ_ERROR(spkl_therm_shutdown) 137 CS42L43_IRQ_ERROR(spkr_therm_warm) 138 CS42L43_IRQ_ERROR(spkl_therm_warm) 139 CS42L43_IRQ_ERROR(spkr_sc_detect) 140 CS42L43_IRQ_ERROR(spkl_sc_detect) 141 142 static void cs42l43_hp_ilimit_clear_work(struct work_struct *work) 143 { 144 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec, 145 hp_ilimit_clear_work.work); 146 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component); 147 148 snd_soc_dapm_mutex_lock(dapm); 149 150 priv->hp_ilimit_count--; 151 152 if (priv->hp_ilimit_count) 153 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work, 154 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 155 156 snd_soc_dapm_mutex_unlock(dapm); 157 } 158 159 static void cs42l43_hp_ilimit_work(struct work_struct *work) 160 { 161 struct cs42l43_codec *priv = container_of(work, struct cs42l43_codec, 162 hp_ilimit_work); 163 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component); 164 struct cs42l43 *cs42l43 = priv->core; 165 166 snd_soc_dapm_mutex_lock(dapm); 167 168 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) { 169 if (!priv->hp_ilimit_count) 170 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work, 171 msecs_to_jiffies(CS42L43_HP_ILIMIT_DECAY_MS)); 172 173 priv->hp_ilimit_count++; 174 snd_soc_dapm_mutex_unlock(dapm); 175 return; 176 } 177 178 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n", 179 CS42L43_HP_ILIMIT_BACKOFF_MS); 180 181 priv->hp_ilimited = true; 182 183 // No need to wait for disable, as just disabling for a period of time 184 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 185 CS42L43_HP_EN_MASK, 0); 186 187 snd_soc_dapm_mutex_unlock(dapm); 188 189 msleep(CS42L43_HP_ILIMIT_BACKOFF_MS); 190 191 snd_soc_dapm_mutex_lock(dapm); 192 193 if (priv->hp_ena && !priv->load_detect_running) { 194 unsigned long time_left; 195 196 reinit_completion(&priv->hp_startup); 197 198 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 199 CS42L43_HP_EN_MASK, priv->hp_ena); 200 201 time_left = wait_for_completion_timeout(&priv->hp_startup, 202 msecs_to_jiffies(CS42L43_HP_TIMEOUT_MS)); 203 if (!time_left) 204 dev_err(priv->dev, "ilimit HP restore timed out\n"); 205 } 206 207 priv->hp_ilimited = false; 208 209 snd_soc_dapm_mutex_unlock(dapm); 210 } 211 212 static irqreturn_t cs42l43_hp_ilimit(int irq, void *data) 213 { 214 struct cs42l43_codec *priv = data; 215 216 dev_dbg(priv->dev, "headphone ilimit IRQ\n"); 217 218 queue_work(system_long_wq, &priv->hp_ilimit_work); 219 220 return IRQ_HANDLED; 221 } 222 223 #define CS42L43_IRQ_COMPLETE(name) \ 224 static irqreturn_t cs42l43_##name(int irq, void *data) \ 225 { \ 226 struct cs42l43_codec *priv = data; \ 227 dev_dbg(priv->dev, #name " completed\n"); \ 228 complete(&priv->name); \ 229 return IRQ_HANDLED; \ 230 } 231 232 CS42L43_IRQ_COMPLETE(pll_ready) 233 CS42L43_IRQ_COMPLETE(hp_startup) 234 CS42L43_IRQ_COMPLETE(hp_shutdown) 235 CS42L43_IRQ_COMPLETE(type_detect) 236 CS42L43_IRQ_COMPLETE(spkr_shutdown) 237 CS42L43_IRQ_COMPLETE(spkl_shutdown) 238 CS42L43_IRQ_COMPLETE(spkr_startup) 239 CS42L43_IRQ_COMPLETE(spkl_startup) 240 CS42L43_IRQ_COMPLETE(load_detect) 241 242 static irqreturn_t cs42l43_mic_shutter(int irq, void *data) 243 { 244 struct cs42l43_codec *priv = data; 245 static const char * const controls[] = { 246 "Decimator 1 Switch", 247 "Decimator 2 Switch", 248 "Decimator 3 Switch", 249 "Decimator 4 Switch", 250 }; 251 int i, ret; 252 253 dev_dbg(priv->dev, "Microphone shutter changed\n"); 254 255 if (!priv->component) 256 return IRQ_NONE; 257 258 for (i = 0; i < ARRAY_SIZE(controls); i++) { 259 ret = snd_soc_component_notify_control(priv->component, 260 controls[i]); 261 if (ret) 262 return IRQ_NONE; 263 } 264 265 return IRQ_HANDLED; 266 } 267 268 static irqreturn_t cs42l43_spk_shutter(int irq, void *data) 269 { 270 struct cs42l43_codec *priv = data; 271 int ret; 272 273 dev_dbg(priv->dev, "Speaker shutter changed\n"); 274 275 if (!priv->component) 276 return IRQ_NONE; 277 278 ret = snd_soc_component_notify_control(priv->component, 279 "Speaker Digital Switch"); 280 if (ret) 281 return IRQ_NONE; 282 283 return IRQ_HANDLED; 284 } 285 286 static const unsigned int cs42l43_sample_rates[] = { 287 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000, 288 }; 289 290 #define CS42L43_CONSUMER_RATE_MASK 0xFF 291 #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer 292 293 static const struct snd_pcm_hw_constraint_list cs42l43_constraint = { 294 .count = ARRAY_SIZE(cs42l43_sample_rates), 295 .list = cs42l43_sample_rates, 296 }; 297 298 static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 299 { 300 struct snd_soc_component *component = dai->component; 301 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 302 struct cs42l43 *cs42l43 = priv->core; 303 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 304 CS42L43_ASP_MASTER_MODE_MASK); 305 306 if (provider) 307 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK; 308 else 309 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; 310 311 return snd_pcm_hw_constraint_list(substream->runtime, 0, 312 SNDRV_PCM_HW_PARAM_RATE, 313 &priv->constraint); 314 } 315 316 static int cs42l43_convert_sample_rate(unsigned int rate) 317 { 318 switch (rate) { 319 case 8000: 320 return 0x11; 321 case 16000: 322 return 0x12; 323 case 24000: 324 return 0x02; 325 case 32000: 326 return 0x13; 327 case 44100: 328 return 0x0B; 329 case 48000: 330 return 0x03; 331 case 96000: 332 return 0x04; 333 case 192000: 334 return 0x05; 335 default: 336 return -EINVAL; 337 } 338 } 339 340 static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream, 341 struct snd_pcm_hw_params *params, 342 struct snd_soc_dai *dai) 343 { 344 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 345 struct cs42l43 *cs42l43 = priv->core; 346 int ret; 347 348 ret = cs42l43_convert_sample_rate(params_rate(params)); 349 if (ret < 0) { 350 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret); 351 return ret; 352 } 353 354 //FIXME: For now lets just set sample rate 1, this needs expanded in the future 355 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1, 356 CS42L43_SAMPLE_RATE_MASK, ret); 357 358 return 0; 359 } 360 361 static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream, 362 struct snd_pcm_hw_params *params, 363 struct snd_soc_dai *dai) 364 { 365 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); 366 struct cs42l43 *cs42l43 = priv->core; 367 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 368 CS42L43_ASP_FSYNC_MODE_MASK); 369 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 370 CS42L43_ASP_MASTER_MODE_MASK); 371 int n_chans = params_channels(params); 372 int data_width = params_width(params); 373 int n_slots = n_chans; 374 int slot_width = data_width; 375 int frame, bclk_target, i; 376 unsigned int reg; 377 int *slots; 378 379 if (priv->n_slots) { 380 n_slots = priv->n_slots; 381 slot_width = priv->slot_width; 382 } 383 384 if (!dsp_mode && (n_slots & 0x1)) { 385 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n"); 386 n_slots++; 387 } 388 389 frame = n_slots * slot_width; 390 bclk_target = params_rate(params) * frame; 391 392 if (provider) { 393 unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK); 394 int n = bclk_target / gcd_nm; 395 int m = CS42L43_INTERNAL_SYSCLK / gcd_nm; 396 397 if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) || 398 m > CS42L43_ASP_BCLK_M_MASK) { 399 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target); 400 return -EINVAL; 401 } 402 403 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n", 404 n, m, bclk_target, n_slots, slot_width); 405 406 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1, 407 CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK, 408 n << CS42L43_ASP_BCLK_N_SHIFT | 409 m << CS42L43_ASP_BCLK_M_SHIFT); 410 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1, 411 CS42L43_ASP_FSYNC_M_MASK, frame); 412 } 413 414 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4, 415 CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK, 416 frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT); 417 418 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 419 reg = CS42L43_ASP_TX_CH1_CTRL; 420 slots = priv->tx_slots; 421 } else { 422 reg = CS42L43_ASP_RX_CH1_CTRL; 423 slots = priv->rx_slots; 424 } 425 426 for (i = 0; i < n_chans; i++, reg += 4) { 427 int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK); 428 int slot_pos; 429 430 if (dsp_mode) 431 slot_pos = slots[i] * slot_width; 432 else 433 slot_pos = (slots[i] / 2) * slot_width; 434 435 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n", 436 i, slots[i], slot_pos, slot_phase); 437 438 regmap_update_bits(cs42l43->regmap, reg, 439 CS42L43_ASP_CH_WIDTH_MASK | 440 CS42L43_ASP_CH_SLOT_MASK | 441 CS42L43_ASP_CH_SLOT_PHASE_MASK, 442 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) | 443 (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) | 444 slot_phase); 445 } 446 447 return cs42l43_set_sample_rate(substream, params, dai); 448 } 449 450 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 451 { 452 struct snd_soc_component *component = dai->component; 453 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 454 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 455 struct cs42l43 *cs42l43 = priv->core; 456 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 457 CS42L43_ASP_MASTER_MODE_MASK); 458 struct snd_soc_dapm_route routes[] = { 459 { "BCLK", NULL, "FSYNC" }, 460 }; 461 unsigned int asp_ctrl = 0; 462 unsigned int data_ctrl = 0; 463 unsigned int fsync_ctrl = 0; 464 unsigned int clk_config = 0; 465 466 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 467 case SND_SOC_DAIFMT_DSP_A: 468 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 469 fallthrough; 470 case SND_SOC_DAIFMT_DSP_B: 471 asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK; 472 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 473 break; 474 case SND_SOC_DAIFMT_I2S: 475 data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; 476 break; 477 case SND_SOC_DAIFMT_LEFT_J: 478 data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; 479 break; 480 default: 481 dev_err(priv->dev, "Unsupported DAI format 0x%x\n", 482 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 483 return -EINVAL; 484 } 485 486 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 487 case SND_SOC_DAIFMT_CBC_CFC: 488 if (provider) 489 snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes)); 490 break; 491 case SND_SOC_DAIFMT_CBP_CFP: 492 if (!provider) 493 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); 494 clk_config |= CS42L43_ASP_MASTER_MODE_MASK; 495 break; 496 default: 497 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n", 498 fmt & SND_SOC_DAIFMT_MASTER_MASK); 499 return -EINVAL; 500 } 501 502 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 503 case SND_SOC_DAIFMT_NB_NF: 504 clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */ 505 break; 506 case SND_SOC_DAIFMT_IB_NF: 507 break; 508 case SND_SOC_DAIFMT_NB_IF: 509 clk_config |= CS42L43_ASP_BCLK_INV_MASK; 510 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 511 CS42L43_ASP_FSYNC_OUT_INV_MASK; 512 break; 513 case SND_SOC_DAIFMT_IB_IF: 514 fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | 515 CS42L43_ASP_FSYNC_OUT_INV_MASK; 516 break; 517 default: 518 dev_err(priv->dev, "Unsupported invert mode 0x%x\n", 519 fmt & SND_SOC_DAIFMT_INV_MASK); 520 return -EINVAL; 521 } 522 523 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL, 524 CS42L43_ASP_FSYNC_MODE_MASK, 525 asp_ctrl); 526 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL, 527 CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK | 528 CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK, 529 data_ctrl); 530 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, 531 CS42L43_ASP_MASTER_MODE_MASK | 532 CS42L43_ASP_BCLK_INV_MASK, 533 clk_config); 534 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3, 535 CS42L43_ASP_FSYNC_IN_INV_MASK | 536 CS42L43_ASP_FSYNC_OUT_INV_MASK, 537 fsync_ctrl); 538 539 return 0; 540 } 541 542 static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned int mask, int *slots) 543 { 544 int i; 545 546 for (i = 0; i < CS42L43_ASP_MAX_CHANNELS; ++i) { 547 int slot = ffs(mask) - 1; 548 549 if (slot < 0) 550 return; 551 552 slots[i] = slot; 553 554 mask &= ~(1 << slot); 555 } 556 557 if (mask) 558 dev_warn(priv->dev, "Too many channels in TDM mask\n"); 559 } 560 561 static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, 562 unsigned int rx_mask, int slots, int slot_width) 563 { 564 struct snd_soc_component *component = dai->component; 565 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 566 567 priv->n_slots = slots; 568 priv->slot_width = slot_width; 569 570 if (!slots) { 571 tx_mask = CS42L43_DEFAULT_SLOTS; 572 rx_mask = CS42L43_DEFAULT_SLOTS; 573 } 574 575 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots); 576 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots); 577 578 return 0; 579 } 580 581 static const struct snd_soc_dai_ops cs42l43_asp_ops = { 582 .startup = cs42l43_startup, 583 .hw_params = cs42l43_asp_hw_params, 584 .set_fmt = cs42l43_asp_set_fmt, 585 .set_tdm_slot = cs42l43_asp_set_tdm_slot, 586 }; 587 588 static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream, 589 struct snd_pcm_hw_params *params, 590 struct snd_soc_dai *dai) 591 { 592 int ret; 593 594 ret = cs42l43_sdw_add_peripheral(substream, params, dai); 595 if (ret) 596 return ret; 597 598 return cs42l43_set_sample_rate(substream, params, dai); 599 }; 600 601 static const struct snd_soc_dai_ops cs42l43_sdw_ops = { 602 .startup = cs42l43_startup, 603 .set_stream = cs42l43_sdw_set_stream, 604 .hw_params = cs42l43_sdw_hw_params, 605 .hw_free = cs42l43_sdw_remove_peripheral, 606 }; 607 608 #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ 609 SNDRV_PCM_FMTBIT_S32_LE) 610 #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 611 612 static struct snd_soc_dai_driver cs42l43_dais[] = { 613 { 614 .name = "cs42l43-asp", 615 .ops = &cs42l43_asp_ops, 616 .symmetric_rate = 1, 617 .capture = { 618 .stream_name = "ASP Capture", 619 .channels_min = 1, 620 .channels_max = CS42L43_ASP_MAX_CHANNELS, 621 .rates = SNDRV_PCM_RATE_KNOT, 622 .formats = CS42L43_ASP_FORMATS, 623 }, 624 .playback = { 625 .stream_name = "ASP Playback", 626 .channels_min = 1, 627 .channels_max = CS42L43_ASP_MAX_CHANNELS, 628 .rates = SNDRV_PCM_RATE_KNOT, 629 .formats = CS42L43_ASP_FORMATS, 630 }, 631 }, 632 { 633 .name = "cs42l43-dp1", 634 .id = 1, 635 .ops = &cs42l43_sdw_ops, 636 .capture = { 637 .stream_name = "DP1 Capture", 638 .channels_min = 1, 639 .channels_max = 4, 640 .rates = SNDRV_PCM_RATE_KNOT, 641 .formats = CS42L43_SDW_FORMATS, 642 }, 643 }, 644 { 645 .name = "cs42l43-dp2", 646 .id = 2, 647 .ops = &cs42l43_sdw_ops, 648 .capture = { 649 .stream_name = "DP2 Capture", 650 .channels_min = 1, 651 .channels_max = 2, 652 .rates = SNDRV_PCM_RATE_KNOT, 653 .formats = CS42L43_SDW_FORMATS, 654 }, 655 }, 656 { 657 .name = "cs42l43-dp3", 658 .id = 3, 659 .ops = &cs42l43_sdw_ops, 660 .capture = { 661 .stream_name = "DP3 Capture", 662 .channels_min = 1, 663 .channels_max = 2, 664 .rates = SNDRV_PCM_RATE_KNOT, 665 .formats = CS42L43_SDW_FORMATS, 666 }, 667 }, 668 { 669 .name = "cs42l43-dp4", 670 .id = 4, 671 .ops = &cs42l43_sdw_ops, 672 .capture = { 673 .stream_name = "DP4 Capture", 674 .channels_min = 1, 675 .channels_max = 2, 676 .rates = SNDRV_PCM_RATE_KNOT, 677 .formats = CS42L43_SDW_FORMATS, 678 }, 679 }, 680 { 681 .name = "cs42l43-dp5", 682 .id = 5, 683 .ops = &cs42l43_sdw_ops, 684 .playback = { 685 .stream_name = "DP5 Playback", 686 .channels_min = 1, 687 .channels_max = 2, 688 .rates = SNDRV_PCM_RATE_KNOT, 689 .formats = CS42L43_SDW_FORMATS, 690 }, 691 }, 692 { 693 .name = "cs42l43-dp6", 694 .id = 6, 695 .ops = &cs42l43_sdw_ops, 696 .playback = { 697 .stream_name = "DP6 Playback", 698 .channels_min = 1, 699 .channels_max = 2, 700 .rates = SNDRV_PCM_RATE_KNOT, 701 .formats = CS42L43_SDW_FORMATS, 702 }, 703 }, 704 { 705 .name = "cs42l43-dp7", 706 .id = 7, 707 .ops = &cs42l43_sdw_ops, 708 .playback = { 709 .stream_name = "DP7 Playback", 710 .channels_min = 1, 711 .channels_max = 2, 712 .rates = SNDRV_PCM_RATE_KNOT, 713 .formats = CS42L43_SDW_FORMATS, 714 }, 715 }, 716 }; 717 718 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0); 719 720 static const char * const cs42l43_ramp_text[] = { 721 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", 722 "15ms/6dB", "30ms/6dB", 723 }; 724 725 static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" }; 726 727 static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1, 728 CS42L43_ADC_AIN_SEL_SHIFT, 729 cs42l43_adc1_input_text); 730 731 static const struct snd_kcontrol_new cs42l43_adc1_input_ctl = 732 SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input); 733 734 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" }; 735 736 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text); 737 static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text); 738 739 static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = { 740 SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode), 741 SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode), 742 }; 743 744 static const char * const cs42l43_pdm_clk_text[] = { 745 "3.072MHz", "1.536MHz", "768kHz", 746 }; 747 748 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL, 749 CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 750 static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL, 751 CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); 752 753 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0); 754 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0); 755 756 static const char * const cs42l43_wnf_corner_text[] = { 757 "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", 758 }; 759 760 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 761 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 762 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 763 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 764 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 765 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 766 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 767 CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); 768 769 static const char * const cs42l43_hpf_corner_text[] = { 770 "3Hz", "12Hz", "48Hz", "96Hz", 771 }; 772 773 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, 774 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 775 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, 776 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 777 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, 778 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 779 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, 780 CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); 781 782 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 783 CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); 784 static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 785 CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); 786 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 787 CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); 788 static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, 789 CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); 790 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 791 CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); 792 static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 793 CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); 794 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 795 CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); 796 static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, 797 CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); 798 799 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); 800 801 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP, 802 CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text); 803 804 static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP, 805 CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text); 806 807 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1); 808 809 static const char * const cs42l43_headphone_ramp_text[] = { 810 "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44", 811 "48", "66", "72", 812 }; 813 814 static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL, 815 CS42L43_HP_PATH_VOL_RAMP_SHIFT, 816 cs42l43_headphone_ramp_text); 817 818 static const char * const cs42l43_tone_freq_text[] = { 819 "1kHz", "2kHz", "4kHz", "6kHz", "8kHz", 820 }; 821 822 static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL, 823 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 824 825 static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL, 826 CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); 827 828 static const char * const cs42l43_mixer_texts[] = { 829 "None", 830 "Tone Generator 1", "Tone Generator 2", 831 "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", 832 "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", 833 "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", 834 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", 835 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", 836 "ISRC1 INT1", "ISRC1 INT2", 837 "ISRC1 DEC1", "ISRC1 DEC2", 838 "ISRC2 INT1", "ISRC2 INT2", 839 "ISRC2 DEC1", "ISRC2 DEC2", 840 "EQ1", "EQ2", 841 }; 842 843 static const unsigned int cs42l43_mixer_values[] = { 844 0x00, // None 845 0x04, 0x05, // Tone Generator 1, 2 846 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4 847 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 848 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 849 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 850 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 851 0x50, 0x51, // ISRC1 INT1, 2 852 0x52, 0x53, // ISRC1 DEC1, 2 853 0x54, 0x55, // ISRC2 INT1, 2 854 0x56, 0x57, // ISRC2 DEC1, 2 855 0x58, 0x59, // EQ1, 2 856 }; 857 858 CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); 859 CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); 860 CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); 861 CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT); 862 CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT); 863 CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT); 864 865 CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); 866 CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); 867 CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); 868 CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); 869 CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); 870 CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); 871 CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); 872 CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); 873 CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); 874 CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); 875 876 CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1); 877 CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1); 878 CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1); 879 CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1); 880 CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1); 881 CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1); 882 CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1); 883 CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1); 884 885 CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1); 886 CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1); 887 CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); 888 CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); 889 CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1); 890 CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1); 891 CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); 892 CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); 893 894 CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1); 895 CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1); 896 897 CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1); 898 CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1); 899 900 CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1); 901 CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1); 902 903 CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); 904 CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); 905 906 static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, 907 struct snd_ctl_elem_value *ucontrol) 908 { 909 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 910 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 911 int ret; 912 913 snd_soc_dapm_mutex_lock(dapm); 914 ret = snd_soc_get_volsw(kcontrol, ucontrol); 915 snd_soc_dapm_mutex_unlock(dapm); 916 917 return ret; 918 } 919 920 static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol, 921 struct snd_ctl_elem_value *ucontrol) 922 { 923 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 924 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 925 int ret; 926 927 snd_soc_dapm_mutex_lock(dapm); 928 ret = snd_soc_put_volsw(kcontrol, ucontrol); 929 snd_soc_dapm_mutex_unlock(dapm); 930 931 return ret; 932 } 933 934 static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol, 935 struct snd_ctl_elem_value *ucontrol) 936 { 937 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 938 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 939 int ret; 940 941 snd_soc_dapm_mutex_lock(dapm); 942 ret = snd_soc_get_enum_double(kcontrol, ucontrol); 943 snd_soc_dapm_mutex_unlock(dapm); 944 945 return ret; 946 } 947 948 static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol, 949 struct snd_ctl_elem_value *ucontrol) 950 { 951 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 952 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 953 int ret; 954 955 snd_soc_dapm_mutex_lock(dapm); 956 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 957 snd_soc_dapm_mutex_unlock(dapm); 958 959 return ret; 960 } 961 962 static int cs42l43_eq_get(struct snd_kcontrol *kcontrol, 963 struct snd_ctl_elem_value *ucontrol) 964 { 965 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 966 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 967 968 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs)); 969 970 return 0; 971 } 972 973 static int cs42l43_eq_put(struct snd_kcontrol *kcontrol, 974 struct snd_ctl_elem_value *ucontrol) 975 { 976 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 977 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 978 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 979 980 snd_soc_dapm_mutex_lock(dapm); 981 982 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs)); 983 984 snd_soc_dapm_mutex_unlock(dapm); 985 986 return 0; 987 } 988 989 static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv) 990 { 991 struct cs42l43 *cs42l43 = priv->core; 992 993 mutex_lock(&priv->spk_vu_lock); 994 995 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 996 CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK); 997 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, 998 CS42L43_AMP1_2_VU_MASK, 0); 999 1000 mutex_unlock(&priv->spk_vu_lock); 1001 } 1002 1003 static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift) 1004 { 1005 struct cs42l43 *cs42l43 = priv->core; 1006 unsigned int val; 1007 int ret; 1008 1009 ret = pm_runtime_resume_and_get(priv->dev); 1010 if (ret) { 1011 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret); 1012 return ret; 1013 } 1014 1015 /* 1016 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must 1017 * be cached for the non-volatiles, so drop it from the cache here so 1018 * we force a read. 1019 */ 1020 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, 1021 CS42L43_SHUTTER_CONTROL); 1022 if (ret) { 1023 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret); 1024 goto error; 1025 } 1026 1027 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 1028 if (ret) { 1029 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret); 1030 goto error; 1031 } 1032 1033 ret = !(val & BIT(shift)); 1034 1035 dev_dbg(priv->dev, "%s shutter is %s\n", 1036 BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker", 1037 ret ? "open" : "closed"); 1038 1039 error: 1040 pm_runtime_mark_last_busy(priv->dev); 1041 pm_runtime_put_autosuspend(priv->dev); 1042 1043 return ret; 1044 } 1045 1046 static int cs42l43_decim_get(struct snd_kcontrol *kcontrol, 1047 struct snd_ctl_elem_value *ucontrol) 1048 { 1049 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1050 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1051 int ret; 1052 1053 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT); 1054 if (ret < 0) 1055 return ret; 1056 else if (!ret) 1057 ucontrol->value.integer.value[0] = ret; 1058 else 1059 ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol); 1060 1061 return ret; 1062 } 1063 1064 static int cs42l43_spk_get(struct snd_kcontrol *kcontrol, 1065 struct snd_ctl_elem_value *ucontrol) 1066 { 1067 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1068 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1069 int ret; 1070 1071 ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT); 1072 if (ret < 0) 1073 return ret; 1074 else if (!ret) 1075 ucontrol->value.integer.value[0] = ret; 1076 else 1077 ret = snd_soc_get_volsw(kcontrol, ucontrol); 1078 1079 return ret; 1080 } 1081 1082 static int cs42l43_spk_put(struct snd_kcontrol *kcontrol, 1083 struct snd_ctl_elem_value *ucontrol) 1084 { 1085 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1086 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1087 int ret; 1088 1089 ret = snd_soc_put_volsw(kcontrol, ucontrol); 1090 if (ret > 0) 1091 cs42l43_spk_vu_sync(priv); 1092 1093 return ret; 1094 } 1095 1096 static const struct snd_kcontrol_new cs42l43_controls[] = { 1097 SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum, 1098 cs42l43_jack_get, cs42l43_jack_put), 1099 1100 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2, 1101 CS42L43_ADC_PGA_GAIN_SHIFT, 1102 0xF, 5, cs42l43_adc_tlv), 1103 1104 SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1105 CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0), 1106 SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL, 1107 CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0), 1108 SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk), 1109 SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk), 1110 1111 SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1112 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1113 SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1114 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1115 SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1116 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1117 SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1118 CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), 1119 1120 SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner), 1121 SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner), 1122 SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner), 1123 SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner), 1124 1125 SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, 1126 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1127 SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, 1128 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1129 SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, 1130 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1131 SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, 1132 CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), 1133 1134 SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner), 1135 SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner), 1136 SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), 1137 SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), 1138 1139 SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1140 CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1141 SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1142 CS42L43_DECIM1_MUTE_SHIFT, 1, 1, 1143 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1144 SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1145 CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1146 SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, 1147 CS42L43_DECIM2_MUTE_SHIFT, 1, 1, 1148 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1149 SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1150 CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1151 SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1152 CS42L43_DECIM3_MUTE_SHIFT, 1, 1, 1153 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1154 SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1155 CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), 1156 SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, 1157 CS42L43_DECIM4_MUTE_SHIFT, 1, 1, 1158 cs42l43_decim_get, cs42l43_dapm_put_volsw), 1159 1160 SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, 1161 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1162 SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, 1163 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1164 SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, 1165 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1166 SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, 1167 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1168 SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, 1169 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1170 SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, 1171 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1172 SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, 1173 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1174 SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, 1175 cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), 1176 1177 SOC_DOUBLE_R_EXT("Speaker Digital Switch", 1178 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1179 CS42L43_AMP_MUTE_SHIFT, 1, 1, 1180 cs42l43_spk_get, cs42l43_spk_put), 1181 1182 SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume", 1183 CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, 1184 CS42L43_AMP_VOL_SHIFT, 1185 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put, 1186 cs42l43_speaker_tlv), 1187 1188 SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up), 1189 SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down), 1190 1191 CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1), 1192 CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1), 1193 1194 SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL, 1195 CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT, 1196 0x11B, 229, cs42l43_headphone_tlv), 1197 1198 SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1, 1199 CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0), 1200 1201 SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL, 1202 CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0), 1203 SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL, 1204 CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0), 1205 SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp), 1206 1207 CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1), 1208 CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1), 1209 1210 SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq), 1211 SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq), 1212 1213 SOC_DOUBLE_EXT("EQ Switch", 1214 CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT, 1215 CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1, 1216 cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw), 1217 1218 SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS, 1219 cs42l43_eq_get, cs42l43_eq_put), 1220 1221 CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1), 1222 CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1), 1223 }; 1224 1225 static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w, 1226 struct snd_kcontrol *kcontrol, int event) 1227 { 1228 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1229 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1230 struct cs42l43 *cs42l43 = priv->core; 1231 unsigned int val; 1232 int i, ret; 1233 1234 switch (event) { 1235 case SND_SOC_DAPM_PRE_PMU: 1236 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1237 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 1238 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK); 1239 1240 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1241 CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK); 1242 1243 for (i = 0; i < CS42L43_N_EQ_COEFFS; i++) 1244 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0, 1245 priv->eq_coeffs[i]); 1246 1247 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, 1248 CS42L43_WRITE_MODE_MASK, 0); 1249 1250 return 0; 1251 case SND_SOC_DAPM_POST_PMU: 1252 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0, 1253 val, (val & CS42L43_INITIALIZE_DONE_MASK), 1254 2000, 10000); 1255 if (ret) 1256 dev_err(priv->dev, "Failed to start EQs: %d\n", ret); 1257 1258 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, 1259 CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0); 1260 return ret; 1261 default: 1262 return 0; 1263 } 1264 } 1265 1266 struct cs42l43_pll_config { 1267 unsigned int freq; 1268 1269 unsigned int div; 1270 unsigned int mode; 1271 unsigned int cal; 1272 }; 1273 1274 static const struct cs42l43_pll_config cs42l43_pll_configs[] = { 1275 { 2400000, 0x50000000, 0x1, 0xA4 }, 1276 { 3000000, 0x40000000, 0x1, 0x83 }, 1277 { 3072000, 0x40000000, 0x3, 0x80 }, 1278 }; 1279 1280 static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src, 1281 unsigned int freq) 1282 { 1283 struct cs42l43 *cs42l43 = priv->core; 1284 1285 lockdep_assert_held(&cs42l43->pll_lock); 1286 1287 if (priv->refclk_src == src && priv->refclk_freq == freq) 1288 return 0; 1289 1290 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) { 1291 dev_err(priv->dev, "PLL active, can't change configuration\n"); 1292 return -EBUSY; 1293 } 1294 1295 switch (src) { 1296 case CS42L43_SYSCLK_MCLK: 1297 case CS42L43_SYSCLK_SDW: 1298 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n", 1299 src ? "SoundWire" : "MCLK", freq); 1300 1301 priv->refclk_src = src; 1302 priv->refclk_freq = freq; 1303 1304 return 0; 1305 default: 1306 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src); 1307 return -EINVAL; 1308 } 1309 } 1310 1311 static int cs42l43_enable_pll(struct cs42l43_codec *priv) 1312 { 1313 static const struct reg_sequence enable_seq[] = { 1314 { CS42L43_OSC_DIV_SEL, 0x0, }, 1315 { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, }, 1316 }; 1317 struct cs42l43 *cs42l43 = priv->core; 1318 const struct cs42l43_pll_config *config = NULL; 1319 unsigned int div = 0; 1320 unsigned int freq = priv->refclk_freq; 1321 unsigned long time_left; 1322 1323 lockdep_assert_held(&cs42l43->pll_lock); 1324 1325 if (priv->refclk_src == CS42L43_SYSCLK_SDW) { 1326 if (!freq) 1327 freq = cs42l43->sdw_freq; 1328 else if (!cs42l43->sdw_freq) 1329 cs42l43->sdw_freq = freq; 1330 } 1331 1332 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq); 1333 1334 while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) { 1335 div++; 1336 freq /= 2; 1337 } 1338 1339 if (div <= CS42L43_PLL_REFCLK_DIV_MASK) { 1340 int i; 1341 1342 for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) { 1343 if (freq == cs42l43_pll_configs[i].freq) { 1344 config = &cs42l43_pll_configs[i]; 1345 break; 1346 } 1347 } 1348 } 1349 1350 if (!config) { 1351 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq); 1352 return -EINVAL; 1353 } 1354 1355 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1356 CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK, 1357 div << CS42L43_PLL_REFCLK_DIV_SHIFT | 1358 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT); 1359 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div); 1360 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1361 CS42L43_PLL_MODE_BYPASS_500_MASK | 1362 CS42L43_PLL_MODE_BYPASS_1029_MASK, 1363 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT); 1364 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO, 1365 CS42L43_PLL_CAL_RATIO_MASK, config->cal); 1366 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1367 CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK); 1368 1369 reinit_completion(&priv->pll_ready); 1370 1371 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1372 CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK); 1373 1374 time_left = wait_for_completion_timeout(&priv->pll_ready, 1375 msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS)); 1376 if (!time_left) { 1377 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, 1378 CS42L43_PLL_EN_MASK, 0); 1379 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1380 CS42L43_PLL_REFCLK_EN_MASK, 0); 1381 1382 dev_err(priv->dev, "Timeout out waiting for PLL\n"); 1383 return -ETIMEDOUT; 1384 } 1385 1386 if (priv->refclk_src == CS42L43_SYSCLK_SDW) 1387 cs42l43->sdw_pll_active = true; 1388 1389 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left)); 1390 1391 /* 1392 * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL, 1393 * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole 1394 * change over happens under the regmap lock to prevent any reads. 1395 */ 1396 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq)); 1397 1398 return 0; 1399 } 1400 1401 static int cs42l43_disable_pll(struct cs42l43_codec *priv) 1402 { 1403 static const struct reg_sequence disable_seq[] = { 1404 { CS42L43_MCLK_SRC_SEL, 0x0, 5, }, 1405 { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, }, 1406 }; 1407 struct cs42l43 *cs42l43 = priv->core; 1408 1409 dev_dbg(priv->dev, "Disabling PLL\n"); 1410 1411 lockdep_assert_held(&cs42l43->pll_lock); 1412 1413 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq)); 1414 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0); 1415 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, 1416 CS42L43_PLL_REFCLK_EN_MASK, 0); 1417 1418 cs42l43->sdw_pll_active = false; 1419 1420 return 0; 1421 } 1422 1423 static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w, 1424 struct snd_kcontrol *kcontrol, int event) 1425 { 1426 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1427 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1428 struct cs42l43 *cs42l43 = priv->core; 1429 int ret; 1430 1431 mutex_lock(&cs42l43->pll_lock); 1432 1433 switch (event) { 1434 case SND_SOC_DAPM_PRE_PMU: 1435 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) { 1436 ret = clk_prepare_enable(priv->mclk); 1437 if (ret) { 1438 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret); 1439 break; 1440 } 1441 } 1442 1443 ret = cs42l43_enable_pll(priv); 1444 break; 1445 case SND_SOC_DAPM_POST_PMD: 1446 ret = cs42l43_disable_pll(priv); 1447 1448 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) 1449 clk_disable_unprepare(priv->mclk); 1450 break; 1451 default: 1452 ret = 0; 1453 break; 1454 } 1455 1456 mutex_unlock(&cs42l43->pll_lock); 1457 1458 return ret; 1459 } 1460 1461 static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd, 1462 int event, int timeout_ms) 1463 { 1464 unsigned long time_left; 1465 1466 switch (event) { 1467 case SND_SOC_DAPM_PRE_PMU: 1468 reinit_completion(pmu); 1469 return 0; 1470 case SND_SOC_DAPM_PRE_PMD: 1471 reinit_completion(pmd); 1472 return 0; 1473 case SND_SOC_DAPM_POST_PMU: 1474 time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms)); 1475 break; 1476 case SND_SOC_DAPM_POST_PMD: 1477 time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms)); 1478 break; 1479 default: 1480 return 0; 1481 } 1482 1483 if (!time_left) 1484 return -ETIMEDOUT; 1485 else 1486 return 0; 1487 } 1488 1489 static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w, 1490 struct snd_kcontrol *kcontrol, int event) 1491 { 1492 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1493 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1494 1495 return cs42l43_dapm_wait_completion(&priv->spkr_startup, 1496 &priv->spkr_shutdown, event, 1497 CS42L43_SPK_TIMEOUT_MS); 1498 } 1499 1500 static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w, 1501 struct snd_kcontrol *kcontrol, int event) 1502 { 1503 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1504 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1505 1506 return cs42l43_dapm_wait_completion(&priv->spkl_startup, 1507 &priv->spkl_shutdown, event, 1508 CS42L43_SPK_TIMEOUT_MS); 1509 } 1510 1511 static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w, 1512 struct snd_kcontrol *kcontrol, int event) 1513 { 1514 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1515 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1516 struct cs42l43 *cs42l43 = priv->core; 1517 unsigned int mask = 1 << w->shift; 1518 unsigned int val = 0; 1519 int ret; 1520 1521 switch (event) { 1522 case SND_SOC_DAPM_PRE_PMU: 1523 val = mask; 1524 fallthrough; 1525 case SND_SOC_DAPM_PRE_PMD: 1526 priv->hp_ena &= ~mask; 1527 priv->hp_ena |= val; 1528 1529 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1530 &priv->hp_shutdown, event, 1531 CS42L43_HP_TIMEOUT_MS); 1532 if (ret) 1533 return ret; 1534 1535 if (!priv->load_detect_running && !priv->hp_ilimited) 1536 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, 1537 mask, val); 1538 break; 1539 case SND_SOC_DAPM_POST_PMU: 1540 case SND_SOC_DAPM_POST_PMD: 1541 if (priv->load_detect_running || priv->hp_ilimited) 1542 break; 1543 1544 ret = cs42l43_dapm_wait_completion(&priv->hp_startup, 1545 &priv->hp_shutdown, event, 1546 CS42L43_HP_TIMEOUT_MS); 1547 if (ret) 1548 return ret; 1549 break; 1550 default: 1551 break; 1552 } 1553 1554 return 0; 1555 } 1556 1557 static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w, 1558 struct snd_kcontrol *kcontrol, int event) 1559 { 1560 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1561 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1562 struct cs42l43 *cs42l43 = priv->core; 1563 unsigned int reg, ramp, mute; 1564 unsigned int *val; 1565 int ret; 1566 1567 switch (w->shift) { 1568 case CS42L43_ADC1_EN_SHIFT: 1569 case CS42L43_PDM1_DIN_L_EN_SHIFT: 1570 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1571 ramp = CS42L43_DECIM1_VD_RAMP_MASK; 1572 mute = CS42L43_DECIM1_MUTE_MASK; 1573 val = &priv->decim_cache[0]; 1574 break; 1575 case CS42L43_ADC2_EN_SHIFT: 1576 case CS42L43_PDM1_DIN_R_EN_SHIFT: 1577 reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; 1578 ramp = CS42L43_DECIM2_VD_RAMP_MASK; 1579 mute = CS42L43_DECIM2_MUTE_MASK; 1580 val = &priv->decim_cache[1]; 1581 break; 1582 case CS42L43_PDM2_DIN_L_EN_SHIFT: 1583 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1584 ramp = CS42L43_DECIM3_VD_RAMP_MASK; 1585 mute = CS42L43_DECIM3_MUTE_MASK; 1586 val = &priv->decim_cache[2]; 1587 break; 1588 case CS42L43_PDM2_DIN_R_EN_SHIFT: 1589 reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; 1590 ramp = CS42L43_DECIM4_VD_RAMP_MASK; 1591 mute = CS42L43_DECIM4_MUTE_MASK; 1592 val = &priv->decim_cache[3]; 1593 break; 1594 default: 1595 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); 1596 return -EINVAL; 1597 } 1598 1599 switch (event) { 1600 case SND_SOC_DAPM_PRE_PMU: 1601 ret = regmap_read(cs42l43->regmap, reg, val); 1602 if (ret) { 1603 dev_err(priv->dev, 1604 "Failed to cache decimator settings: %d\n", 1605 ret); 1606 return ret; 1607 } 1608 1609 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute); 1610 break; 1611 case SND_SOC_DAPM_POST_PMU: 1612 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val); 1613 break; 1614 default: 1615 break; 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w, 1622 struct snd_kcontrol *kcontrol, int event) 1623 { 1624 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1625 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 1626 struct cs42l43 *cs42l43 = priv->core; 1627 unsigned int mask = 1 << w->shift; 1628 unsigned int val = 0; 1629 int ret; 1630 1631 ret = cs42l43_mic_ev(w, kcontrol, event); 1632 if (ret) 1633 return ret; 1634 1635 switch (event) { 1636 case SND_SOC_DAPM_PRE_PMU: 1637 val = mask; 1638 fallthrough; 1639 case SND_SOC_DAPM_PRE_PMD: 1640 priv->adc_ena &= ~mask; 1641 priv->adc_ena |= val; 1642 1643 if (!priv->load_detect_running) 1644 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3, 1645 mask, val); 1646 fallthrough; 1647 default: 1648 return 0; 1649 } 1650 } 1651 1652 static const struct snd_soc_dapm_widget cs42l43_widgets[] = { 1653 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev, 1654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1655 1656 SND_SOC_DAPM_INPUT("ADC1_IN1_P"), 1657 SND_SOC_DAPM_INPUT("ADC1_IN1_N"), 1658 SND_SOC_DAPM_INPUT("ADC1_IN2_P"), 1659 SND_SOC_DAPM_INPUT("ADC1_IN2_N"), 1660 SND_SOC_DAPM_INPUT("ADC2_IN_P"), 1661 SND_SOC_DAPM_INPUT("ADC2_IN_N"), 1662 1663 SND_SOC_DAPM_INPUT("PDM1_DIN"), 1664 SND_SOC_DAPM_INPUT("PDM2_DIN"), 1665 1666 SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl), 1667 1668 SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0, 1669 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1670 SND_SOC_DAPM_PRE_PMD), 1671 SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0, 1672 cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1673 SND_SOC_DAPM_PRE_PMD), 1674 1675 SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT, 1676 0, NULL, 0, cs42l43_mic_ev, 1677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1678 SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT, 1679 0, NULL, 0, cs42l43_mic_ev, 1680 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1681 SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT, 1682 0, NULL, 0, cs42l43_mic_ev, 1683 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1684 SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT, 1685 0, NULL, 0, cs42l43_mic_ev, 1686 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1687 1688 SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, 1689 &cs42l43_dec_mode_ctl[0]), 1690 SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, 1691 &cs42l43_dec_mode_ctl[1]), 1692 1693 SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), 1694 SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), 1695 SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0), 1696 SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0), 1697 1698 SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT, 1699 0, NULL, 0), 1700 SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT, 1701 0, NULL, 0), 1702 1703 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, 1704 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0), 1705 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, 1706 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0), 1707 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, 1708 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0), 1709 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, 1710 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0), 1711 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, 1712 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0), 1713 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, 1714 CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0), 1715 1716 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, 1717 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0), 1718 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1, 1719 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0), 1720 SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2, 1721 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0), 1722 SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3, 1723 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0), 1724 SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4, 1725 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0), 1726 SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5, 1727 CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0), 1728 1729 SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1730 SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1731 SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0), 1732 SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0), 1733 1734 SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1735 SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1736 1737 SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1738 SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1739 1740 SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1741 SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1742 1743 SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1744 SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1745 1746 SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1747 SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1748 1749 SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 1750 SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0), 1751 1752 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0), 1753 1754 SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0, 1755 cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1756 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1757 SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0, 1758 cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1759 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1760 1761 SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"), 1762 SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"), 1763 SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"), 1764 SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"), 1765 1766 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT, 1767 0, NULL, 0), 1768 SND_SOC_DAPM_OUTPUT("SPDIF_TX"), 1769 1770 SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0, 1771 cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1772 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1773 SND_SOC_DAPM_OUTPUT("AMP3_OUT"), 1774 SND_SOC_DAPM_OUTPUT("AMP4_OUT"), 1775 1776 SND_SOC_DAPM_SIGGEN("Tone"), 1777 SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT, 1778 0, NULL, 0), 1779 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL, 1780 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1781 SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL, 1782 CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), 1783 1784 SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT, 1785 0, NULL, 0), 1786 SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT, 1787 0, NULL, 0), 1788 1789 SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL, 1790 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 1791 SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL, 1792 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 1793 SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL, 1794 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 1795 SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL, 1796 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 1797 1798 SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL, 1799 CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), 1800 SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL, 1801 CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), 1802 SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL, 1803 CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), 1804 SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL, 1805 CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), 1806 1807 SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4, 1808 CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0), 1809 SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4, 1810 CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0), 1811 1812 SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES, 1813 CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0), 1814 SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES, 1815 CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0), 1816 SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES, 1817 CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0), 1818 SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES, 1819 CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0), 1820 SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES, 1821 CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0), 1822 SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES, 1823 CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0), 1824 SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES, 1825 CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0), 1826 SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES, 1827 CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0), 1828 1829 SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT, 1830 0, NULL, 0), 1831 SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT, 1832 0, NULL, 0, cs42l43_eq_ev, 1833 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), 1834 1835 SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, 1836 0, NULL, 0), 1837 CS42L43_DAPM_MUX("ASPTX1", asptx1), 1838 CS42L43_DAPM_MUX("ASPTX2", asptx2), 1839 CS42L43_DAPM_MUX("ASPTX3", asptx3), 1840 CS42L43_DAPM_MUX("ASPTX4", asptx4), 1841 CS42L43_DAPM_MUX("ASPTX5", asptx5), 1842 CS42L43_DAPM_MUX("ASPTX6", asptx6), 1843 1844 CS42L43_DAPM_MUX("DP1TX1", dp1tx1), 1845 CS42L43_DAPM_MUX("DP1TX2", dp1tx2), 1846 CS42L43_DAPM_MUX("DP1TX3", dp1tx3), 1847 CS42L43_DAPM_MUX("DP1TX4", dp1tx4), 1848 CS42L43_DAPM_MUX("DP2TX1", dp2tx1), 1849 CS42L43_DAPM_MUX("DP2TX2", dp2tx2), 1850 CS42L43_DAPM_MUX("DP3TX1", dp3tx1), 1851 CS42L43_DAPM_MUX("DP3TX2", dp3tx2), 1852 CS42L43_DAPM_MUX("DP4TX1", dp4tx1), 1853 CS42L43_DAPM_MUX("DP4TX2", dp4tx2), 1854 1855 CS42L43_DAPM_MUX("ASRC INT1", asrcint1), 1856 CS42L43_DAPM_MUX("ASRC INT2", asrcint2), 1857 CS42L43_DAPM_MUX("ASRC INT3", asrcint3), 1858 CS42L43_DAPM_MUX("ASRC INT4", asrcint4), 1859 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), 1860 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), 1861 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), 1862 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), 1863 1864 CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), 1865 CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), 1866 CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), 1867 CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), 1868 CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), 1869 CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), 1870 CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), 1871 CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), 1872 1873 CS42L43_DAPM_MUX("SPDIF1", spdif1), 1874 CS42L43_DAPM_MUX("SPDIF2", spdif2), 1875 1876 CS42L43_DAPM_MIXER("EQ1", eq1), 1877 CS42L43_DAPM_MIXER("EQ2", eq2), 1878 1879 CS42L43_DAPM_MIXER("Speaker L", amp1), 1880 CS42L43_DAPM_MIXER("Speaker R", amp2), 1881 1882 CS42L43_DAPM_MIXER("Headphone L", amp3), 1883 CS42L43_DAPM_MIXER("Headphone R", amp4), 1884 }; 1885 1886 static const struct snd_soc_dapm_route cs42l43_routes[] = { 1887 { "ADC1_IN1_P", NULL, "PLL" }, 1888 { "ADC1_IN1_N", NULL, "PLL" }, 1889 { "ADC1_IN2_P", NULL, "PLL" }, 1890 { "ADC1_IN2_N", NULL, "PLL" }, 1891 { "ADC2_IN_P", NULL, "PLL" }, 1892 { "ADC2_IN_N", NULL, "PLL" }, 1893 { "PDM1_DIN", NULL, "PLL" }, 1894 { "PDM2_DIN", NULL, "PLL" }, 1895 { "AMP1_OUT_P", NULL, "PLL" }, 1896 { "AMP1_OUT_N", NULL, "PLL" }, 1897 { "AMP2_OUT_P", NULL, "PLL" }, 1898 { "AMP2_OUT_N", NULL, "PLL" }, 1899 { "SPDIF_TX", NULL, "PLL" }, 1900 { "HP", NULL, "PLL" }, 1901 { "AMP3_OUT", NULL, "PLL" }, 1902 { "AMP4_OUT", NULL, "PLL" }, 1903 { "Tone 1", NULL, "PLL" }, 1904 { "Tone 2", NULL, "PLL" }, 1905 { "ASP Playback", NULL, "PLL" }, 1906 { "ASP Capture", NULL, "PLL" }, 1907 { "DP1 Capture", NULL, "PLL" }, 1908 { "DP2 Capture", NULL, "PLL" }, 1909 { "DP3 Capture", NULL, "PLL" }, 1910 { "DP4 Capture", NULL, "PLL" }, 1911 { "DP5 Playback", NULL, "PLL" }, 1912 { "DP6 Playback", NULL, "PLL" }, 1913 { "DP7 Playback", NULL, "PLL" }, 1914 1915 { "ADC1 Input", "IN1", "ADC1_IN1_P" }, 1916 { "ADC1 Input", "IN1", "ADC1_IN1_N" }, 1917 { "ADC1 Input", "IN2", "ADC1_IN2_P" }, 1918 { "ADC1 Input", "IN2", "ADC1_IN2_N" }, 1919 1920 { "ADC1", NULL, "ADC1 Input" }, 1921 { "ADC2", NULL, "ADC2_IN_P" }, 1922 { "ADC2", NULL, "ADC2_IN_N" }, 1923 1924 { "PDM1L", NULL, "PDM1_DIN" }, 1925 { "PDM1R", NULL, "PDM1_DIN" }, 1926 { "PDM2L", NULL, "PDM2_DIN" }, 1927 { "PDM2R", NULL, "PDM2_DIN" }, 1928 1929 { "Decimator 1 Mode", "PDM", "PDM1L" }, 1930 { "Decimator 1 Mode", "ADC", "ADC1" }, 1931 { "Decimator 2 Mode", "PDM", "PDM1R" }, 1932 { "Decimator 2 Mode", "ADC", "ADC2" }, 1933 1934 { "Decimator 1", NULL, "Decimator 1 Mode" }, 1935 { "Decimator 2", NULL, "Decimator 2 Mode" }, 1936 { "Decimator 3", NULL, "PDM2L" }, 1937 { "Decimator 4", NULL, "PDM2R" }, 1938 1939 { "ASP Capture", NULL, "ASPTX1" }, 1940 { "ASP Capture", NULL, "ASPTX2" }, 1941 { "ASP Capture", NULL, "ASPTX3" }, 1942 { "ASP Capture", NULL, "ASPTX4" }, 1943 { "ASP Capture", NULL, "ASPTX5" }, 1944 { "ASP Capture", NULL, "ASPTX6" }, 1945 { "ASPTX1", NULL, "BCLK" }, 1946 { "ASPTX2", NULL, "BCLK" }, 1947 { "ASPTX3", NULL, "BCLK" }, 1948 { "ASPTX4", NULL, "BCLK" }, 1949 { "ASPTX5", NULL, "BCLK" }, 1950 { "ASPTX6", NULL, "BCLK" }, 1951 1952 { "ASPRX1", NULL, "ASP Playback" }, 1953 { "ASPRX2", NULL, "ASP Playback" }, 1954 { "ASPRX3", NULL, "ASP Playback" }, 1955 { "ASPRX4", NULL, "ASP Playback" }, 1956 { "ASPRX5", NULL, "ASP Playback" }, 1957 { "ASPRX6", NULL, "ASP Playback" }, 1958 { "ASPRX1", NULL, "BCLK" }, 1959 { "ASPRX2", NULL, "BCLK" }, 1960 { "ASPRX3", NULL, "BCLK" }, 1961 { "ASPRX4", NULL, "BCLK" }, 1962 { "ASPRX5", NULL, "BCLK" }, 1963 { "ASPRX6", NULL, "BCLK" }, 1964 1965 { "DP1 Capture", NULL, "DP1TX1" }, 1966 { "DP1 Capture", NULL, "DP1TX2" }, 1967 { "DP1 Capture", NULL, "DP1TX3" }, 1968 { "DP1 Capture", NULL, "DP1TX4" }, 1969 1970 { "DP2 Capture", NULL, "DP2TX1" }, 1971 { "DP2 Capture", NULL, "DP2TX2" }, 1972 1973 { "DP3 Capture", NULL, "DP3TX1" }, 1974 { "DP3 Capture", NULL, "DP3TX2" }, 1975 1976 { "DP4 Capture", NULL, "DP4TX1" }, 1977 { "DP4 Capture", NULL, "DP4TX2" }, 1978 1979 { "DP5RX1", NULL, "DP5 Playback" }, 1980 { "DP5RX2", NULL, "DP5 Playback" }, 1981 1982 { "DP6RX1", NULL, "DP6 Playback" }, 1983 { "DP6RX2", NULL, "DP6 Playback" }, 1984 1985 { "DP7RX1", NULL, "DP7 Playback" }, 1986 { "DP7RX2", NULL, "DP7 Playback" }, 1987 1988 { "AMP1", NULL, "vdd-amp" }, 1989 { "AMP2", NULL, "vdd-amp" }, 1990 1991 { "AMP1_OUT_P", NULL, "AMP1" }, 1992 { "AMP1_OUT_N", NULL, "AMP1" }, 1993 { "AMP2_OUT_P", NULL, "AMP2" }, 1994 { "AMP2_OUT_N", NULL, "AMP2" }, 1995 1996 { "SPDIF_TX", NULL, "SPDIF" }, 1997 1998 { "AMP3_OUT", NULL, "HP" }, 1999 { "AMP4_OUT", NULL, "HP" }, 2000 2001 { "Tone 1", NULL, "Tone" }, 2002 { "Tone 1", NULL, "Tone Generator" }, 2003 { "Tone 2", NULL, "Tone" }, 2004 { "Tone 2", NULL, "Tone Generator" }, 2005 2006 { "ISRC1INT2", NULL, "ISRC1" }, 2007 { "ISRC1INT1", NULL, "ISRC1" }, 2008 { "ISRC1DEC2", NULL, "ISRC1" }, 2009 { "ISRC1DEC1", NULL, "ISRC1" }, 2010 2011 { "ISRC2INT2", NULL, "ISRC2" }, 2012 { "ISRC2INT1", NULL, "ISRC2" }, 2013 { "ISRC2DEC2", NULL, "ISRC2" }, 2014 { "ISRC2DEC1", NULL, "ISRC2" }, 2015 2016 { "ASRC_INT1", NULL, "ASRC_INT" }, 2017 { "ASRC_INT2", NULL, "ASRC_INT" }, 2018 { "ASRC_INT3", NULL, "ASRC_INT" }, 2019 { "ASRC_INT4", NULL, "ASRC_INT" }, 2020 { "ASRC_DEC1", NULL, "ASRC_DEC" }, 2021 { "ASRC_DEC2", NULL, "ASRC_DEC" }, 2022 { "ASRC_DEC3", NULL, "ASRC_DEC" }, 2023 { "ASRC_DEC4", NULL, "ASRC_DEC" }, 2024 2025 { "EQ", NULL, "EQ Clock" }, 2026 2027 CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), 2028 CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), 2029 CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"), 2030 CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"), 2031 CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"), 2032 CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"), 2033 2034 CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"), 2035 CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"), 2036 CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"), 2037 CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"), 2038 CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"), 2039 CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"), 2040 CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"), 2041 CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"), 2042 CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"), 2043 CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"), 2044 2045 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), 2046 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), 2047 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), 2048 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), 2049 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), 2050 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), 2051 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), 2052 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), 2053 2054 CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), 2055 CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), 2056 CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), 2057 CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), 2058 CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), 2059 CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), 2060 CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), 2061 CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), 2062 2063 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"), 2064 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"), 2065 2066 CS42L43_MIXER_ROUTES("EQ1", "EQ"), 2067 CS42L43_MIXER_ROUTES("EQ2", "EQ"), 2068 2069 CS42L43_MIXER_ROUTES("Speaker L", "AMP1"), 2070 CS42L43_MIXER_ROUTES("Speaker R", "AMP2"), 2071 2072 CS42L43_MIXER_ROUTES("Headphone L", "HP"), 2073 CS42L43_MIXER_ROUTES("Headphone R", "HP"), 2074 }; 2075 2076 static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, 2077 int src, unsigned int freq, int dir) 2078 { 2079 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2080 struct cs42l43 *cs42l43 = priv->core; 2081 int ret; 2082 2083 mutex_lock(&cs42l43->pll_lock); 2084 ret = cs42l43_set_pll(priv, src, freq); 2085 mutex_unlock(&cs42l43->pll_lock); 2086 2087 return ret; 2088 } 2089 2090 static int cs42l43_component_probe(struct snd_soc_component *component) 2091 { 2092 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); 2093 struct cs42l43 *cs42l43 = priv->core; 2094 2095 snd_soc_component_init_regmap(component, cs42l43->regmap); 2096 2097 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots); 2098 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots); 2099 2100 priv->component = component; 2101 priv->constraint = cs42l43_constraint; 2102 2103 return 0; 2104 } 2105 2106 static const struct snd_soc_component_driver cs42l43_component_drv = { 2107 .name = "cs42l43-codec", 2108 2109 .probe = cs42l43_component_probe, 2110 .set_sysclk = cs42l43_set_sysclk, 2111 .set_jack = cs42l43_set_jack, 2112 2113 .endianness = 1, 2114 2115 .controls = cs42l43_controls, 2116 .num_controls = ARRAY_SIZE(cs42l43_controls), 2117 .dapm_widgets = cs42l43_widgets, 2118 .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets), 2119 .dapm_routes = cs42l43_routes, 2120 .num_dapm_routes = ARRAY_SIZE(cs42l43_routes), 2121 }; 2122 2123 struct cs42l43_irq { 2124 unsigned int irq; 2125 const char *name; 2126 irq_handler_t handler; 2127 }; 2128 2129 static const struct cs42l43_irq cs42l43_irqs[] = { 2130 { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock }, 2131 { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready }, 2132 { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup }, 2133 { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown }, 2134 { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect }, 2135 { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense }, 2136 { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense }, 2137 { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press }, 2138 { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release }, 2139 { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp }, 2140 { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop }, 2141 { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop }, 2142 { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out }, 2143 { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out }, 2144 { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown }, 2145 { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown }, 2146 { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup }, 2147 { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup }, 2148 { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown }, 2149 { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown }, 2150 { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm }, 2151 { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm }, 2152 { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect }, 2153 { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect }, 2154 { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit }, 2155 { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect }, 2156 }; 2157 2158 static int cs42l43_request_irq(struct cs42l43_codec *priv, 2159 struct irq_domain *dom, const char * const name, 2160 unsigned int irq, irq_handler_t handler, 2161 unsigned long flags) 2162 { 2163 int ret; 2164 2165 ret = irq_create_mapping(dom, irq); 2166 if (ret < 0) 2167 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name); 2168 2169 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name); 2170 2171 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler, 2172 IRQF_ONESHOT | flags, name, priv); 2173 if (ret) 2174 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name); 2175 2176 return 0; 2177 } 2178 2179 static int cs42l43_shutter_irq(struct cs42l43_codec *priv, 2180 struct irq_domain *dom, unsigned int shutter, 2181 const char * const open_name, 2182 const char * const close_name, 2183 irq_handler_t handler) 2184 { 2185 unsigned int open_irq, close_irq; 2186 int ret; 2187 2188 switch (shutter) { 2189 case 0x1: 2190 dev_warn(priv->dev, "Manual shutters, notifications not available\n"); 2191 return 0; 2192 case 0x2: 2193 open_irq = CS42L43_GPIO1_RISE; 2194 close_irq = CS42L43_GPIO1_FALL; 2195 break; 2196 case 0x4: 2197 open_irq = CS42L43_GPIO2_RISE; 2198 close_irq = CS42L43_GPIO2_FALL; 2199 break; 2200 case 0x8: 2201 open_irq = CS42L43_GPIO3_RISE; 2202 close_irq = CS42L43_GPIO3_FALL; 2203 break; 2204 default: 2205 return 0; 2206 } 2207 2208 ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler, IRQF_SHARED); 2209 if (ret) 2210 return ret; 2211 2212 return cs42l43_request_irq(priv, dom, open_name, open_irq, handler, IRQF_SHARED); 2213 } 2214 2215 static int cs42l43_codec_probe(struct platform_device *pdev) 2216 { 2217 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); 2218 struct cs42l43_codec *priv; 2219 struct irq_domain *dom; 2220 unsigned int val; 2221 int i, ret; 2222 2223 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY); 2224 if (!dom) 2225 return -EPROBE_DEFER; 2226 2227 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2228 if (!priv) 2229 return -ENOMEM; 2230 2231 priv->dev = &pdev->dev; 2232 priv->core = cs42l43; 2233 2234 platform_set_drvdata(pdev, priv); 2235 2236 mutex_init(&priv->jack_lock); 2237 mutex_init(&priv->spk_vu_lock); 2238 2239 init_completion(&priv->hp_startup); 2240 init_completion(&priv->hp_shutdown); 2241 init_completion(&priv->spkr_shutdown); 2242 init_completion(&priv->spkl_shutdown); 2243 init_completion(&priv->spkr_startup); 2244 init_completion(&priv->spkl_startup); 2245 init_completion(&priv->pll_ready); 2246 init_completion(&priv->type_detect); 2247 init_completion(&priv->load_detect); 2248 2249 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work); 2250 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout); 2251 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work); 2252 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work); 2253 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work); 2254 INIT_WORK(&priv->hp_ilimit_work, cs42l43_hp_ilimit_work); 2255 2256 pm_runtime_set_autosuspend_delay(priv->dev, 100); 2257 pm_runtime_use_autosuspend(priv->dev); 2258 pm_runtime_set_active(priv->dev); 2259 pm_runtime_get_noresume(priv->dev); 2260 2261 ret = devm_pm_runtime_enable(priv->dev); 2262 if (ret) 2263 goto err_pm; 2264 2265 for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) { 2266 ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name, 2267 cs42l43_irqs[i].irq, 2268 cs42l43_irqs[i].handler, 0); 2269 if (ret) 2270 goto err_pm; 2271 } 2272 2273 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); 2274 if (ret) { 2275 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret); 2276 goto err_pm; 2277 } 2278 2279 ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK, 2280 "mic shutter open", "mic shutter close", 2281 cs42l43_mic_shutter); 2282 if (ret) 2283 goto err_pm; 2284 2285 ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >> 2286 CS42L43_SPK_SHUTTER_CFG_SHIFT, 2287 "spk shutter open", "spk shutter close", 2288 cs42l43_spk_shutter); 2289 if (ret) 2290 goto err_pm; 2291 2292 // Don't use devm as we need to get against the MFD device 2293 priv->mclk = clk_get_optional(cs42l43->dev, "mclk"); 2294 if (IS_ERR(priv->mclk)) { 2295 ret = PTR_ERR(priv->mclk); 2296 dev_err_probe(priv->dev, ret, "Failed to get mclk\n"); 2297 goto err_pm; 2298 } 2299 2300 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv, 2301 cs42l43_dais, ARRAY_SIZE(cs42l43_dais)); 2302 if (ret) { 2303 dev_err_probe(priv->dev, ret, "Failed to register component\n"); 2304 goto err_clk; 2305 } 2306 2307 pm_runtime_mark_last_busy(priv->dev); 2308 pm_runtime_put_autosuspend(priv->dev); 2309 2310 return 0; 2311 2312 err_clk: 2313 clk_put(priv->mclk); 2314 err_pm: 2315 pm_runtime_put_sync(priv->dev); 2316 2317 return ret; 2318 } 2319 2320 static void cs42l43_codec_remove(struct platform_device *pdev) 2321 { 2322 struct cs42l43_codec *priv = platform_get_drvdata(pdev); 2323 2324 clk_put(priv->mclk); 2325 } 2326 2327 static int cs42l43_codec_runtime_resume(struct device *dev) 2328 { 2329 struct cs42l43_codec *priv = dev_get_drvdata(dev); 2330 2331 dev_dbg(priv->dev, "Runtime resume\n"); 2332 2333 // Toggle the speaker volume update incase the speaker volume was synced 2334 cs42l43_spk_vu_sync(priv); 2335 2336 return 0; 2337 } 2338 2339 static int cs42l43_codec_suspend(struct device *dev) 2340 { 2341 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 2342 2343 disable_irq(cs42l43->irq); 2344 2345 return 0; 2346 } 2347 2348 static int cs42l43_codec_suspend_noirq(struct device *dev) 2349 { 2350 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 2351 2352 enable_irq(cs42l43->irq); 2353 2354 return 0; 2355 } 2356 2357 static int cs42l43_codec_resume(struct device *dev) 2358 { 2359 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 2360 2361 enable_irq(cs42l43->irq); 2362 2363 return 0; 2364 } 2365 2366 static int cs42l43_codec_resume_noirq(struct device *dev) 2367 { 2368 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 2369 2370 disable_irq(cs42l43->irq); 2371 2372 return 0; 2373 } 2374 2375 static const struct dev_pm_ops cs42l43_codec_pm_ops = { 2376 SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend, cs42l43_codec_resume) 2377 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_codec_suspend_noirq, cs42l43_codec_resume_noirq) 2378 RUNTIME_PM_OPS(NULL, cs42l43_codec_runtime_resume, NULL) 2379 }; 2380 2381 static const struct platform_device_id cs42l43_codec_id_table[] = { 2382 { "cs42l43-codec", }, 2383 {} 2384 }; 2385 MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table); 2386 2387 static struct platform_driver cs42l43_codec_driver = { 2388 .driver = { 2389 .name = "cs42l43-codec", 2390 .pm = &cs42l43_codec_pm_ops, 2391 }, 2392 2393 .probe = cs42l43_codec_probe, 2394 .remove_new = cs42l43_codec_remove, 2395 .id_table = cs42l43_codec_id_table, 2396 }; 2397 module_platform_driver(cs42l43_codec_driver); 2398 2399 MODULE_IMPORT_NS(SND_SOC_CS42L43); 2400 2401 MODULE_DESCRIPTION("CS42L43 CODEC Driver"); 2402 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); 2403 MODULE_LICENSE("GPL"); 2404