1620e1902SWu Hao /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2620e1902SWu Hao /* 3620e1902SWu Hao * Header File for FPGA DFL User API 4620e1902SWu Hao * 5620e1902SWu Hao * Copyright (C) 2017-2018 Intel Corporation, Inc. 6620e1902SWu Hao * 7620e1902SWu Hao * Authors: 8620e1902SWu Hao * Kang Luwei <luwei.kang@intel.com> 9620e1902SWu Hao * Zhang Yi <yi.z.zhang@intel.com> 10620e1902SWu Hao * Wu Hao <hao.wu@intel.com> 11620e1902SWu Hao * Xiao Guangrong <guangrong.xiao@linux.intel.com> 12620e1902SWu Hao */ 13620e1902SWu Hao 14620e1902SWu Hao #ifndef _UAPI_LINUX_FPGA_DFL_H 15620e1902SWu Hao #define _UAPI_LINUX_FPGA_DFL_H 16620e1902SWu Hao 1729de7624SKang Luwei #include <linux/types.h> 18620e1902SWu Hao #include <linux/ioctl.h> 19620e1902SWu Hao 20620e1902SWu Hao #define DFL_FPGA_API_VERSION 0 21620e1902SWu Hao 22620e1902SWu Hao /* 23620e1902SWu Hao * The IOCTL interface for DFL based FPGA is designed for extensibility by 24620e1902SWu Hao * embedding the structure length (argsz) and flags into structures passed 25620e1902SWu Hao * between kernel and userspace. This design referenced the VFIO IOCTL 26620e1902SWu Hao * interface (include/uapi/linux/vfio.h). 27620e1902SWu Hao */ 28620e1902SWu Hao 29620e1902SWu Hao #define DFL_FPGA_MAGIC 0xB6 30620e1902SWu Hao 31620e1902SWu Hao #define DFL_FPGA_BASE 0 32e4664c0eSWu Hao #define DFL_PORT_BASE 0x40 3329de7624SKang Luwei #define DFL_FME_BASE 0x80 34620e1902SWu Hao 35e4664c0eSWu Hao /* Common IOCTLs for both FME and AFU file descriptor */ 36e4664c0eSWu Hao 37620e1902SWu Hao /** 38620e1902SWu Hao * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) 39620e1902SWu Hao * 40620e1902SWu Hao * Report the version of the driver API. 41620e1902SWu Hao * Return: Driver API Version. 42620e1902SWu Hao */ 43620e1902SWu Hao 44620e1902SWu Hao #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) 45620e1902SWu Hao 46620e1902SWu Hao /** 47620e1902SWu Hao * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) 48620e1902SWu Hao * 49620e1902SWu Hao * Check whether an extension is supported. 50620e1902SWu Hao * Return: 0 if not supported, otherwise the extension is supported. 51620e1902SWu Hao */ 52620e1902SWu Hao 53620e1902SWu Hao #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) 54620e1902SWu Hao 55e4664c0eSWu Hao /* IOCTLs for AFU file descriptor */ 56e4664c0eSWu Hao 57e4664c0eSWu Hao /** 58e4664c0eSWu Hao * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) 59e4664c0eSWu Hao * 60e4664c0eSWu Hao * Reset the FPGA Port and its AFU. No parameters are supported. 61e4664c0eSWu Hao * Userspace can do Port reset at any time, e.g. during DMA or PR. But 62e4664c0eSWu Hao * it should never cause any system level issue, only functional failure 63e4664c0eSWu Hao * (e.g. DMA or PR operation failure) and be recoverable from the failure. 64e4664c0eSWu Hao * Return: 0 on success, -errno of failure 65e4664c0eSWu Hao */ 66e4664c0eSWu Hao 67e4664c0eSWu Hao #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) 68e4664c0eSWu Hao 69857a2622SXiao Guangrong /** 70857a2622SXiao Guangrong * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1, 71857a2622SXiao Guangrong * struct dfl_fpga_port_info) 72857a2622SXiao Guangrong * 73857a2622SXiao Guangrong * Retrieve information about the fpga port. 74857a2622SXiao Guangrong * Driver fills the info in provided struct dfl_fpga_port_info. 75857a2622SXiao Guangrong * Return: 0 on success, -errno on failure. 76857a2622SXiao Guangrong */ 77857a2622SXiao Guangrong struct dfl_fpga_port_info { 78857a2622SXiao Guangrong /* Input */ 79857a2622SXiao Guangrong __u32 argsz; /* Structure length */ 80857a2622SXiao Guangrong /* Output */ 81857a2622SXiao Guangrong __u32 flags; /* Zero for now */ 82857a2622SXiao Guangrong __u32 num_regions; /* The number of supported regions */ 83857a2622SXiao Guangrong __u32 num_umsgs; /* The number of allocated umsgs */ 84857a2622SXiao Guangrong }; 85857a2622SXiao Guangrong 86857a2622SXiao Guangrong #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) 87857a2622SXiao Guangrong 88857a2622SXiao Guangrong /** 89857a2622SXiao Guangrong * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2, 90857a2622SXiao Guangrong * struct dfl_fpga_port_region_info) 91857a2622SXiao Guangrong * 92857a2622SXiao Guangrong * Retrieve information about a device memory region. 93857a2622SXiao Guangrong * Caller provides struct dfl_fpga_port_region_info with index value set. 94857a2622SXiao Guangrong * Driver returns the region info in other fields. 95857a2622SXiao Guangrong * Return: 0 on success, -errno on failure. 96857a2622SXiao Guangrong */ 97857a2622SXiao Guangrong struct dfl_fpga_port_region_info { 98857a2622SXiao Guangrong /* input */ 99857a2622SXiao Guangrong __u32 argsz; /* Structure length */ 100857a2622SXiao Guangrong /* Output */ 101857a2622SXiao Guangrong __u32 flags; /* Access permission */ 102857a2622SXiao Guangrong #define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */ 103857a2622SXiao Guangrong #define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */ 104857a2622SXiao Guangrong #define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */ 105857a2622SXiao Guangrong /* Input */ 106857a2622SXiao Guangrong __u32 index; /* Region index */ 107857a2622SXiao Guangrong #define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */ 108857a2622SXiao Guangrong #define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */ 109857a2622SXiao Guangrong __u32 padding; 110857a2622SXiao Guangrong /* Output */ 111857a2622SXiao Guangrong __u64 size; /* Region size (bytes) */ 112857a2622SXiao Guangrong __u64 offset; /* Region offset from start of device fd */ 113857a2622SXiao Guangrong }; 114857a2622SXiao Guangrong 115857a2622SXiao Guangrong #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) 116857a2622SXiao Guangrong 117fa8dda1eSWu Hao /** 118fa8dda1eSWu Hao * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3, 119fa8dda1eSWu Hao * struct dfl_fpga_port_dma_map) 120fa8dda1eSWu Hao * 121fa8dda1eSWu Hao * Map the dma memory per user_addr and length which are provided by caller. 122fa8dda1eSWu Hao * Driver fills the iova in provided struct afu_port_dma_map. 123fa8dda1eSWu Hao * This interface only accepts page-size aligned user memory for dma mapping. 124fa8dda1eSWu Hao * Return: 0 on success, -errno on failure. 125fa8dda1eSWu Hao */ 126fa8dda1eSWu Hao struct dfl_fpga_port_dma_map { 127fa8dda1eSWu Hao /* Input */ 128fa8dda1eSWu Hao __u32 argsz; /* Structure length */ 129fa8dda1eSWu Hao __u32 flags; /* Zero for now */ 130fa8dda1eSWu Hao __u64 user_addr; /* Process virtual address */ 131fa8dda1eSWu Hao __u64 length; /* Length of mapping (bytes)*/ 132fa8dda1eSWu Hao /* Output */ 133fa8dda1eSWu Hao __u64 iova; /* IO virtual address */ 134fa8dda1eSWu Hao }; 135fa8dda1eSWu Hao 136fa8dda1eSWu Hao #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) 137fa8dda1eSWu Hao 138fa8dda1eSWu Hao /** 139fa8dda1eSWu Hao * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4, 140fa8dda1eSWu Hao * struct dfl_fpga_port_dma_unmap) 141fa8dda1eSWu Hao * 142fa8dda1eSWu Hao * Unmap the dma memory per iova provided by caller. 143fa8dda1eSWu Hao * Return: 0 on success, -errno on failure. 144fa8dda1eSWu Hao */ 145fa8dda1eSWu Hao struct dfl_fpga_port_dma_unmap { 146fa8dda1eSWu Hao /* Input */ 147fa8dda1eSWu Hao __u32 argsz; /* Structure length */ 148fa8dda1eSWu Hao __u32 flags; /* Zero for now */ 149fa8dda1eSWu Hao __u64 iova; /* IO virtual address */ 150fa8dda1eSWu Hao }; 151fa8dda1eSWu Hao 152fa8dda1eSWu Hao #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) 153fa8dda1eSWu Hao 154322b598bSXu Yilun /** 155322b598bSXu Yilun * struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl. 156322b598bSXu Yilun * 157322b598bSXu Yilun * @start: Index of the first irq. 158322b598bSXu Yilun * @count: The number of eventfd handler. 159322b598bSXu Yilun * @evtfds: Eventfd handlers. 160322b598bSXu Yilun */ 161322b598bSXu Yilun struct dfl_fpga_irq_set { 162322b598bSXu Yilun __u32 start; 163322b598bSXu Yilun __u32 count; 164322b598bSXu Yilun __s32 evtfds[]; 165322b598bSXu Yilun }; 166322b598bSXu Yilun 167fe6a3d65SXu Yilun /** 168fe6a3d65SXu Yilun * DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, 169fe6a3d65SXu Yilun * __u32 num_irqs) 170fe6a3d65SXu Yilun * 171fe6a3d65SXu Yilun * Get the number of irqs supported by the fpga port error reporting private 172fe6a3d65SXu Yilun * feature. Currently hardware supports up to 1 irq. 173fe6a3d65SXu Yilun * Return: 0 on success, -errno on failure. 174fe6a3d65SXu Yilun */ 175fe6a3d65SXu Yilun #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ 176fe6a3d65SXu Yilun DFL_PORT_BASE + 5, __u32) 177fe6a3d65SXu Yilun 178fe6a3d65SXu Yilun /** 179fe6a3d65SXu Yilun * DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, 180fe6a3d65SXu Yilun * struct dfl_fpga_irq_set) 181fe6a3d65SXu Yilun * 182fe6a3d65SXu Yilun * Set fpga port error reporting interrupt trigger if evtfds[n] is valid. 183fe6a3d65SXu Yilun * Unset related interrupt trigger if evtfds[n] is a negative value. 184fe6a3d65SXu Yilun * Return: 0 on success, -errno on failure. 185fe6a3d65SXu Yilun */ 186fe6a3d65SXu Yilun #define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ 187fe6a3d65SXu Yilun DFL_PORT_BASE + 6, \ 188fe6a3d65SXu Yilun struct dfl_fpga_irq_set) 189fe6a3d65SXu Yilun 190*09d86150SXu Yilun /** 191*09d86150SXu Yilun * DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, 192*09d86150SXu Yilun * __u32 num_irqs) 193*09d86150SXu Yilun * 194*09d86150SXu Yilun * Get the number of irqs supported by the fpga AFU interrupt private 195*09d86150SXu Yilun * feature. 196*09d86150SXu Yilun * Return: 0 on success, -errno on failure. 197*09d86150SXu Yilun */ 198*09d86150SXu Yilun #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ 199*09d86150SXu Yilun DFL_PORT_BASE + 7, __u32) 200*09d86150SXu Yilun 201*09d86150SXu Yilun /** 202*09d86150SXu Yilun * DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, 203*09d86150SXu Yilun * struct dfl_fpga_irq_set) 204*09d86150SXu Yilun * 205*09d86150SXu Yilun * Set fpga AFU interrupt trigger if evtfds[n] is valid. 206*09d86150SXu Yilun * Unset related interrupt trigger if evtfds[n] is a negative value. 207*09d86150SXu Yilun * Return: 0 on success, -errno on failure. 208*09d86150SXu Yilun */ 209*09d86150SXu Yilun #define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ 210*09d86150SXu Yilun DFL_PORT_BASE + 8, \ 211*09d86150SXu Yilun struct dfl_fpga_irq_set) 212*09d86150SXu Yilun 21329de7624SKang Luwei /* IOCTLs for FME file descriptor */ 21429de7624SKang Luwei 21529de7624SKang Luwei /** 21629de7624SKang Luwei * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0, 21729de7624SKang Luwei * struct dfl_fpga_fme_port_pr) 21829de7624SKang Luwei * 21929de7624SKang Luwei * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) 22029de7624SKang Luwei * provided by caller. 22129de7624SKang Luwei * Return: 0 on success, -errno on failure. 22229de7624SKang Luwei * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected 22329de7624SKang Luwei * some errors during PR, under this case, the user can fetch HW error info 22429de7624SKang Luwei * from the status of FME's fpga manager. 22529de7624SKang Luwei */ 22629de7624SKang Luwei 22729de7624SKang Luwei struct dfl_fpga_fme_port_pr { 22829de7624SKang Luwei /* Input */ 22929de7624SKang Luwei __u32 argsz; /* Structure length */ 23029de7624SKang Luwei __u32 flags; /* Zero for now */ 23129de7624SKang Luwei __u32 port_id; 23229de7624SKang Luwei __u32 buffer_size; 23329de7624SKang Luwei __u64 buffer_address; /* Userspace address to the buffer for PR */ 23429de7624SKang Luwei }; 23529de7624SKang Luwei 23629de7624SKang Luwei #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) 23729de7624SKang Luwei 23869bb18ddSWu Hao /** 23969bb18ddSWu Hao * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, 24069bb18ddSWu Hao * int port_id) 24169bb18ddSWu Hao * 24269bb18ddSWu Hao * Driver releases the port per Port ID provided by caller. 24369bb18ddSWu Hao * Return: 0 on success, -errno on failure. 24469bb18ddSWu Hao */ 24569bb18ddSWu Hao #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int) 24669bb18ddSWu Hao 24769bb18ddSWu Hao /** 24869bb18ddSWu Hao * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, 24969bb18ddSWu Hao * int port_id) 25069bb18ddSWu Hao * 25169bb18ddSWu Hao * Driver assigns the port back per Port ID provided by caller. 25269bb18ddSWu Hao * Return: 0 on success, -errno on failure. 25369bb18ddSWu Hao */ 25469bb18ddSWu Hao #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int) 25569bb18ddSWu Hao 256d43f20baSXu Yilun /** 257d43f20baSXu Yilun * DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, 258d43f20baSXu Yilun * __u32 num_irqs) 259d43f20baSXu Yilun * 260d43f20baSXu Yilun * Get the number of irqs supported by the fpga fme error reporting private 261d43f20baSXu Yilun * feature. Currently hardware supports up to 1 irq. 262d43f20baSXu Yilun * Return: 0 on success, -errno on failure. 263d43f20baSXu Yilun */ 264d43f20baSXu Yilun #define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \ 265d43f20baSXu Yilun DFL_FME_BASE + 3, __u32) 266d43f20baSXu Yilun 267d43f20baSXu Yilun /** 268d43f20baSXu Yilun * DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, 269d43f20baSXu Yilun * struct dfl_fpga_irq_set) 270d43f20baSXu Yilun * 271d43f20baSXu Yilun * Set fpga fme error reporting interrupt trigger if evtfds[n] is valid. 272d43f20baSXu Yilun * Unset related interrupt trigger if evtfds[n] is a negative value. 273d43f20baSXu Yilun * Return: 0 on success, -errno on failure. 274d43f20baSXu Yilun */ 275d43f20baSXu Yilun #define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \ 276d43f20baSXu Yilun DFL_FME_BASE + 4, \ 277d43f20baSXu Yilun struct dfl_fpga_irq_set) 278d43f20baSXu Yilun 279620e1902SWu Hao #endif /* _UAPI_LINUX_FPGA_DFL_H */ 280