1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __LINUX_XILINX_LL_TEMAC_H 3 #define __LINUX_XILINX_LL_TEMAC_H 4 5 #include <linux/if_ether.h> 6 #include <linux/phy.h> 7 8 struct ll_temac_platform_data { 9 bool txcsum; /* Enable/disable TX checksum */ 10 bool rxcsum; /* Enable/disable RX checksum */ 11 u8 mac_addr[ETH_ALEN]; /* MAC address (6 bytes) */ 12 /* Clock frequency for input to MDIO clock generator */ 13 u32 mdio_clk_freq; 14 unsigned long long mdio_bus_id; /* Unique id for MDIO bus */ 15 int phy_addr; /* Address of the PHY to connect to */ 16 phy_interface_t phy_interface; /* PHY interface mode */ 17 bool reg_little_endian; /* Little endian TEMAC register access */ 18 bool dma_little_endian; /* Little endian DMA register access */ 19 /* Pre-initialized mutex to use for synchronizing indirect 20 * register access. When using both interfaces of a single 21 * TEMAC IP block, the same mutex should be passed here, as 22 * they share the same DCR bus bridge. 23 */ 24 struct mutex *indirect_mutex; 25 /* DMA channel control setup */ 26 u8 tx_irq_timeout; /* TX Interrupt Delay Time-out */ 27 u8 tx_irq_count; /* TX Interrupt Coalescing Threshold Count */ 28 u8 rx_irq_timeout; /* RX Interrupt Delay Time-out */ 29 u8 rx_irq_count; /* RX Interrupt Coalescing Threshold Count */ 30 }; 31 32 #endif /* __LINUX_XILINX_LL_TEMAC_H */ 33