1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * Copyright (C) 2009 Samsung Electronics Ltd. 5 * Jaswinder Singh <jassi.brar@samsung.com> 6 */ 7 8 #ifndef __SPI_S3C64XX_H 9 #define __SPI_S3C64XX_H 10 11 #include <linux/dmaengine.h> 12 13 struct platform_device; 14 15 /** 16 * struct s3c64xx_spi_csinfo - ChipSelect description 17 * @fb_delay: Slave specific feedback delay. 18 * Refer to FB_CLK_SEL register definition in SPI chapter. 19 * 20 * This is per SPI-Slave Chipselect information. 21 * Allocate and initialize one in machine init code and make the 22 * spi_board_info.controller_data point to it. 23 */ 24 struct s3c64xx_spi_csinfo { 25 u8 fb_delay; 26 }; 27 28 /** 29 * struct s3c64xx_spi_info - SPI Controller defining structure 30 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 31 * @num_cs: Number of CS this controller emulates. 32 * @no_cs: Used when CS line is not connected. 33 * @cfg_gpio: Configure pins for this SPI controller. 34 */ 35 struct s3c64xx_spi_info { 36 int src_clk_nr; 37 int num_cs; 38 bool no_cs; 39 bool polling; 40 int (*cfg_gpio)(void); 41 }; 42 43 /** 44 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board 45 * initialization code. 46 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 47 * @num_cs: Number of elements in the 'cs' array. 48 * 49 * Call this from machine init code for each SPI Controller that 50 * has some chips attached to it. 51 */ 52 extern void s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs); 53 54 /* defined by architecture to configure gpio */ 55 extern int s3c64xx_spi0_cfg_gpio(void); 56 57 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; 58 #endif /*__SPI_S3C64XX_H */ 59