1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for the NVM Express interface 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #ifndef _LINUX_NVME_H 8 #define _LINUX_NVME_H 9 10 #include <linux/bits.h> 11 #include <linux/types.h> 12 #include <linux/uuid.h> 13 14 /* NQN names in commands fields specified one size */ 15 #define NVMF_NQN_FIELD_LEN 256 16 17 /* However the max length of a qualified name is another size */ 18 #define NVMF_NQN_SIZE 223 19 20 #define NVMF_TRSVCID_SIZE 32 21 #define NVMF_TRADDR_SIZE 256 22 #define NVMF_TSAS_SIZE 256 23 24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" 25 26 #define NVME_RDMA_IP_PORT 4420 27 28 #define NVME_NSID_ALL 0xffffffff 29 30 enum nvme_subsys_type { 31 /* Referral to another discovery type target subsystem */ 32 NVME_NQN_DISC = 1, 33 34 /* NVME type target subsystem */ 35 NVME_NQN_NVME = 2, 36 37 /* Current discovery type target subsystem */ 38 NVME_NQN_CURR = 3, 39 }; 40 41 enum nvme_ctrl_type { 42 NVME_CTRL_IO = 1, /* I/O controller */ 43 NVME_CTRL_DISC = 2, /* Discovery controller */ 44 NVME_CTRL_ADMIN = 3, /* Administrative controller */ 45 }; 46 47 enum nvme_dctype { 48 NVME_DCTYPE_NOT_REPORTED = 0, 49 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */ 50 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */ 51 }; 52 53 /* Address Family codes for Discovery Log Page entry ADRFAM field */ 54 enum { 55 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ 56 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ 57 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ 58 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ 59 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ 60 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ 61 NVMF_ADDR_FAMILY_MAX, 62 }; 63 64 /* Transport Type codes for Discovery Log Page entry TRTYPE field */ 65 enum { 66 NVMF_TRTYPE_RDMA = 1, /* RDMA */ 67 NVMF_TRTYPE_FC = 2, /* Fibre Channel */ 68 NVMF_TRTYPE_TCP = 3, /* TCP/IP */ 69 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ 70 NVMF_TRTYPE_MAX, 71 }; 72 73 /* Transport Requirements codes for Discovery Log Page entry TREQ field */ 74 enum { 75 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ 76 NVMF_TREQ_REQUIRED = 1, /* Required */ 77 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ 78 #define NVME_TREQ_SECURE_CHANNEL_MASK \ 79 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) 80 81 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ 82 }; 83 84 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 85 * RDMA_QPTYPE field 86 */ 87 enum { 88 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ 89 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ 90 }; 91 92 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS 93 * RDMA_QPTYPE field 94 */ 95 enum { 96 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ 97 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ 98 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ 99 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ 100 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ 101 }; 102 103 /* RDMA Connection Management Service Type codes for Discovery Log Page 104 * entry TSAS RDMA_CMS field 105 */ 106 enum { 107 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ 108 }; 109 110 /* TSAS SECTYPE for TCP transport */ 111 enum { 112 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */ 113 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 114 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */ 115 }; 116 117 #define NVME_AQ_DEPTH 32 118 #define NVME_NR_AEN_COMMANDS 1 119 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) 120 121 /* 122 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See 123 * NVM-Express 1.2 specification, section 4.1.2. 124 */ 125 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) 126 127 enum { 128 NVME_REG_CAP = 0x0000, /* Controller Capabilities */ 129 NVME_REG_VS = 0x0008, /* Version */ 130 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ 131 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ 132 NVME_REG_CC = 0x0014, /* Controller Configuration */ 133 NVME_REG_CSTS = 0x001c, /* Controller Status */ 134 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ 135 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ 136 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ 137 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ 138 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ 139 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ 140 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ 141 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ 142 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer 143 * Location 144 */ 145 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory 146 * Space Control 147 */ 148 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */ 149 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ 150 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ 151 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ 152 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity 153 * Buffer Size 154 */ 155 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained 156 * Write Throughput 157 */ 158 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ 159 }; 160 161 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 162 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 163 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 164 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) 165 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) 166 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 167 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 168 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) 169 170 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) 171 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) 172 173 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16) 174 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff) 175 176 enum { 177 NVME_CMBSZ_SQS = 1 << 0, 178 NVME_CMBSZ_CQS = 1 << 1, 179 NVME_CMBSZ_LISTS = 1 << 2, 180 NVME_CMBSZ_RDS = 1 << 3, 181 NVME_CMBSZ_WDS = 1 << 4, 182 183 NVME_CMBSZ_SZ_SHIFT = 12, 184 NVME_CMBSZ_SZ_MASK = 0xfffff, 185 186 NVME_CMBSZ_SZU_SHIFT = 8, 187 NVME_CMBSZ_SZU_MASK = 0xf, 188 }; 189 190 /* 191 * Submission and Completion Queue Entry Sizes for the NVM command set. 192 * (In bytes and specified as a power of two (2^n)). 193 */ 194 #define NVME_ADM_SQES 6 195 #define NVME_NVM_IOSQES 6 196 #define NVME_NVM_IOCQES 4 197 198 enum { 199 NVME_CC_ENABLE = 1 << 0, 200 NVME_CC_EN_SHIFT = 0, 201 NVME_CC_CSS_SHIFT = 4, 202 NVME_CC_MPS_SHIFT = 7, 203 NVME_CC_AMS_SHIFT = 11, 204 NVME_CC_SHN_SHIFT = 14, 205 NVME_CC_IOSQES_SHIFT = 16, 206 NVME_CC_IOCQES_SHIFT = 20, 207 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, 208 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, 209 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, 210 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, 211 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, 212 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, 213 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, 214 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, 215 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, 216 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, 217 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, 218 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, 219 NVME_CC_CRIME = 1 << 24, 220 }; 221 222 enum { 223 NVME_CSTS_RDY = 1 << 0, 224 NVME_CSTS_CFS = 1 << 1, 225 NVME_CSTS_NSSRO = 1 << 4, 226 NVME_CSTS_PP = 1 << 5, 227 NVME_CSTS_SHST_NORMAL = 0 << 2, 228 NVME_CSTS_SHST_OCCUR = 1 << 2, 229 NVME_CSTS_SHST_CMPLT = 2 << 2, 230 NVME_CSTS_SHST_MASK = 3 << 2, 231 }; 232 233 enum { 234 NVME_CMBMSC_CRE = 1 << 0, 235 NVME_CMBMSC_CMSE = 1 << 1, 236 }; 237 238 enum { 239 NVME_CAP_CSS_NVM = 1 << 0, 240 NVME_CAP_CSS_CSI = 1 << 6, 241 }; 242 243 enum { 244 NVME_CAP_CRMS_CRWMS = 1ULL << 59, 245 NVME_CAP_CRMS_CRIMS = 1ULL << 60, 246 }; 247 248 struct nvme_id_power_state { 249 __le16 max_power; /* centiwatts */ 250 __u8 rsvd2; 251 __u8 flags; 252 __le32 entry_lat; /* microseconds */ 253 __le32 exit_lat; /* microseconds */ 254 __u8 read_tput; 255 __u8 read_lat; 256 __u8 write_tput; 257 __u8 write_lat; 258 __le16 idle_power; 259 __u8 idle_scale; 260 __u8 rsvd19; 261 __le16 active_power; 262 __u8 active_work_scale; 263 __u8 rsvd23[9]; 264 }; 265 266 enum { 267 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, 268 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, 269 }; 270 271 enum nvme_ctrl_attr { 272 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), 273 NVME_CTRL_ATTR_TBKAS = (1 << 6), 274 NVME_CTRL_ATTR_ELBAS = (1 << 15), 275 }; 276 277 struct nvme_id_ctrl { 278 __le16 vid; 279 __le16 ssvid; 280 char sn[20]; 281 char mn[40]; 282 char fr[8]; 283 __u8 rab; 284 __u8 ieee[3]; 285 __u8 cmic; 286 __u8 mdts; 287 __le16 cntlid; 288 __le32 ver; 289 __le32 rtd3r; 290 __le32 rtd3e; 291 __le32 oaes; 292 __le32 ctratt; 293 __u8 rsvd100[11]; 294 __u8 cntrltype; 295 __u8 fguid[16]; 296 __le16 crdt1; 297 __le16 crdt2; 298 __le16 crdt3; 299 __u8 rsvd134[122]; 300 __le16 oacs; 301 __u8 acl; 302 __u8 aerl; 303 __u8 frmw; 304 __u8 lpa; 305 __u8 elpe; 306 __u8 npss; 307 __u8 avscc; 308 __u8 apsta; 309 __le16 wctemp; 310 __le16 cctemp; 311 __le16 mtfa; 312 __le32 hmpre; 313 __le32 hmmin; 314 __u8 tnvmcap[16]; 315 __u8 unvmcap[16]; 316 __le32 rpmbs; 317 __le16 edstt; 318 __u8 dsto; 319 __u8 fwug; 320 __le16 kas; 321 __le16 hctma; 322 __le16 mntmt; 323 __le16 mxtmt; 324 __le32 sanicap; 325 __le32 hmminds; 326 __le16 hmmaxd; 327 __u8 rsvd338[4]; 328 __u8 anatt; 329 __u8 anacap; 330 __le32 anagrpmax; 331 __le32 nanagrpid; 332 __u8 rsvd352[160]; 333 __u8 sqes; 334 __u8 cqes; 335 __le16 maxcmd; 336 __le32 nn; 337 __le16 oncs; 338 __le16 fuses; 339 __u8 fna; 340 __u8 vwc; 341 __le16 awun; 342 __le16 awupf; 343 __u8 nvscc; 344 __u8 nwpc; 345 __le16 acwu; 346 __u8 rsvd534[2]; 347 __le32 sgls; 348 __le32 mnan; 349 __u8 rsvd544[224]; 350 char subnqn[256]; 351 __u8 rsvd1024[768]; 352 __le32 ioccsz; 353 __le32 iorcsz; 354 __le16 icdoff; 355 __u8 ctrattr; 356 __u8 msdbd; 357 __u8 rsvd1804[2]; 358 __u8 dctype; 359 __u8 rsvd1807[241]; 360 struct nvme_id_power_state psd[32]; 361 __u8 vs[1024]; 362 }; 363 364 enum { 365 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0, 366 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, 367 NVME_CTRL_CMIC_ANA = 1 << 3, 368 NVME_CTRL_ONCS_COMPARE = 1 << 0, 369 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, 370 NVME_CTRL_ONCS_DSM = 1 << 2, 371 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, 372 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, 373 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, 374 NVME_CTRL_VWC_PRESENT = 1 << 0, 375 NVME_CTRL_OACS_SEC_SUPP = 1 << 0, 376 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, 377 NVME_CTRL_OACS_DIRECTIVES = 1 << 5, 378 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, 379 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, 380 NVME_CTRL_CTRATT_128_ID = 1 << 0, 381 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, 382 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, 383 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, 384 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, 385 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, 386 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, 387 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, 388 }; 389 390 struct nvme_lbaf { 391 __le16 ms; 392 __u8 ds; 393 __u8 rp; 394 }; 395 396 struct nvme_id_ns { 397 __le64 nsze; 398 __le64 ncap; 399 __le64 nuse; 400 __u8 nsfeat; 401 __u8 nlbaf; 402 __u8 flbas; 403 __u8 mc; 404 __u8 dpc; 405 __u8 dps; 406 __u8 nmic; 407 __u8 rescap; 408 __u8 fpi; 409 __u8 dlfeat; 410 __le16 nawun; 411 __le16 nawupf; 412 __le16 nacwu; 413 __le16 nabsn; 414 __le16 nabo; 415 __le16 nabspf; 416 __le16 noiob; 417 __u8 nvmcap[16]; 418 __le16 npwg; 419 __le16 npwa; 420 __le16 npdg; 421 __le16 npda; 422 __le16 nows; 423 __u8 rsvd74[18]; 424 __le32 anagrpid; 425 __u8 rsvd96[3]; 426 __u8 nsattr; 427 __le16 nvmsetid; 428 __le16 endgid; 429 __u8 nguid[16]; 430 __u8 eui64[8]; 431 struct nvme_lbaf lbaf[64]; 432 __u8 vs[3712]; 433 }; 434 435 /* I/O Command Set Independent Identify Namespace Data Structure */ 436 struct nvme_id_ns_cs_indep { 437 __u8 nsfeat; 438 __u8 nmic; 439 __u8 rescap; 440 __u8 fpi; 441 __le32 anagrpid; 442 __u8 nsattr; 443 __u8 rsvd9; 444 __le16 nvmsetid; 445 __le16 endgid; 446 __u8 nstat; 447 __u8 rsvd15[4081]; 448 }; 449 450 struct nvme_zns_lbafe { 451 __le64 zsze; 452 __u8 zdes; 453 __u8 rsvd9[7]; 454 }; 455 456 struct nvme_id_ns_zns { 457 __le16 zoc; 458 __le16 ozcs; 459 __le32 mar; 460 __le32 mor; 461 __le32 rrl; 462 __le32 frl; 463 __u8 rsvd20[2796]; 464 struct nvme_zns_lbafe lbafe[64]; 465 __u8 vs[256]; 466 }; 467 468 struct nvme_id_ctrl_zns { 469 __u8 zasl; 470 __u8 rsvd1[4095]; 471 }; 472 473 struct nvme_id_ns_nvm { 474 __le64 lbstm; 475 __u8 pic; 476 __u8 rsvd9[3]; 477 __le32 elbaf[64]; 478 __u8 rsvd268[3828]; 479 }; 480 481 enum { 482 NVME_ID_NS_NVM_STS_MASK = 0x7f, 483 NVME_ID_NS_NVM_GUARD_SHIFT = 7, 484 NVME_ID_NS_NVM_GUARD_MASK = 0x3, 485 }; 486 487 static inline __u8 nvme_elbaf_sts(__u32 elbaf) 488 { 489 return elbaf & NVME_ID_NS_NVM_STS_MASK; 490 } 491 492 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf) 493 { 494 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK; 495 } 496 497 struct nvme_id_ctrl_nvm { 498 __u8 vsl; 499 __u8 wzsl; 500 __u8 wusl; 501 __u8 dmrl; 502 __le32 dmrsl; 503 __le64 dmsl; 504 __u8 rsvd16[4080]; 505 }; 506 507 enum { 508 NVME_ID_CNS_NS = 0x00, 509 NVME_ID_CNS_CTRL = 0x01, 510 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, 511 NVME_ID_CNS_NS_DESC_LIST = 0x03, 512 NVME_ID_CNS_CS_NS = 0x05, 513 NVME_ID_CNS_CS_CTRL = 0x06, 514 NVME_ID_CNS_NS_CS_INDEP = 0x08, 515 NVME_ID_CNS_NS_PRESENT_LIST = 0x10, 516 NVME_ID_CNS_NS_PRESENT = 0x11, 517 NVME_ID_CNS_CTRL_NS_LIST = 0x12, 518 NVME_ID_CNS_CTRL_LIST = 0x13, 519 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, 520 NVME_ID_CNS_NS_GRANULARITY = 0x16, 521 NVME_ID_CNS_UUID_LIST = 0x17, 522 }; 523 524 enum { 525 NVME_CSI_NVM = 0, 526 NVME_CSI_ZNS = 2, 527 }; 528 529 enum { 530 NVME_DIR_IDENTIFY = 0x00, 531 NVME_DIR_STREAMS = 0x01, 532 NVME_DIR_SND_ID_OP_ENABLE = 0x01, 533 NVME_DIR_SND_ST_OP_REL_ID = 0x01, 534 NVME_DIR_SND_ST_OP_REL_RSC = 0x02, 535 NVME_DIR_RCV_ID_OP_PARAM = 0x01, 536 NVME_DIR_RCV_ST_OP_PARAM = 0x01, 537 NVME_DIR_RCV_ST_OP_STATUS = 0x02, 538 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, 539 NVME_DIR_ENDIR = 0x01, 540 }; 541 542 enum { 543 NVME_NS_FEAT_THIN = 1 << 0, 544 NVME_NS_FEAT_ATOMICS = 1 << 1, 545 NVME_NS_FEAT_IO_OPT = 1 << 4, 546 NVME_NS_ATTR_RO = 1 << 0, 547 NVME_NS_FLBAS_LBA_MASK = 0xf, 548 NVME_NS_FLBAS_LBA_UMASK = 0x60, 549 NVME_NS_FLBAS_LBA_SHIFT = 1, 550 NVME_NS_FLBAS_META_EXT = 0x10, 551 NVME_NS_NMIC_SHARED = 1 << 0, 552 NVME_LBAF_RP_BEST = 0, 553 NVME_LBAF_RP_BETTER = 1, 554 NVME_LBAF_RP_GOOD = 2, 555 NVME_LBAF_RP_DEGRADED = 3, 556 NVME_NS_DPC_PI_LAST = 1 << 4, 557 NVME_NS_DPC_PI_FIRST = 1 << 3, 558 NVME_NS_DPC_PI_TYPE3 = 1 << 2, 559 NVME_NS_DPC_PI_TYPE2 = 1 << 1, 560 NVME_NS_DPC_PI_TYPE1 = 1 << 0, 561 NVME_NS_DPS_PI_FIRST = 1 << 3, 562 NVME_NS_DPS_PI_MASK = 0x7, 563 NVME_NS_DPS_PI_TYPE1 = 1, 564 NVME_NS_DPS_PI_TYPE2 = 2, 565 NVME_NS_DPS_PI_TYPE3 = 3, 566 }; 567 568 enum { 569 NVME_NSTAT_NRDY = 1 << 0, 570 }; 571 572 enum { 573 NVME_NVM_NS_16B_GUARD = 0, 574 NVME_NVM_NS_32B_GUARD = 1, 575 NVME_NVM_NS_64B_GUARD = 2, 576 }; 577 578 static inline __u8 nvme_lbaf_index(__u8 flbas) 579 { 580 return (flbas & NVME_NS_FLBAS_LBA_MASK) | 581 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT); 582 } 583 584 /* Identify Namespace Metadata Capabilities (MC): */ 585 enum { 586 NVME_MC_EXTENDED_LBA = (1 << 0), 587 NVME_MC_METADATA_PTR = (1 << 1), 588 }; 589 590 struct nvme_ns_id_desc { 591 __u8 nidt; 592 __u8 nidl; 593 __le16 reserved; 594 }; 595 596 #define NVME_NIDT_EUI64_LEN 8 597 #define NVME_NIDT_NGUID_LEN 16 598 #define NVME_NIDT_UUID_LEN 16 599 #define NVME_NIDT_CSI_LEN 1 600 601 enum { 602 NVME_NIDT_EUI64 = 0x01, 603 NVME_NIDT_NGUID = 0x02, 604 NVME_NIDT_UUID = 0x03, 605 NVME_NIDT_CSI = 0x04, 606 }; 607 608 struct nvme_smart_log { 609 __u8 critical_warning; 610 __u8 temperature[2]; 611 __u8 avail_spare; 612 __u8 spare_thresh; 613 __u8 percent_used; 614 __u8 endu_grp_crit_warn_sumry; 615 __u8 rsvd7[25]; 616 __u8 data_units_read[16]; 617 __u8 data_units_written[16]; 618 __u8 host_reads[16]; 619 __u8 host_writes[16]; 620 __u8 ctrl_busy_time[16]; 621 __u8 power_cycles[16]; 622 __u8 power_on_hours[16]; 623 __u8 unsafe_shutdowns[16]; 624 __u8 media_errors[16]; 625 __u8 num_err_log_entries[16]; 626 __le32 warning_temp_time; 627 __le32 critical_comp_time; 628 __le16 temp_sensor[8]; 629 __le32 thm_temp1_trans_count; 630 __le32 thm_temp2_trans_count; 631 __le32 thm_temp1_total_time; 632 __le32 thm_temp2_total_time; 633 __u8 rsvd232[280]; 634 }; 635 636 struct nvme_fw_slot_info_log { 637 __u8 afi; 638 __u8 rsvd1[7]; 639 __le64 frs[7]; 640 __u8 rsvd64[448]; 641 }; 642 643 enum { 644 NVME_CMD_EFFECTS_CSUPP = 1 << 0, 645 NVME_CMD_EFFECTS_LBCC = 1 << 1, 646 NVME_CMD_EFFECTS_NCC = 1 << 2, 647 NVME_CMD_EFFECTS_NIC = 1 << 3, 648 NVME_CMD_EFFECTS_CCC = 1 << 4, 649 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14), 650 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), 651 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, 652 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20), 653 }; 654 655 struct nvme_effects_log { 656 __le32 acs[256]; 657 __le32 iocs[256]; 658 __u8 resv[2048]; 659 }; 660 661 enum nvme_ana_state { 662 NVME_ANA_OPTIMIZED = 0x01, 663 NVME_ANA_NONOPTIMIZED = 0x02, 664 NVME_ANA_INACCESSIBLE = 0x03, 665 NVME_ANA_PERSISTENT_LOSS = 0x04, 666 NVME_ANA_CHANGE = 0x0f, 667 }; 668 669 struct nvme_ana_group_desc { 670 __le32 grpid; 671 __le32 nnsids; 672 __le64 chgcnt; 673 __u8 state; 674 __u8 rsvd17[15]; 675 __le32 nsids[]; 676 }; 677 678 /* flag for the log specific field of the ANA log */ 679 #define NVME_ANA_LOG_RGO (1 << 0) 680 681 struct nvme_ana_rsp_hdr { 682 __le64 chgcnt; 683 __le16 ngrps; 684 __le16 rsvd10[3]; 685 }; 686 687 struct nvme_zone_descriptor { 688 __u8 zt; 689 __u8 zs; 690 __u8 za; 691 __u8 rsvd3[5]; 692 __le64 zcap; 693 __le64 zslba; 694 __le64 wp; 695 __u8 rsvd32[32]; 696 }; 697 698 enum { 699 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, 700 }; 701 702 struct nvme_zone_report { 703 __le64 nr_zones; 704 __u8 resv8[56]; 705 struct nvme_zone_descriptor entries[]; 706 }; 707 708 enum { 709 NVME_SMART_CRIT_SPARE = 1 << 0, 710 NVME_SMART_CRIT_TEMPERATURE = 1 << 1, 711 NVME_SMART_CRIT_RELIABILITY = 1 << 2, 712 NVME_SMART_CRIT_MEDIA = 1 << 3, 713 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, 714 }; 715 716 enum { 717 NVME_AER_ERROR = 0, 718 NVME_AER_SMART = 1, 719 NVME_AER_NOTICE = 2, 720 NVME_AER_CSS = 6, 721 NVME_AER_VS = 7, 722 }; 723 724 enum { 725 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03, 726 }; 727 728 enum { 729 NVME_AER_NOTICE_NS_CHANGED = 0x00, 730 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, 731 NVME_AER_NOTICE_ANA = 0x03, 732 NVME_AER_NOTICE_DISC_CHANGED = 0xf0, 733 }; 734 735 enum { 736 NVME_AEN_BIT_NS_ATTR = 8, 737 NVME_AEN_BIT_FW_ACT = 9, 738 NVME_AEN_BIT_ANA_CHANGE = 11, 739 NVME_AEN_BIT_DISC_CHANGE = 31, 740 }; 741 742 enum { 743 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, 744 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, 745 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, 746 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, 747 }; 748 749 struct nvme_lba_range_type { 750 __u8 type; 751 __u8 attributes; 752 __u8 rsvd2[14]; 753 __le64 slba; 754 __le64 nlb; 755 __u8 guid[16]; 756 __u8 rsvd48[16]; 757 }; 758 759 enum { 760 NVME_LBART_TYPE_FS = 0x01, 761 NVME_LBART_TYPE_RAID = 0x02, 762 NVME_LBART_TYPE_CACHE = 0x03, 763 NVME_LBART_TYPE_SWAP = 0x04, 764 765 NVME_LBART_ATTRIB_TEMP = 1 << 0, 766 NVME_LBART_ATTRIB_HIDE = 1 << 1, 767 }; 768 769 enum nvme_pr_type { 770 NVME_PR_WRITE_EXCLUSIVE = 1, 771 NVME_PR_EXCLUSIVE_ACCESS = 2, 772 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3, 773 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4, 774 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5, 775 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6, 776 }; 777 778 enum nvme_eds { 779 NVME_EXTENDED_DATA_STRUCT = 0x1, 780 }; 781 782 struct nvme_registered_ctrl { 783 __le16 cntlid; 784 __u8 rcsts; 785 __u8 rsvd3[5]; 786 __le64 hostid; 787 __le64 rkey; 788 }; 789 790 struct nvme_reservation_status { 791 __le32 gen; 792 __u8 rtype; 793 __u8 regctl[2]; 794 __u8 resv5[2]; 795 __u8 ptpls; 796 __u8 resv10[14]; 797 struct nvme_registered_ctrl regctl_ds[]; 798 }; 799 800 struct nvme_registered_ctrl_ext { 801 __le16 cntlid; 802 __u8 rcsts; 803 __u8 rsvd3[5]; 804 __le64 rkey; 805 __u8 hostid[16]; 806 __u8 rsvd32[32]; 807 }; 808 809 struct nvme_reservation_status_ext { 810 __le32 gen; 811 __u8 rtype; 812 __u8 regctl[2]; 813 __u8 resv5[2]; 814 __u8 ptpls; 815 __u8 resv10[14]; 816 __u8 rsvd24[40]; 817 struct nvme_registered_ctrl_ext regctl_eds[]; 818 }; 819 820 /* I/O commands */ 821 822 enum nvme_opcode { 823 nvme_cmd_flush = 0x00, 824 nvme_cmd_write = 0x01, 825 nvme_cmd_read = 0x02, 826 nvme_cmd_write_uncor = 0x04, 827 nvme_cmd_compare = 0x05, 828 nvme_cmd_write_zeroes = 0x08, 829 nvme_cmd_dsm = 0x09, 830 nvme_cmd_verify = 0x0c, 831 nvme_cmd_resv_register = 0x0d, 832 nvme_cmd_resv_report = 0x0e, 833 nvme_cmd_resv_acquire = 0x11, 834 nvme_cmd_resv_release = 0x15, 835 nvme_cmd_zone_mgmt_send = 0x79, 836 nvme_cmd_zone_mgmt_recv = 0x7a, 837 nvme_cmd_zone_append = 0x7d, 838 nvme_cmd_vendor_start = 0x80, 839 }; 840 841 #define nvme_opcode_name(opcode) { opcode, #opcode } 842 #define show_nvm_opcode_name(val) \ 843 __print_symbolic(val, \ 844 nvme_opcode_name(nvme_cmd_flush), \ 845 nvme_opcode_name(nvme_cmd_write), \ 846 nvme_opcode_name(nvme_cmd_read), \ 847 nvme_opcode_name(nvme_cmd_write_uncor), \ 848 nvme_opcode_name(nvme_cmd_compare), \ 849 nvme_opcode_name(nvme_cmd_write_zeroes), \ 850 nvme_opcode_name(nvme_cmd_dsm), \ 851 nvme_opcode_name(nvme_cmd_verify), \ 852 nvme_opcode_name(nvme_cmd_resv_register), \ 853 nvme_opcode_name(nvme_cmd_resv_report), \ 854 nvme_opcode_name(nvme_cmd_resv_acquire), \ 855 nvme_opcode_name(nvme_cmd_resv_release), \ 856 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ 857 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ 858 nvme_opcode_name(nvme_cmd_zone_append)) 859 860 861 862 /* 863 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier 864 * 865 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block 866 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block 867 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA 868 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation 869 * request subtype 870 */ 871 enum { 872 NVME_SGL_FMT_ADDRESS = 0x00, 873 NVME_SGL_FMT_OFFSET = 0x01, 874 NVME_SGL_FMT_TRANSPORT_A = 0x0A, 875 NVME_SGL_FMT_INVALIDATE = 0x0f, 876 }; 877 878 /* 879 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier 880 * 881 * For struct nvme_sgl_desc: 882 * @NVME_SGL_FMT_DATA_DESC: data block descriptor 883 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor 884 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor 885 * 886 * For struct nvme_keyed_sgl_desc: 887 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor 888 * 889 * Transport-specific SGL types: 890 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor 891 */ 892 enum { 893 NVME_SGL_FMT_DATA_DESC = 0x00, 894 NVME_SGL_FMT_SEG_DESC = 0x02, 895 NVME_SGL_FMT_LAST_SEG_DESC = 0x03, 896 NVME_KEY_SGL_FMT_DATA_DESC = 0x04, 897 NVME_TRANSPORT_SGL_DATA_DESC = 0x05, 898 }; 899 900 struct nvme_sgl_desc { 901 __le64 addr; 902 __le32 length; 903 __u8 rsvd[3]; 904 __u8 type; 905 }; 906 907 struct nvme_keyed_sgl_desc { 908 __le64 addr; 909 __u8 length[3]; 910 __u8 key[4]; 911 __u8 type; 912 }; 913 914 union nvme_data_ptr { 915 struct { 916 __le64 prp1; 917 __le64 prp2; 918 }; 919 struct nvme_sgl_desc sgl; 920 struct nvme_keyed_sgl_desc ksgl; 921 }; 922 923 /* 924 * Lowest two bits of our flags field (FUSE field in the spec): 925 * 926 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command 927 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command 928 * 929 * Highest two bits in our flags field (PSDT field in the spec): 930 * 931 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, 932 * If used, MPTR contains addr of single physical buffer (byte aligned). 933 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, 934 * If used, MPTR contains an address of an SGL segment containing 935 * exactly 1 SGL descriptor (qword aligned). 936 */ 937 enum { 938 NVME_CMD_FUSE_FIRST = (1 << 0), 939 NVME_CMD_FUSE_SECOND = (1 << 1), 940 941 NVME_CMD_SGL_METABUF = (1 << 6), 942 NVME_CMD_SGL_METASEG = (1 << 7), 943 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, 944 }; 945 946 struct nvme_common_command { 947 __u8 opcode; 948 __u8 flags; 949 __u16 command_id; 950 __le32 nsid; 951 __le32 cdw2[2]; 952 __le64 metadata; 953 union nvme_data_ptr dptr; 954 struct_group(cdws, 955 __le32 cdw10; 956 __le32 cdw11; 957 __le32 cdw12; 958 __le32 cdw13; 959 __le32 cdw14; 960 __le32 cdw15; 961 ); 962 }; 963 964 struct nvme_rw_command { 965 __u8 opcode; 966 __u8 flags; 967 __u16 command_id; 968 __le32 nsid; 969 __le32 cdw2; 970 __le32 cdw3; 971 __le64 metadata; 972 union nvme_data_ptr dptr; 973 __le64 slba; 974 __le16 length; 975 __le16 control; 976 __le32 dsmgmt; 977 __le32 reftag; 978 __le16 apptag; 979 __le16 appmask; 980 }; 981 982 enum { 983 NVME_RW_LR = 1 << 15, 984 NVME_RW_FUA = 1 << 14, 985 NVME_RW_APPEND_PIREMAP = 1 << 9, 986 NVME_RW_DSM_FREQ_UNSPEC = 0, 987 NVME_RW_DSM_FREQ_TYPICAL = 1, 988 NVME_RW_DSM_FREQ_RARE = 2, 989 NVME_RW_DSM_FREQ_READS = 3, 990 NVME_RW_DSM_FREQ_WRITES = 4, 991 NVME_RW_DSM_FREQ_RW = 5, 992 NVME_RW_DSM_FREQ_ONCE = 6, 993 NVME_RW_DSM_FREQ_PREFETCH = 7, 994 NVME_RW_DSM_FREQ_TEMP = 8, 995 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 996 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 997 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 998 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 999 NVME_RW_DSM_SEQ_REQ = 1 << 6, 1000 NVME_RW_DSM_COMPRESSED = 1 << 7, 1001 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 1002 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 1003 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 1004 NVME_RW_PRINFO_PRACT = 1 << 13, 1005 NVME_RW_DTYPE_STREAMS = 1 << 4, 1006 NVME_WZ_DEAC = 1 << 9, 1007 }; 1008 1009 struct nvme_dsm_cmd { 1010 __u8 opcode; 1011 __u8 flags; 1012 __u16 command_id; 1013 __le32 nsid; 1014 __u64 rsvd2[2]; 1015 union nvme_data_ptr dptr; 1016 __le32 nr; 1017 __le32 attributes; 1018 __u32 rsvd12[4]; 1019 }; 1020 1021 enum { 1022 NVME_DSMGMT_IDR = 1 << 0, 1023 NVME_DSMGMT_IDW = 1 << 1, 1024 NVME_DSMGMT_AD = 1 << 2, 1025 }; 1026 1027 #define NVME_DSM_MAX_RANGES 256 1028 1029 struct nvme_dsm_range { 1030 __le32 cattr; 1031 __le32 nlb; 1032 __le64 slba; 1033 }; 1034 1035 struct nvme_write_zeroes_cmd { 1036 __u8 opcode; 1037 __u8 flags; 1038 __u16 command_id; 1039 __le32 nsid; 1040 __u64 rsvd2; 1041 __le64 metadata; 1042 union nvme_data_ptr dptr; 1043 __le64 slba; 1044 __le16 length; 1045 __le16 control; 1046 __le32 dsmgmt; 1047 __le32 reftag; 1048 __le16 apptag; 1049 __le16 appmask; 1050 }; 1051 1052 enum nvme_zone_mgmt_action { 1053 NVME_ZONE_CLOSE = 0x1, 1054 NVME_ZONE_FINISH = 0x2, 1055 NVME_ZONE_OPEN = 0x3, 1056 NVME_ZONE_RESET = 0x4, 1057 NVME_ZONE_OFFLINE = 0x5, 1058 NVME_ZONE_SET_DESC_EXT = 0x10, 1059 }; 1060 1061 struct nvme_zone_mgmt_send_cmd { 1062 __u8 opcode; 1063 __u8 flags; 1064 __u16 command_id; 1065 __le32 nsid; 1066 __le32 cdw2[2]; 1067 __le64 metadata; 1068 union nvme_data_ptr dptr; 1069 __le64 slba; 1070 __le32 cdw12; 1071 __u8 zsa; 1072 __u8 select_all; 1073 __u8 rsvd13[2]; 1074 __le32 cdw14[2]; 1075 }; 1076 1077 struct nvme_zone_mgmt_recv_cmd { 1078 __u8 opcode; 1079 __u8 flags; 1080 __u16 command_id; 1081 __le32 nsid; 1082 __le64 rsvd2[2]; 1083 union nvme_data_ptr dptr; 1084 __le64 slba; 1085 __le32 numd; 1086 __u8 zra; 1087 __u8 zrasf; 1088 __u8 pr; 1089 __u8 rsvd13; 1090 __le32 cdw14[2]; 1091 }; 1092 1093 enum { 1094 NVME_ZRA_ZONE_REPORT = 0, 1095 NVME_ZRASF_ZONE_REPORT_ALL = 0, 1096 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, 1097 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, 1098 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, 1099 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, 1100 NVME_ZRASF_ZONE_STATE_READONLY = 0x05, 1101 NVME_ZRASF_ZONE_STATE_FULL = 0x06, 1102 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, 1103 NVME_REPORT_ZONE_PARTIAL = 1, 1104 }; 1105 1106 /* Features */ 1107 1108 enum { 1109 NVME_TEMP_THRESH_MASK = 0xffff, 1110 NVME_TEMP_THRESH_SELECT_SHIFT = 16, 1111 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, 1112 }; 1113 1114 struct nvme_feat_auto_pst { 1115 __le64 entries[32]; 1116 }; 1117 1118 enum { 1119 NVME_HOST_MEM_ENABLE = (1 << 0), 1120 NVME_HOST_MEM_RETURN = (1 << 1), 1121 }; 1122 1123 struct nvme_feat_host_behavior { 1124 __u8 acre; 1125 __u8 etdas; 1126 __u8 lbafee; 1127 __u8 resv1[509]; 1128 }; 1129 1130 enum { 1131 NVME_ENABLE_ACRE = 1, 1132 NVME_ENABLE_LBAFEE = 1, 1133 }; 1134 1135 /* Admin commands */ 1136 1137 enum nvme_admin_opcode { 1138 nvme_admin_delete_sq = 0x00, 1139 nvme_admin_create_sq = 0x01, 1140 nvme_admin_get_log_page = 0x02, 1141 nvme_admin_delete_cq = 0x04, 1142 nvme_admin_create_cq = 0x05, 1143 nvme_admin_identify = 0x06, 1144 nvme_admin_abort_cmd = 0x08, 1145 nvme_admin_set_features = 0x09, 1146 nvme_admin_get_features = 0x0a, 1147 nvme_admin_async_event = 0x0c, 1148 nvme_admin_ns_mgmt = 0x0d, 1149 nvme_admin_activate_fw = 0x10, 1150 nvme_admin_download_fw = 0x11, 1151 nvme_admin_dev_self_test = 0x14, 1152 nvme_admin_ns_attach = 0x15, 1153 nvme_admin_keep_alive = 0x18, 1154 nvme_admin_directive_send = 0x19, 1155 nvme_admin_directive_recv = 0x1a, 1156 nvme_admin_virtual_mgmt = 0x1c, 1157 nvme_admin_nvme_mi_send = 0x1d, 1158 nvme_admin_nvme_mi_recv = 0x1e, 1159 nvme_admin_dbbuf = 0x7C, 1160 nvme_admin_format_nvm = 0x80, 1161 nvme_admin_security_send = 0x81, 1162 nvme_admin_security_recv = 0x82, 1163 nvme_admin_sanitize_nvm = 0x84, 1164 nvme_admin_get_lba_status = 0x86, 1165 nvme_admin_vendor_start = 0xC0, 1166 }; 1167 1168 #define nvme_admin_opcode_name(opcode) { opcode, #opcode } 1169 #define show_admin_opcode_name(val) \ 1170 __print_symbolic(val, \ 1171 nvme_admin_opcode_name(nvme_admin_delete_sq), \ 1172 nvme_admin_opcode_name(nvme_admin_create_sq), \ 1173 nvme_admin_opcode_name(nvme_admin_get_log_page), \ 1174 nvme_admin_opcode_name(nvme_admin_delete_cq), \ 1175 nvme_admin_opcode_name(nvme_admin_create_cq), \ 1176 nvme_admin_opcode_name(nvme_admin_identify), \ 1177 nvme_admin_opcode_name(nvme_admin_abort_cmd), \ 1178 nvme_admin_opcode_name(nvme_admin_set_features), \ 1179 nvme_admin_opcode_name(nvme_admin_get_features), \ 1180 nvme_admin_opcode_name(nvme_admin_async_event), \ 1181 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ 1182 nvme_admin_opcode_name(nvme_admin_activate_fw), \ 1183 nvme_admin_opcode_name(nvme_admin_download_fw), \ 1184 nvme_admin_opcode_name(nvme_admin_dev_self_test), \ 1185 nvme_admin_opcode_name(nvme_admin_ns_attach), \ 1186 nvme_admin_opcode_name(nvme_admin_keep_alive), \ 1187 nvme_admin_opcode_name(nvme_admin_directive_send), \ 1188 nvme_admin_opcode_name(nvme_admin_directive_recv), \ 1189 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \ 1190 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \ 1191 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \ 1192 nvme_admin_opcode_name(nvme_admin_dbbuf), \ 1193 nvme_admin_opcode_name(nvme_admin_format_nvm), \ 1194 nvme_admin_opcode_name(nvme_admin_security_send), \ 1195 nvme_admin_opcode_name(nvme_admin_security_recv), \ 1196 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ 1197 nvme_admin_opcode_name(nvme_admin_get_lba_status)) 1198 1199 enum { 1200 NVME_QUEUE_PHYS_CONTIG = (1 << 0), 1201 NVME_CQ_IRQ_ENABLED = (1 << 1), 1202 NVME_SQ_PRIO_URGENT = (0 << 1), 1203 NVME_SQ_PRIO_HIGH = (1 << 1), 1204 NVME_SQ_PRIO_MEDIUM = (2 << 1), 1205 NVME_SQ_PRIO_LOW = (3 << 1), 1206 NVME_FEAT_ARBITRATION = 0x01, 1207 NVME_FEAT_POWER_MGMT = 0x02, 1208 NVME_FEAT_LBA_RANGE = 0x03, 1209 NVME_FEAT_TEMP_THRESH = 0x04, 1210 NVME_FEAT_ERR_RECOVERY = 0x05, 1211 NVME_FEAT_VOLATILE_WC = 0x06, 1212 NVME_FEAT_NUM_QUEUES = 0x07, 1213 NVME_FEAT_IRQ_COALESCE = 0x08, 1214 NVME_FEAT_IRQ_CONFIG = 0x09, 1215 NVME_FEAT_WRITE_ATOMIC = 0x0a, 1216 NVME_FEAT_ASYNC_EVENT = 0x0b, 1217 NVME_FEAT_AUTO_PST = 0x0c, 1218 NVME_FEAT_HOST_MEM_BUF = 0x0d, 1219 NVME_FEAT_TIMESTAMP = 0x0e, 1220 NVME_FEAT_KATO = 0x0f, 1221 NVME_FEAT_HCTM = 0x10, 1222 NVME_FEAT_NOPSC = 0x11, 1223 NVME_FEAT_RRL = 0x12, 1224 NVME_FEAT_PLM_CONFIG = 0x13, 1225 NVME_FEAT_PLM_WINDOW = 0x14, 1226 NVME_FEAT_HOST_BEHAVIOR = 0x16, 1227 NVME_FEAT_SANITIZE = 0x17, 1228 NVME_FEAT_SW_PROGRESS = 0x80, 1229 NVME_FEAT_HOST_ID = 0x81, 1230 NVME_FEAT_RESV_MASK = 0x82, 1231 NVME_FEAT_RESV_PERSIST = 0x83, 1232 NVME_FEAT_WRITE_PROTECT = 0x84, 1233 NVME_FEAT_VENDOR_START = 0xC0, 1234 NVME_FEAT_VENDOR_END = 0xFF, 1235 NVME_LOG_ERROR = 0x01, 1236 NVME_LOG_SMART = 0x02, 1237 NVME_LOG_FW_SLOT = 0x03, 1238 NVME_LOG_CHANGED_NS = 0x04, 1239 NVME_LOG_CMD_EFFECTS = 0x05, 1240 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1241 NVME_LOG_TELEMETRY_HOST = 0x07, 1242 NVME_LOG_TELEMETRY_CTRL = 0x08, 1243 NVME_LOG_ENDURANCE_GROUP = 0x09, 1244 NVME_LOG_ANA = 0x0c, 1245 NVME_LOG_DISC = 0x70, 1246 NVME_LOG_RESERVATION = 0x80, 1247 NVME_FWACT_REPL = (0 << 3), 1248 NVME_FWACT_REPL_ACTV = (1 << 3), 1249 NVME_FWACT_ACTV = (2 << 3), 1250 }; 1251 1252 /* NVMe Namespace Write Protect State */ 1253 enum { 1254 NVME_NS_NO_WRITE_PROTECT = 0, 1255 NVME_NS_WRITE_PROTECT, 1256 NVME_NS_WRITE_PROTECT_POWER_CYCLE, 1257 NVME_NS_WRITE_PROTECT_PERMANENT, 1258 }; 1259 1260 #define NVME_MAX_CHANGED_NAMESPACES 1024 1261 1262 struct nvme_identify { 1263 __u8 opcode; 1264 __u8 flags; 1265 __u16 command_id; 1266 __le32 nsid; 1267 __u64 rsvd2[2]; 1268 union nvme_data_ptr dptr; 1269 __u8 cns; 1270 __u8 rsvd3; 1271 __le16 ctrlid; 1272 __u8 rsvd11[3]; 1273 __u8 csi; 1274 __u32 rsvd12[4]; 1275 }; 1276 1277 #define NVME_IDENTIFY_DATA_SIZE 4096 1278 1279 struct nvme_features { 1280 __u8 opcode; 1281 __u8 flags; 1282 __u16 command_id; 1283 __le32 nsid; 1284 __u64 rsvd2[2]; 1285 union nvme_data_ptr dptr; 1286 __le32 fid; 1287 __le32 dword11; 1288 __le32 dword12; 1289 __le32 dword13; 1290 __le32 dword14; 1291 __le32 dword15; 1292 }; 1293 1294 struct nvme_host_mem_buf_desc { 1295 __le64 addr; 1296 __le32 size; 1297 __u32 rsvd; 1298 }; 1299 1300 struct nvme_create_cq { 1301 __u8 opcode; 1302 __u8 flags; 1303 __u16 command_id; 1304 __u32 rsvd1[5]; 1305 __le64 prp1; 1306 __u64 rsvd8; 1307 __le16 cqid; 1308 __le16 qsize; 1309 __le16 cq_flags; 1310 __le16 irq_vector; 1311 __u32 rsvd12[4]; 1312 }; 1313 1314 struct nvme_create_sq { 1315 __u8 opcode; 1316 __u8 flags; 1317 __u16 command_id; 1318 __u32 rsvd1[5]; 1319 __le64 prp1; 1320 __u64 rsvd8; 1321 __le16 sqid; 1322 __le16 qsize; 1323 __le16 sq_flags; 1324 __le16 cqid; 1325 __u32 rsvd12[4]; 1326 }; 1327 1328 struct nvme_delete_queue { 1329 __u8 opcode; 1330 __u8 flags; 1331 __u16 command_id; 1332 __u32 rsvd1[9]; 1333 __le16 qid; 1334 __u16 rsvd10; 1335 __u32 rsvd11[5]; 1336 }; 1337 1338 struct nvme_abort_cmd { 1339 __u8 opcode; 1340 __u8 flags; 1341 __u16 command_id; 1342 __u32 rsvd1[9]; 1343 __le16 sqid; 1344 __u16 cid; 1345 __u32 rsvd11[5]; 1346 }; 1347 1348 struct nvme_download_firmware { 1349 __u8 opcode; 1350 __u8 flags; 1351 __u16 command_id; 1352 __u32 rsvd1[5]; 1353 union nvme_data_ptr dptr; 1354 __le32 numd; 1355 __le32 offset; 1356 __u32 rsvd12[4]; 1357 }; 1358 1359 struct nvme_format_cmd { 1360 __u8 opcode; 1361 __u8 flags; 1362 __u16 command_id; 1363 __le32 nsid; 1364 __u64 rsvd2[4]; 1365 __le32 cdw10; 1366 __u32 rsvd11[5]; 1367 }; 1368 1369 struct nvme_get_log_page_command { 1370 __u8 opcode; 1371 __u8 flags; 1372 __u16 command_id; 1373 __le32 nsid; 1374 __u64 rsvd2[2]; 1375 union nvme_data_ptr dptr; 1376 __u8 lid; 1377 __u8 lsp; /* upper 4 bits reserved */ 1378 __le16 numdl; 1379 __le16 numdu; 1380 __u16 rsvd11; 1381 union { 1382 struct { 1383 __le32 lpol; 1384 __le32 lpou; 1385 }; 1386 __le64 lpo; 1387 }; 1388 __u8 rsvd14[3]; 1389 __u8 csi; 1390 __u32 rsvd15; 1391 }; 1392 1393 struct nvme_directive_cmd { 1394 __u8 opcode; 1395 __u8 flags; 1396 __u16 command_id; 1397 __le32 nsid; 1398 __u64 rsvd2[2]; 1399 union nvme_data_ptr dptr; 1400 __le32 numd; 1401 __u8 doper; 1402 __u8 dtype; 1403 __le16 dspec; 1404 __u8 endir; 1405 __u8 tdtype; 1406 __u16 rsvd15; 1407 1408 __u32 rsvd16[3]; 1409 }; 1410 1411 /* 1412 * Fabrics subcommands. 1413 */ 1414 enum nvmf_fabrics_opcode { 1415 nvme_fabrics_command = 0x7f, 1416 }; 1417 1418 enum nvmf_capsule_command { 1419 nvme_fabrics_type_property_set = 0x00, 1420 nvme_fabrics_type_connect = 0x01, 1421 nvme_fabrics_type_property_get = 0x04, 1422 nvme_fabrics_type_auth_send = 0x05, 1423 nvme_fabrics_type_auth_receive = 0x06, 1424 }; 1425 1426 #define nvme_fabrics_type_name(type) { type, #type } 1427 #define show_fabrics_type_name(type) \ 1428 __print_symbolic(type, \ 1429 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ 1430 nvme_fabrics_type_name(nvme_fabrics_type_connect), \ 1431 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \ 1432 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \ 1433 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive)) 1434 1435 /* 1436 * If not fabrics command, fctype will be ignored. 1437 */ 1438 #define show_opcode_name(qid, opcode, fctype) \ 1439 ((opcode) == nvme_fabrics_command ? \ 1440 show_fabrics_type_name(fctype) : \ 1441 ((qid) ? \ 1442 show_nvm_opcode_name(opcode) : \ 1443 show_admin_opcode_name(opcode))) 1444 1445 struct nvmf_common_command { 1446 __u8 opcode; 1447 __u8 resv1; 1448 __u16 command_id; 1449 __u8 fctype; 1450 __u8 resv2[35]; 1451 __u8 ts[24]; 1452 }; 1453 1454 /* 1455 * The legal cntlid range a NVMe Target will provide. 1456 * Note that cntlid of value 0 is considered illegal in the fabrics world. 1457 * Devices based on earlier specs did not have the subsystem concept; 1458 * therefore, those devices had their cntlid value set to 0 as a result. 1459 */ 1460 #define NVME_CNTLID_MIN 1 1461 #define NVME_CNTLID_MAX 0xffef 1462 #define NVME_CNTLID_DYNAMIC 0xffff 1463 1464 #define MAX_DISC_LOGS 255 1465 1466 /* Discovery log page entry flags (EFLAGS): */ 1467 enum { 1468 NVME_DISC_EFLAGS_EPCSD = (1 << 1), 1469 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0), 1470 }; 1471 1472 /* Discovery log page entry */ 1473 struct nvmf_disc_rsp_page_entry { 1474 __u8 trtype; 1475 __u8 adrfam; 1476 __u8 subtype; 1477 __u8 treq; 1478 __le16 portid; 1479 __le16 cntlid; 1480 __le16 asqsz; 1481 __le16 eflags; 1482 __u8 resv10[20]; 1483 char trsvcid[NVMF_TRSVCID_SIZE]; 1484 __u8 resv64[192]; 1485 char subnqn[NVMF_NQN_FIELD_LEN]; 1486 char traddr[NVMF_TRADDR_SIZE]; 1487 union tsas { 1488 char common[NVMF_TSAS_SIZE]; 1489 struct rdma { 1490 __u8 qptype; 1491 __u8 prtype; 1492 __u8 cms; 1493 __u8 resv3[5]; 1494 __u16 pkey; 1495 __u8 resv10[246]; 1496 } rdma; 1497 struct tcp { 1498 __u8 sectype; 1499 } tcp; 1500 } tsas; 1501 }; 1502 1503 /* Discovery log page header */ 1504 struct nvmf_disc_rsp_page_hdr { 1505 __le64 genctr; 1506 __le64 numrec; 1507 __le16 recfmt; 1508 __u8 resv14[1006]; 1509 struct nvmf_disc_rsp_page_entry entries[]; 1510 }; 1511 1512 enum { 1513 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), 1514 }; 1515 1516 struct nvmf_connect_command { 1517 __u8 opcode; 1518 __u8 resv1; 1519 __u16 command_id; 1520 __u8 fctype; 1521 __u8 resv2[19]; 1522 union nvme_data_ptr dptr; 1523 __le16 recfmt; 1524 __le16 qid; 1525 __le16 sqsize; 1526 __u8 cattr; 1527 __u8 resv3; 1528 __le32 kato; 1529 __u8 resv4[12]; 1530 }; 1531 1532 enum { 1533 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18), 1534 NVME_CONNECT_AUTHREQ_ATR = (1U << 17), 1535 }; 1536 1537 struct nvmf_connect_data { 1538 uuid_t hostid; 1539 __le16 cntlid; 1540 char resv4[238]; 1541 char subsysnqn[NVMF_NQN_FIELD_LEN]; 1542 char hostnqn[NVMF_NQN_FIELD_LEN]; 1543 char resv5[256]; 1544 }; 1545 1546 struct nvmf_property_set_command { 1547 __u8 opcode; 1548 __u8 resv1; 1549 __u16 command_id; 1550 __u8 fctype; 1551 __u8 resv2[35]; 1552 __u8 attrib; 1553 __u8 resv3[3]; 1554 __le32 offset; 1555 __le64 value; 1556 __u8 resv4[8]; 1557 }; 1558 1559 struct nvmf_property_get_command { 1560 __u8 opcode; 1561 __u8 resv1; 1562 __u16 command_id; 1563 __u8 fctype; 1564 __u8 resv2[35]; 1565 __u8 attrib; 1566 __u8 resv3[3]; 1567 __le32 offset; 1568 __u8 resv4[16]; 1569 }; 1570 1571 struct nvmf_auth_common_command { 1572 __u8 opcode; 1573 __u8 resv1; 1574 __u16 command_id; 1575 __u8 fctype; 1576 __u8 resv2[19]; 1577 union nvme_data_ptr dptr; 1578 __u8 resv3; 1579 __u8 spsp0; 1580 __u8 spsp1; 1581 __u8 secp; 1582 __le32 al_tl; 1583 __u8 resv4[16]; 1584 }; 1585 1586 struct nvmf_auth_send_command { 1587 __u8 opcode; 1588 __u8 resv1; 1589 __u16 command_id; 1590 __u8 fctype; 1591 __u8 resv2[19]; 1592 union nvme_data_ptr dptr; 1593 __u8 resv3; 1594 __u8 spsp0; 1595 __u8 spsp1; 1596 __u8 secp; 1597 __le32 tl; 1598 __u8 resv4[16]; 1599 }; 1600 1601 struct nvmf_auth_receive_command { 1602 __u8 opcode; 1603 __u8 resv1; 1604 __u16 command_id; 1605 __u8 fctype; 1606 __u8 resv2[19]; 1607 union nvme_data_ptr dptr; 1608 __u8 resv3; 1609 __u8 spsp0; 1610 __u8 spsp1; 1611 __u8 secp; 1612 __le32 al; 1613 __u8 resv4[16]; 1614 }; 1615 1616 /* Value for secp */ 1617 enum { 1618 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9, 1619 }; 1620 1621 /* Defined value for auth_type */ 1622 enum { 1623 NVME_AUTH_COMMON_MESSAGES = 0x00, 1624 NVME_AUTH_DHCHAP_MESSAGES = 0x01, 1625 }; 1626 1627 /* Defined messages for auth_id */ 1628 enum { 1629 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00, 1630 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01, 1631 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02, 1632 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03, 1633 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04, 1634 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0, 1635 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1, 1636 }; 1637 1638 struct nvmf_auth_dhchap_protocol_descriptor { 1639 __u8 authid; 1640 __u8 rsvd; 1641 __u8 halen; 1642 __u8 dhlen; 1643 __u8 idlist[60]; 1644 }; 1645 1646 enum { 1647 NVME_AUTH_DHCHAP_AUTH_ID = 0x01, 1648 }; 1649 1650 /* Defined hash functions for DH-HMAC-CHAP authentication */ 1651 enum { 1652 NVME_AUTH_HASH_SHA256 = 0x01, 1653 NVME_AUTH_HASH_SHA384 = 0x02, 1654 NVME_AUTH_HASH_SHA512 = 0x03, 1655 NVME_AUTH_HASH_INVALID = 0xff, 1656 }; 1657 1658 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */ 1659 enum { 1660 NVME_AUTH_DHGROUP_NULL = 0x00, 1661 NVME_AUTH_DHGROUP_2048 = 0x01, 1662 NVME_AUTH_DHGROUP_3072 = 0x02, 1663 NVME_AUTH_DHGROUP_4096 = 0x03, 1664 NVME_AUTH_DHGROUP_6144 = 0x04, 1665 NVME_AUTH_DHGROUP_8192 = 0x05, 1666 NVME_AUTH_DHGROUP_INVALID = 0xff, 1667 }; 1668 1669 union nvmf_auth_protocol { 1670 struct nvmf_auth_dhchap_protocol_descriptor dhchap; 1671 }; 1672 1673 struct nvmf_auth_dhchap_negotiate_data { 1674 __u8 auth_type; 1675 __u8 auth_id; 1676 __le16 rsvd; 1677 __le16 t_id; 1678 __u8 sc_c; 1679 __u8 napd; 1680 union nvmf_auth_protocol auth_protocol[]; 1681 }; 1682 1683 struct nvmf_auth_dhchap_challenge_data { 1684 __u8 auth_type; 1685 __u8 auth_id; 1686 __u16 rsvd1; 1687 __le16 t_id; 1688 __u8 hl; 1689 __u8 rsvd2; 1690 __u8 hashid; 1691 __u8 dhgid; 1692 __le16 dhvlen; 1693 __le32 seqnum; 1694 /* 'hl' bytes of challenge value */ 1695 __u8 cval[]; 1696 /* followed by 'dhvlen' bytes of DH value */ 1697 }; 1698 1699 struct nvmf_auth_dhchap_reply_data { 1700 __u8 auth_type; 1701 __u8 auth_id; 1702 __le16 rsvd1; 1703 __le16 t_id; 1704 __u8 hl; 1705 __u8 rsvd2; 1706 __u8 cvalid; 1707 __u8 rsvd3; 1708 __le16 dhvlen; 1709 __le32 seqnum; 1710 /* 'hl' bytes of response data */ 1711 __u8 rval[]; 1712 /* followed by 'hl' bytes of Challenge value */ 1713 /* followed by 'dhvlen' bytes of DH value */ 1714 }; 1715 1716 enum { 1717 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0), 1718 }; 1719 1720 struct nvmf_auth_dhchap_success1_data { 1721 __u8 auth_type; 1722 __u8 auth_id; 1723 __le16 rsvd1; 1724 __le16 t_id; 1725 __u8 hl; 1726 __u8 rsvd2; 1727 __u8 rvalid; 1728 __u8 rsvd3[7]; 1729 /* 'hl' bytes of response value */ 1730 __u8 rval[]; 1731 }; 1732 1733 struct nvmf_auth_dhchap_success2_data { 1734 __u8 auth_type; 1735 __u8 auth_id; 1736 __le16 rsvd1; 1737 __le16 t_id; 1738 __u8 rsvd2[10]; 1739 }; 1740 1741 struct nvmf_auth_dhchap_failure_data { 1742 __u8 auth_type; 1743 __u8 auth_id; 1744 __le16 rsvd1; 1745 __le16 t_id; 1746 __u8 rescode; 1747 __u8 rescode_exp; 1748 }; 1749 1750 enum { 1751 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01, 1752 }; 1753 1754 enum { 1755 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01, 1756 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02, 1757 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03, 1758 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04, 1759 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05, 1760 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06, 1761 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07, 1762 }; 1763 1764 1765 struct nvme_dbbuf { 1766 __u8 opcode; 1767 __u8 flags; 1768 __u16 command_id; 1769 __u32 rsvd1[5]; 1770 __le64 prp1; 1771 __le64 prp2; 1772 __u32 rsvd12[6]; 1773 }; 1774 1775 struct streams_directive_params { 1776 __le16 msl; 1777 __le16 nssa; 1778 __le16 nsso; 1779 __u8 rsvd[10]; 1780 __le32 sws; 1781 __le16 sgs; 1782 __le16 nsa; 1783 __le16 nso; 1784 __u8 rsvd2[6]; 1785 }; 1786 1787 struct nvme_command { 1788 union { 1789 struct nvme_common_command common; 1790 struct nvme_rw_command rw; 1791 struct nvme_identify identify; 1792 struct nvme_features features; 1793 struct nvme_create_cq create_cq; 1794 struct nvme_create_sq create_sq; 1795 struct nvme_delete_queue delete_queue; 1796 struct nvme_download_firmware dlfw; 1797 struct nvme_format_cmd format; 1798 struct nvme_dsm_cmd dsm; 1799 struct nvme_write_zeroes_cmd write_zeroes; 1800 struct nvme_zone_mgmt_send_cmd zms; 1801 struct nvme_zone_mgmt_recv_cmd zmr; 1802 struct nvme_abort_cmd abort; 1803 struct nvme_get_log_page_command get_log_page; 1804 struct nvmf_common_command fabrics; 1805 struct nvmf_connect_command connect; 1806 struct nvmf_property_set_command prop_set; 1807 struct nvmf_property_get_command prop_get; 1808 struct nvmf_auth_common_command auth_common; 1809 struct nvmf_auth_send_command auth_send; 1810 struct nvmf_auth_receive_command auth_receive; 1811 struct nvme_dbbuf dbbuf; 1812 struct nvme_directive_cmd directive; 1813 }; 1814 }; 1815 1816 static inline bool nvme_is_fabrics(const struct nvme_command *cmd) 1817 { 1818 return cmd->common.opcode == nvme_fabrics_command; 1819 } 1820 1821 struct nvme_error_slot { 1822 __le64 error_count; 1823 __le16 sqid; 1824 __le16 cmdid; 1825 __le16 status_field; 1826 __le16 param_error_location; 1827 __le64 lba; 1828 __le32 nsid; 1829 __u8 vs; 1830 __u8 resv[3]; 1831 __le64 cs; 1832 __u8 resv2[24]; 1833 }; 1834 1835 static inline bool nvme_is_write(const struct nvme_command *cmd) 1836 { 1837 /* 1838 * What a mess... 1839 * 1840 * Why can't we simply have a Fabrics In and Fabrics out command? 1841 */ 1842 if (unlikely(nvme_is_fabrics(cmd))) 1843 return cmd->fabrics.fctype & 1; 1844 return cmd->common.opcode & 1; 1845 } 1846 1847 enum { 1848 /* 1849 * Generic Command Status: 1850 */ 1851 NVME_SC_SUCCESS = 0x0, 1852 NVME_SC_INVALID_OPCODE = 0x1, 1853 NVME_SC_INVALID_FIELD = 0x2, 1854 NVME_SC_CMDID_CONFLICT = 0x3, 1855 NVME_SC_DATA_XFER_ERROR = 0x4, 1856 NVME_SC_POWER_LOSS = 0x5, 1857 NVME_SC_INTERNAL = 0x6, 1858 NVME_SC_ABORT_REQ = 0x7, 1859 NVME_SC_ABORT_QUEUE = 0x8, 1860 NVME_SC_FUSED_FAIL = 0x9, 1861 NVME_SC_FUSED_MISSING = 0xa, 1862 NVME_SC_INVALID_NS = 0xb, 1863 NVME_SC_CMD_SEQ_ERROR = 0xc, 1864 NVME_SC_SGL_INVALID_LAST = 0xd, 1865 NVME_SC_SGL_INVALID_COUNT = 0xe, 1866 NVME_SC_SGL_INVALID_DATA = 0xf, 1867 NVME_SC_SGL_INVALID_METADATA = 0x10, 1868 NVME_SC_SGL_INVALID_TYPE = 0x11, 1869 NVME_SC_CMB_INVALID_USE = 0x12, 1870 NVME_SC_PRP_INVALID_OFFSET = 0x13, 1871 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, 1872 NVME_SC_OP_DENIED = 0x15, 1873 NVME_SC_SGL_INVALID_OFFSET = 0x16, 1874 NVME_SC_RESERVED = 0x17, 1875 NVME_SC_HOST_ID_INCONSIST = 0x18, 1876 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, 1877 NVME_SC_KA_TIMEOUT_INVALID = 0x1A, 1878 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, 1879 NVME_SC_SANITIZE_FAILED = 0x1C, 1880 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, 1881 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, 1882 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, 1883 NVME_SC_NS_WRITE_PROTECTED = 0x20, 1884 NVME_SC_CMD_INTERRUPTED = 0x21, 1885 NVME_SC_TRANSIENT_TR_ERR = 0x22, 1886 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24, 1887 NVME_SC_INVALID_IO_CMD_SET = 0x2C, 1888 1889 NVME_SC_LBA_RANGE = 0x80, 1890 NVME_SC_CAP_EXCEEDED = 0x81, 1891 NVME_SC_NS_NOT_READY = 0x82, 1892 NVME_SC_RESERVATION_CONFLICT = 0x83, 1893 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 1894 1895 /* 1896 * Command Specific Status: 1897 */ 1898 NVME_SC_CQ_INVALID = 0x100, 1899 NVME_SC_QID_INVALID = 0x101, 1900 NVME_SC_QUEUE_SIZE = 0x102, 1901 NVME_SC_ABORT_LIMIT = 0x103, 1902 NVME_SC_ABORT_MISSING = 0x104, 1903 NVME_SC_ASYNC_LIMIT = 0x105, 1904 NVME_SC_FIRMWARE_SLOT = 0x106, 1905 NVME_SC_FIRMWARE_IMAGE = 0x107, 1906 NVME_SC_INVALID_VECTOR = 0x108, 1907 NVME_SC_INVALID_LOG_PAGE = 0x109, 1908 NVME_SC_INVALID_FORMAT = 0x10a, 1909 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, 1910 NVME_SC_INVALID_QUEUE = 0x10c, 1911 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, 1912 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, 1913 NVME_SC_FEATURE_NOT_PER_NS = 0x10f, 1914 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, 1915 NVME_SC_FW_NEEDS_RESET = 0x111, 1916 NVME_SC_FW_NEEDS_MAX_TIME = 0x112, 1917 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, 1918 NVME_SC_OVERLAPPING_RANGE = 0x114, 1919 NVME_SC_NS_INSUFFICIENT_CAP = 0x115, 1920 NVME_SC_NS_ID_UNAVAILABLE = 0x116, 1921 NVME_SC_NS_ALREADY_ATTACHED = 0x118, 1922 NVME_SC_NS_IS_PRIVATE = 0x119, 1923 NVME_SC_NS_NOT_ATTACHED = 0x11a, 1924 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, 1925 NVME_SC_CTRL_LIST_INVALID = 0x11c, 1926 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, 1927 NVME_SC_BP_WRITE_PROHIBITED = 0x11e, 1928 NVME_SC_CTRL_ID_INVALID = 0x11f, 1929 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, 1930 NVME_SC_CTRL_RES_NUM_INVALID = 0x121, 1931 NVME_SC_RES_ID_INVALID = 0x122, 1932 NVME_SC_PMR_SAN_PROHIBITED = 0x123, 1933 NVME_SC_ANA_GROUP_ID_INVALID = 0x124, 1934 NVME_SC_ANA_ATTACH_FAILED = 0x125, 1935 1936 /* 1937 * I/O Command Set Specific - NVM commands: 1938 */ 1939 NVME_SC_BAD_ATTRIBUTES = 0x180, 1940 NVME_SC_INVALID_PI = 0x181, 1941 NVME_SC_READ_ONLY = 0x182, 1942 NVME_SC_ONCS_NOT_SUPPORTED = 0x183, 1943 1944 /* 1945 * I/O Command Set Specific - Fabrics commands: 1946 */ 1947 NVME_SC_CONNECT_FORMAT = 0x180, 1948 NVME_SC_CONNECT_CTRL_BUSY = 0x181, 1949 NVME_SC_CONNECT_INVALID_PARAM = 0x182, 1950 NVME_SC_CONNECT_RESTART_DISC = 0x183, 1951 NVME_SC_CONNECT_INVALID_HOST = 0x184, 1952 1953 NVME_SC_DISCOVERY_RESTART = 0x190, 1954 NVME_SC_AUTH_REQUIRED = 0x191, 1955 1956 /* 1957 * I/O Command Set Specific - Zoned commands: 1958 */ 1959 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, 1960 NVME_SC_ZONE_FULL = 0x1b9, 1961 NVME_SC_ZONE_READ_ONLY = 0x1ba, 1962 NVME_SC_ZONE_OFFLINE = 0x1bb, 1963 NVME_SC_ZONE_INVALID_WRITE = 0x1bc, 1964 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, 1965 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, 1966 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, 1967 1968 /* 1969 * Media and Data Integrity Errors: 1970 */ 1971 NVME_SC_WRITE_FAULT = 0x280, 1972 NVME_SC_READ_ERROR = 0x281, 1973 NVME_SC_GUARD_CHECK = 0x282, 1974 NVME_SC_APPTAG_CHECK = 0x283, 1975 NVME_SC_REFTAG_CHECK = 0x284, 1976 NVME_SC_COMPARE_FAILED = 0x285, 1977 NVME_SC_ACCESS_DENIED = 0x286, 1978 NVME_SC_UNWRITTEN_BLOCK = 0x287, 1979 1980 /* 1981 * Path-related Errors: 1982 */ 1983 NVME_SC_INTERNAL_PATH_ERROR = 0x300, 1984 NVME_SC_ANA_PERSISTENT_LOSS = 0x301, 1985 NVME_SC_ANA_INACCESSIBLE = 0x302, 1986 NVME_SC_ANA_TRANSITION = 0x303, 1987 NVME_SC_CTRL_PATH_ERROR = 0x360, 1988 NVME_SC_HOST_PATH_ERROR = 0x370, 1989 NVME_SC_HOST_ABORTED_CMD = 0x371, 1990 1991 NVME_SC_CRD = 0x1800, 1992 NVME_SC_MORE = 0x2000, 1993 NVME_SC_DNR = 0x4000, 1994 }; 1995 1996 struct nvme_completion { 1997 /* 1998 * Used by Admin and Fabrics commands to return data: 1999 */ 2000 union nvme_result { 2001 __le16 u16; 2002 __le32 u32; 2003 __le64 u64; 2004 } result; 2005 __le16 sq_head; /* how much of this queue may be reclaimed */ 2006 __le16 sq_id; /* submission queue that generated this entry */ 2007 __u16 command_id; /* of the command which completed */ 2008 __le16 status; /* did the command fail, and if so, why? */ 2009 }; 2010 2011 #define NVME_VS(major, minor, tertiary) \ 2012 (((major) << 16) | ((minor) << 8) | (tertiary)) 2013 2014 #define NVME_MAJOR(ver) ((ver) >> 16) 2015 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) 2016 #define NVME_TERTIARY(ver) ((ver) & 0xff) 2017 2018 #endif /* _LINUX_NVME_H */ 2019