1 /* 2 * Definitions for the NVM Express interface 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _LINUX_NVME_H 16 #define _LINUX_NVME_H 17 18 #include <uapi/linux/nvme.h> 19 #include <linux/pci.h> 20 #include <linux/kref.h> 21 #include <linux/blk-mq.h> 22 23 struct nvme_bar { 24 __u64 cap; /* Controller Capabilities */ 25 __u32 vs; /* Version */ 26 __u32 intms; /* Interrupt Mask Set */ 27 __u32 intmc; /* Interrupt Mask Clear */ 28 __u32 cc; /* Controller Configuration */ 29 __u32 rsvd1; /* Reserved */ 30 __u32 csts; /* Controller Status */ 31 __u32 rsvd2; /* Reserved */ 32 __u32 aqa; /* Admin Queue Attributes */ 33 __u64 asq; /* Admin SQ Base Address */ 34 __u64 acq; /* Admin CQ Base Address */ 35 }; 36 37 #define NVME_CAP_MQES(cap) ((cap) & 0xffff) 38 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) 39 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) 40 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) 41 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) 42 43 enum { 44 NVME_CC_ENABLE = 1 << 0, 45 NVME_CC_CSS_NVM = 0 << 4, 46 NVME_CC_MPS_SHIFT = 7, 47 NVME_CC_ARB_RR = 0 << 11, 48 NVME_CC_ARB_WRRU = 1 << 11, 49 NVME_CC_ARB_VS = 7 << 11, 50 NVME_CC_SHN_NONE = 0 << 14, 51 NVME_CC_SHN_NORMAL = 1 << 14, 52 NVME_CC_SHN_ABRUPT = 2 << 14, 53 NVME_CC_SHN_MASK = 3 << 14, 54 NVME_CC_IOSQES = 6 << 16, 55 NVME_CC_IOCQES = 4 << 20, 56 NVME_CSTS_RDY = 1 << 0, 57 NVME_CSTS_CFS = 1 << 1, 58 NVME_CSTS_SHST_NORMAL = 0 << 2, 59 NVME_CSTS_SHST_OCCUR = 1 << 2, 60 NVME_CSTS_SHST_CMPLT = 2 << 2, 61 NVME_CSTS_SHST_MASK = 3 << 2, 62 }; 63 64 extern unsigned char nvme_io_timeout; 65 #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) 66 67 /* 68 * Represents an NVM Express device. Each nvme_dev is a PCI function. 69 */ 70 struct nvme_dev { 71 struct list_head node; 72 struct nvme_queue **queues; 73 struct request_queue *admin_q; 74 struct blk_mq_tag_set tagset; 75 struct blk_mq_tag_set admin_tagset; 76 u32 __iomem *dbs; 77 struct device *dev; 78 struct dma_pool *prp_page_pool; 79 struct dma_pool *prp_small_pool; 80 int instance; 81 unsigned queue_count; 82 unsigned online_queues; 83 unsigned max_qid; 84 int q_depth; 85 u32 db_stride; 86 u32 ctrl_config; 87 struct msix_entry *entry; 88 struct nvme_bar __iomem *bar; 89 struct list_head namespaces; 90 struct kref kref; 91 struct device *device; 92 work_func_t reset_workfn; 93 struct work_struct reset_work; 94 struct work_struct probe_work; 95 struct work_struct scan_work; 96 char name[12]; 97 char serial[20]; 98 char model[40]; 99 char firmware_rev[8]; 100 u32 max_hw_sectors; 101 u32 stripe_size; 102 u32 page_size; 103 u16 oncs; 104 u16 abort_limit; 105 u8 event_limit; 106 u8 vwc; 107 }; 108 109 /* 110 * An NVM Express namespace is equivalent to a SCSI LUN 111 */ 112 struct nvme_ns { 113 struct list_head list; 114 115 struct nvme_dev *dev; 116 struct request_queue *queue; 117 struct gendisk *disk; 118 119 unsigned ns_id; 120 int lba_shift; 121 u16 ms; 122 bool ext; 123 u8 pi_type; 124 u64 mode_select_num_blocks; 125 u32 mode_select_block_len; 126 }; 127 128 /* 129 * The nvme_iod describes the data in an I/O, including the list of PRP 130 * entries. You can't see it in this data structure because C doesn't let 131 * me express that. Use nvme_alloc_iod to ensure there's enough space 132 * allocated to store the PRP list. 133 */ 134 struct nvme_iod { 135 unsigned long private; /* For the use of the submitter of the I/O */ 136 int npages; /* In the PRP list. 0 means small pool in use */ 137 int offset; /* Of PRP list */ 138 int nents; /* Used in scatterlist */ 139 int length; /* Of data, in bytes */ 140 dma_addr_t first_dma; 141 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ 142 struct scatterlist sg[0]; 143 }; 144 145 static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) 146 { 147 return (sector >> (ns->lba_shift - 9)); 148 } 149 150 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 151 void *buf, unsigned bufflen); 152 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, 153 void *buffer, void __user *ubuffer, unsigned bufflen, 154 u32 *result, unsigned timeout); 155 int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id); 156 int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid, 157 struct nvme_id_ns **id); 158 int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log); 159 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, 160 dma_addr_t dma_addr, u32 *result); 161 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, 162 dma_addr_t dma_addr, u32 *result); 163 164 struct sg_io_hdr; 165 166 int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr); 167 int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg); 168 int nvme_sg_get_version_num(int __user *ip); 169 170 #endif /* _LINUX_NVME_H */ 171