1 /* 2 * Copyright (C) ST Ericsson SA 2011 3 * 4 * License Terms: GNU General Public License v2 5 * 6 * STE Ux500 PRCMU API 7 */ 8 #ifndef __MACH_PRCMU_H 9 #define __MACH_PRCMU_H 10 11 #include <linux/interrupt.h> 12 #include <linux/notifier.h> 13 #include <linux/err.h> 14 15 /* Offset for the firmware version within the TCPM */ 16 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4 17 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8 18 19 /* PRCMU Wakeup defines */ 20 enum prcmu_wakeup_index { 21 PRCMU_WAKEUP_INDEX_RTC, 22 PRCMU_WAKEUP_INDEX_RTT0, 23 PRCMU_WAKEUP_INDEX_RTT1, 24 PRCMU_WAKEUP_INDEX_HSI0, 25 PRCMU_WAKEUP_INDEX_HSI1, 26 PRCMU_WAKEUP_INDEX_USB, 27 PRCMU_WAKEUP_INDEX_ABB, 28 PRCMU_WAKEUP_INDEX_ABB_FIFO, 29 PRCMU_WAKEUP_INDEX_ARM, 30 PRCMU_WAKEUP_INDEX_CD_IRQ, 31 NUM_PRCMU_WAKEUP_INDICES 32 }; 33 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) 34 35 /* EPOD (power domain) IDs */ 36 37 /* 38 * DB8500 EPODs 39 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP 40 * - EPOD_ID_SVAPIPE: power domain for SVA pipe 41 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP 42 * - EPOD_ID_SIAPIPE: power domain for SIA pipe 43 * - EPOD_ID_SGA: power domain for SGA 44 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE 45 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 46 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 47 * - NUM_EPOD_ID: number of power domains 48 * 49 * TODO: These should be prefixed. 50 */ 51 #define EPOD_ID_SVAMMDSP 0 52 #define EPOD_ID_SVAPIPE 1 53 #define EPOD_ID_SIAMMDSP 2 54 #define EPOD_ID_SIAPIPE 3 55 #define EPOD_ID_SGA 4 56 #define EPOD_ID_B2R2_MCDE 5 57 #define EPOD_ID_ESRAM12 6 58 #define EPOD_ID_ESRAM34 7 59 #define NUM_EPOD_ID 8 60 61 /* 62 * state definition for EPOD (power domain) 63 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 64 * - EPOD_STATE_OFF: The EPOD is switched off 65 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in 66 * retention 67 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off 68 * - EPOD_STATE_ON: Same as above, but with clock enabled 69 */ 70 #define EPOD_STATE_NO_CHANGE 0x00 71 #define EPOD_STATE_OFF 0x01 72 #define EPOD_STATE_RAMRET 0x02 73 #define EPOD_STATE_ON_CLK_OFF 0x03 74 #define EPOD_STATE_ON 0x04 75 76 /* 77 * CLKOUT sources 78 */ 79 #define PRCMU_CLKSRC_CLK38M 0x00 80 #define PRCMU_CLKSRC_ACLK 0x01 81 #define PRCMU_CLKSRC_SYSCLK 0x02 82 #define PRCMU_CLKSRC_LCDCLK 0x03 83 #define PRCMU_CLKSRC_SDMMCCLK 0x04 84 #define PRCMU_CLKSRC_TVCLK 0x05 85 #define PRCMU_CLKSRC_TIMCLK 0x06 86 #define PRCMU_CLKSRC_CLK009 0x07 87 /* These are only valid for CLKOUT1: */ 88 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 89 #define PRCMU_CLKSRC_I2CCLK 0x41 90 #define PRCMU_CLKSRC_MSP02CLK 0x42 91 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 92 #define PRCMU_CLKSRC_HSIRXCLK 0x44 93 #define PRCMU_CLKSRC_HSITXCLK 0x45 94 #define PRCMU_CLKSRC_ARMCLKFIX 0x46 95 #define PRCMU_CLKSRC_HDMICLK 0x47 96 97 /* 98 * Clock identifiers. 99 */ 100 enum prcmu_clock { 101 PRCMU_SGACLK, 102 PRCMU_UARTCLK, 103 PRCMU_MSP02CLK, 104 PRCMU_MSP1CLK, 105 PRCMU_I2CCLK, 106 PRCMU_SDMMCCLK, 107 PRCMU_SPARE1CLK, 108 PRCMU_SLIMCLK, 109 PRCMU_PER1CLK, 110 PRCMU_PER2CLK, 111 PRCMU_PER3CLK, 112 PRCMU_PER5CLK, 113 PRCMU_PER6CLK, 114 PRCMU_PER7CLK, 115 PRCMU_LCDCLK, 116 PRCMU_BMLCLK, 117 PRCMU_HSITXCLK, 118 PRCMU_HSIRXCLK, 119 PRCMU_HDMICLK, 120 PRCMU_APEATCLK, 121 PRCMU_APETRACECLK, 122 PRCMU_MCDECLK, 123 PRCMU_IPI2CCLK, 124 PRCMU_DSIALTCLK, 125 PRCMU_DMACLK, 126 PRCMU_B2R2CLK, 127 PRCMU_TVCLK, 128 PRCMU_SSPCLK, 129 PRCMU_RNGCLK, 130 PRCMU_UICCCLK, 131 PRCMU_PWMCLK, 132 PRCMU_IRDACLK, 133 PRCMU_IRRCCLK, 134 PRCMU_SIACLK, 135 PRCMU_SVACLK, 136 PRCMU_ACLK, 137 PRCMU_NUM_REG_CLOCKS, 138 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, 139 PRCMU_CDCLK, 140 PRCMU_TIMCLK, 141 PRCMU_PLLSOC0, 142 PRCMU_PLLSOC1, 143 PRCMU_ARMSS, 144 PRCMU_PLLDDR, 145 PRCMU_PLLDSI, 146 PRCMU_DSI0CLK, 147 PRCMU_DSI1CLK, 148 PRCMU_DSI0ESCCLK, 149 PRCMU_DSI1ESCCLK, 150 PRCMU_DSI2ESCCLK, 151 }; 152 153 /** 154 * enum prcmu_wdog_id - PRCMU watchdog IDs 155 * @PRCMU_WDOG_ALL: use all timers 156 * @PRCMU_WDOG_CPU1: use first CPU timer only 157 * @PRCMU_WDOG_CPU2: use second CPU timer conly 158 */ 159 enum prcmu_wdog_id { 160 PRCMU_WDOG_ALL = 0x00, 161 PRCMU_WDOG_CPU1 = 0x01, 162 PRCMU_WDOG_CPU2 = 0x02, 163 }; 164 165 /** 166 * enum ape_opp - APE OPP states definition 167 * @APE_OPP_INIT: 168 * @APE_NO_CHANGE: The APE operating point is unchanged 169 * @APE_100_OPP: The new APE operating point is ape100opp 170 * @APE_50_OPP: 50% 171 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. 172 */ 173 enum ape_opp { 174 APE_OPP_INIT = 0x00, 175 APE_NO_CHANGE = 0x01, 176 APE_100_OPP = 0x02, 177 APE_50_OPP = 0x03, 178 APE_50_PARTLY_25_OPP = 0xFF, 179 }; 180 181 /** 182 * enum arm_opp - ARM OPP states definition 183 * @ARM_OPP_INIT: 184 * @ARM_NO_CHANGE: The ARM operating point is unchanged 185 * @ARM_100_OPP: The new ARM operating point is arm100opp 186 * @ARM_50_OPP: The new ARM operating point is arm50opp 187 * @ARM_MAX_OPP: Operating point is "max" (more than 100) 188 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 189 * @ARM_EXTCLK: The new ARM operating point is armExtClk 190 */ 191 enum arm_opp { 192 ARM_OPP_INIT = 0x00, 193 ARM_NO_CHANGE = 0x01, 194 ARM_100_OPP = 0x02, 195 ARM_50_OPP = 0x03, 196 ARM_MAX_OPP = 0x04, 197 ARM_MAX_FREQ100OPP = 0x05, 198 ARM_EXTCLK = 0x07 199 }; 200 201 /** 202 * enum ddr_opp - DDR OPP states definition 203 * @DDR_100_OPP: The new DDR operating point is ddr100opp 204 * @DDR_50_OPP: The new DDR operating point is ddr50opp 205 * @DDR_25_OPP: The new DDR operating point is ddr25opp 206 */ 207 enum ddr_opp { 208 DDR_100_OPP = 0x00, 209 DDR_50_OPP = 0x01, 210 DDR_25_OPP = 0x02, 211 }; 212 213 /* 214 * Definitions for controlling ESRAM0 in deep sleep. 215 */ 216 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 217 #define ESRAM0_DEEP_SLEEP_STATE_RET 2 218 219 /** 220 * enum ddr_pwrst - DDR power states definition 221 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged 222 * @DDR_PWR_STATE_ON: 223 * @DDR_PWR_STATE_OFFLOWLAT: 224 * @DDR_PWR_STATE_OFFHIGHLAT: 225 */ 226 enum ddr_pwrst { 227 DDR_PWR_STATE_UNCHANGED = 0x00, 228 DDR_PWR_STATE_ON = 0x01, 229 DDR_PWR_STATE_OFFLOWLAT = 0x02, 230 DDR_PWR_STATE_OFFHIGHLAT = 0x03 231 }; 232 233 #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4 234 235 struct prcmu_pdata 236 { 237 bool enable_set_ddr_opp; 238 bool enable_ape_opp_100_voltage; 239 struct ab8500_platform_data *ab_platdata; 240 u32 version_offset; 241 u32 legacy_offset; 242 u32 adt_offset; 243 }; 244 245 #define PRCMU_FW_PROJECT_U8500 2 246 #define PRCMU_FW_PROJECT_U8400 3 247 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */ 248 #define PRCMU_FW_PROJECT_U8500_MBB 5 249 #define PRCMU_FW_PROJECT_U8500_C1 6 250 #define PRCMU_FW_PROJECT_U8500_C2 7 251 #define PRCMU_FW_PROJECT_U8500_C3 8 252 #define PRCMU_FW_PROJECT_U8500_C4 9 253 #define PRCMU_FW_PROJECT_U9500_MBL 10 254 #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ 255 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ 256 #define PRCMU_FW_PROJECT_U8520 13 257 #define PRCMU_FW_PROJECT_U8420 14 258 #define PRCMU_FW_PROJECT_A9420 20 259 /* [32..63] 9540 and derivatives */ 260 #define PRCMU_FW_PROJECT_U9540 32 261 /* [64..95] 8540 and derivatives */ 262 #define PRCMU_FW_PROJECT_L8540 64 263 /* [96..126] 8580 and derivatives */ 264 #define PRCMU_FW_PROJECT_L8580 96 265 266 #define PRCMU_FW_PROJECT_NAME_LEN 20 267 struct prcmu_fw_version { 268 u32 project; /* Notice, project shifted with 8 on ux540 */ 269 u8 api_version; 270 u8 func_version; 271 u8 errata; 272 char project_name[PRCMU_FW_PROJECT_NAME_LEN]; 273 }; 274 275 #include <linux/mfd/db8500-prcmu.h> 276 277 #if defined(CONFIG_UX500_SOC_DB8500) 278 279 static inline void __init prcmu_early_init(void) 280 { 281 return db8500_prcmu_early_init(); 282 } 283 284 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 285 bool keep_ap_pll) 286 { 287 return db8500_prcmu_set_power_state(state, keep_ulp_clk, 288 keep_ap_pll); 289 } 290 291 static inline u8 prcmu_get_power_state_result(void) 292 { 293 return db8500_prcmu_get_power_state_result(); 294 } 295 296 static inline int prcmu_gic_decouple(void) 297 { 298 return db8500_prcmu_gic_decouple(); 299 } 300 301 static inline int prcmu_gic_recouple(void) 302 { 303 return db8500_prcmu_gic_recouple(); 304 } 305 306 static inline bool prcmu_gic_pending_irq(void) 307 { 308 return db8500_prcmu_gic_pending_irq(); 309 } 310 311 static inline bool prcmu_is_cpu_in_wfi(int cpu) 312 { 313 return db8500_prcmu_is_cpu_in_wfi(cpu); 314 } 315 316 static inline int prcmu_copy_gic_settings(void) 317 { 318 return db8500_prcmu_copy_gic_settings(); 319 } 320 321 static inline bool prcmu_pending_irq(void) 322 { 323 return db8500_prcmu_pending_irq(); 324 } 325 326 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 327 { 328 return db8500_prcmu_set_epod(epod_id, epod_state); 329 } 330 331 static inline void prcmu_enable_wakeups(u32 wakeups) 332 { 333 db8500_prcmu_enable_wakeups(wakeups); 334 } 335 336 static inline void prcmu_disable_wakeups(void) 337 { 338 prcmu_enable_wakeups(0); 339 } 340 341 static inline void prcmu_config_abb_event_readout(u32 abb_events) 342 { 343 db8500_prcmu_config_abb_event_readout(abb_events); 344 } 345 346 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 347 { 348 db8500_prcmu_get_abb_event_buffer(buf); 349 } 350 351 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 352 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); 353 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); 354 355 int prcmu_config_clkout(u8 clkout, u8 source, u8 div); 356 357 static inline int prcmu_request_clock(u8 clock, bool enable) 358 { 359 return db8500_prcmu_request_clock(clock, enable); 360 } 361 362 unsigned long prcmu_clock_rate(u8 clock); 363 long prcmu_round_clock_rate(u8 clock, unsigned long rate); 364 int prcmu_set_clock_rate(u8 clock, unsigned long rate); 365 366 static inline int prcmu_set_ddr_opp(u8 opp) 367 { 368 return db8500_prcmu_set_ddr_opp(opp); 369 } 370 static inline int prcmu_get_ddr_opp(void) 371 { 372 return db8500_prcmu_get_ddr_opp(); 373 } 374 375 static inline int prcmu_set_arm_opp(u8 opp) 376 { 377 return db8500_prcmu_set_arm_opp(opp); 378 } 379 380 static inline int prcmu_get_arm_opp(void) 381 { 382 return db8500_prcmu_get_arm_opp(); 383 } 384 385 static inline int prcmu_set_ape_opp(u8 opp) 386 { 387 return db8500_prcmu_set_ape_opp(opp); 388 } 389 390 static inline int prcmu_get_ape_opp(void) 391 { 392 return db8500_prcmu_get_ape_opp(); 393 } 394 395 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 396 { 397 return db8500_prcmu_request_ape_opp_100_voltage(enable); 398 } 399 400 static inline void prcmu_system_reset(u16 reset_code) 401 { 402 return db8500_prcmu_system_reset(reset_code); 403 } 404 405 static inline u16 prcmu_get_reset_code(void) 406 { 407 return db8500_prcmu_get_reset_code(); 408 } 409 410 int prcmu_ac_wake_req(void); 411 void prcmu_ac_sleep_req(void); 412 static inline void prcmu_modem_reset(void) 413 { 414 return db8500_prcmu_modem_reset(); 415 } 416 417 static inline bool prcmu_is_ac_wake_requested(void) 418 { 419 return db8500_prcmu_is_ac_wake_requested(); 420 } 421 422 static inline int prcmu_set_display_clocks(void) 423 { 424 return db8500_prcmu_set_display_clocks(); 425 } 426 427 static inline int prcmu_disable_dsipll(void) 428 { 429 return db8500_prcmu_disable_dsipll(); 430 } 431 432 static inline int prcmu_enable_dsipll(void) 433 { 434 return db8500_prcmu_enable_dsipll(); 435 } 436 437 static inline int prcmu_config_esram0_deep_sleep(u8 state) 438 { 439 return db8500_prcmu_config_esram0_deep_sleep(state); 440 } 441 442 static inline int prcmu_config_hotdog(u8 threshold) 443 { 444 return db8500_prcmu_config_hotdog(threshold); 445 } 446 447 static inline int prcmu_config_hotmon(u8 low, u8 high) 448 { 449 return db8500_prcmu_config_hotmon(low, high); 450 } 451 452 static inline int prcmu_start_temp_sense(u16 cycles32k) 453 { 454 return db8500_prcmu_start_temp_sense(cycles32k); 455 } 456 457 static inline int prcmu_stop_temp_sense(void) 458 { 459 return db8500_prcmu_stop_temp_sense(); 460 } 461 462 static inline u32 prcmu_read(unsigned int reg) 463 { 464 return db8500_prcmu_read(reg); 465 } 466 467 static inline void prcmu_write(unsigned int reg, u32 value) 468 { 469 db8500_prcmu_write(reg, value); 470 } 471 472 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 473 { 474 db8500_prcmu_write_masked(reg, mask, value); 475 } 476 477 static inline int prcmu_enable_a9wdog(u8 id) 478 { 479 return db8500_prcmu_enable_a9wdog(id); 480 } 481 482 static inline int prcmu_disable_a9wdog(u8 id) 483 { 484 return db8500_prcmu_disable_a9wdog(id); 485 } 486 487 static inline int prcmu_kick_a9wdog(u8 id) 488 { 489 return db8500_prcmu_kick_a9wdog(id); 490 } 491 492 static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 493 { 494 return db8500_prcmu_load_a9wdog(id, timeout); 495 } 496 497 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 498 { 499 return db8500_prcmu_config_a9wdog(num, sleep_auto_off); 500 } 501 #else 502 503 static inline void __init prcmu_early_init(void) {} 504 505 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 506 bool keep_ap_pll) 507 { 508 return 0; 509 } 510 511 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 512 { 513 return 0; 514 } 515 516 static inline void prcmu_enable_wakeups(u32 wakeups) {} 517 518 static inline void prcmu_disable_wakeups(void) {} 519 520 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) 521 { 522 return -ENOSYS; 523 } 524 525 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) 526 { 527 return -ENOSYS; 528 } 529 530 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, 531 u8 size) 532 { 533 return -ENOSYS; 534 } 535 536 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) 537 { 538 return 0; 539 } 540 541 static inline int prcmu_request_clock(u8 clock, bool enable) 542 { 543 return 0; 544 } 545 546 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) 547 { 548 return 0; 549 } 550 551 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) 552 { 553 return 0; 554 } 555 556 static inline unsigned long prcmu_clock_rate(u8 clock) 557 { 558 return 0; 559 } 560 561 static inline int prcmu_set_ape_opp(u8 opp) 562 { 563 return 0; 564 } 565 566 static inline int prcmu_get_ape_opp(void) 567 { 568 return APE_100_OPP; 569 } 570 571 static inline int prcmu_request_ape_opp_100_voltage(bool enable) 572 { 573 return 0; 574 } 575 576 static inline int prcmu_set_arm_opp(u8 opp) 577 { 578 return 0; 579 } 580 581 static inline int prcmu_get_arm_opp(void) 582 { 583 return ARM_100_OPP; 584 } 585 586 static inline int prcmu_set_ddr_opp(u8 opp) 587 { 588 return 0; 589 } 590 591 static inline int prcmu_get_ddr_opp(void) 592 { 593 return DDR_100_OPP; 594 } 595 596 static inline void prcmu_system_reset(u16 reset_code) {} 597 598 static inline u16 prcmu_get_reset_code(void) 599 { 600 return 0; 601 } 602 603 static inline int prcmu_ac_wake_req(void) 604 { 605 return 0; 606 } 607 608 static inline void prcmu_ac_sleep_req(void) {} 609 610 static inline void prcmu_modem_reset(void) {} 611 612 static inline bool prcmu_is_ac_wake_requested(void) 613 { 614 return false; 615 } 616 617 static inline int prcmu_set_display_clocks(void) 618 { 619 return 0; 620 } 621 622 static inline int prcmu_disable_dsipll(void) 623 { 624 return 0; 625 } 626 627 static inline int prcmu_enable_dsipll(void) 628 { 629 return 0; 630 } 631 632 static inline int prcmu_config_esram0_deep_sleep(u8 state) 633 { 634 return 0; 635 } 636 637 static inline void prcmu_config_abb_event_readout(u32 abb_events) {} 638 639 static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 640 { 641 *buf = NULL; 642 } 643 644 static inline int prcmu_config_hotdog(u8 threshold) 645 { 646 return 0; 647 } 648 649 static inline int prcmu_config_hotmon(u8 low, u8 high) 650 { 651 return 0; 652 } 653 654 static inline int prcmu_start_temp_sense(u16 cycles32k) 655 { 656 return 0; 657 } 658 659 static inline int prcmu_stop_temp_sense(void) 660 { 661 return 0; 662 } 663 664 static inline u32 prcmu_read(unsigned int reg) 665 { 666 return 0; 667 } 668 669 static inline void prcmu_write(unsigned int reg, u32 value) {} 670 671 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} 672 673 #endif 674 675 static inline void prcmu_set(unsigned int reg, u32 bits) 676 { 677 prcmu_write_masked(reg, bits, bits); 678 } 679 680 static inline void prcmu_clear(unsigned int reg, u32 bits) 681 { 682 prcmu_write_masked(reg, bits, 0); 683 } 684 685 /* PRCMU QoS APE OPP class */ 686 #define PRCMU_QOS_APE_OPP 1 687 #define PRCMU_QOS_DDR_OPP 2 688 #define PRCMU_QOS_ARM_OPP 3 689 #define PRCMU_QOS_DEFAULT_VALUE -1 690 691 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER 692 693 unsigned long prcmu_qos_get_cpufreq_opp_delay(void); 694 void prcmu_qos_set_cpufreq_opp_delay(unsigned long); 695 void prcmu_qos_force_opp(int, s32); 696 int prcmu_qos_requirement(int pm_qos_class); 697 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); 698 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); 699 void prcmu_qos_remove_requirement(int pm_qos_class, char *name); 700 int prcmu_qos_add_notifier(int prcmu_qos_class, 701 struct notifier_block *notifier); 702 int prcmu_qos_remove_notifier(int prcmu_qos_class, 703 struct notifier_block *notifier); 704 705 #else 706 707 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) 708 { 709 return 0; 710 } 711 712 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} 713 714 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} 715 716 static inline int prcmu_qos_requirement(int prcmu_qos_class) 717 { 718 return 0; 719 } 720 721 static inline int prcmu_qos_add_requirement(int prcmu_qos_class, 722 char *name, s32 value) 723 { 724 return 0; 725 } 726 727 static inline int prcmu_qos_update_requirement(int prcmu_qos_class, 728 char *name, s32 new_value) 729 { 730 return 0; 731 } 732 733 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) 734 { 735 } 736 737 static inline int prcmu_qos_add_notifier(int prcmu_qos_class, 738 struct notifier_block *notifier) 739 { 740 return 0; 741 } 742 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, 743 struct notifier_block *notifier) 744 { 745 return 0; 746 } 747 748 #endif 749 750 #endif /* __MACH_PRCMU_H */ 751