1 #ifndef __LINUX_GPIO_DRIVER_H 2 #define __LINUX_GPIO_DRIVER_H 3 4 #include <linux/device.h> 5 #include <linux/types.h> 6 #include <linux/module.h> 7 #include <linux/irq.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/lockdep.h> 11 #include <linux/pinctrl/pinctrl.h> 12 #include <linux/kconfig.h> 13 14 struct gpio_desc; 15 struct of_phandle_args; 16 struct device_node; 17 struct seq_file; 18 struct gpio_device; 19 20 #ifdef CONFIG_GPIOLIB 21 22 /** 23 * enum single_ended_mode - mode for single ended operation 24 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low 25 * @LINE_MODE_OPEN_DRAIN: set line to be open drain 26 * @LINE_MODE_OPEN_SOURCE: set line to be open source 27 */ 28 enum single_ended_mode { 29 LINE_MODE_PUSH_PULL, 30 LINE_MODE_OPEN_DRAIN, 31 LINE_MODE_OPEN_SOURCE, 32 }; 33 34 /** 35 * struct gpio_chip - abstract a GPIO controller 36 * @label: a functional name for the GPIO device, such as a part 37 * number or the name of the SoC IP-block implementing it. 38 * @gpiodev: the internal state holder, opaque struct 39 * @parent: optional parent device providing the GPIOs 40 * @owner: helps prevent removal of modules exporting active GPIOs 41 * @request: optional hook for chip-specific activation, such as 42 * enabling module power and clock; may sleep 43 * @free: optional hook for chip-specific deactivation, such as 44 * disabling module power and clock; may sleep 45 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 46 * (same as GPIOF_DIR_XXX), or negative error 47 * @direction_input: configures signal "offset" as input, or returns error 48 * @direction_output: configures signal "offset" as output, or returns error 49 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 50 * @set: assigns output value for signal "offset" 51 * @set_multiple: assigns output values for multiple signals defined by "mask" 52 * @set_debounce: optional hook for setting debounce time for specified gpio in 53 * interrupt triggered gpio chips 54 * @set_single_ended: optional hook for setting a line as open drain, open 55 * source, or non-single ended (restore from open drain/source to normal 56 * push-pull mode) this should be implemented if the hardware supports 57 * open drain or open source settings. The GPIOlib will otherwise try 58 * to emulate open drain/source by not actively driving lines high/low 59 * if a consumer request this. The driver may return -ENOTSUPP if e.g. 60 * it supports just open drain but not open source and is called 61 * with LINE_MODE_OPEN_SOURCE as mode argument. 62 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings; 63 * implementation may not sleep 64 * @dbg_show: optional routine to show contents in debugfs; default code 65 * will be used when this is omitted, but custom code can show extra 66 * state (such as pullup/pulldown configuration). 67 * @base: identifies the first GPIO number handled by this chip; 68 * or, if negative during registration, requests dynamic ID allocation. 69 * DEPRECATION: providing anything non-negative and nailing the base 70 * offset of GPIO chips is deprecated. Please pass -1 as base to 71 * let gpiolib select the chip base in all possible cases. We want to 72 * get rid of the static GPIO number space in the long run. 73 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 74 * handled is (base + ngpio - 1). 75 * @names: if set, must be an array of strings to use as alternative 76 * names for the GPIOs in this chip. Any entry in the array 77 * may be NULL if there is no alias for the GPIO, however the 78 * array must be @ngpio entries long. A name can include a single printk 79 * format specifier for an unsigned int. It is substituted by the actual 80 * number of the gpio. 81 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 82 * must while accessing GPIO expander chips over I2C or SPI. This 83 * implies that if the chip supports IRQs, these IRQs need to be threaded 84 * as the chip access may sleep when e.g. reading out the IRQ status 85 * registers. 86 * @irq_not_threaded: flag must be set if @can_sleep is set but the 87 * IRQs don't need to be threaded 88 * @read_reg: reader function for generic GPIO 89 * @write_reg: writer function for generic GPIO 90 * @pin2mask: some generic GPIO controllers work with the big-endian bits 91 * notation, e.g. in a 8-bits register, GPIO7 is the least significant 92 * bit. This callback assigns the right bit mask. 93 * @reg_dat: data (in) register for generic GPIO 94 * @reg_set: output set register (out=high) for generic GPIO 95 * @reg_clk: output clear register (out=low) for generic GPIO 96 * @reg_dir: direction setting register for generic GPIO 97 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 98 * <register width> * 8 99 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 100 * shadowed and real data registers writes together. 101 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 102 * safely. 103 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 104 * direction safely. 105 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver 106 * @irqdomain: Interrupt translation domain; responsible for mapping 107 * between GPIO hwirq number and linux irq number 108 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated) 109 * @irq_handler: the irq handler to use (often a predefined irq core function) 110 * for GPIO IRQs, provided by GPIO driver 111 * @irq_default_type: default IRQ triggering type applied during GPIO driver 112 * initialization, provided by GPIO driver 113 * @irq_parent: GPIO IRQ chip parent/bank linux irq number, 114 * provided by GPIO driver 115 * @lock_key: per GPIO IRQ chip lockdep class 116 * 117 * A gpio_chip can help platforms abstract various sources of GPIOs so 118 * they can all be accessed through a common programing interface. 119 * Example sources would be SOC controllers, FPGAs, multifunction 120 * chips, dedicated GPIO expanders, and so on. 121 * 122 * Each chip controls a number of signals, identified in method calls 123 * by "offset" values in the range 0..(@ngpio - 1). When those signals 124 * are referenced through calls like gpio_get_value(gpio), the offset 125 * is calculated by subtracting @base from the gpio number. 126 */ 127 struct gpio_chip { 128 const char *label; 129 struct gpio_device *gpiodev; 130 struct device *parent; 131 struct module *owner; 132 133 int (*request)(struct gpio_chip *chip, 134 unsigned offset); 135 void (*free)(struct gpio_chip *chip, 136 unsigned offset); 137 int (*get_direction)(struct gpio_chip *chip, 138 unsigned offset); 139 int (*direction_input)(struct gpio_chip *chip, 140 unsigned offset); 141 int (*direction_output)(struct gpio_chip *chip, 142 unsigned offset, int value); 143 int (*get)(struct gpio_chip *chip, 144 unsigned offset); 145 void (*set)(struct gpio_chip *chip, 146 unsigned offset, int value); 147 void (*set_multiple)(struct gpio_chip *chip, 148 unsigned long *mask, 149 unsigned long *bits); 150 int (*set_debounce)(struct gpio_chip *chip, 151 unsigned offset, 152 unsigned debounce); 153 int (*set_single_ended)(struct gpio_chip *chip, 154 unsigned offset, 155 enum single_ended_mode mode); 156 157 int (*to_irq)(struct gpio_chip *chip, 158 unsigned offset); 159 160 void (*dbg_show)(struct seq_file *s, 161 struct gpio_chip *chip); 162 int base; 163 u16 ngpio; 164 const char *const *names; 165 bool can_sleep; 166 bool irq_not_threaded; 167 168 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 169 unsigned long (*read_reg)(void __iomem *reg); 170 void (*write_reg)(void __iomem *reg, unsigned long data); 171 unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin); 172 void __iomem *reg_dat; 173 void __iomem *reg_set; 174 void __iomem *reg_clr; 175 void __iomem *reg_dir; 176 int bgpio_bits; 177 spinlock_t bgpio_lock; 178 unsigned long bgpio_data; 179 unsigned long bgpio_dir; 180 #endif 181 182 #ifdef CONFIG_GPIOLIB_IRQCHIP 183 /* 184 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 185 * to handle IRQs for most practical cases. 186 */ 187 struct irq_chip *irqchip; 188 struct irq_domain *irqdomain; 189 unsigned int irq_base; 190 irq_flow_handler_t irq_handler; 191 unsigned int irq_default_type; 192 int irq_parent; 193 struct lock_class_key *lock_key; 194 #endif 195 196 #if defined(CONFIG_OF_GPIO) 197 /* 198 * If CONFIG_OF is enabled, then all GPIO controllers described in the 199 * device tree automatically may have an OF translation 200 */ 201 struct device_node *of_node; 202 int of_gpio_n_cells; 203 int (*of_xlate)(struct gpio_chip *gc, 204 const struct of_phandle_args *gpiospec, u32 *flags); 205 #endif 206 }; 207 208 extern const char *gpiochip_is_requested(struct gpio_chip *chip, 209 unsigned offset); 210 211 /* add/remove chips */ 212 extern int gpiochip_add_data(struct gpio_chip *chip, void *data); 213 static inline int gpiochip_add(struct gpio_chip *chip) 214 { 215 return gpiochip_add_data(chip, NULL); 216 } 217 extern void gpiochip_remove(struct gpio_chip *chip); 218 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip, 219 void *data); 220 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip); 221 222 extern struct gpio_chip *gpiochip_find(void *data, 223 int (*match)(struct gpio_chip *chip, void *data)); 224 225 /* lock/unlock as IRQ */ 226 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset); 227 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset); 228 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset); 229 230 /* Line status inquiry for drivers */ 231 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset); 232 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset); 233 234 /* get driver data */ 235 void *gpiochip_get_data(struct gpio_chip *chip); 236 237 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 238 239 struct bgpio_pdata { 240 const char *label; 241 int base; 242 int ngpio; 243 }; 244 245 #if IS_ENABLED(CONFIG_GPIO_GENERIC) 246 247 int bgpio_init(struct gpio_chip *gc, struct device *dev, 248 unsigned long sz, void __iomem *dat, void __iomem *set, 249 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 250 unsigned long flags); 251 252 #define BGPIOF_BIG_ENDIAN BIT(0) 253 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 254 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 255 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 256 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 257 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 258 259 #endif 260 261 #ifdef CONFIG_GPIOLIB_IRQCHIP 262 263 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, 264 struct irq_chip *irqchip, 265 int parent_irq, 266 irq_flow_handler_t parent_handler); 267 268 int _gpiochip_irqchip_add(struct gpio_chip *gpiochip, 269 struct irq_chip *irqchip, 270 unsigned int first_irq, 271 irq_flow_handler_t handler, 272 unsigned int type, 273 struct lock_class_key *lock_key); 274 275 #ifdef CONFIG_LOCKDEP 276 #define gpiochip_irqchip_add(...) \ 277 ( \ 278 ({ \ 279 static struct lock_class_key _key; \ 280 _gpiochip_irqchip_add(__VA_ARGS__, &_key); \ 281 }) \ 282 ) 283 #else 284 #define gpiochip_irqchip_add(...) \ 285 _gpiochip_irqchip_add(__VA_ARGS__, NULL) 286 #endif 287 288 #endif /* CONFIG_GPIOLIB_IRQCHIP */ 289 290 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset); 291 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset); 292 293 #ifdef CONFIG_PINCTRL 294 295 /** 296 * struct gpio_pin_range - pin range controlled by a gpio chip 297 * @head: list for maintaining set of pin ranges, used internally 298 * @pctldev: pinctrl device which handles corresponding pins 299 * @range: actual range of pins controlled by a gpio controller 300 */ 301 302 struct gpio_pin_range { 303 struct list_head node; 304 struct pinctrl_dev *pctldev; 305 struct pinctrl_gpio_range range; 306 }; 307 308 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 309 unsigned int gpio_offset, unsigned int pin_offset, 310 unsigned int npins); 311 int gpiochip_add_pingroup_range(struct gpio_chip *chip, 312 struct pinctrl_dev *pctldev, 313 unsigned int gpio_offset, const char *pin_group); 314 void gpiochip_remove_pin_ranges(struct gpio_chip *chip); 315 316 #else 317 318 static inline int 319 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, 320 unsigned int gpio_offset, unsigned int pin_offset, 321 unsigned int npins) 322 { 323 return 0; 324 } 325 static inline int 326 gpiochip_add_pingroup_range(struct gpio_chip *chip, 327 struct pinctrl_dev *pctldev, 328 unsigned int gpio_offset, const char *pin_group) 329 { 330 return 0; 331 } 332 333 static inline void 334 gpiochip_remove_pin_ranges(struct gpio_chip *chip) 335 { 336 } 337 338 #endif /* CONFIG_PINCTRL */ 339 340 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum, 341 const char *label); 342 void gpiochip_free_own_desc(struct gpio_desc *desc); 343 344 #else /* CONFIG_GPIOLIB */ 345 346 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 347 { 348 /* GPIO can never have been requested */ 349 WARN_ON(1); 350 return ERR_PTR(-ENODEV); 351 } 352 353 #endif /* CONFIG_GPIOLIB */ 354 355 #endif 356