1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* Copyright 2019 NXP */ 3 4 #ifndef _FSL_ENETC_MDIO_H_ 5 #define _FSL_ENETC_MDIO_H_ 6 7 #include <linux/phy.h> 8 9 /* PCS registers */ 10 #define ENETC_PCS_LINK_TIMER1 0x12 11 #define ENETC_PCS_LINK_TIMER1_VAL 0x06a0 12 #define ENETC_PCS_LINK_TIMER2 0x13 13 #define ENETC_PCS_LINK_TIMER2_VAL 0x0003 14 #define ENETC_PCS_IF_MODE 0x14 15 #define ENETC_PCS_IF_MODE_SGMII_EN BIT(0) 16 #define ENETC_PCS_IF_MODE_USE_SGMII_AN BIT(1) 17 #define ENETC_PCS_IF_MODE_SGMII_SPEED(x) (((x) << 2) & GENMASK(3, 2)) 18 19 /* Not a mistake, the SerDes PLL needs to be set at 3.125 GHz by Reset 20 * Configuration Word (RCW, outside Linux control) for 2.5G SGMII mode. The PCS 21 * still thinks it's at gigabit. 22 */ 23 enum enetc_pcs_speed { 24 ENETC_PCS_SPEED_10 = 0, 25 ENETC_PCS_SPEED_100 = 1, 26 ENETC_PCS_SPEED_1000 = 2, 27 ENETC_PCS_SPEED_2500 = 2, 28 }; 29 30 struct enetc_hw; 31 32 struct enetc_mdio_priv { 33 struct enetc_hw *hw; 34 int mdio_base; 35 }; 36 37 #if IS_REACHABLE(CONFIG_FSL_ENETC_MDIO) 38 39 int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum); 40 int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value); 41 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs); 42 43 #else 44 45 static inline int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum) 46 { return -EINVAL; } 47 static inline int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, 48 u16 value) 49 { return -EINVAL; } 50 struct enetc_hw *enetc_hw_alloc(struct device *dev, void __iomem *port_regs) 51 { return ERR_PTR(-EINVAL); } 52 53 #endif 54 55 #endif 56