1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 5 */ 6 #ifndef __LINUX_CLK_PROVIDER_H 7 #define __LINUX_CLK_PROVIDER_H 8 9 #include <linux/of.h> 10 #include <linux/of_clk.h> 11 12 #ifdef CONFIG_COMMON_CLK 13 14 /* 15 * flags used across common struct clk. these flags should only affect the 16 * top-level framework. custom flags for dealing with hardware specifics 17 * belong in struct clk_foo 18 * 19 * Please update clk_flags[] in drivers/clk/clk.c when making changes here! 20 */ 21 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 22 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 23 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 24 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 25 /* unused */ 26 /* unused */ 27 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 28 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 29 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 30 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ 31 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ 32 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ 33 /* parents need enable during gate/ungate, set rate and re-parent */ 34 #define CLK_OPS_PARENT_ENABLE BIT(12) 35 /* duty cycle call may be forwarded to the parent clock */ 36 #define CLK_DUTY_CYCLE_PARENT BIT(13) 37 38 struct clk; 39 struct clk_hw; 40 struct clk_core; 41 struct dentry; 42 43 /** 44 * struct clk_rate_request - Structure encoding the clk constraints that 45 * a clock user might require. 46 * 47 * @rate: Requested clock rate. This field will be adjusted by 48 * clock drivers according to hardware capabilities. 49 * @min_rate: Minimum rate imposed by clk users. 50 * @max_rate: Maximum rate imposed by clk users. 51 * @best_parent_rate: The best parent rate a parent can provide to fulfill the 52 * requested constraints. 53 * @best_parent_hw: The most appropriate parent clock that fulfills the 54 * requested constraints. 55 * 56 */ 57 struct clk_rate_request { 58 unsigned long rate; 59 unsigned long min_rate; 60 unsigned long max_rate; 61 unsigned long best_parent_rate; 62 struct clk_hw *best_parent_hw; 63 }; 64 65 /** 66 * struct clk_duty - Struture encoding the duty cycle ratio of a clock 67 * 68 * @num: Numerator of the duty cycle ratio 69 * @den: Denominator of the duty cycle ratio 70 */ 71 struct clk_duty { 72 unsigned int num; 73 unsigned int den; 74 }; 75 76 /** 77 * struct clk_ops - Callback operations for hardware clocks; these are to 78 * be provided by the clock implementation, and will be called by drivers 79 * through the clk_* api. 80 * 81 * @prepare: Prepare the clock for enabling. This must not return until 82 * the clock is fully prepared, and it's safe to call clk_enable. 83 * This callback is intended to allow clock implementations to 84 * do any initialisation that may sleep. Called with 85 * prepare_lock held. 86 * 87 * @unprepare: Release the clock from its prepared state. This will typically 88 * undo any work done in the @prepare callback. Called with 89 * prepare_lock held. 90 * 91 * @is_prepared: Queries the hardware to determine if the clock is prepared. 92 * This function is allowed to sleep. Optional, if this op is not 93 * set then the prepare count will be used. 94 * 95 * @unprepare_unused: Unprepare the clock atomically. Only called from 96 * clk_disable_unused for prepare clocks with special needs. 97 * Called with prepare mutex held. This function may sleep. 98 * 99 * @enable: Enable the clock atomically. This must not return until the 100 * clock is generating a valid clock signal, usable by consumer 101 * devices. Called with enable_lock held. This function must not 102 * sleep. 103 * 104 * @disable: Disable the clock atomically. Called with enable_lock held. 105 * This function must not sleep. 106 * 107 * @is_enabled: Queries the hardware to determine if the clock is enabled. 108 * This function must not sleep. Optional, if this op is not 109 * set then the enable count will be used. 110 * 111 * @disable_unused: Disable the clock atomically. Only called from 112 * clk_disable_unused for gate clocks with special needs. 113 * Called with enable_lock held. This function must not 114 * sleep. 115 * 116 * @save_context: Save the context of the clock in prepration for poweroff. 117 * 118 * @restore_context: Restore the context of the clock after a restoration 119 * of power. 120 * 121 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 122 * parent rate is an input parameter. It is up to the caller to 123 * ensure that the prepare_mutex is held across this call. 124 * Returns the calculated rate. Optional, but recommended - if 125 * this op is not set then clock rate will be initialized to 0. 126 * 127 * @round_rate: Given a target rate as input, returns the closest rate actually 128 * supported by the clock. The parent rate is an input/output 129 * parameter. 130 * 131 * @determine_rate: Given a target rate as input, returns the closest rate 132 * actually supported by the clock, and optionally the parent clock 133 * that should be used to provide the clock rate. 134 * 135 * @set_parent: Change the input source of this clock; for clocks with multiple 136 * possible parents specify a new parent by passing in the index 137 * as a u8 corresponding to the parent in either the .parent_names 138 * or .parents arrays. This function in affect translates an 139 * array index into the value programmed into the hardware. 140 * Returns 0 on success, -EERROR otherwise. 141 * 142 * @get_parent: Queries the hardware to determine the parent of a clock. The 143 * return value is a u8 which specifies the index corresponding to 144 * the parent clock. This index can be applied to either the 145 * .parent_names or .parents arrays. In short, this function 146 * translates the parent value read from hardware into an array 147 * index. Currently only called when the clock is initialized by 148 * __clk_init. This callback is mandatory for clocks with 149 * multiple parents. It is optional (and unnecessary) for clocks 150 * with 0 or 1 parents. 151 * 152 * @set_rate: Change the rate of this clock. The requested rate is specified 153 * by the second argument, which should typically be the return 154 * of .round_rate call. The third argument gives the parent rate 155 * which is likely helpful for most .set_rate implementation. 156 * Returns 0 on success, -EERROR otherwise. 157 * 158 * @set_rate_and_parent: Change the rate and the parent of this clock. The 159 * requested rate is specified by the second argument, which 160 * should typically be the return of .round_rate call. The 161 * third argument gives the parent rate which is likely helpful 162 * for most .set_rate_and_parent implementation. The fourth 163 * argument gives the parent index. This callback is optional (and 164 * unnecessary) for clocks with 0 or 1 parents as well as 165 * for clocks that can tolerate switching the rate and the parent 166 * separately via calls to .set_parent and .set_rate. 167 * Returns 0 on success, -EERROR otherwise. 168 * 169 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 170 * is expressed in ppb (parts per billion). The parent accuracy is 171 * an input parameter. 172 * Returns the calculated accuracy. Optional - if this op is not 173 * set then clock accuracy will be initialized to parent accuracy 174 * or 0 (perfect clock) if clock has no parent. 175 * 176 * @get_phase: Queries the hardware to get the current phase of a clock. 177 * Returned values are 0-359 degrees on success, negative 178 * error codes on failure. 179 * 180 * @set_phase: Shift the phase this clock signal in degrees specified 181 * by the second argument. Valid values for degrees are 182 * 0-359. Return 0 on success, otherwise -EERROR. 183 * 184 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio 185 * of a clock. Returned values denominator cannot be 0 and must be 186 * superior or equal to the numerator. 187 * 188 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by 189 * the numerator (2nd argurment) and denominator (3rd argument). 190 * Argument must be a valid ratio (denominator > 0 191 * and >= numerator) Return 0 on success, otherwise -EERROR. 192 * 193 * @init: Perform platform-specific initialization magic. 194 * This is not not used by any of the basic clock types. 195 * Please consider other ways of solving initialization problems 196 * before using this callback, as its use is discouraged. 197 * 198 * @debug_init: Set up type-specific debugfs entries for this clock. This 199 * is called once, after the debugfs directory entry for this 200 * clock has been created. The dentry pointer representing that 201 * directory is provided as an argument. Called with 202 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 203 * 204 * 205 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 206 * implementations to split any work between atomic (enable) and sleepable 207 * (prepare) contexts. If enabling a clock requires code that might sleep, 208 * this must be done in clk_prepare. Clock enable code that will never be 209 * called in a sleepable context may be implemented in clk_enable. 210 * 211 * Typically, drivers will call clk_prepare when a clock may be needed later 212 * (eg. when a device is opened), and clk_enable when the clock is actually 213 * required (eg. from an interrupt). Note that clk_prepare MUST have been 214 * called before clk_enable. 215 */ 216 struct clk_ops { 217 int (*prepare)(struct clk_hw *hw); 218 void (*unprepare)(struct clk_hw *hw); 219 int (*is_prepared)(struct clk_hw *hw); 220 void (*unprepare_unused)(struct clk_hw *hw); 221 int (*enable)(struct clk_hw *hw); 222 void (*disable)(struct clk_hw *hw); 223 int (*is_enabled)(struct clk_hw *hw); 224 void (*disable_unused)(struct clk_hw *hw); 225 int (*save_context)(struct clk_hw *hw); 226 void (*restore_context)(struct clk_hw *hw); 227 unsigned long (*recalc_rate)(struct clk_hw *hw, 228 unsigned long parent_rate); 229 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 230 unsigned long *parent_rate); 231 int (*determine_rate)(struct clk_hw *hw, 232 struct clk_rate_request *req); 233 int (*set_parent)(struct clk_hw *hw, u8 index); 234 u8 (*get_parent)(struct clk_hw *hw); 235 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 236 unsigned long parent_rate); 237 int (*set_rate_and_parent)(struct clk_hw *hw, 238 unsigned long rate, 239 unsigned long parent_rate, u8 index); 240 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 241 unsigned long parent_accuracy); 242 int (*get_phase)(struct clk_hw *hw); 243 int (*set_phase)(struct clk_hw *hw, int degrees); 244 int (*get_duty_cycle)(struct clk_hw *hw, 245 struct clk_duty *duty); 246 int (*set_duty_cycle)(struct clk_hw *hw, 247 struct clk_duty *duty); 248 void (*init)(struct clk_hw *hw); 249 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 250 }; 251 252 /** 253 * struct clk_parent_data - clk parent information 254 * @hw: parent clk_hw pointer (used for clk providers with internal clks) 255 * @fw_name: parent name local to provider registering clk 256 * @name: globally unique parent name (used as a fallback) 257 * @index: parent index local to provider registering clk (if @fw_name absent) 258 */ 259 struct clk_parent_data { 260 const struct clk_hw *hw; 261 const char *fw_name; 262 const char *name; 263 int index; 264 }; 265 266 /** 267 * struct clk_init_data - holds init data that's common to all clocks and is 268 * shared between the clock provider and the common clock framework. 269 * 270 * @name: clock name 271 * @ops: operations this clock supports 272 * @parent_names: array of string names for all possible parents 273 * @parent_data: array of parent data for all possible parents (when some 274 * parents are external to the clk controller) 275 * @parent_hws: array of pointers to all possible parents (when all parents 276 * are internal to the clk controller) 277 * @num_parents: number of possible parents 278 * @flags: framework-level hints and quirks 279 */ 280 struct clk_init_data { 281 const char *name; 282 const struct clk_ops *ops; 283 /* Only one of the following three should be assigned */ 284 const char * const *parent_names; 285 const struct clk_parent_data *parent_data; 286 const struct clk_hw **parent_hws; 287 u8 num_parents; 288 unsigned long flags; 289 }; 290 291 /** 292 * struct clk_hw - handle for traversing from a struct clk to its corresponding 293 * hardware-specific structure. struct clk_hw should be declared within struct 294 * clk_foo and then referenced by the struct clk instance that uses struct 295 * clk_foo's clk_ops 296 * 297 * @core: pointer to the struct clk_core instance that points back to this 298 * struct clk_hw instance 299 * 300 * @clk: pointer to the per-user struct clk instance that can be used to call 301 * into the clk API 302 * 303 * @init: pointer to struct clk_init_data that contains the init data shared 304 * with the common clock framework. 305 */ 306 struct clk_hw { 307 struct clk_core *core; 308 struct clk *clk; 309 const struct clk_init_data *init; 310 }; 311 312 /* 313 * DOC: Basic clock implementations common to many platforms 314 * 315 * Each basic clock hardware type is comprised of a structure describing the 316 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 317 * unique flags for that hardware type, a registration function and an 318 * alternative macro for static initialization 319 */ 320 321 /** 322 * struct clk_fixed_rate - fixed-rate clock 323 * @hw: handle between common and hardware-specific interfaces 324 * @fixed_rate: constant frequency of clock 325 */ 326 struct clk_fixed_rate { 327 struct clk_hw hw; 328 unsigned long fixed_rate; 329 unsigned long fixed_accuracy; 330 }; 331 332 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) 333 334 extern const struct clk_ops clk_fixed_rate_ops; 335 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 336 const char *parent_name, unsigned long flags, 337 unsigned long fixed_rate); 338 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name, 339 const char *parent_name, unsigned long flags, 340 unsigned long fixed_rate); 341 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 342 const char *name, const char *parent_name, unsigned long flags, 343 unsigned long fixed_rate, unsigned long fixed_accuracy); 344 void clk_unregister_fixed_rate(struct clk *clk); 345 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev, 346 const char *name, const char *parent_name, unsigned long flags, 347 unsigned long fixed_rate, unsigned long fixed_accuracy); 348 void clk_hw_unregister_fixed_rate(struct clk_hw *hw); 349 350 void of_fixed_clk_setup(struct device_node *np); 351 352 /** 353 * struct clk_gate - gating clock 354 * 355 * @hw: handle between common and hardware-specific interfaces 356 * @reg: register controlling gate 357 * @bit_idx: single bit controlling gate 358 * @flags: hardware-specific flags 359 * @lock: register lock 360 * 361 * Clock which can gate its output. Implements .enable & .disable 362 * 363 * Flags: 364 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 365 * enable the clock. Setting this flag does the opposite: setting the bit 366 * disable the clock and clearing it enables the clock 367 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 368 * of this register, and mask of gate bits are in higher 16-bit of this 369 * register. While setting the gate bits, higher 16-bit should also be 370 * updated to indicate changing gate bits. 371 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for 372 * the gate register. Setting this flag makes the register accesses big 373 * endian. 374 */ 375 struct clk_gate { 376 struct clk_hw hw; 377 void __iomem *reg; 378 u8 bit_idx; 379 u8 flags; 380 spinlock_t *lock; 381 }; 382 383 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 384 385 #define CLK_GATE_SET_TO_DISABLE BIT(0) 386 #define CLK_GATE_HIWORD_MASK BIT(1) 387 #define CLK_GATE_BIG_ENDIAN BIT(2) 388 389 extern const struct clk_ops clk_gate_ops; 390 struct clk *clk_register_gate(struct device *dev, const char *name, 391 const char *parent_name, unsigned long flags, 392 void __iomem *reg, u8 bit_idx, 393 u8 clk_gate_flags, spinlock_t *lock); 394 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name, 395 const char *parent_name, unsigned long flags, 396 void __iomem *reg, u8 bit_idx, 397 u8 clk_gate_flags, spinlock_t *lock); 398 void clk_unregister_gate(struct clk *clk); 399 void clk_hw_unregister_gate(struct clk_hw *hw); 400 int clk_gate_is_enabled(struct clk_hw *hw); 401 402 struct clk_div_table { 403 unsigned int val; 404 unsigned int div; 405 }; 406 407 /** 408 * struct clk_divider - adjustable divider clock 409 * 410 * @hw: handle between common and hardware-specific interfaces 411 * @reg: register containing the divider 412 * @shift: shift to the divider bit field 413 * @width: width of the divider bit field 414 * @table: array of value/divider pairs, last entry should have div = 0 415 * @lock: register lock 416 * 417 * Clock with an adjustable divider affecting its output frequency. Implements 418 * .recalc_rate, .set_rate and .round_rate 419 * 420 * Flags: 421 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 422 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 423 * the raw value read from the register, with the value of zero considered 424 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 425 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 426 * the hardware register 427 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 428 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 429 * Some hardware implementations gracefully handle this case and allow a 430 * zero divisor by not modifying their input clock 431 * (divide by one / bypass). 432 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 433 * of this register, and mask of divider bits are in higher 16-bit of this 434 * register. While setting the divider bits, higher 16-bit should also be 435 * updated to indicate changing divider bits. 436 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 437 * to the closest integer instead of the up one. 438 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 439 * not be changed by the clock framework. 440 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED 441 * except when the value read from the register is zero, the divisor is 442 * 2^width of the field. 443 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used 444 * for the divider register. Setting this flag makes the register accesses 445 * big endian. 446 */ 447 struct clk_divider { 448 struct clk_hw hw; 449 void __iomem *reg; 450 u8 shift; 451 u8 width; 452 u8 flags; 453 const struct clk_div_table *table; 454 spinlock_t *lock; 455 }; 456 457 #define clk_div_mask(width) ((1 << (width)) - 1) 458 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 459 460 #define CLK_DIVIDER_ONE_BASED BIT(0) 461 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 462 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 463 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 464 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 465 #define CLK_DIVIDER_READ_ONLY BIT(5) 466 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 467 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 468 469 extern const struct clk_ops clk_divider_ops; 470 extern const struct clk_ops clk_divider_ro_ops; 471 472 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, 473 unsigned int val, const struct clk_div_table *table, 474 unsigned long flags, unsigned long width); 475 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 476 unsigned long rate, unsigned long *prate, 477 const struct clk_div_table *table, 478 u8 width, unsigned long flags); 479 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, 480 unsigned long rate, unsigned long *prate, 481 const struct clk_div_table *table, u8 width, 482 unsigned long flags, unsigned int val); 483 int divider_get_val(unsigned long rate, unsigned long parent_rate, 484 const struct clk_div_table *table, u8 width, 485 unsigned long flags); 486 487 struct clk *clk_register_divider(struct device *dev, const char *name, 488 const char *parent_name, unsigned long flags, 489 void __iomem *reg, u8 shift, u8 width, 490 u8 clk_divider_flags, spinlock_t *lock); 491 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name, 492 const char *parent_name, unsigned long flags, 493 void __iomem *reg, u8 shift, u8 width, 494 u8 clk_divider_flags, spinlock_t *lock); 495 struct clk *clk_register_divider_table(struct device *dev, const char *name, 496 const char *parent_name, unsigned long flags, 497 void __iomem *reg, u8 shift, u8 width, 498 u8 clk_divider_flags, const struct clk_div_table *table, 499 spinlock_t *lock); 500 struct clk_hw *clk_hw_register_divider_table(struct device *dev, 501 const char *name, const char *parent_name, unsigned long flags, 502 void __iomem *reg, u8 shift, u8 width, 503 u8 clk_divider_flags, const struct clk_div_table *table, 504 spinlock_t *lock); 505 void clk_unregister_divider(struct clk *clk); 506 void clk_hw_unregister_divider(struct clk_hw *hw); 507 508 /** 509 * struct clk_mux - multiplexer clock 510 * 511 * @hw: handle between common and hardware-specific interfaces 512 * @reg: register controlling multiplexer 513 * @table: array of register values corresponding to the parent index 514 * @shift: shift to multiplexer bit field 515 * @mask: mask of mutliplexer bit field 516 * @flags: hardware-specific flags 517 * @lock: register lock 518 * 519 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 520 * and .recalc_rate 521 * 522 * Flags: 523 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 524 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 525 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 526 * register, and mask of mux bits are in higher 16-bit of this register. 527 * While setting the mux bits, higher 16-bit should also be updated to 528 * indicate changing mux bits. 529 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the 530 * .get_parent clk_op. 531 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired 532 * frequency. 533 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for 534 * the mux register. Setting this flag makes the register accesses big 535 * endian. 536 */ 537 struct clk_mux { 538 struct clk_hw hw; 539 void __iomem *reg; 540 u32 *table; 541 u32 mask; 542 u8 shift; 543 u8 flags; 544 spinlock_t *lock; 545 }; 546 547 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) 548 549 #define CLK_MUX_INDEX_ONE BIT(0) 550 #define CLK_MUX_INDEX_BIT BIT(1) 551 #define CLK_MUX_HIWORD_MASK BIT(2) 552 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ 553 #define CLK_MUX_ROUND_CLOSEST BIT(4) 554 #define CLK_MUX_BIG_ENDIAN BIT(5) 555 556 extern const struct clk_ops clk_mux_ops; 557 extern const struct clk_ops clk_mux_ro_ops; 558 559 struct clk *clk_register_mux(struct device *dev, const char *name, 560 const char * const *parent_names, u8 num_parents, 561 unsigned long flags, 562 void __iomem *reg, u8 shift, u8 width, 563 u8 clk_mux_flags, spinlock_t *lock); 564 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name, 565 const char * const *parent_names, u8 num_parents, 566 unsigned long flags, 567 void __iomem *reg, u8 shift, u8 width, 568 u8 clk_mux_flags, spinlock_t *lock); 569 570 struct clk *clk_register_mux_table(struct device *dev, const char *name, 571 const char * const *parent_names, u8 num_parents, 572 unsigned long flags, 573 void __iomem *reg, u8 shift, u32 mask, 574 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 575 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name, 576 const char * const *parent_names, u8 num_parents, 577 unsigned long flags, 578 void __iomem *reg, u8 shift, u32 mask, 579 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 580 581 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, 582 unsigned int val); 583 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index); 584 585 void clk_unregister_mux(struct clk *clk); 586 void clk_hw_unregister_mux(struct clk_hw *hw); 587 588 void of_fixed_factor_clk_setup(struct device_node *node); 589 590 /** 591 * struct clk_fixed_factor - fixed multiplier and divider clock 592 * 593 * @hw: handle between common and hardware-specific interfaces 594 * @mult: multiplier 595 * @div: divider 596 * 597 * Clock with a fixed multiplier and divider. The output frequency is the 598 * parent clock rate divided by div and multiplied by mult. 599 * Implements .recalc_rate, .set_rate and .round_rate 600 */ 601 602 struct clk_fixed_factor { 603 struct clk_hw hw; 604 unsigned int mult; 605 unsigned int div; 606 }; 607 608 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) 609 610 extern const struct clk_ops clk_fixed_factor_ops; 611 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 612 const char *parent_name, unsigned long flags, 613 unsigned int mult, unsigned int div); 614 void clk_unregister_fixed_factor(struct clk *clk); 615 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 616 const char *name, const char *parent_name, unsigned long flags, 617 unsigned int mult, unsigned int div); 618 void clk_hw_unregister_fixed_factor(struct clk_hw *hw); 619 620 /** 621 * struct clk_fractional_divider - adjustable fractional divider clock 622 * 623 * @hw: handle between common and hardware-specific interfaces 624 * @reg: register containing the divider 625 * @mshift: shift to the numerator bit field 626 * @mwidth: width of the numerator bit field 627 * @nshift: shift to the denominator bit field 628 * @nwidth: width of the denominator bit field 629 * @lock: register lock 630 * 631 * Clock with adjustable fractional divider affecting its output frequency. 632 * 633 * Flags: 634 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator 635 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED 636 * is set then the numerator and denominator are both the value read 637 * plus one. 638 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are 639 * used for the divider register. Setting this flag makes the register 640 * accesses big endian. 641 */ 642 struct clk_fractional_divider { 643 struct clk_hw hw; 644 void __iomem *reg; 645 u8 mshift; 646 u8 mwidth; 647 u32 mmask; 648 u8 nshift; 649 u8 nwidth; 650 u32 nmask; 651 u8 flags; 652 void (*approximation)(struct clk_hw *hw, 653 unsigned long rate, unsigned long *parent_rate, 654 unsigned long *m, unsigned long *n); 655 spinlock_t *lock; 656 }; 657 658 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) 659 660 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) 661 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) 662 663 extern const struct clk_ops clk_fractional_divider_ops; 664 struct clk *clk_register_fractional_divider(struct device *dev, 665 const char *name, const char *parent_name, unsigned long flags, 666 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 667 u8 clk_divider_flags, spinlock_t *lock); 668 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, 669 const char *name, const char *parent_name, unsigned long flags, 670 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 671 u8 clk_divider_flags, spinlock_t *lock); 672 void clk_hw_unregister_fractional_divider(struct clk_hw *hw); 673 674 /** 675 * struct clk_multiplier - adjustable multiplier clock 676 * 677 * @hw: handle between common and hardware-specific interfaces 678 * @reg: register containing the multiplier 679 * @shift: shift to the multiplier bit field 680 * @width: width of the multiplier bit field 681 * @lock: register lock 682 * 683 * Clock with an adjustable multiplier affecting its output frequency. 684 * Implements .recalc_rate, .set_rate and .round_rate 685 * 686 * Flags: 687 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read 688 * from the register, with 0 being a valid value effectively 689 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is 690 * set, then a null multiplier will be considered as a bypass, 691 * leaving the parent rate unmodified. 692 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be 693 * rounded to the closest integer instead of the down one. 694 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are 695 * used for the multiplier register. Setting this flag makes the register 696 * accesses big endian. 697 */ 698 struct clk_multiplier { 699 struct clk_hw hw; 700 void __iomem *reg; 701 u8 shift; 702 u8 width; 703 u8 flags; 704 spinlock_t *lock; 705 }; 706 707 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) 708 709 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) 710 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) 711 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2) 712 713 extern const struct clk_ops clk_multiplier_ops; 714 715 /*** 716 * struct clk_composite - aggregate clock of mux, divider and gate clocks 717 * 718 * @hw: handle between common and hardware-specific interfaces 719 * @mux_hw: handle between composite and hardware-specific mux clock 720 * @rate_hw: handle between composite and hardware-specific rate clock 721 * @gate_hw: handle between composite and hardware-specific gate clock 722 * @mux_ops: clock ops for mux 723 * @rate_ops: clock ops for rate 724 * @gate_ops: clock ops for gate 725 */ 726 struct clk_composite { 727 struct clk_hw hw; 728 struct clk_ops ops; 729 730 struct clk_hw *mux_hw; 731 struct clk_hw *rate_hw; 732 struct clk_hw *gate_hw; 733 734 const struct clk_ops *mux_ops; 735 const struct clk_ops *rate_ops; 736 const struct clk_ops *gate_ops; 737 }; 738 739 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) 740 741 struct clk *clk_register_composite(struct device *dev, const char *name, 742 const char * const *parent_names, int num_parents, 743 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 744 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 745 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 746 unsigned long flags); 747 void clk_unregister_composite(struct clk *clk); 748 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, 749 const char * const *parent_names, int num_parents, 750 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 751 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 752 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 753 unsigned long flags); 754 void clk_hw_unregister_composite(struct clk_hw *hw); 755 756 /** 757 * struct clk_gpio - gpio gated clock 758 * 759 * @hw: handle between common and hardware-specific interfaces 760 * @gpiod: gpio descriptor 761 * 762 * Clock with a gpio control for enabling and disabling the parent clock 763 * or switching between two parents by asserting or deasserting the gpio. 764 * 765 * Implements .enable, .disable and .is_enabled or 766 * .get_parent, .set_parent and .determine_rate depending on which clk_ops 767 * is used. 768 */ 769 struct clk_gpio { 770 struct clk_hw hw; 771 struct gpio_desc *gpiod; 772 }; 773 774 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) 775 776 extern const struct clk_ops clk_gpio_gate_ops; 777 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 778 const char *parent_name, struct gpio_desc *gpiod, 779 unsigned long flags); 780 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 781 const char *parent_name, struct gpio_desc *gpiod, 782 unsigned long flags); 783 void clk_hw_unregister_gpio_gate(struct clk_hw *hw); 784 785 extern const struct clk_ops clk_gpio_mux_ops; 786 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 787 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 788 unsigned long flags); 789 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 790 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod, 791 unsigned long flags); 792 void clk_hw_unregister_gpio_mux(struct clk_hw *hw); 793 794 struct clk *clk_register(struct device *dev, struct clk_hw *hw); 795 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 796 797 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw); 798 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw); 799 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw); 800 801 void clk_unregister(struct clk *clk); 802 void devm_clk_unregister(struct device *dev, struct clk *clk); 803 804 void clk_hw_unregister(struct clk_hw *hw); 805 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw); 806 807 /* helper functions */ 808 const char *__clk_get_name(const struct clk *clk); 809 const char *clk_hw_get_name(const struct clk_hw *hw); 810 struct clk_hw *__clk_get_hw(struct clk *clk); 811 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); 812 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 813 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 814 unsigned int index); 815 unsigned int __clk_get_enable_count(struct clk *clk); 816 unsigned long clk_hw_get_rate(const struct clk_hw *hw); 817 unsigned long __clk_get_flags(struct clk *clk); 818 unsigned long clk_hw_get_flags(const struct clk_hw *hw); 819 #define clk_hw_can_set_rate_parent(hw) \ 820 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) 821 822 bool clk_hw_is_prepared(const struct clk_hw *hw); 823 bool clk_hw_rate_is_protected(const struct clk_hw *hw); 824 bool clk_hw_is_enabled(const struct clk_hw *hw); 825 bool __clk_is_enabled(struct clk *clk); 826 struct clk *__clk_lookup(const char *name); 827 int __clk_mux_determine_rate(struct clk_hw *hw, 828 struct clk_rate_request *req); 829 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req); 830 int __clk_mux_determine_rate_closest(struct clk_hw *hw, 831 struct clk_rate_request *req); 832 int clk_mux_determine_rate_flags(struct clk_hw *hw, 833 struct clk_rate_request *req, 834 unsigned long flags); 835 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent); 836 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, 837 unsigned long max_rate); 838 839 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) 840 { 841 dst->clk = src->clk; 842 dst->core = src->core; 843 } 844 845 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, 846 unsigned long *prate, 847 const struct clk_div_table *table, 848 u8 width, unsigned long flags) 849 { 850 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 851 rate, prate, table, width, flags); 852 } 853 854 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, 855 unsigned long *prate, 856 const struct clk_div_table *table, 857 u8 width, unsigned long flags, 858 unsigned int val) 859 { 860 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), 861 rate, prate, table, width, flags, 862 val); 863 } 864 865 /* 866 * FIXME clock api without lock protection 867 */ 868 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate); 869 870 struct of_device_id; 871 872 struct clk_onecell_data { 873 struct clk **clks; 874 unsigned int clk_num; 875 }; 876 877 struct clk_hw_onecell_data { 878 unsigned int num; 879 struct clk_hw *hws[]; 880 }; 881 882 extern struct of_device_id __clk_of_table; 883 884 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 885 886 /* 887 * Use this macro when you have a driver that requires two initialization 888 * routines, one at of_clk_init(), and one at platform device probe 889 */ 890 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \ 891 static void __init name##_of_clk_init_driver(struct device_node *np) \ 892 { \ 893 of_node_clear_flag(np, OF_POPULATED); \ 894 fn(np); \ 895 } \ 896 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver) 897 898 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ 899 (&(struct clk_init_data) { \ 900 .flags = _flags, \ 901 .name = _name, \ 902 .parent_names = (const char *[]) { _parent }, \ 903 .num_parents = 1, \ 904 .ops = _ops, \ 905 }) 906 907 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ 908 (&(struct clk_init_data) { \ 909 .flags = _flags, \ 910 .name = _name, \ 911 .parent_names = _parents, \ 912 .num_parents = ARRAY_SIZE(_parents), \ 913 .ops = _ops, \ 914 }) 915 916 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \ 917 (&(struct clk_init_data) { \ 918 .flags = _flags, \ 919 .name = _name, \ 920 .parent_names = NULL, \ 921 .num_parents = 0, \ 922 .ops = _ops, \ 923 }) 924 925 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ 926 _div, _mult, _flags) \ 927 struct clk_fixed_factor _struct = { \ 928 .div = _div, \ 929 .mult = _mult, \ 930 .hw.init = CLK_HW_INIT(_name, \ 931 _parent, \ 932 &clk_fixed_factor_ops, \ 933 _flags), \ 934 } 935 936 #ifdef CONFIG_OF 937 int of_clk_add_provider(struct device_node *np, 938 struct clk *(*clk_src_get)(struct of_phandle_args *args, 939 void *data), 940 void *data); 941 int of_clk_add_hw_provider(struct device_node *np, 942 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 943 void *data), 944 void *data); 945 int devm_of_clk_add_hw_provider(struct device *dev, 946 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 947 void *data), 948 void *data); 949 void of_clk_del_provider(struct device_node *np); 950 void devm_of_clk_del_provider(struct device *dev); 951 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 952 void *data); 953 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 954 void *data); 955 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 956 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, 957 void *data); 958 int of_clk_parent_fill(struct device_node *np, const char **parents, 959 unsigned int size); 960 int of_clk_detect_critical(struct device_node *np, int index, 961 unsigned long *flags); 962 963 #else /* !CONFIG_OF */ 964 965 static inline int of_clk_add_provider(struct device_node *np, 966 struct clk *(*clk_src_get)(struct of_phandle_args *args, 967 void *data), 968 void *data) 969 { 970 return 0; 971 } 972 static inline int of_clk_add_hw_provider(struct device_node *np, 973 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 974 void *data), 975 void *data) 976 { 977 return 0; 978 } 979 static inline int devm_of_clk_add_hw_provider(struct device *dev, 980 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 981 void *data), 982 void *data) 983 { 984 return 0; 985 } 986 static inline void of_clk_del_provider(struct device_node *np) {} 987 static inline void devm_of_clk_del_provider(struct device *dev) {} 988 static inline struct clk *of_clk_src_simple_get( 989 struct of_phandle_args *clkspec, void *data) 990 { 991 return ERR_PTR(-ENOENT); 992 } 993 static inline struct clk_hw * 994 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data) 995 { 996 return ERR_PTR(-ENOENT); 997 } 998 static inline struct clk *of_clk_src_onecell_get( 999 struct of_phandle_args *clkspec, void *data) 1000 { 1001 return ERR_PTR(-ENOENT); 1002 } 1003 static inline struct clk_hw * 1004 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data) 1005 { 1006 return ERR_PTR(-ENOENT); 1007 } 1008 static inline int of_clk_parent_fill(struct device_node *np, 1009 const char **parents, unsigned int size) 1010 { 1011 return 0; 1012 } 1013 static inline int of_clk_detect_critical(struct device_node *np, int index, 1014 unsigned long *flags) 1015 { 1016 return 0; 1017 } 1018 #endif /* CONFIG_OF */ 1019 1020 void clk_gate_restore_context(struct clk_hw *hw); 1021 1022 #endif /* CONFIG_COMMON_CLK */ 1023 #endif /* CLK_PROVIDER_H */ 1024