1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2017 Texas Instruments, Inc. 4 */ 5 #ifndef __DT_BINDINGS_CLK_OMAP4_H 6 #define __DT_BINDINGS_CLK_OMAP4_H 7 8 #define OMAP4_CLKCTRL_OFFSET 0x20 9 #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) 10 11 /* mpuss clocks */ 12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 13 14 /* tesla clocks */ 15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 16 17 /* abe clocks */ 18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) 24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 25 #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 26 #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 27 #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 28 #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) 29 #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 30 #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) 31 #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) 32 33 /* l4_ao clocks */ 34 #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 35 #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 36 #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 37 38 /* l3_1 clocks */ 39 #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 40 41 /* l3_2 clocks */ 42 #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 43 #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 44 #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 45 46 /* ducati clocks */ 47 #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 48 49 /* l3_dma clocks */ 50 #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 51 52 /* l3_emif clocks */ 53 #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 54 #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 55 #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 56 57 /* d2d clocks */ 58 #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 59 60 /* l4_cfg clocks */ 61 #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 62 #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 63 #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 64 65 /* l3_instr clocks */ 66 #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 67 #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 68 #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 69 70 /* ivahd clocks */ 71 #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 72 #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 73 74 /* iss clocks */ 75 #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 76 #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 77 78 /* l3_dss clocks */ 79 #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 80 81 /* l3_gfx clocks */ 82 #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 83 84 /* l3_init clocks */ 85 #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 86 #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 87 #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 88 #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 89 #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 90 #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 91 #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) 92 #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) 93 94 /* l4_per clocks */ 95 #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 96 #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 97 #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 98 #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 99 #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) 100 #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 101 #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 102 #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 103 #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 104 #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) 105 #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 106 #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) 107 #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) 108 #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) 109 #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) 110 #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) 111 #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) 112 #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) 113 #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) 114 #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) 115 #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) 116 #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) 117 #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) 118 #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) 119 #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) 120 #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) 121 #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) 122 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) 123 #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) 124 #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) 125 #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) 126 127 /* l4_wkup clocks */ 128 #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 129 #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 130 #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 131 #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 132 #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 133 #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 134 135 /* emu_sys clocks */ 136 #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 137 138 #endif 139