1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * xHCI host controller driver 4 * 5 * Copyright (C) 2008 Intel Corp. 6 * 7 * Author: Sarah Sharp 8 * Some code borrowed from the Linux EHCI driver. 9 */ 10 11 /* 12 * Ring initialization rules: 13 * 1. Each segment is initialized to zero, except for link TRBs. 14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or 15 * Consumer Cycle State (CCS), depending on ring function. 16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. 17 * 18 * Ring behavior rules: 19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at 20 * least one free TRB in the ring. This is useful if you want to turn that 21 * into a link TRB and expand the ring. 22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a 23 * link TRB, then load the pointer with the address in the link TRB. If the 24 * link TRB had its toggle bit set, you may need to update the ring cycle 25 * state (see cycle bit rules). You may have to do this multiple times 26 * until you reach a non-link TRB. 27 * 3. A ring is full if enqueue++ (for the definition of increment above) 28 * equals the dequeue pointer. 29 * 30 * Cycle bit rules: 31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit 32 * in a link TRB, it must toggle the ring cycle state. 33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit 34 * in a link TRB, it must toggle the ring cycle state. 35 * 36 * Producer rules: 37 * 1. Check if ring is full before you enqueue. 38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. 39 * Update enqueue pointer between each write (which may update the ring 40 * cycle state). 41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command 42 * and endpoint rings. If HC is the producer for the event ring, 43 * and it generates an interrupt according to interrupt modulation rules. 44 * 45 * Consumer rules: 46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, 47 * the TRB is owned by the consumer. 48 * 2. Update dequeue pointer (which may update the ring cycle state) and 49 * continue processing TRBs until you reach a TRB which is not owned by you. 50 * 3. Notify the producer. SW is the consumer for the event ring, and it 51 * updates event ring dequeue pointer. HC is the consumer for the command and 52 * endpoint rings; it generates events on the event ring for these. 53 */ 54 55 #include <linux/scatterlist.h> 56 #include <linux/slab.h> 57 #include <linux/dma-mapping.h> 58 #include "xhci.h" 59 #include "xhci-trace.h" 60 #include "xhci-mtk.h" 61 62 /* 63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA 64 * address of the TRB. 65 */ 66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, 67 union xhci_trb *trb) 68 { 69 unsigned long segment_offset; 70 71 if (!seg || !trb || trb < seg->trbs) 72 return 0; 73 /* offset in TRBs */ 74 segment_offset = trb - seg->trbs; 75 if (segment_offset >= TRBS_PER_SEGMENT) 76 return 0; 77 return seg->dma + (segment_offset * sizeof(*trb)); 78 } 79 80 static bool trb_is_noop(union xhci_trb *trb) 81 { 82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); 83 } 84 85 static bool trb_is_link(union xhci_trb *trb) 86 { 87 return TRB_TYPE_LINK_LE32(trb->link.control); 88 } 89 90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) 91 { 92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; 93 } 94 95 static bool last_trb_on_ring(struct xhci_ring *ring, 96 struct xhci_segment *seg, union xhci_trb *trb) 97 { 98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); 99 } 100 101 static bool link_trb_toggles_cycle(union xhci_trb *trb) 102 { 103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE; 104 } 105 106 static bool last_td_in_urb(struct xhci_td *td) 107 { 108 struct urb_priv *urb_priv = td->urb->hcpriv; 109 110 return urb_priv->num_tds_done == urb_priv->num_tds; 111 } 112 113 static void inc_td_cnt(struct urb *urb) 114 { 115 struct urb_priv *urb_priv = urb->hcpriv; 116 117 urb_priv->num_tds_done++; 118 } 119 120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type) 121 { 122 if (trb_is_link(trb)) { 123 /* unchain chained link TRBs */ 124 trb->link.control &= cpu_to_le32(~TRB_CHAIN); 125 } else { 126 trb->generic.field[0] = 0; 127 trb->generic.field[1] = 0; 128 trb->generic.field[2] = 0; 129 /* Preserve only the cycle bit of this TRB */ 130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); 131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); 132 } 133 } 134 135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next 136 * TRB is in a new segment. This does not skip over link TRBs, and it does not 137 * effect the ring dequeue or enqueue pointers. 138 */ 139 static void next_trb(struct xhci_hcd *xhci, 140 struct xhci_ring *ring, 141 struct xhci_segment **seg, 142 union xhci_trb **trb) 143 { 144 if (trb_is_link(*trb)) { 145 *seg = (*seg)->next; 146 *trb = ((*seg)->trbs); 147 } else { 148 (*trb)++; 149 } 150 } 151 152 /* 153 * See Cycle bit rules. SW is the consumer for the event ring only. 154 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 155 */ 156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) 157 { 158 /* event ring doesn't have link trbs, check for last trb */ 159 if (ring->type == TYPE_EVENT) { 160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { 161 ring->dequeue++; 162 goto out; 163 } 164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) 165 ring->cycle_state ^= 1; 166 ring->deq_seg = ring->deq_seg->next; 167 ring->dequeue = ring->deq_seg->trbs; 168 goto out; 169 } 170 171 /* All other rings have link trbs */ 172 if (!trb_is_link(ring->dequeue)) { 173 ring->dequeue++; 174 ring->num_trbs_free++; 175 } 176 while (trb_is_link(ring->dequeue)) { 177 ring->deq_seg = ring->deq_seg->next; 178 ring->dequeue = ring->deq_seg->trbs; 179 } 180 181 out: 182 trace_xhci_inc_deq(ring); 183 184 return; 185 } 186 187 /* 188 * See Cycle bit rules. SW is the consumer for the event ring only. 189 * Don't make a ring full of link TRBs. That would be dumb and this would loop. 190 * 191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the 192 * chain bit is set), then set the chain bit in all the following link TRBs. 193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs 194 * have their chain bit cleared (so that each Link TRB is a separate TD). 195 * 196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit 197 * set, but other sections talk about dealing with the chain bit set. This was 198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95 199 * xHCI hardware can't handle the chain bit being cleared on a link TRB. 200 * 201 * @more_trbs_coming: Will you enqueue more TRBs before calling 202 * prepare_transfer()? 203 */ 204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, 205 bool more_trbs_coming) 206 { 207 u32 chain; 208 union xhci_trb *next; 209 210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; 211 /* If this is not event ring, there is one less usable TRB */ 212 if (!trb_is_link(ring->enqueue)) 213 ring->num_trbs_free--; 214 next = ++(ring->enqueue); 215 216 /* Update the dequeue pointer further if that was a link TRB */ 217 while (trb_is_link(next)) { 218 219 /* 220 * If the caller doesn't plan on enqueueing more TDs before 221 * ringing the doorbell, then we don't want to give the link TRB 222 * to the hardware just yet. We'll give the link TRB back in 223 * prepare_ring() just before we enqueue the TD at the top of 224 * the ring. 225 */ 226 if (!chain && !more_trbs_coming) 227 break; 228 229 /* If we're not dealing with 0.95 hardware or isoc rings on 230 * AMD 0.96 host, carry over the chain bit of the previous TRB 231 * (which may mean the chain bit is cleared). 232 */ 233 if (!(ring->type == TYPE_ISOC && 234 (xhci->quirks & XHCI_AMD_0x96_HOST)) && 235 !xhci_link_trb_quirk(xhci)) { 236 next->link.control &= cpu_to_le32(~TRB_CHAIN); 237 next->link.control |= cpu_to_le32(chain); 238 } 239 /* Give this link TRB to the hardware */ 240 wmb(); 241 next->link.control ^= cpu_to_le32(TRB_CYCLE); 242 243 /* Toggle the cycle bit after the last ring segment. */ 244 if (link_trb_toggles_cycle(next)) 245 ring->cycle_state ^= 1; 246 247 ring->enq_seg = ring->enq_seg->next; 248 ring->enqueue = ring->enq_seg->trbs; 249 next = ring->enqueue; 250 } 251 252 trace_xhci_inc_enq(ring); 253 } 254 255 /* 256 * Check to see if there's room to enqueue num_trbs on the ring and make sure 257 * enqueue pointer will not advance into dequeue segment. See rules above. 258 */ 259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, 260 unsigned int num_trbs) 261 { 262 int num_trbs_in_deq_seg; 263 264 if (ring->num_trbs_free < num_trbs) 265 return 0; 266 267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { 268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; 269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) 270 return 0; 271 } 272 273 return 1; 274 } 275 276 /* Ring the host controller doorbell after placing a command on the ring */ 277 void xhci_ring_cmd_db(struct xhci_hcd *xhci) 278 { 279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) 280 return; 281 282 xhci_dbg(xhci, "// Ding dong!\n"); 283 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); 284 /* Flush PCI posted writes */ 285 readl(&xhci->dba->doorbell[0]); 286 } 287 288 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) 289 { 290 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); 291 } 292 293 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) 294 { 295 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, 296 cmd_list); 297 } 298 299 /* 300 * Turn all commands on command ring with status set to "aborted" to no-op trbs. 301 * If there are other commands waiting then restart the ring and kick the timer. 302 * This must be called with command ring stopped and xhci->lock held. 303 */ 304 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, 305 struct xhci_command *cur_cmd) 306 { 307 struct xhci_command *i_cmd; 308 309 /* Turn all aborted commands in list to no-ops, then restart */ 310 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { 311 312 if (i_cmd->status != COMP_COMMAND_ABORTED) 313 continue; 314 315 i_cmd->status = COMP_COMMAND_RING_STOPPED; 316 317 xhci_dbg(xhci, "Turn aborted command %p to no-op\n", 318 i_cmd->command_trb); 319 320 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); 321 322 /* 323 * caller waiting for completion is called when command 324 * completion event is received for these no-op commands 325 */ 326 } 327 328 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; 329 330 /* ring command ring doorbell to restart the command ring */ 331 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && 332 !(xhci->xhc_state & XHCI_STATE_DYING)) { 333 xhci->current_cmd = cur_cmd; 334 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 335 xhci_ring_cmd_db(xhci); 336 } 337 } 338 339 /* Must be called with xhci->lock held, releases and aquires lock back */ 340 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) 341 { 342 u64 temp_64; 343 int ret; 344 345 xhci_dbg(xhci, "Abort command ring\n"); 346 347 reinit_completion(&xhci->cmd_ring_stop_completion); 348 349 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 350 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, 351 &xhci->op_regs->cmd_ring); 352 353 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the 354 * completion of the Command Abort operation. If CRR is not negated in 5 355 * seconds then driver handles it as if host died (-ENODEV). 356 * In the future we should distinguish between -ENODEV and -ETIMEDOUT 357 * and try to recover a -ETIMEDOUT with a host controller reset. 358 */ 359 ret = xhci_handshake(&xhci->op_regs->cmd_ring, 360 CMD_RING_RUNNING, 0, 5 * 1000 * 1000); 361 if (ret < 0) { 362 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); 363 xhci_halt(xhci); 364 xhci_hc_died(xhci); 365 return ret; 366 } 367 /* 368 * Writing the CMD_RING_ABORT bit should cause a cmd completion event, 369 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared 370 * but the completion event in never sent. Wait 2 secs (arbitrary 371 * number) to handle those cases after negation of CMD_RING_RUNNING. 372 */ 373 spin_unlock_irqrestore(&xhci->lock, flags); 374 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, 375 msecs_to_jiffies(2000)); 376 spin_lock_irqsave(&xhci->lock, flags); 377 if (!ret) { 378 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); 379 xhci_cleanup_command_queue(xhci); 380 } else { 381 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); 382 } 383 return 0; 384 } 385 386 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, 387 unsigned int slot_id, 388 unsigned int ep_index, 389 unsigned int stream_id) 390 { 391 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; 392 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 393 unsigned int ep_state = ep->ep_state; 394 395 /* Don't ring the doorbell for this endpoint if there are pending 396 * cancellations because we don't want to interrupt processing. 397 * We don't want to restart any stream rings if there's a set dequeue 398 * pointer command pending because the device can choose to start any 399 * stream once the endpoint is on the HW schedule. 400 */ 401 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || 402 (ep_state & EP_HALTED)) 403 return; 404 writel(DB_VALUE(ep_index, stream_id), db_addr); 405 /* The CPU has better things to do at this point than wait for a 406 * write-posting flush. It'll get there soon enough. 407 */ 408 } 409 410 /* Ring the doorbell for any rings with pending URBs */ 411 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, 412 unsigned int slot_id, 413 unsigned int ep_index) 414 { 415 unsigned int stream_id; 416 struct xhci_virt_ep *ep; 417 418 ep = &xhci->devs[slot_id]->eps[ep_index]; 419 420 /* A ring has pending URBs if its TD list is not empty */ 421 if (!(ep->ep_state & EP_HAS_STREAMS)) { 422 if (ep->ring && !(list_empty(&ep->ring->td_list))) 423 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); 424 return; 425 } 426 427 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 428 stream_id++) { 429 struct xhci_stream_info *stream_info = ep->stream_info; 430 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) 431 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 432 stream_id); 433 } 434 } 435 436 /* Get the right ring for the given slot_id, ep_index and stream_id. 437 * If the endpoint supports streams, boundary check the URB's stream ID. 438 * If the endpoint doesn't support streams, return the singular endpoint ring. 439 */ 440 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 441 unsigned int slot_id, unsigned int ep_index, 442 unsigned int stream_id) 443 { 444 struct xhci_virt_ep *ep; 445 446 ep = &xhci->devs[slot_id]->eps[ep_index]; 447 /* Common case: no streams */ 448 if (!(ep->ep_state & EP_HAS_STREAMS)) 449 return ep->ring; 450 451 if (stream_id == 0) { 452 xhci_warn(xhci, 453 "WARN: Slot ID %u, ep index %u has streams, " 454 "but URB has no stream ID.\n", 455 slot_id, ep_index); 456 return NULL; 457 } 458 459 if (stream_id < ep->stream_info->num_streams) 460 return ep->stream_info->stream_rings[stream_id]; 461 462 xhci_warn(xhci, 463 "WARN: Slot ID %u, ep index %u has " 464 "stream IDs 1 to %u allocated, " 465 "but stream ID %u is requested.\n", 466 slot_id, ep_index, 467 ep->stream_info->num_streams - 1, 468 stream_id); 469 return NULL; 470 } 471 472 473 /* 474 * Get the hw dequeue pointer xHC stopped on, either directly from the 475 * endpoint context, or if streams are in use from the stream context. 476 * The returned hw_dequeue contains the lowest four bits with cycle state 477 * and possbile stream context type. 478 */ 479 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, 480 unsigned int ep_index, unsigned int stream_id) 481 { 482 struct xhci_ep_ctx *ep_ctx; 483 struct xhci_stream_ctx *st_ctx; 484 struct xhci_virt_ep *ep; 485 486 ep = &vdev->eps[ep_index]; 487 488 if (ep->ep_state & EP_HAS_STREAMS) { 489 st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; 490 return le64_to_cpu(st_ctx->stream_ring); 491 } 492 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 493 return le64_to_cpu(ep_ctx->deq); 494 } 495 496 /* 497 * Move the xHC's endpoint ring dequeue pointer past cur_td. 498 * Record the new state of the xHC's endpoint ring dequeue segment, 499 * dequeue pointer, stream id, and new consumer cycle state in state. 500 * Update our internal representation of the ring's dequeue pointer. 501 * 502 * We do this in three jumps: 503 * - First we update our new ring state to be the same as when the xHC stopped. 504 * - Then we traverse the ring to find the segment that contains 505 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass 506 * any link TRBs with the toggle cycle bit set. 507 * - Finally we move the dequeue state one TRB further, toggling the cycle bit 508 * if we've moved it past a link TRB with the toggle cycle bit set. 509 * 510 * Some of the uses of xhci_generic_trb are grotty, but if they're done 511 * with correct __le32 accesses they should work fine. Only users of this are 512 * in here. 513 */ 514 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 515 unsigned int slot_id, unsigned int ep_index, 516 unsigned int stream_id, struct xhci_td *cur_td, 517 struct xhci_dequeue_state *state) 518 { 519 struct xhci_virt_device *dev = xhci->devs[slot_id]; 520 struct xhci_virt_ep *ep = &dev->eps[ep_index]; 521 struct xhci_ring *ep_ring; 522 struct xhci_segment *new_seg; 523 union xhci_trb *new_deq; 524 dma_addr_t addr; 525 u64 hw_dequeue; 526 bool cycle_found = false; 527 bool td_last_trb_found = false; 528 529 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, 530 ep_index, stream_id); 531 if (!ep_ring) { 532 xhci_warn(xhci, "WARN can't find new dequeue state " 533 "for invalid stream ID %u.\n", 534 stream_id); 535 return; 536 } 537 /* Dig out the cycle state saved by the xHC during the stop ep cmd */ 538 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 539 "Finding endpoint context"); 540 541 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); 542 new_seg = ep_ring->deq_seg; 543 new_deq = ep_ring->dequeue; 544 state->new_cycle_state = hw_dequeue & 0x1; 545 state->stream_id = stream_id; 546 547 /* 548 * We want to find the pointer, segment and cycle state of the new trb 549 * (the one after current TD's last_trb). We know the cycle state at 550 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are 551 * found. 552 */ 553 do { 554 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) 555 == (dma_addr_t)(hw_dequeue & ~0xf)) { 556 cycle_found = true; 557 if (td_last_trb_found) 558 break; 559 } 560 if (new_deq == cur_td->last_trb) 561 td_last_trb_found = true; 562 563 if (cycle_found && trb_is_link(new_deq) && 564 link_trb_toggles_cycle(new_deq)) 565 state->new_cycle_state ^= 0x1; 566 567 next_trb(xhci, ep_ring, &new_seg, &new_deq); 568 569 /* Search wrapped around, bail out */ 570 if (new_deq == ep->ring->dequeue) { 571 xhci_err(xhci, "Error: Failed finding new dequeue state\n"); 572 state->new_deq_seg = NULL; 573 state->new_deq_ptr = NULL; 574 return; 575 } 576 577 } while (!cycle_found || !td_last_trb_found); 578 579 state->new_deq_seg = new_seg; 580 state->new_deq_ptr = new_deq; 581 582 /* Don't update the ring cycle state for the producer (us). */ 583 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 584 "Cycle state = 0x%x", state->new_cycle_state); 585 586 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 587 "New dequeue segment = %p (virtual)", 588 state->new_deq_seg); 589 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); 590 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 591 "New dequeue pointer = 0x%llx (DMA)", 592 (unsigned long long) addr); 593 } 594 595 /* flip_cycle means flip the cycle bit of all but the first and last TRB. 596 * (The last TRB actually points to the ring enqueue pointer, which is not part 597 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. 598 */ 599 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 600 struct xhci_td *td, bool flip_cycle) 601 { 602 struct xhci_segment *seg = td->start_seg; 603 union xhci_trb *trb = td->first_trb; 604 605 while (1) { 606 trb_to_noop(trb, TRB_TR_NOOP); 607 608 /* flip cycle if asked to */ 609 if (flip_cycle && trb != td->first_trb && trb != td->last_trb) 610 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); 611 612 if (trb == td->last_trb) 613 break; 614 615 next_trb(xhci, ep_ring, &seg, &trb); 616 } 617 } 618 619 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, 620 struct xhci_virt_ep *ep) 621 { 622 ep->ep_state &= ~EP_STOP_CMD_PENDING; 623 /* Can't del_timer_sync in interrupt */ 624 del_timer(&ep->stop_cmd_timer); 625 } 626 627 /* 628 * Must be called with xhci->lock held in interrupt context, 629 * releases and re-acquires xhci->lock 630 */ 631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, 632 struct xhci_td *cur_td, int status) 633 { 634 struct urb *urb = cur_td->urb; 635 struct urb_priv *urb_priv = urb->hcpriv; 636 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); 637 638 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 639 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; 640 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 641 if (xhci->quirks & XHCI_AMD_PLL_FIX) 642 usb_amd_quirk_pll_enable(); 643 } 644 } 645 xhci_urb_free_priv(urb_priv); 646 usb_hcd_unlink_urb_from_ep(hcd, urb); 647 spin_unlock(&xhci->lock); 648 trace_xhci_urb_giveback(urb); 649 usb_hcd_giveback_urb(hcd, urb, status); 650 spin_lock(&xhci->lock); 651 } 652 653 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, 654 struct xhci_ring *ring, struct xhci_td *td) 655 { 656 struct device *dev = xhci_to_hcd(xhci)->self.controller; 657 struct xhci_segment *seg = td->bounce_seg; 658 struct urb *urb = td->urb; 659 size_t len; 660 661 if (!ring || !seg || !urb) 662 return; 663 664 if (usb_urb_dir_out(urb)) { 665 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 666 DMA_TO_DEVICE); 667 return; 668 } 669 670 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, 671 DMA_FROM_DEVICE); 672 /* for in tranfers we need to copy the data from bounce to sg */ 673 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, 674 seg->bounce_len, seg->bounce_offs); 675 if (len != seg->bounce_len) 676 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n", 677 len, seg->bounce_len); 678 seg->bounce_len = 0; 679 seg->bounce_offs = 0; 680 } 681 682 /* 683 * When we get a command completion for a Stop Endpoint Command, we need to 684 * unlink any cancelled TDs from the ring. There are two ways to do that: 685 * 686 * 1. If the HW was in the middle of processing the TD that needs to be 687 * cancelled, then we must move the ring's dequeue pointer past the last TRB 688 * in the TD with a Set Dequeue Pointer Command. 689 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain 690 * bit cleared) so that the HW will skip over them. 691 */ 692 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, 693 union xhci_trb *trb, struct xhci_event_cmd *event) 694 { 695 unsigned int ep_index; 696 struct xhci_ring *ep_ring; 697 struct xhci_virt_ep *ep; 698 struct xhci_td *cur_td = NULL; 699 struct xhci_td *last_unlinked_td; 700 struct xhci_ep_ctx *ep_ctx; 701 struct xhci_virt_device *vdev; 702 u64 hw_deq; 703 struct xhci_dequeue_state deq_state; 704 705 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { 706 if (!xhci->devs[slot_id]) 707 xhci_warn(xhci, "Stop endpoint command " 708 "completion for disabled slot %u\n", 709 slot_id); 710 return; 711 } 712 713 memset(&deq_state, 0, sizeof(deq_state)); 714 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 715 716 vdev = xhci->devs[slot_id]; 717 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 718 trace_xhci_handle_cmd_stop_ep(ep_ctx); 719 720 ep = &xhci->devs[slot_id]->eps[ep_index]; 721 last_unlinked_td = list_last_entry(&ep->cancelled_td_list, 722 struct xhci_td, cancelled_td_list); 723 724 if (list_empty(&ep->cancelled_td_list)) { 725 xhci_stop_watchdog_timer_in_irq(xhci, ep); 726 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 727 return; 728 } 729 730 /* Fix up the ep ring first, so HW stops executing cancelled TDs. 731 * We have the xHCI lock, so nothing can modify this list until we drop 732 * it. We're also in the event handler, so we can't get re-interrupted 733 * if another Stop Endpoint command completes 734 */ 735 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { 736 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 737 "Removing canceled TD starting at 0x%llx (dma).", 738 (unsigned long long)xhci_trb_virt_to_dma( 739 cur_td->start_seg, cur_td->first_trb)); 740 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 741 if (!ep_ring) { 742 /* This shouldn't happen unless a driver is mucking 743 * with the stream ID after submission. This will 744 * leave the TD on the hardware ring, and the hardware 745 * will try to execute it, and may access a buffer 746 * that has already been freed. In the best case, the 747 * hardware will execute it, and the event handler will 748 * ignore the completion event for that TD, since it was 749 * removed from the td_list for that endpoint. In 750 * short, don't muck with the stream ID after 751 * submission. 752 */ 753 xhci_warn(xhci, "WARN Cancelled URB %p " 754 "has invalid stream ID %u.\n", 755 cur_td->urb, 756 cur_td->urb->stream_id); 757 goto remove_finished_td; 758 } 759 /* 760 * If we stopped on the TD we need to cancel, then we have to 761 * move the xHC endpoint ring dequeue pointer past this TD. 762 */ 763 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index, 764 cur_td->urb->stream_id); 765 hw_deq &= ~0xf; 766 767 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb, 768 cur_td->last_trb, hw_deq, false)) { 769 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, 770 cur_td->urb->stream_id, 771 cur_td, &deq_state); 772 } else { 773 td_to_noop(xhci, ep_ring, cur_td, false); 774 } 775 776 remove_finished_td: 777 /* 778 * The event handler won't see a completion for this TD anymore, 779 * so remove it from the endpoint ring's TD list. Keep it in 780 * the cancelled TD list for URB completion later. 781 */ 782 list_del_init(&cur_td->td_list); 783 } 784 785 xhci_stop_watchdog_timer_in_irq(xhci, ep); 786 787 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ 788 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { 789 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, 790 &deq_state); 791 xhci_ring_cmd_db(xhci); 792 } else { 793 /* Otherwise ring the doorbell(s) to restart queued transfers */ 794 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 795 } 796 797 /* 798 * Drop the lock and complete the URBs in the cancelled TD list. 799 * New TDs to be cancelled might be added to the end of the list before 800 * we can complete all the URBs for the TDs we already unlinked. 801 * So stop when we've completed the URB for the last TD we unlinked. 802 */ 803 do { 804 cur_td = list_first_entry(&ep->cancelled_td_list, 805 struct xhci_td, cancelled_td_list); 806 list_del_init(&cur_td->cancelled_td_list); 807 808 /* Clean up the cancelled URB */ 809 /* Doesn't matter what we pass for status, since the core will 810 * just overwrite it (because the URB has been unlinked). 811 */ 812 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); 813 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); 814 inc_td_cnt(cur_td->urb); 815 if (last_td_in_urb(cur_td)) 816 xhci_giveback_urb_in_irq(xhci, cur_td, 0); 817 818 /* Stop processing the cancelled list if the watchdog timer is 819 * running. 820 */ 821 if (xhci->xhc_state & XHCI_STATE_DYING) 822 return; 823 } while (cur_td != last_unlinked_td); 824 825 /* Return to the event handler with xhci->lock re-acquired */ 826 } 827 828 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) 829 { 830 struct xhci_td *cur_td; 831 struct xhci_td *tmp; 832 833 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { 834 list_del_init(&cur_td->td_list); 835 836 if (!list_empty(&cur_td->cancelled_td_list)) 837 list_del_init(&cur_td->cancelled_td_list); 838 839 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); 840 841 inc_td_cnt(cur_td->urb); 842 if (last_td_in_urb(cur_td)) 843 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 844 } 845 } 846 847 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, 848 int slot_id, int ep_index) 849 { 850 struct xhci_td *cur_td; 851 struct xhci_td *tmp; 852 struct xhci_virt_ep *ep; 853 struct xhci_ring *ring; 854 855 ep = &xhci->devs[slot_id]->eps[ep_index]; 856 if ((ep->ep_state & EP_HAS_STREAMS) || 857 (ep->ep_state & EP_GETTING_NO_STREAMS)) { 858 int stream_id; 859 860 for (stream_id = 1; stream_id < ep->stream_info->num_streams; 861 stream_id++) { 862 ring = ep->stream_info->stream_rings[stream_id]; 863 if (!ring) 864 continue; 865 866 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 867 "Killing URBs for slot ID %u, ep index %u, stream %u", 868 slot_id, ep_index, stream_id); 869 xhci_kill_ring_urbs(xhci, ring); 870 } 871 } else { 872 ring = ep->ring; 873 if (!ring) 874 return; 875 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 876 "Killing URBs for slot ID %u, ep index %u", 877 slot_id, ep_index); 878 xhci_kill_ring_urbs(xhci, ring); 879 } 880 881 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, 882 cancelled_td_list) { 883 list_del_init(&cur_td->cancelled_td_list); 884 inc_td_cnt(cur_td->urb); 885 886 if (last_td_in_urb(cur_td)) 887 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); 888 } 889 } 890 891 /* 892 * host controller died, register read returns 0xffffffff 893 * Complete pending commands, mark them ABORTED. 894 * URBs need to be given back as usb core might be waiting with device locks 895 * held for the URBs to finish during device disconnect, blocking host remove. 896 * 897 * Call with xhci->lock held. 898 * lock is relased and re-acquired while giving back urb. 899 */ 900 void xhci_hc_died(struct xhci_hcd *xhci) 901 { 902 int i, j; 903 904 if (xhci->xhc_state & XHCI_STATE_DYING) 905 return; 906 907 xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); 908 xhci->xhc_state |= XHCI_STATE_DYING; 909 910 xhci_cleanup_command_queue(xhci); 911 912 /* return any pending urbs, remove may be waiting for them */ 913 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { 914 if (!xhci->devs[i]) 915 continue; 916 for (j = 0; j < 31; j++) 917 xhci_kill_endpoint_urbs(xhci, i, j); 918 } 919 920 /* inform usb core hc died if PCI remove isn't already handling it */ 921 if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) 922 usb_hc_died(xhci_to_hcd(xhci)); 923 } 924 925 /* Watchdog timer function for when a stop endpoint command fails to complete. 926 * In this case, we assume the host controller is broken or dying or dead. The 927 * host may still be completing some other events, so we have to be careful to 928 * let the event ring handler and the URB dequeueing/enqueueing functions know 929 * through xhci->state. 930 * 931 * The timer may also fire if the host takes a very long time to respond to the 932 * command, and the stop endpoint command completion handler cannot delete the 933 * timer before the timer function is called. Another endpoint cancellation may 934 * sneak in before the timer function can grab the lock, and that may queue 935 * another stop endpoint command and add the timer back. So we cannot use a 936 * simple flag to say whether there is a pending stop endpoint command for a 937 * particular endpoint. 938 * 939 * Instead we use a combination of that flag and checking if a new timer is 940 * pending. 941 */ 942 void xhci_stop_endpoint_command_watchdog(struct timer_list *t) 943 { 944 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer); 945 struct xhci_hcd *xhci = ep->xhci; 946 unsigned long flags; 947 948 spin_lock_irqsave(&xhci->lock, flags); 949 950 /* bail out if cmd completed but raced with stop ep watchdog timer.*/ 951 if (!(ep->ep_state & EP_STOP_CMD_PENDING) || 952 timer_pending(&ep->stop_cmd_timer)) { 953 spin_unlock_irqrestore(&xhci->lock, flags); 954 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); 955 return; 956 } 957 958 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); 959 ep->ep_state &= ~EP_STOP_CMD_PENDING; 960 961 xhci_halt(xhci); 962 963 /* 964 * handle a stop endpoint cmd timeout as if host died (-ENODEV). 965 * In the future we could distinguish between -ENODEV and -ETIMEDOUT 966 * and try to recover a -ETIMEDOUT with a host controller reset 967 */ 968 xhci_hc_died(xhci); 969 970 spin_unlock_irqrestore(&xhci->lock, flags); 971 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 972 "xHCI host controller is dead."); 973 } 974 975 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, 976 struct xhci_virt_device *dev, 977 struct xhci_ring *ep_ring, 978 unsigned int ep_index) 979 { 980 union xhci_trb *dequeue_temp; 981 int num_trbs_free_temp; 982 bool revert = false; 983 984 num_trbs_free_temp = ep_ring->num_trbs_free; 985 dequeue_temp = ep_ring->dequeue; 986 987 /* If we get two back-to-back stalls, and the first stalled transfer 988 * ends just before a link TRB, the dequeue pointer will be left on 989 * the link TRB by the code in the while loop. So we have to update 990 * the dequeue pointer one segment further, or we'll jump off 991 * the segment into la-la-land. 992 */ 993 if (trb_is_link(ep_ring->dequeue)) { 994 ep_ring->deq_seg = ep_ring->deq_seg->next; 995 ep_ring->dequeue = ep_ring->deq_seg->trbs; 996 } 997 998 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { 999 /* We have more usable TRBs */ 1000 ep_ring->num_trbs_free++; 1001 ep_ring->dequeue++; 1002 if (trb_is_link(ep_ring->dequeue)) { 1003 if (ep_ring->dequeue == 1004 dev->eps[ep_index].queued_deq_ptr) 1005 break; 1006 ep_ring->deq_seg = ep_ring->deq_seg->next; 1007 ep_ring->dequeue = ep_ring->deq_seg->trbs; 1008 } 1009 if (ep_ring->dequeue == dequeue_temp) { 1010 revert = true; 1011 break; 1012 } 1013 } 1014 1015 if (revert) { 1016 xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); 1017 ep_ring->num_trbs_free = num_trbs_free_temp; 1018 } 1019 } 1020 1021 /* 1022 * When we get a completion for a Set Transfer Ring Dequeue Pointer command, 1023 * we need to clear the set deq pending flag in the endpoint ring state, so that 1024 * the TD queueing code can ring the doorbell again. We also need to ring the 1025 * endpoint doorbell to restart the ring, but only if there aren't more 1026 * cancellations pending. 1027 */ 1028 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, 1029 union xhci_trb *trb, u32 cmd_comp_code) 1030 { 1031 unsigned int ep_index; 1032 unsigned int stream_id; 1033 struct xhci_ring *ep_ring; 1034 struct xhci_virt_device *dev; 1035 struct xhci_virt_ep *ep; 1036 struct xhci_ep_ctx *ep_ctx; 1037 struct xhci_slot_ctx *slot_ctx; 1038 1039 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1040 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); 1041 dev = xhci->devs[slot_id]; 1042 ep = &dev->eps[ep_index]; 1043 1044 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); 1045 if (!ep_ring) { 1046 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", 1047 stream_id); 1048 /* XXX: Harmless??? */ 1049 goto cleanup; 1050 } 1051 1052 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); 1053 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); 1054 trace_xhci_handle_cmd_set_deq(slot_ctx); 1055 trace_xhci_handle_cmd_set_deq_ep(ep_ctx); 1056 1057 if (cmd_comp_code != COMP_SUCCESS) { 1058 unsigned int ep_state; 1059 unsigned int slot_state; 1060 1061 switch (cmd_comp_code) { 1062 case COMP_TRB_ERROR: 1063 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); 1064 break; 1065 case COMP_CONTEXT_STATE_ERROR: 1066 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); 1067 ep_state = GET_EP_CTX_STATE(ep_ctx); 1068 slot_state = le32_to_cpu(slot_ctx->dev_state); 1069 slot_state = GET_SLOT_STATE(slot_state); 1070 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1071 "Slot state = %u, EP state = %u", 1072 slot_state, ep_state); 1073 break; 1074 case COMP_SLOT_NOT_ENABLED_ERROR: 1075 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", 1076 slot_id); 1077 break; 1078 default: 1079 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", 1080 cmd_comp_code); 1081 break; 1082 } 1083 /* OK what do we do now? The endpoint state is hosed, and we 1084 * should never get to this point if the synchronization between 1085 * queueing, and endpoint state are correct. This might happen 1086 * if the device gets disconnected after we've finished 1087 * cancelling URBs, which might not be an error... 1088 */ 1089 } else { 1090 u64 deq; 1091 /* 4.6.10 deq ptr is written to the stream ctx for streams */ 1092 if (ep->ep_state & EP_HAS_STREAMS) { 1093 struct xhci_stream_ctx *ctx = 1094 &ep->stream_info->stream_ctx_array[stream_id]; 1095 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; 1096 } else { 1097 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; 1098 } 1099 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 1100 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); 1101 if (xhci_trb_virt_to_dma(ep->queued_deq_seg, 1102 ep->queued_deq_ptr) == deq) { 1103 /* Update the ring's dequeue segment and dequeue pointer 1104 * to reflect the new position. 1105 */ 1106 update_ring_for_set_deq_completion(xhci, dev, 1107 ep_ring, ep_index); 1108 } else { 1109 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); 1110 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", 1111 ep->queued_deq_seg, ep->queued_deq_ptr); 1112 } 1113 } 1114 1115 cleanup: 1116 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; 1117 dev->eps[ep_index].queued_deq_seg = NULL; 1118 dev->eps[ep_index].queued_deq_ptr = NULL; 1119 /* Restart any rings with pending URBs */ 1120 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1121 } 1122 1123 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, 1124 union xhci_trb *trb, u32 cmd_comp_code) 1125 { 1126 struct xhci_virt_device *vdev; 1127 struct xhci_ep_ctx *ep_ctx; 1128 unsigned int ep_index; 1129 1130 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); 1131 vdev = xhci->devs[slot_id]; 1132 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); 1133 trace_xhci_handle_cmd_reset_ep(ep_ctx); 1134 1135 /* This command will only fail if the endpoint wasn't halted, 1136 * but we don't care. 1137 */ 1138 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, 1139 "Ignoring reset ep completion code of %u", cmd_comp_code); 1140 1141 /* HW with the reset endpoint quirk needs to have a configure endpoint 1142 * command complete before the endpoint can be used. Queue that here 1143 * because the HW can't handle two commands being queued in a row. 1144 */ 1145 if (xhci->quirks & XHCI_RESET_EP_QUIRK) { 1146 struct xhci_command *command; 1147 1148 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 1149 if (!command) 1150 return; 1151 1152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1153 "Queueing configure endpoint command"); 1154 xhci_queue_configure_endpoint(xhci, command, 1155 xhci->devs[slot_id]->in_ctx->dma, slot_id, 1156 false); 1157 xhci_ring_cmd_db(xhci); 1158 } else { 1159 /* Clear our internal halted state */ 1160 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; 1161 } 1162 1163 /* if this was a soft reset, then restart */ 1164 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) 1165 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1166 } 1167 1168 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, 1169 struct xhci_command *command, u32 cmd_comp_code) 1170 { 1171 if (cmd_comp_code == COMP_SUCCESS) 1172 command->slot_id = slot_id; 1173 else 1174 command->slot_id = 0; 1175 } 1176 1177 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) 1178 { 1179 struct xhci_virt_device *virt_dev; 1180 struct xhci_slot_ctx *slot_ctx; 1181 1182 virt_dev = xhci->devs[slot_id]; 1183 if (!virt_dev) 1184 return; 1185 1186 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); 1187 trace_xhci_handle_cmd_disable_slot(slot_ctx); 1188 1189 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) 1190 /* Delete default control endpoint resources */ 1191 xhci_free_device_endpoint_resources(xhci, virt_dev, true); 1192 xhci_free_virt_device(xhci, slot_id); 1193 } 1194 1195 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, 1196 struct xhci_event_cmd *event, u32 cmd_comp_code) 1197 { 1198 struct xhci_virt_device *virt_dev; 1199 struct xhci_input_control_ctx *ctrl_ctx; 1200 struct xhci_ep_ctx *ep_ctx; 1201 unsigned int ep_index; 1202 unsigned int ep_state; 1203 u32 add_flags, drop_flags; 1204 1205 /* 1206 * Configure endpoint commands can come from the USB core 1207 * configuration or alt setting changes, or because the HW 1208 * needed an extra configure endpoint command after a reset 1209 * endpoint command or streams were being configured. 1210 * If the command was for a halted endpoint, the xHCI driver 1211 * is not waiting on the configure endpoint command. 1212 */ 1213 virt_dev = xhci->devs[slot_id]; 1214 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 1215 if (!ctrl_ctx) { 1216 xhci_warn(xhci, "Could not get input context, bad type.\n"); 1217 return; 1218 } 1219 1220 add_flags = le32_to_cpu(ctrl_ctx->add_flags); 1221 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); 1222 /* Input ctx add_flags are the endpoint index plus one */ 1223 ep_index = xhci_last_valid_endpoint(add_flags) - 1; 1224 1225 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); 1226 trace_xhci_handle_cmd_config_ep(ep_ctx); 1227 1228 /* A usb_set_interface() call directly after clearing a halted 1229 * condition may race on this quirky hardware. Not worth 1230 * worrying about, since this is prototype hardware. Not sure 1231 * if this will work for streams, but streams support was 1232 * untested on this prototype. 1233 */ 1234 if (xhci->quirks & XHCI_RESET_EP_QUIRK && 1235 ep_index != (unsigned int) -1 && 1236 add_flags - SLOT_FLAG == drop_flags) { 1237 ep_state = virt_dev->eps[ep_index].ep_state; 1238 if (!(ep_state & EP_HALTED)) 1239 return; 1240 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1241 "Completed config ep cmd - " 1242 "last ep index = %d, state = %d", 1243 ep_index, ep_state); 1244 /* Clear internal halted state and restart ring(s) */ 1245 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; 1246 ring_doorbell_for_active_rings(xhci, slot_id, ep_index); 1247 return; 1248 } 1249 return; 1250 } 1251 1252 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) 1253 { 1254 struct xhci_virt_device *vdev; 1255 struct xhci_slot_ctx *slot_ctx; 1256 1257 vdev = xhci->devs[slot_id]; 1258 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1259 trace_xhci_handle_cmd_addr_dev(slot_ctx); 1260 } 1261 1262 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, 1263 struct xhci_event_cmd *event) 1264 { 1265 struct xhci_virt_device *vdev; 1266 struct xhci_slot_ctx *slot_ctx; 1267 1268 vdev = xhci->devs[slot_id]; 1269 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); 1270 trace_xhci_handle_cmd_reset_dev(slot_ctx); 1271 1272 xhci_dbg(xhci, "Completed reset device command.\n"); 1273 if (!xhci->devs[slot_id]) 1274 xhci_warn(xhci, "Reset device command completion " 1275 "for disabled slot %u\n", slot_id); 1276 } 1277 1278 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, 1279 struct xhci_event_cmd *event) 1280 { 1281 if (!(xhci->quirks & XHCI_NEC_HOST)) { 1282 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); 1283 return; 1284 } 1285 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, 1286 "NEC firmware version %2x.%02x", 1287 NEC_FW_MAJOR(le32_to_cpu(event->status)), 1288 NEC_FW_MINOR(le32_to_cpu(event->status))); 1289 } 1290 1291 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) 1292 { 1293 list_del(&cmd->cmd_list); 1294 1295 if (cmd->completion) { 1296 cmd->status = status; 1297 complete(cmd->completion); 1298 } else { 1299 kfree(cmd); 1300 } 1301 } 1302 1303 void xhci_cleanup_command_queue(struct xhci_hcd *xhci) 1304 { 1305 struct xhci_command *cur_cmd, *tmp_cmd; 1306 xhci->current_cmd = NULL; 1307 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) 1308 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); 1309 } 1310 1311 void xhci_handle_command_timeout(struct work_struct *work) 1312 { 1313 struct xhci_hcd *xhci; 1314 unsigned long flags; 1315 u64 hw_ring_state; 1316 1317 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); 1318 1319 spin_lock_irqsave(&xhci->lock, flags); 1320 1321 /* 1322 * If timeout work is pending, or current_cmd is NULL, it means we 1323 * raced with command completion. Command is handled so just return. 1324 */ 1325 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { 1326 spin_unlock_irqrestore(&xhci->lock, flags); 1327 return; 1328 } 1329 /* mark this command to be cancelled */ 1330 xhci->current_cmd->status = COMP_COMMAND_ABORTED; 1331 1332 /* Make sure command ring is running before aborting it */ 1333 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); 1334 if (hw_ring_state == ~(u64)0) { 1335 xhci_hc_died(xhci); 1336 goto time_out_completed; 1337 } 1338 1339 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && 1340 (hw_ring_state & CMD_RING_RUNNING)) { 1341 /* Prevent new doorbell, and start command abort */ 1342 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; 1343 xhci_dbg(xhci, "Command timeout\n"); 1344 xhci_abort_cmd_ring(xhci, flags); 1345 goto time_out_completed; 1346 } 1347 1348 /* host removed. Bail out */ 1349 if (xhci->xhc_state & XHCI_STATE_REMOVING) { 1350 xhci_dbg(xhci, "host removed, ring start fail?\n"); 1351 xhci_cleanup_command_queue(xhci); 1352 1353 goto time_out_completed; 1354 } 1355 1356 /* command timeout on stopped ring, ring can't be aborted */ 1357 xhci_dbg(xhci, "Command timeout on stopped ring\n"); 1358 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); 1359 1360 time_out_completed: 1361 spin_unlock_irqrestore(&xhci->lock, flags); 1362 return; 1363 } 1364 1365 static void handle_cmd_completion(struct xhci_hcd *xhci, 1366 struct xhci_event_cmd *event) 1367 { 1368 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1369 u64 cmd_dma; 1370 dma_addr_t cmd_dequeue_dma; 1371 u32 cmd_comp_code; 1372 union xhci_trb *cmd_trb; 1373 struct xhci_command *cmd; 1374 u32 cmd_type; 1375 1376 cmd_dma = le64_to_cpu(event->cmd_trb); 1377 cmd_trb = xhci->cmd_ring->dequeue; 1378 1379 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); 1380 1381 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, 1382 cmd_trb); 1383 /* 1384 * Check whether the completion event is for our internal kept 1385 * command. 1386 */ 1387 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { 1388 xhci_warn(xhci, 1389 "ERROR mismatched command completion event\n"); 1390 return; 1391 } 1392 1393 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); 1394 1395 cancel_delayed_work(&xhci->cmd_timer); 1396 1397 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); 1398 1399 /* If CMD ring stopped we own the trbs between enqueue and dequeue */ 1400 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { 1401 complete_all(&xhci->cmd_ring_stop_completion); 1402 return; 1403 } 1404 1405 if (cmd->command_trb != xhci->cmd_ring->dequeue) { 1406 xhci_err(xhci, 1407 "Command completion event does not match command\n"); 1408 return; 1409 } 1410 1411 /* 1412 * Host aborted the command ring, check if the current command was 1413 * supposed to be aborted, otherwise continue normally. 1414 * The command ring is stopped now, but the xHC will issue a Command 1415 * Ring Stopped event which will cause us to restart it. 1416 */ 1417 if (cmd_comp_code == COMP_COMMAND_ABORTED) { 1418 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; 1419 if (cmd->status == COMP_COMMAND_ABORTED) { 1420 if (xhci->current_cmd == cmd) 1421 xhci->current_cmd = NULL; 1422 goto event_handled; 1423 } 1424 } 1425 1426 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); 1427 switch (cmd_type) { 1428 case TRB_ENABLE_SLOT: 1429 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); 1430 break; 1431 case TRB_DISABLE_SLOT: 1432 xhci_handle_cmd_disable_slot(xhci, slot_id); 1433 break; 1434 case TRB_CONFIG_EP: 1435 if (!cmd->completion) 1436 xhci_handle_cmd_config_ep(xhci, slot_id, event, 1437 cmd_comp_code); 1438 break; 1439 case TRB_EVAL_CONTEXT: 1440 break; 1441 case TRB_ADDR_DEV: 1442 xhci_handle_cmd_addr_dev(xhci, slot_id); 1443 break; 1444 case TRB_STOP_RING: 1445 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1446 le32_to_cpu(cmd_trb->generic.field[3]))); 1447 if (!cmd->completion) 1448 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); 1449 break; 1450 case TRB_SET_DEQ: 1451 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1452 le32_to_cpu(cmd_trb->generic.field[3]))); 1453 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); 1454 break; 1455 case TRB_CMD_NOOP: 1456 /* Is this an aborted command turned to NO-OP? */ 1457 if (cmd->status == COMP_COMMAND_RING_STOPPED) 1458 cmd_comp_code = COMP_COMMAND_RING_STOPPED; 1459 break; 1460 case TRB_RESET_EP: 1461 WARN_ON(slot_id != TRB_TO_SLOT_ID( 1462 le32_to_cpu(cmd_trb->generic.field[3]))); 1463 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); 1464 break; 1465 case TRB_RESET_DEV: 1466 /* SLOT_ID field in reset device cmd completion event TRB is 0. 1467 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) 1468 */ 1469 slot_id = TRB_TO_SLOT_ID( 1470 le32_to_cpu(cmd_trb->generic.field[3])); 1471 xhci_handle_cmd_reset_dev(xhci, slot_id, event); 1472 break; 1473 case TRB_NEC_GET_FW: 1474 xhci_handle_cmd_nec_get_fw(xhci, event); 1475 break; 1476 default: 1477 /* Skip over unknown commands on the event ring */ 1478 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); 1479 break; 1480 } 1481 1482 /* restart timer if this wasn't the last command */ 1483 if (!list_is_singular(&xhci->cmd_list)) { 1484 xhci->current_cmd = list_first_entry(&cmd->cmd_list, 1485 struct xhci_command, cmd_list); 1486 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 1487 } else if (xhci->current_cmd == cmd) { 1488 xhci->current_cmd = NULL; 1489 } 1490 1491 event_handled: 1492 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); 1493 1494 inc_deq(xhci, xhci->cmd_ring); 1495 } 1496 1497 static void handle_vendor_event(struct xhci_hcd *xhci, 1498 union xhci_trb *event) 1499 { 1500 u32 trb_type; 1501 1502 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); 1503 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); 1504 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) 1505 handle_cmd_completion(xhci, &event->event_cmd); 1506 } 1507 1508 static void handle_device_notification(struct xhci_hcd *xhci, 1509 union xhci_trb *event) 1510 { 1511 u32 slot_id; 1512 struct usb_device *udev; 1513 1514 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); 1515 if (!xhci->devs[slot_id]) { 1516 xhci_warn(xhci, "Device Notification event for " 1517 "unused slot %u\n", slot_id); 1518 return; 1519 } 1520 1521 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", 1522 slot_id); 1523 udev = xhci->devs[slot_id]->udev; 1524 if (udev && udev->parent) 1525 usb_wakeup_notification(udev->parent, udev->portnum); 1526 } 1527 1528 /* 1529 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI 1530 * Controller. 1531 * As per ThunderX2errata-129 USB 2 device may come up as USB 1 1532 * If a connection to a USB 1 device is followed by another connection 1533 * to a USB 2 device. 1534 * 1535 * Reset the PHY after the USB device is disconnected if device speed 1536 * is less than HCD_USB3. 1537 * Retry the reset sequence max of 4 times checking the PLL lock status. 1538 * 1539 */ 1540 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) 1541 { 1542 struct usb_hcd *hcd = xhci_to_hcd(xhci); 1543 u32 pll_lock_check; 1544 u32 retry_count = 4; 1545 1546 do { 1547 /* Assert PHY reset */ 1548 writel(0x6F, hcd->regs + 0x1048); 1549 udelay(10); 1550 /* De-assert the PHY reset */ 1551 writel(0x7F, hcd->regs + 0x1048); 1552 udelay(200); 1553 pll_lock_check = readl(hcd->regs + 0x1070); 1554 } while (!(pll_lock_check & 0x1) && --retry_count); 1555 } 1556 1557 static void handle_port_status(struct xhci_hcd *xhci, 1558 union xhci_trb *event) 1559 { 1560 struct usb_hcd *hcd; 1561 u32 port_id; 1562 u32 portsc, cmd_reg; 1563 int max_ports; 1564 int slot_id; 1565 unsigned int hcd_portnum; 1566 struct xhci_bus_state *bus_state; 1567 bool bogus_port_status = false; 1568 struct xhci_port *port; 1569 1570 /* Port status change events always have a successful completion code */ 1571 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) 1572 xhci_warn(xhci, 1573 "WARN: xHC returned failed port status event\n"); 1574 1575 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); 1576 max_ports = HCS_MAX_PORTS(xhci->hcs_params1); 1577 1578 if ((port_id <= 0) || (port_id > max_ports)) { 1579 xhci_warn(xhci, "Port change event with invalid port ID %d\n", 1580 port_id); 1581 inc_deq(xhci, xhci->event_ring); 1582 return; 1583 } 1584 1585 port = &xhci->hw_ports[port_id - 1]; 1586 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { 1587 xhci_warn(xhci, "Port change event, no port for port ID %u\n", 1588 port_id); 1589 bogus_port_status = true; 1590 goto cleanup; 1591 } 1592 1593 /* We might get interrupts after shared_hcd is removed */ 1594 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { 1595 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); 1596 bogus_port_status = true; 1597 goto cleanup; 1598 } 1599 1600 hcd = port->rhub->hcd; 1601 bus_state = &port->rhub->bus_state; 1602 hcd_portnum = port->hcd_portnum; 1603 portsc = readl(port->addr); 1604 1605 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", 1606 hcd->self.busnum, hcd_portnum + 1, port_id, portsc); 1607 1608 trace_xhci_handle_port_status(hcd_portnum, portsc); 1609 1610 if (hcd->state == HC_STATE_SUSPENDED) { 1611 xhci_dbg(xhci, "resume root hub\n"); 1612 usb_hcd_resume_root_hub(hcd); 1613 } 1614 1615 if (hcd->speed >= HCD_USB3 && 1616 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) { 1617 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); 1618 if (slot_id && xhci->devs[slot_id]) 1619 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR; 1620 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum); 1621 } 1622 1623 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { 1624 xhci_dbg(xhci, "port resume event for port %d\n", port_id); 1625 1626 cmd_reg = readl(&xhci->op_regs->command); 1627 if (!(cmd_reg & CMD_RUN)) { 1628 xhci_warn(xhci, "xHC is not running.\n"); 1629 goto cleanup; 1630 } 1631 1632 if (DEV_SUPERSPEED_ANY(portsc)) { 1633 xhci_dbg(xhci, "remote wake SS port %d\n", port_id); 1634 /* Set a flag to say the port signaled remote wakeup, 1635 * so we can tell the difference between the end of 1636 * device and host initiated resume. 1637 */ 1638 bus_state->port_remote_wakeup |= 1 << hcd_portnum; 1639 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1640 xhci_set_link_state(xhci, port, XDEV_U0); 1641 /* Need to wait until the next link state change 1642 * indicates the device is actually in U0. 1643 */ 1644 bogus_port_status = true; 1645 goto cleanup; 1646 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { 1647 xhci_dbg(xhci, "resume HS port %d\n", port_id); 1648 bus_state->resume_done[hcd_portnum] = jiffies + 1649 msecs_to_jiffies(USB_RESUME_TIMEOUT); 1650 set_bit(hcd_portnum, &bus_state->resuming_ports); 1651 /* Do the rest in GetPortStatus after resume time delay. 1652 * Avoid polling roothub status before that so that a 1653 * usb device auto-resume latency around ~40ms. 1654 */ 1655 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1656 mod_timer(&hcd->rh_timer, 1657 bus_state->resume_done[hcd_portnum]); 1658 usb_hcd_start_port_resume(&hcd->self, hcd_portnum); 1659 bogus_port_status = true; 1660 } 1661 } 1662 1663 if ((portsc & PORT_PLC) && 1664 DEV_SUPERSPEED_ANY(portsc) && 1665 ((portsc & PORT_PLS_MASK) == XDEV_U0 || 1666 (portsc & PORT_PLS_MASK) == XDEV_U1 || 1667 (portsc & PORT_PLS_MASK) == XDEV_U2)) { 1668 xhci_dbg(xhci, "resume SS port %d finished\n", port_id); 1669 /* We've just brought the device into U0/1/2 through either the 1670 * Resume state after a device remote wakeup, or through the 1671 * U3Exit state after a host-initiated resume. If it's a device 1672 * initiated remote wake, don't pass up the link state change, 1673 * so the roothub behavior is consistent with external 1674 * USB 3.0 hub behavior. 1675 */ 1676 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); 1677 if (slot_id && xhci->devs[slot_id]) 1678 xhci_ring_device(xhci, slot_id); 1679 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { 1680 bus_state->port_remote_wakeup &= ~(1 << hcd_portnum); 1681 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1682 usb_wakeup_notification(hcd->self.root_hub, 1683 hcd_portnum + 1); 1684 bogus_port_status = true; 1685 goto cleanup; 1686 } 1687 } 1688 1689 /* 1690 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or 1691 * RExit to a disconnect state). If so, let the the driver know it's 1692 * out of the RExit state. 1693 */ 1694 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 && 1695 test_and_clear_bit(hcd_portnum, 1696 &bus_state->rexit_ports)) { 1697 complete(&bus_state->rexit_done[hcd_portnum]); 1698 bogus_port_status = true; 1699 goto cleanup; 1700 } 1701 1702 if (hcd->speed < HCD_USB3) { 1703 xhci_test_and_clear_bit(xhci, port, PORT_PLC); 1704 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && 1705 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) 1706 xhci_cavium_reset_phy_quirk(xhci); 1707 } 1708 1709 cleanup: 1710 /* Update event ring dequeue pointer before dropping the lock */ 1711 inc_deq(xhci, xhci->event_ring); 1712 1713 /* Don't make the USB core poll the roothub if we got a bad port status 1714 * change event. Besides, at that point we can't tell which roothub 1715 * (USB 2.0 or USB 3.0) to kick. 1716 */ 1717 if (bogus_port_status) 1718 return; 1719 1720 /* 1721 * xHCI port-status-change events occur when the "or" of all the 1722 * status-change bits in the portsc register changes from 0 to 1. 1723 * New status changes won't cause an event if any other change 1724 * bits are still set. When an event occurs, switch over to 1725 * polling to avoid losing status changes. 1726 */ 1727 xhci_dbg(xhci, "%s: starting port polling.\n", __func__); 1728 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 1729 spin_unlock(&xhci->lock); 1730 /* Pass this up to the core */ 1731 usb_hcd_poll_rh_status(hcd); 1732 spin_lock(&xhci->lock); 1733 } 1734 1735 /* 1736 * This TD is defined by the TRBs starting at start_trb in start_seg and ending 1737 * at end_trb, which may be in another segment. If the suspect DMA address is a 1738 * TRB in this TD, this function returns that TRB's segment. Otherwise it 1739 * returns 0. 1740 */ 1741 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 1742 struct xhci_segment *start_seg, 1743 union xhci_trb *start_trb, 1744 union xhci_trb *end_trb, 1745 dma_addr_t suspect_dma, 1746 bool debug) 1747 { 1748 dma_addr_t start_dma; 1749 dma_addr_t end_seg_dma; 1750 dma_addr_t end_trb_dma; 1751 struct xhci_segment *cur_seg; 1752 1753 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); 1754 cur_seg = start_seg; 1755 1756 do { 1757 if (start_dma == 0) 1758 return NULL; 1759 /* We may get an event for a Link TRB in the middle of a TD */ 1760 end_seg_dma = xhci_trb_virt_to_dma(cur_seg, 1761 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); 1762 /* If the end TRB isn't in this segment, this is set to 0 */ 1763 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); 1764 1765 if (debug) 1766 xhci_warn(xhci, 1767 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", 1768 (unsigned long long)suspect_dma, 1769 (unsigned long long)start_dma, 1770 (unsigned long long)end_trb_dma, 1771 (unsigned long long)cur_seg->dma, 1772 (unsigned long long)end_seg_dma); 1773 1774 if (end_trb_dma > 0) { 1775 /* The end TRB is in this segment, so suspect should be here */ 1776 if (start_dma <= end_trb_dma) { 1777 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) 1778 return cur_seg; 1779 } else { 1780 /* Case for one segment with 1781 * a TD wrapped around to the top 1782 */ 1783 if ((suspect_dma >= start_dma && 1784 suspect_dma <= end_seg_dma) || 1785 (suspect_dma >= cur_seg->dma && 1786 suspect_dma <= end_trb_dma)) 1787 return cur_seg; 1788 } 1789 return NULL; 1790 } else { 1791 /* Might still be somewhere in this segment */ 1792 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) 1793 return cur_seg; 1794 } 1795 cur_seg = cur_seg->next; 1796 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); 1797 } while (cur_seg != start_seg); 1798 1799 return NULL; 1800 } 1801 1802 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, 1803 unsigned int slot_id, unsigned int ep_index, 1804 unsigned int stream_id, struct xhci_td *td, 1805 enum xhci_ep_reset_type reset_type) 1806 { 1807 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; 1808 struct xhci_command *command; 1809 1810 /* 1811 * Avoid resetting endpoint if link is inactive. Can cause host hang. 1812 * Device will be reset soon to recover the link so don't do anything 1813 */ 1814 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) 1815 return; 1816 1817 command = xhci_alloc_command(xhci, false, GFP_ATOMIC); 1818 if (!command) 1819 return; 1820 1821 ep->ep_state |= EP_HALTED; 1822 1823 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); 1824 1825 if (reset_type == EP_HARD_RESET) { 1826 ep->ep_state |= EP_HARD_CLEAR_TOGGLE; 1827 xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td); 1828 } 1829 xhci_ring_cmd_db(xhci); 1830 } 1831 1832 /* Check if an error has halted the endpoint ring. The class driver will 1833 * cleanup the halt for a non-default control endpoint if we indicate a stall. 1834 * However, a babble and other errors also halt the endpoint ring, and the class 1835 * driver won't clear the halt in that case, so we need to issue a Set Transfer 1836 * Ring Dequeue Pointer command manually. 1837 */ 1838 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, 1839 struct xhci_ep_ctx *ep_ctx, 1840 unsigned int trb_comp_code) 1841 { 1842 /* TRB completion codes that may require a manual halt cleanup */ 1843 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || 1844 trb_comp_code == COMP_BABBLE_DETECTED_ERROR || 1845 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) 1846 /* The 0.95 spec says a babbling control endpoint 1847 * is not halted. The 0.96 spec says it is. Some HW 1848 * claims to be 0.95 compliant, but it halts the control 1849 * endpoint anyway. Check if a babble halted the 1850 * endpoint. 1851 */ 1852 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) 1853 return 1; 1854 1855 return 0; 1856 } 1857 1858 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) 1859 { 1860 if (trb_comp_code >= 224 && trb_comp_code <= 255) { 1861 /* Vendor defined "informational" completion code, 1862 * treat as not-an-error. 1863 */ 1864 xhci_dbg(xhci, "Vendor defined info completion code %u\n", 1865 trb_comp_code); 1866 xhci_dbg(xhci, "Treating code as success.\n"); 1867 return 1; 1868 } 1869 return 0; 1870 } 1871 1872 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, 1873 struct xhci_ring *ep_ring, int *status) 1874 { 1875 struct urb *urb = NULL; 1876 1877 /* Clean up the endpoint's TD list */ 1878 urb = td->urb; 1879 1880 /* if a bounce buffer was used to align this td then unmap it */ 1881 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); 1882 1883 /* Do one last check of the actual transfer length. 1884 * If the host controller said we transferred more data than the buffer 1885 * length, urb->actual_length will be a very big number (since it's 1886 * unsigned). Play it safe and say we didn't transfer anything. 1887 */ 1888 if (urb->actual_length > urb->transfer_buffer_length) { 1889 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", 1890 urb->transfer_buffer_length, urb->actual_length); 1891 urb->actual_length = 0; 1892 *status = 0; 1893 } 1894 list_del_init(&td->td_list); 1895 /* Was this TD slated to be cancelled but completed anyway? */ 1896 if (!list_empty(&td->cancelled_td_list)) 1897 list_del_init(&td->cancelled_td_list); 1898 1899 inc_td_cnt(urb); 1900 /* Giveback the urb when all the tds are completed */ 1901 if (last_td_in_urb(td)) { 1902 if ((urb->actual_length != urb->transfer_buffer_length && 1903 (urb->transfer_flags & URB_SHORT_NOT_OK)) || 1904 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) 1905 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", 1906 urb, urb->actual_length, 1907 urb->transfer_buffer_length, *status); 1908 1909 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ 1910 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 1911 *status = 0; 1912 xhci_giveback_urb_in_irq(xhci, td, *status); 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, 1919 struct xhci_transfer_event *event, 1920 struct xhci_virt_ep *ep, int *status) 1921 { 1922 struct xhci_virt_device *xdev; 1923 struct xhci_ep_ctx *ep_ctx; 1924 struct xhci_ring *ep_ring; 1925 unsigned int slot_id; 1926 u32 trb_comp_code; 1927 int ep_index; 1928 1929 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1930 xdev = xhci->devs[slot_id]; 1931 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1932 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 1933 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 1934 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 1935 1936 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || 1937 trb_comp_code == COMP_STOPPED || 1938 trb_comp_code == COMP_STOPPED_SHORT_PACKET) { 1939 /* The Endpoint Stop Command completion will take care of any 1940 * stopped TDs. A stopped TD may be restarted, so don't update 1941 * the ring dequeue pointer or take this TD off any lists yet. 1942 */ 1943 return 0; 1944 } 1945 if (trb_comp_code == COMP_STALL_ERROR || 1946 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 1947 trb_comp_code)) { 1948 /* Issue a reset endpoint command to clear the host side 1949 * halt, followed by a set dequeue command to move the 1950 * dequeue pointer past the TD. 1951 * The class driver clears the device side halt later. 1952 */ 1953 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 1954 ep_ring->stream_id, td, EP_HARD_RESET); 1955 } else { 1956 /* Update ring dequeue pointer */ 1957 while (ep_ring->dequeue != td->last_trb) 1958 inc_deq(xhci, ep_ring); 1959 inc_deq(xhci, ep_ring); 1960 } 1961 1962 return xhci_td_cleanup(xhci, td, ep_ring, status); 1963 } 1964 1965 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ 1966 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, 1967 union xhci_trb *stop_trb) 1968 { 1969 u32 sum; 1970 union xhci_trb *trb = ring->dequeue; 1971 struct xhci_segment *seg = ring->deq_seg; 1972 1973 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { 1974 if (!trb_is_noop(trb) && !trb_is_link(trb)) 1975 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); 1976 } 1977 return sum; 1978 } 1979 1980 /* 1981 * Process control tds, update urb status and actual_length. 1982 */ 1983 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, 1984 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 1985 struct xhci_virt_ep *ep, int *status) 1986 { 1987 struct xhci_virt_device *xdev; 1988 unsigned int slot_id; 1989 int ep_index; 1990 struct xhci_ep_ctx *ep_ctx; 1991 u32 trb_comp_code; 1992 u32 remaining, requested; 1993 u32 trb_type; 1994 1995 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); 1996 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 1997 xdev = xhci->devs[slot_id]; 1998 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 1999 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2000 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2001 requested = td->urb->transfer_buffer_length; 2002 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2003 2004 switch (trb_comp_code) { 2005 case COMP_SUCCESS: 2006 if (trb_type != TRB_STATUS) { 2007 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", 2008 (trb_type == TRB_DATA) ? "data" : "setup"); 2009 *status = -ESHUTDOWN; 2010 break; 2011 } 2012 *status = 0; 2013 break; 2014 case COMP_SHORT_PACKET: 2015 *status = 0; 2016 break; 2017 case COMP_STOPPED_SHORT_PACKET: 2018 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2019 td->urb->actual_length = remaining; 2020 else 2021 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); 2022 goto finish_td; 2023 case COMP_STOPPED: 2024 switch (trb_type) { 2025 case TRB_SETUP: 2026 td->urb->actual_length = 0; 2027 goto finish_td; 2028 case TRB_DATA: 2029 case TRB_NORMAL: 2030 td->urb->actual_length = requested - remaining; 2031 goto finish_td; 2032 case TRB_STATUS: 2033 td->urb->actual_length = requested; 2034 goto finish_td; 2035 default: 2036 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", 2037 trb_type); 2038 goto finish_td; 2039 } 2040 case COMP_STOPPED_LENGTH_INVALID: 2041 goto finish_td; 2042 default: 2043 if (!xhci_requires_manual_halt_cleanup(xhci, 2044 ep_ctx, trb_comp_code)) 2045 break; 2046 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", 2047 trb_comp_code, ep_index); 2048 /* else fall through */ 2049 case COMP_STALL_ERROR: 2050 /* Did we transfer part of the data (middle) phase? */ 2051 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) 2052 td->urb->actual_length = requested - remaining; 2053 else if (!td->urb_length_set) 2054 td->urb->actual_length = 0; 2055 goto finish_td; 2056 } 2057 2058 /* stopped at setup stage, no data transferred */ 2059 if (trb_type == TRB_SETUP) 2060 goto finish_td; 2061 2062 /* 2063 * if on data stage then update the actual_length of the URB and flag it 2064 * as set, so it won't be overwritten in the event for the last TRB. 2065 */ 2066 if (trb_type == TRB_DATA || 2067 trb_type == TRB_NORMAL) { 2068 td->urb_length_set = true; 2069 td->urb->actual_length = requested - remaining; 2070 xhci_dbg(xhci, "Waiting for status stage event\n"); 2071 return 0; 2072 } 2073 2074 /* at status stage */ 2075 if (!td->urb_length_set) 2076 td->urb->actual_length = requested; 2077 2078 finish_td: 2079 return finish_td(xhci, td, event, ep, status); 2080 } 2081 2082 /* 2083 * Process isochronous tds, update urb packet status and actual_length. 2084 */ 2085 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2086 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 2087 struct xhci_virt_ep *ep, int *status) 2088 { 2089 struct xhci_ring *ep_ring; 2090 struct urb_priv *urb_priv; 2091 int idx; 2092 struct usb_iso_packet_descriptor *frame; 2093 u32 trb_comp_code; 2094 bool sum_trbs_for_length = false; 2095 u32 remaining, requested, ep_trb_len; 2096 int short_framestatus; 2097 2098 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2099 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2100 urb_priv = td->urb->hcpriv; 2101 idx = urb_priv->num_tds_done; 2102 frame = &td->urb->iso_frame_desc[idx]; 2103 requested = frame->length; 2104 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2105 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2106 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? 2107 -EREMOTEIO : 0; 2108 2109 /* handle completion code */ 2110 switch (trb_comp_code) { 2111 case COMP_SUCCESS: 2112 if (remaining) { 2113 frame->status = short_framestatus; 2114 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2115 sum_trbs_for_length = true; 2116 break; 2117 } 2118 frame->status = 0; 2119 break; 2120 case COMP_SHORT_PACKET: 2121 frame->status = short_framestatus; 2122 sum_trbs_for_length = true; 2123 break; 2124 case COMP_BANDWIDTH_OVERRUN_ERROR: 2125 frame->status = -ECOMM; 2126 break; 2127 case COMP_ISOCH_BUFFER_OVERRUN: 2128 case COMP_BABBLE_DETECTED_ERROR: 2129 frame->status = -EOVERFLOW; 2130 break; 2131 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2132 case COMP_STALL_ERROR: 2133 frame->status = -EPROTO; 2134 break; 2135 case COMP_USB_TRANSACTION_ERROR: 2136 frame->status = -EPROTO; 2137 if (ep_trb != td->last_trb) 2138 return 0; 2139 break; 2140 case COMP_STOPPED: 2141 sum_trbs_for_length = true; 2142 break; 2143 case COMP_STOPPED_SHORT_PACKET: 2144 /* field normally containing residue now contains tranferred */ 2145 frame->status = short_framestatus; 2146 requested = remaining; 2147 break; 2148 case COMP_STOPPED_LENGTH_INVALID: 2149 requested = 0; 2150 remaining = 0; 2151 break; 2152 default: 2153 sum_trbs_for_length = true; 2154 frame->status = -1; 2155 break; 2156 } 2157 2158 if (sum_trbs_for_length) 2159 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + 2160 ep_trb_len - remaining; 2161 else 2162 frame->actual_length = requested; 2163 2164 td->urb->actual_length += frame->actual_length; 2165 2166 return finish_td(xhci, td, event, ep, status); 2167 } 2168 2169 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, 2170 struct xhci_transfer_event *event, 2171 struct xhci_virt_ep *ep, int *status) 2172 { 2173 struct xhci_ring *ep_ring; 2174 struct urb_priv *urb_priv; 2175 struct usb_iso_packet_descriptor *frame; 2176 int idx; 2177 2178 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2179 urb_priv = td->urb->hcpriv; 2180 idx = urb_priv->num_tds_done; 2181 frame = &td->urb->iso_frame_desc[idx]; 2182 2183 /* The transfer is partly done. */ 2184 frame->status = -EXDEV; 2185 2186 /* calc actual length */ 2187 frame->actual_length = 0; 2188 2189 /* Update ring dequeue pointer */ 2190 while (ep_ring->dequeue != td->last_trb) 2191 inc_deq(xhci, ep_ring); 2192 inc_deq(xhci, ep_ring); 2193 2194 return xhci_td_cleanup(xhci, td, ep_ring, status); 2195 } 2196 2197 /* 2198 * Process bulk and interrupt tds, update urb status and actual_length. 2199 */ 2200 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, 2201 union xhci_trb *ep_trb, struct xhci_transfer_event *event, 2202 struct xhci_virt_ep *ep, int *status) 2203 { 2204 struct xhci_slot_ctx *slot_ctx; 2205 struct xhci_ring *ep_ring; 2206 u32 trb_comp_code; 2207 u32 remaining, requested, ep_trb_len; 2208 unsigned int slot_id; 2209 int ep_index; 2210 2211 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2212 slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx); 2213 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2214 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); 2215 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2216 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); 2217 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); 2218 requested = td->urb->transfer_buffer_length; 2219 2220 switch (trb_comp_code) { 2221 case COMP_SUCCESS: 2222 ep_ring->err_count = 0; 2223 /* handle success with untransferred data as short packet */ 2224 if (ep_trb != td->last_trb || remaining) { 2225 xhci_warn(xhci, "WARN Successful completion on short TX\n"); 2226 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2227 td->urb->ep->desc.bEndpointAddress, 2228 requested, remaining); 2229 } 2230 *status = 0; 2231 break; 2232 case COMP_SHORT_PACKET: 2233 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", 2234 td->urb->ep->desc.bEndpointAddress, 2235 requested, remaining); 2236 *status = 0; 2237 break; 2238 case COMP_STOPPED_SHORT_PACKET: 2239 td->urb->actual_length = remaining; 2240 goto finish_td; 2241 case COMP_STOPPED_LENGTH_INVALID: 2242 /* stopped on ep trb with invalid length, exclude it */ 2243 ep_trb_len = 0; 2244 remaining = 0; 2245 break; 2246 case COMP_USB_TRANSACTION_ERROR: 2247 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) || 2248 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) 2249 break; 2250 *status = 0; 2251 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 2252 ep_ring->stream_id, td, EP_SOFT_RESET); 2253 return 0; 2254 default: 2255 /* do nothing */ 2256 break; 2257 } 2258 2259 if (ep_trb == td->last_trb) 2260 td->urb->actual_length = requested - remaining; 2261 else 2262 td->urb->actual_length = 2263 sum_trb_lengths(xhci, ep_ring, ep_trb) + 2264 ep_trb_len - remaining; 2265 finish_td: 2266 if (remaining > requested) { 2267 xhci_warn(xhci, "bad transfer trb length %d in event trb\n", 2268 remaining); 2269 td->urb->actual_length = 0; 2270 } 2271 return finish_td(xhci, td, event, ep, status); 2272 } 2273 2274 /* 2275 * If this function returns an error condition, it means it got a Transfer 2276 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. 2277 * At this point, the host controller is probably hosed and should be reset. 2278 */ 2279 static int handle_tx_event(struct xhci_hcd *xhci, 2280 struct xhci_transfer_event *event) 2281 { 2282 struct xhci_virt_device *xdev; 2283 struct xhci_virt_ep *ep; 2284 struct xhci_ring *ep_ring; 2285 unsigned int slot_id; 2286 int ep_index; 2287 struct xhci_td *td = NULL; 2288 dma_addr_t ep_trb_dma; 2289 struct xhci_segment *ep_seg; 2290 union xhci_trb *ep_trb; 2291 int status = -EINPROGRESS; 2292 struct xhci_ep_ctx *ep_ctx; 2293 struct list_head *tmp; 2294 u32 trb_comp_code; 2295 int td_num = 0; 2296 bool handling_skipped_tds = false; 2297 2298 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); 2299 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; 2300 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); 2301 ep_trb_dma = le64_to_cpu(event->buffer); 2302 2303 xdev = xhci->devs[slot_id]; 2304 if (!xdev) { 2305 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", 2306 slot_id); 2307 goto err_out; 2308 } 2309 2310 ep = &xdev->eps[ep_index]; 2311 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); 2312 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2313 2314 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { 2315 xhci_err(xhci, 2316 "ERROR Transfer event for disabled endpoint slot %u ep %u\n", 2317 slot_id, ep_index); 2318 goto err_out; 2319 } 2320 2321 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ 2322 if (!ep_ring) { 2323 switch (trb_comp_code) { 2324 case COMP_STALL_ERROR: 2325 case COMP_USB_TRANSACTION_ERROR: 2326 case COMP_INVALID_STREAM_TYPE_ERROR: 2327 case COMP_INVALID_STREAM_ID_ERROR: 2328 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0, 2329 NULL, EP_SOFT_RESET); 2330 goto cleanup; 2331 case COMP_RING_UNDERRUN: 2332 case COMP_RING_OVERRUN: 2333 case COMP_STOPPED_LENGTH_INVALID: 2334 goto cleanup; 2335 default: 2336 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", 2337 slot_id, ep_index); 2338 goto err_out; 2339 } 2340 } 2341 2342 /* Count current td numbers if ep->skip is set */ 2343 if (ep->skip) { 2344 list_for_each(tmp, &ep_ring->td_list) 2345 td_num++; 2346 } 2347 2348 /* Look for common error cases */ 2349 switch (trb_comp_code) { 2350 /* Skip codes that require special handling depending on 2351 * transfer type 2352 */ 2353 case COMP_SUCCESS: 2354 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) 2355 break; 2356 if (xhci->quirks & XHCI_TRUST_TX_LENGTH) 2357 trb_comp_code = COMP_SHORT_PACKET; 2358 else 2359 xhci_warn_ratelimited(xhci, 2360 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", 2361 slot_id, ep_index); 2362 case COMP_SHORT_PACKET: 2363 break; 2364 /* Completion codes for endpoint stopped state */ 2365 case COMP_STOPPED: 2366 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", 2367 slot_id, ep_index); 2368 break; 2369 case COMP_STOPPED_LENGTH_INVALID: 2370 xhci_dbg(xhci, 2371 "Stopped on No-op or Link TRB for slot %u ep %u\n", 2372 slot_id, ep_index); 2373 break; 2374 case COMP_STOPPED_SHORT_PACKET: 2375 xhci_dbg(xhci, 2376 "Stopped with short packet transfer detected for slot %u ep %u\n", 2377 slot_id, ep_index); 2378 break; 2379 /* Completion codes for endpoint halted state */ 2380 case COMP_STALL_ERROR: 2381 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, 2382 ep_index); 2383 ep->ep_state |= EP_HALTED; 2384 status = -EPIPE; 2385 break; 2386 case COMP_SPLIT_TRANSACTION_ERROR: 2387 case COMP_USB_TRANSACTION_ERROR: 2388 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", 2389 slot_id, ep_index); 2390 status = -EPROTO; 2391 break; 2392 case COMP_BABBLE_DETECTED_ERROR: 2393 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", 2394 slot_id, ep_index); 2395 status = -EOVERFLOW; 2396 break; 2397 /* Completion codes for endpoint error state */ 2398 case COMP_TRB_ERROR: 2399 xhci_warn(xhci, 2400 "WARN: TRB error for slot %u ep %u on endpoint\n", 2401 slot_id, ep_index); 2402 status = -EILSEQ; 2403 break; 2404 /* completion codes not indicating endpoint state change */ 2405 case COMP_DATA_BUFFER_ERROR: 2406 xhci_warn(xhci, 2407 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", 2408 slot_id, ep_index); 2409 status = -ENOSR; 2410 break; 2411 case COMP_BANDWIDTH_OVERRUN_ERROR: 2412 xhci_warn(xhci, 2413 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", 2414 slot_id, ep_index); 2415 break; 2416 case COMP_ISOCH_BUFFER_OVERRUN: 2417 xhci_warn(xhci, 2418 "WARN: buffer overrun event for slot %u ep %u on endpoint", 2419 slot_id, ep_index); 2420 break; 2421 case COMP_RING_UNDERRUN: 2422 /* 2423 * When the Isoch ring is empty, the xHC will generate 2424 * a Ring Overrun Event for IN Isoch endpoint or Ring 2425 * Underrun Event for OUT Isoch endpoint. 2426 */ 2427 xhci_dbg(xhci, "underrun event on endpoint\n"); 2428 if (!list_empty(&ep_ring->td_list)) 2429 xhci_dbg(xhci, "Underrun Event for slot %d ep %d " 2430 "still with TDs queued?\n", 2431 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2432 ep_index); 2433 goto cleanup; 2434 case COMP_RING_OVERRUN: 2435 xhci_dbg(xhci, "overrun event on endpoint\n"); 2436 if (!list_empty(&ep_ring->td_list)) 2437 xhci_dbg(xhci, "Overrun Event for slot %d ep %d " 2438 "still with TDs queued?\n", 2439 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2440 ep_index); 2441 goto cleanup; 2442 case COMP_MISSED_SERVICE_ERROR: 2443 /* 2444 * When encounter missed service error, one or more isoc tds 2445 * may be missed by xHC. 2446 * Set skip flag of the ep_ring; Complete the missed tds as 2447 * short transfer when process the ep_ring next time. 2448 */ 2449 ep->skip = true; 2450 xhci_dbg(xhci, 2451 "Miss service interval error for slot %u ep %u, set skip flag\n", 2452 slot_id, ep_index); 2453 goto cleanup; 2454 case COMP_NO_PING_RESPONSE_ERROR: 2455 ep->skip = true; 2456 xhci_dbg(xhci, 2457 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", 2458 slot_id, ep_index); 2459 goto cleanup; 2460 2461 case COMP_INCOMPATIBLE_DEVICE_ERROR: 2462 /* needs disable slot command to recover */ 2463 xhci_warn(xhci, 2464 "WARN: detect an incompatible device for slot %u ep %u", 2465 slot_id, ep_index); 2466 status = -EPROTO; 2467 break; 2468 default: 2469 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { 2470 status = 0; 2471 break; 2472 } 2473 xhci_warn(xhci, 2474 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", 2475 trb_comp_code, slot_id, ep_index); 2476 goto cleanup; 2477 } 2478 2479 do { 2480 /* This TRB should be in the TD at the head of this ring's 2481 * TD list. 2482 */ 2483 if (list_empty(&ep_ring->td_list)) { 2484 /* 2485 * Don't print wanings if it's due to a stopped endpoint 2486 * generating an extra completion event if the device 2487 * was suspended. Or, a event for the last TRB of a 2488 * short TD we already got a short event for. 2489 * The short TD is already removed from the TD list. 2490 */ 2491 2492 if (!(trb_comp_code == COMP_STOPPED || 2493 trb_comp_code == COMP_STOPPED_LENGTH_INVALID || 2494 ep_ring->last_td_was_short)) { 2495 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", 2496 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), 2497 ep_index); 2498 } 2499 if (ep->skip) { 2500 ep->skip = false; 2501 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", 2502 slot_id, ep_index); 2503 } 2504 goto cleanup; 2505 } 2506 2507 /* We've skipped all the TDs on the ep ring when ep->skip set */ 2508 if (ep->skip && td_num == 0) { 2509 ep->skip = false; 2510 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", 2511 slot_id, ep_index); 2512 goto cleanup; 2513 } 2514 2515 td = list_first_entry(&ep_ring->td_list, struct xhci_td, 2516 td_list); 2517 if (ep->skip) 2518 td_num--; 2519 2520 /* Is this a TRB in the currently executing TD? */ 2521 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, 2522 td->last_trb, ep_trb_dma, false); 2523 2524 /* 2525 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE 2526 * is not in the current TD pointed by ep_ring->dequeue because 2527 * that the hardware dequeue pointer still at the previous TRB 2528 * of the current TD. The previous TRB maybe a Link TD or the 2529 * last TRB of the previous TD. The command completion handle 2530 * will take care the rest. 2531 */ 2532 if (!ep_seg && (trb_comp_code == COMP_STOPPED || 2533 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { 2534 goto cleanup; 2535 } 2536 2537 if (!ep_seg) { 2538 if (!ep->skip || 2539 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { 2540 /* Some host controllers give a spurious 2541 * successful event after a short transfer. 2542 * Ignore it. 2543 */ 2544 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 2545 ep_ring->last_td_was_short) { 2546 ep_ring->last_td_was_short = false; 2547 goto cleanup; 2548 } 2549 /* HC is busted, give up! */ 2550 xhci_err(xhci, 2551 "ERROR Transfer event TRB DMA ptr not " 2552 "part of current TD ep_index %d " 2553 "comp_code %u\n", ep_index, 2554 trb_comp_code); 2555 trb_in_td(xhci, ep_ring->deq_seg, 2556 ep_ring->dequeue, td->last_trb, 2557 ep_trb_dma, true); 2558 return -ESHUTDOWN; 2559 } 2560 2561 skip_isoc_td(xhci, td, event, ep, &status); 2562 goto cleanup; 2563 } 2564 if (trb_comp_code == COMP_SHORT_PACKET) 2565 ep_ring->last_td_was_short = true; 2566 else 2567 ep_ring->last_td_was_short = false; 2568 2569 if (ep->skip) { 2570 xhci_dbg(xhci, 2571 "Found td. Clear skip flag for slot %u ep %u.\n", 2572 slot_id, ep_index); 2573 ep->skip = false; 2574 } 2575 2576 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / 2577 sizeof(*ep_trb)]; 2578 2579 trace_xhci_handle_transfer(ep_ring, 2580 (struct xhci_generic_trb *) ep_trb); 2581 2582 /* 2583 * No-op TRB could trigger interrupts in a case where 2584 * a URB was killed and a STALL_ERROR happens right 2585 * after the endpoint ring stopped. Reset the halted 2586 * endpoint. Otherwise, the endpoint remains stalled 2587 * indefinitely. 2588 */ 2589 if (trb_is_noop(ep_trb)) { 2590 if (trb_comp_code == COMP_STALL_ERROR || 2591 xhci_requires_manual_halt_cleanup(xhci, ep_ctx, 2592 trb_comp_code)) 2593 xhci_cleanup_halted_endpoint(xhci, slot_id, 2594 ep_index, 2595 ep_ring->stream_id, 2596 td, EP_HARD_RESET); 2597 goto cleanup; 2598 } 2599 2600 /* update the urb's actual_length and give back to the core */ 2601 if (usb_endpoint_xfer_control(&td->urb->ep->desc)) 2602 process_ctrl_td(xhci, td, ep_trb, event, ep, &status); 2603 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) 2604 process_isoc_td(xhci, td, ep_trb, event, ep, &status); 2605 else 2606 process_bulk_intr_td(xhci, td, ep_trb, event, ep, 2607 &status); 2608 cleanup: 2609 handling_skipped_tds = ep->skip && 2610 trb_comp_code != COMP_MISSED_SERVICE_ERROR && 2611 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; 2612 2613 /* 2614 * Do not update event ring dequeue pointer if we're in a loop 2615 * processing missed tds. 2616 */ 2617 if (!handling_skipped_tds) 2618 inc_deq(xhci, xhci->event_ring); 2619 2620 /* 2621 * If ep->skip is set, it means there are missed tds on the 2622 * endpoint ring need to take care of. 2623 * Process them as short transfer until reach the td pointed by 2624 * the event. 2625 */ 2626 } while (handling_skipped_tds); 2627 2628 return 0; 2629 2630 err_out: 2631 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", 2632 (unsigned long long) xhci_trb_virt_to_dma( 2633 xhci->event_ring->deq_seg, 2634 xhci->event_ring->dequeue), 2635 lower_32_bits(le64_to_cpu(event->buffer)), 2636 upper_32_bits(le64_to_cpu(event->buffer)), 2637 le32_to_cpu(event->transfer_len), 2638 le32_to_cpu(event->flags)); 2639 return -ENODEV; 2640 } 2641 2642 /* 2643 * This function handles all OS-owned events on the event ring. It may drop 2644 * xhci->lock between event processing (e.g. to pass up port status changes). 2645 * Returns >0 for "possibly more events to process" (caller should call again), 2646 * otherwise 0 if done. In future, <0 returns should indicate error code. 2647 */ 2648 static int xhci_handle_event(struct xhci_hcd *xhci) 2649 { 2650 union xhci_trb *event; 2651 int update_ptrs = 1; 2652 int ret; 2653 2654 /* Event ring hasn't been allocated yet. */ 2655 if (!xhci->event_ring || !xhci->event_ring->dequeue) { 2656 xhci_err(xhci, "ERROR event ring not ready\n"); 2657 return -ENOMEM; 2658 } 2659 2660 event = xhci->event_ring->dequeue; 2661 /* Does the HC or OS own the TRB? */ 2662 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != 2663 xhci->event_ring->cycle_state) 2664 return 0; 2665 2666 trace_xhci_handle_event(xhci->event_ring, &event->generic); 2667 2668 /* 2669 * Barrier between reading the TRB_CYCLE (valid) flag above and any 2670 * speculative reads of the event's flags/data below. 2671 */ 2672 rmb(); 2673 /* FIXME: Handle more event types. */ 2674 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { 2675 case TRB_TYPE(TRB_COMPLETION): 2676 handle_cmd_completion(xhci, &event->event_cmd); 2677 break; 2678 case TRB_TYPE(TRB_PORT_STATUS): 2679 handle_port_status(xhci, event); 2680 update_ptrs = 0; 2681 break; 2682 case TRB_TYPE(TRB_TRANSFER): 2683 ret = handle_tx_event(xhci, &event->trans_event); 2684 if (ret >= 0) 2685 update_ptrs = 0; 2686 break; 2687 case TRB_TYPE(TRB_DEV_NOTE): 2688 handle_device_notification(xhci, event); 2689 break; 2690 default: 2691 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= 2692 TRB_TYPE(48)) 2693 handle_vendor_event(xhci, event); 2694 else 2695 xhci_warn(xhci, "ERROR unknown event type %d\n", 2696 TRB_FIELD_TO_TYPE( 2697 le32_to_cpu(event->event_cmd.flags))); 2698 } 2699 /* Any of the above functions may drop and re-acquire the lock, so check 2700 * to make sure a watchdog timer didn't mark the host as non-responsive. 2701 */ 2702 if (xhci->xhc_state & XHCI_STATE_DYING) { 2703 xhci_dbg(xhci, "xHCI host dying, returning from " 2704 "event handler.\n"); 2705 return 0; 2706 } 2707 2708 if (update_ptrs) 2709 /* Update SW event ring dequeue pointer */ 2710 inc_deq(xhci, xhci->event_ring); 2711 2712 /* Are there more items on the event ring? Caller will call us again to 2713 * check. 2714 */ 2715 return 1; 2716 } 2717 2718 /* 2719 * xHCI spec says we can get an interrupt, and if the HC has an error condition, 2720 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of 2721 * indicators of an event TRB error, but we check the status *first* to be safe. 2722 */ 2723 irqreturn_t xhci_irq(struct usb_hcd *hcd) 2724 { 2725 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 2726 union xhci_trb *event_ring_deq; 2727 irqreturn_t ret = IRQ_NONE; 2728 unsigned long flags; 2729 dma_addr_t deq; 2730 u64 temp_64; 2731 u32 status; 2732 2733 spin_lock_irqsave(&xhci->lock, flags); 2734 /* Check if the xHC generated the interrupt, or the irq is shared */ 2735 status = readl(&xhci->op_regs->status); 2736 if (status == ~(u32)0) { 2737 xhci_hc_died(xhci); 2738 ret = IRQ_HANDLED; 2739 goto out; 2740 } 2741 2742 if (!(status & STS_EINT)) 2743 goto out; 2744 2745 if (status & STS_FATAL) { 2746 xhci_warn(xhci, "WARNING: Host System Error\n"); 2747 xhci_halt(xhci); 2748 ret = IRQ_HANDLED; 2749 goto out; 2750 } 2751 2752 /* 2753 * Clear the op reg interrupt status first, 2754 * so we can receive interrupts from other MSI-X interrupters. 2755 * Write 1 to clear the interrupt status. 2756 */ 2757 status |= STS_EINT; 2758 writel(status, &xhci->op_regs->status); 2759 2760 if (!hcd->msi_enabled) { 2761 u32 irq_pending; 2762 irq_pending = readl(&xhci->ir_set->irq_pending); 2763 irq_pending |= IMAN_IP; 2764 writel(irq_pending, &xhci->ir_set->irq_pending); 2765 } 2766 2767 if (xhci->xhc_state & XHCI_STATE_DYING || 2768 xhci->xhc_state & XHCI_STATE_HALTED) { 2769 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " 2770 "Shouldn't IRQs be disabled?\n"); 2771 /* Clear the event handler busy flag (RW1C); 2772 * the event ring should be empty. 2773 */ 2774 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2775 xhci_write_64(xhci, temp_64 | ERST_EHB, 2776 &xhci->ir_set->erst_dequeue); 2777 ret = IRQ_HANDLED; 2778 goto out; 2779 } 2780 2781 event_ring_deq = xhci->event_ring->dequeue; 2782 /* FIXME this should be a delayed service routine 2783 * that clears the EHB. 2784 */ 2785 while (xhci_handle_event(xhci) > 0) {} 2786 2787 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); 2788 /* If necessary, update the HW's version of the event ring deq ptr. */ 2789 if (event_ring_deq != xhci->event_ring->dequeue) { 2790 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, 2791 xhci->event_ring->dequeue); 2792 if (deq == 0) 2793 xhci_warn(xhci, "WARN something wrong with SW event " 2794 "ring dequeue ptr.\n"); 2795 /* Update HC event ring dequeue pointer */ 2796 temp_64 &= ERST_PTR_MASK; 2797 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); 2798 } 2799 2800 /* Clear the event handler busy flag (RW1C); event ring is empty. */ 2801 temp_64 |= ERST_EHB; 2802 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); 2803 ret = IRQ_HANDLED; 2804 2805 out: 2806 spin_unlock_irqrestore(&xhci->lock, flags); 2807 2808 return ret; 2809 } 2810 2811 irqreturn_t xhci_msi_irq(int irq, void *hcd) 2812 { 2813 return xhci_irq(hcd); 2814 } 2815 2816 /**** Endpoint Ring Operations ****/ 2817 2818 /* 2819 * Generic function for queueing a TRB on a ring. 2820 * The caller must have checked to make sure there's room on the ring. 2821 * 2822 * @more_trbs_coming: Will you enqueue more TRBs before calling 2823 * prepare_transfer()? 2824 */ 2825 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, 2826 bool more_trbs_coming, 2827 u32 field1, u32 field2, u32 field3, u32 field4) 2828 { 2829 struct xhci_generic_trb *trb; 2830 2831 trb = &ring->enqueue->generic; 2832 trb->field[0] = cpu_to_le32(field1); 2833 trb->field[1] = cpu_to_le32(field2); 2834 trb->field[2] = cpu_to_le32(field3); 2835 trb->field[3] = cpu_to_le32(field4); 2836 2837 trace_xhci_queue_trb(ring, trb); 2838 2839 inc_enq(xhci, ring, more_trbs_coming); 2840 } 2841 2842 /* 2843 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. 2844 * FIXME allocate segments if the ring is full. 2845 */ 2846 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, 2847 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) 2848 { 2849 unsigned int num_trbs_needed; 2850 2851 /* Make sure the endpoint has been added to xHC schedule */ 2852 switch (ep_state) { 2853 case EP_STATE_DISABLED: 2854 /* 2855 * USB core changed config/interfaces without notifying us, 2856 * or hardware is reporting the wrong state. 2857 */ 2858 xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); 2859 return -ENOENT; 2860 case EP_STATE_ERROR: 2861 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); 2862 /* FIXME event handling code for error needs to clear it */ 2863 /* XXX not sure if this should be -ENOENT or not */ 2864 return -EINVAL; 2865 case EP_STATE_HALTED: 2866 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); 2867 case EP_STATE_STOPPED: 2868 case EP_STATE_RUNNING: 2869 break; 2870 default: 2871 xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); 2872 /* 2873 * FIXME issue Configure Endpoint command to try to get the HC 2874 * back into a known state. 2875 */ 2876 return -EINVAL; 2877 } 2878 2879 while (1) { 2880 if (room_on_ring(xhci, ep_ring, num_trbs)) 2881 break; 2882 2883 if (ep_ring == xhci->cmd_ring) { 2884 xhci_err(xhci, "Do not support expand command ring\n"); 2885 return -ENOMEM; 2886 } 2887 2888 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, 2889 "ERROR no room on ep ring, try ring expansion"); 2890 num_trbs_needed = num_trbs - ep_ring->num_trbs_free; 2891 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, 2892 mem_flags)) { 2893 xhci_err(xhci, "Ring expansion failed\n"); 2894 return -ENOMEM; 2895 } 2896 } 2897 2898 while (trb_is_link(ep_ring->enqueue)) { 2899 /* If we're not dealing with 0.95 hardware or isoc rings 2900 * on AMD 0.96 host, clear the chain bit. 2901 */ 2902 if (!xhci_link_trb_quirk(xhci) && 2903 !(ep_ring->type == TYPE_ISOC && 2904 (xhci->quirks & XHCI_AMD_0x96_HOST))) 2905 ep_ring->enqueue->link.control &= 2906 cpu_to_le32(~TRB_CHAIN); 2907 else 2908 ep_ring->enqueue->link.control |= 2909 cpu_to_le32(TRB_CHAIN); 2910 2911 wmb(); 2912 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); 2913 2914 /* Toggle the cycle bit after the last ring segment. */ 2915 if (link_trb_toggles_cycle(ep_ring->enqueue)) 2916 ep_ring->cycle_state ^= 1; 2917 2918 ep_ring->enq_seg = ep_ring->enq_seg->next; 2919 ep_ring->enqueue = ep_ring->enq_seg->trbs; 2920 } 2921 return 0; 2922 } 2923 2924 static int prepare_transfer(struct xhci_hcd *xhci, 2925 struct xhci_virt_device *xdev, 2926 unsigned int ep_index, 2927 unsigned int stream_id, 2928 unsigned int num_trbs, 2929 struct urb *urb, 2930 unsigned int td_index, 2931 gfp_t mem_flags) 2932 { 2933 int ret; 2934 struct urb_priv *urb_priv; 2935 struct xhci_td *td; 2936 struct xhci_ring *ep_ring; 2937 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 2938 2939 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); 2940 if (!ep_ring) { 2941 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", 2942 stream_id); 2943 return -EINVAL; 2944 } 2945 2946 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 2947 num_trbs, mem_flags); 2948 if (ret) 2949 return ret; 2950 2951 urb_priv = urb->hcpriv; 2952 td = &urb_priv->td[td_index]; 2953 2954 INIT_LIST_HEAD(&td->td_list); 2955 INIT_LIST_HEAD(&td->cancelled_td_list); 2956 2957 if (td_index == 0) { 2958 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); 2959 if (unlikely(ret)) 2960 return ret; 2961 } 2962 2963 td->urb = urb; 2964 /* Add this TD to the tail of the endpoint ring's TD list */ 2965 list_add_tail(&td->td_list, &ep_ring->td_list); 2966 td->start_seg = ep_ring->enq_seg; 2967 td->first_trb = ep_ring->enqueue; 2968 2969 return 0; 2970 } 2971 2972 unsigned int count_trbs(u64 addr, u64 len) 2973 { 2974 unsigned int num_trbs; 2975 2976 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), 2977 TRB_MAX_BUFF_SIZE); 2978 if (num_trbs == 0) 2979 num_trbs++; 2980 2981 return num_trbs; 2982 } 2983 2984 static inline unsigned int count_trbs_needed(struct urb *urb) 2985 { 2986 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); 2987 } 2988 2989 static unsigned int count_sg_trbs_needed(struct urb *urb) 2990 { 2991 struct scatterlist *sg; 2992 unsigned int i, len, full_len, num_trbs = 0; 2993 2994 full_len = urb->transfer_buffer_length; 2995 2996 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { 2997 len = sg_dma_len(sg); 2998 num_trbs += count_trbs(sg_dma_address(sg), len); 2999 len = min_t(unsigned int, len, full_len); 3000 full_len -= len; 3001 if (full_len == 0) 3002 break; 3003 } 3004 3005 return num_trbs; 3006 } 3007 3008 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) 3009 { 3010 u64 addr, len; 3011 3012 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); 3013 len = urb->iso_frame_desc[i].length; 3014 3015 return count_trbs(addr, len); 3016 } 3017 3018 static void check_trb_math(struct urb *urb, int running_total) 3019 { 3020 if (unlikely(running_total != urb->transfer_buffer_length)) 3021 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " 3022 "queued %#x (%d), asked for %#x (%d)\n", 3023 __func__, 3024 urb->ep->desc.bEndpointAddress, 3025 running_total, running_total, 3026 urb->transfer_buffer_length, 3027 urb->transfer_buffer_length); 3028 } 3029 3030 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, 3031 unsigned int ep_index, unsigned int stream_id, int start_cycle, 3032 struct xhci_generic_trb *start_trb) 3033 { 3034 /* 3035 * Pass all the TRBs to the hardware at once and make sure this write 3036 * isn't reordered. 3037 */ 3038 wmb(); 3039 if (start_cycle) 3040 start_trb->field[3] |= cpu_to_le32(start_cycle); 3041 else 3042 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 3043 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); 3044 } 3045 3046 static void check_interval(struct xhci_hcd *xhci, struct urb *urb, 3047 struct xhci_ep_ctx *ep_ctx) 3048 { 3049 int xhci_interval; 3050 int ep_interval; 3051 3052 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); 3053 ep_interval = urb->interval; 3054 3055 /* Convert to microframes */ 3056 if (urb->dev->speed == USB_SPEED_LOW || 3057 urb->dev->speed == USB_SPEED_FULL) 3058 ep_interval *= 8; 3059 3060 /* FIXME change this to a warning and a suggestion to use the new API 3061 * to set the polling interval (once the API is added). 3062 */ 3063 if (xhci_interval != ep_interval) { 3064 dev_dbg_ratelimited(&urb->dev->dev, 3065 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", 3066 ep_interval, ep_interval == 1 ? "" : "s", 3067 xhci_interval, xhci_interval == 1 ? "" : "s"); 3068 urb->interval = xhci_interval; 3069 /* Convert back to frames for LS/FS devices */ 3070 if (urb->dev->speed == USB_SPEED_LOW || 3071 urb->dev->speed == USB_SPEED_FULL) 3072 urb->interval /= 8; 3073 } 3074 } 3075 3076 /* 3077 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt 3078 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD 3079 * (comprised of sg list entries) can take several service intervals to 3080 * transmit. 3081 */ 3082 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3083 struct urb *urb, int slot_id, unsigned int ep_index) 3084 { 3085 struct xhci_ep_ctx *ep_ctx; 3086 3087 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); 3088 check_interval(xhci, urb, ep_ctx); 3089 3090 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); 3091 } 3092 3093 /* 3094 * For xHCI 1.0 host controllers, TD size is the number of max packet sized 3095 * packets remaining in the TD (*not* including this TRB). 3096 * 3097 * Total TD packet count = total_packet_count = 3098 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) 3099 * 3100 * Packets transferred up to and including this TRB = packets_transferred = 3101 * rounddown(total bytes transferred including this TRB / wMaxPacketSize) 3102 * 3103 * TD size = total_packet_count - packets_transferred 3104 * 3105 * For xHCI 0.96 and older, TD size field should be the remaining bytes 3106 * including this TRB, right shifted by 10 3107 * 3108 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. 3109 * This is taken care of in the TRB_TD_SIZE() macro 3110 * 3111 * The last TRB in a TD must have the TD size set to zero. 3112 */ 3113 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, 3114 int trb_buff_len, unsigned int td_total_len, 3115 struct urb *urb, bool more_trbs_coming) 3116 { 3117 u32 maxp, total_packet_count; 3118 3119 /* MTK xHCI 0.96 contains some features from 1.0 */ 3120 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) 3121 return ((td_total_len - transferred) >> 10); 3122 3123 /* One TRB with a zero-length data packet. */ 3124 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || 3125 trb_buff_len == td_total_len) 3126 return 0; 3127 3128 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ 3129 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) 3130 trb_buff_len = 0; 3131 3132 maxp = usb_endpoint_maxp(&urb->ep->desc); 3133 total_packet_count = DIV_ROUND_UP(td_total_len, maxp); 3134 3135 /* Queueing functions don't count the current TRB into transferred */ 3136 return (total_packet_count - ((transferred + trb_buff_len) / maxp)); 3137 } 3138 3139 3140 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, 3141 u32 *trb_buff_len, struct xhci_segment *seg) 3142 { 3143 struct device *dev = xhci_to_hcd(xhci)->self.controller; 3144 unsigned int unalign; 3145 unsigned int max_pkt; 3146 u32 new_buff_len; 3147 size_t len; 3148 3149 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3150 unalign = (enqd_len + *trb_buff_len) % max_pkt; 3151 3152 /* we got lucky, last normal TRB data on segment is packet aligned */ 3153 if (unalign == 0) 3154 return 0; 3155 3156 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", 3157 unalign, *trb_buff_len); 3158 3159 /* is the last nornal TRB alignable by splitting it */ 3160 if (*trb_buff_len > unalign) { 3161 *trb_buff_len -= unalign; 3162 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); 3163 return 0; 3164 } 3165 3166 /* 3167 * We want enqd_len + trb_buff_len to sum up to a number aligned to 3168 * number which is divisible by the endpoint's wMaxPacketSize. IOW: 3169 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. 3170 */ 3171 new_buff_len = max_pkt - (enqd_len % max_pkt); 3172 3173 if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) 3174 new_buff_len = (urb->transfer_buffer_length - enqd_len); 3175 3176 /* create a max max_pkt sized bounce buffer pointed to by last trb */ 3177 if (usb_urb_dir_out(urb)) { 3178 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, 3179 seg->bounce_buf, new_buff_len, enqd_len); 3180 if (len != seg->bounce_len) 3181 xhci_warn(xhci, 3182 "WARN Wrong bounce buffer write length: %zu != %d\n", 3183 len, seg->bounce_len); 3184 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3185 max_pkt, DMA_TO_DEVICE); 3186 } else { 3187 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, 3188 max_pkt, DMA_FROM_DEVICE); 3189 } 3190 3191 if (dma_mapping_error(dev, seg->bounce_dma)) { 3192 /* try without aligning. Some host controllers survive */ 3193 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); 3194 return 0; 3195 } 3196 *trb_buff_len = new_buff_len; 3197 seg->bounce_len = new_buff_len; 3198 seg->bounce_offs = enqd_len; 3199 3200 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); 3201 3202 return 1; 3203 } 3204 3205 /* This is very similar to what ehci-q.c qtd_fill() does */ 3206 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3207 struct urb *urb, int slot_id, unsigned int ep_index) 3208 { 3209 struct xhci_ring *ring; 3210 struct urb_priv *urb_priv; 3211 struct xhci_td *td; 3212 struct xhci_generic_trb *start_trb; 3213 struct scatterlist *sg = NULL; 3214 bool more_trbs_coming = true; 3215 bool need_zero_pkt = false; 3216 bool first_trb = true; 3217 unsigned int num_trbs; 3218 unsigned int start_cycle, num_sgs = 0; 3219 unsigned int enqd_len, block_len, trb_buff_len, full_len; 3220 int sent_len, ret; 3221 u32 field, length_field, remainder; 3222 u64 addr, send_addr; 3223 3224 ring = xhci_urb_to_transfer_ring(xhci, urb); 3225 if (!ring) 3226 return -EINVAL; 3227 3228 full_len = urb->transfer_buffer_length; 3229 /* If we have scatter/gather list, we use it. */ 3230 if (urb->num_sgs) { 3231 num_sgs = urb->num_mapped_sgs; 3232 sg = urb->sg; 3233 addr = (u64) sg_dma_address(sg); 3234 block_len = sg_dma_len(sg); 3235 num_trbs = count_sg_trbs_needed(urb); 3236 } else { 3237 num_trbs = count_trbs_needed(urb); 3238 addr = (u64) urb->transfer_dma; 3239 block_len = full_len; 3240 } 3241 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3242 ep_index, urb->stream_id, 3243 num_trbs, urb, 0, mem_flags); 3244 if (unlikely(ret < 0)) 3245 return ret; 3246 3247 urb_priv = urb->hcpriv; 3248 3249 /* Deal with URB_ZERO_PACKET - need one more td/trb */ 3250 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) 3251 need_zero_pkt = true; 3252 3253 td = &urb_priv->td[0]; 3254 3255 /* 3256 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3257 * until we've finished creating all the other TRBs. The ring's cycle 3258 * state may change as we enqueue the other TRBs, so save it too. 3259 */ 3260 start_trb = &ring->enqueue->generic; 3261 start_cycle = ring->cycle_state; 3262 send_addr = addr; 3263 3264 /* Queue the TRBs, even if they are zero-length */ 3265 for (enqd_len = 0; first_trb || enqd_len < full_len; 3266 enqd_len += trb_buff_len) { 3267 field = TRB_TYPE(TRB_NORMAL); 3268 3269 /* TRB buffer should not cross 64KB boundaries */ 3270 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3271 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); 3272 3273 if (enqd_len + trb_buff_len > full_len) 3274 trb_buff_len = full_len - enqd_len; 3275 3276 /* Don't change the cycle bit of the first TRB until later */ 3277 if (first_trb) { 3278 first_trb = false; 3279 if (start_cycle == 0) 3280 field |= TRB_CYCLE; 3281 } else 3282 field |= ring->cycle_state; 3283 3284 /* Chain all the TRBs together; clear the chain bit in the last 3285 * TRB to indicate it's the last TRB in the chain. 3286 */ 3287 if (enqd_len + trb_buff_len < full_len) { 3288 field |= TRB_CHAIN; 3289 if (trb_is_link(ring->enqueue + 1)) { 3290 if (xhci_align_td(xhci, urb, enqd_len, 3291 &trb_buff_len, 3292 ring->enq_seg)) { 3293 send_addr = ring->enq_seg->bounce_dma; 3294 /* assuming TD won't span 2 segs */ 3295 td->bounce_seg = ring->enq_seg; 3296 } 3297 } 3298 } 3299 if (enqd_len + trb_buff_len >= full_len) { 3300 field &= ~TRB_CHAIN; 3301 field |= TRB_IOC; 3302 more_trbs_coming = false; 3303 td->last_trb = ring->enqueue; 3304 3305 if (xhci_urb_suitable_for_idt(urb)) { 3306 memcpy(&send_addr, urb->transfer_buffer, 3307 trb_buff_len); 3308 field |= TRB_IDT; 3309 } 3310 } 3311 3312 /* Only set interrupt on short packet for IN endpoints */ 3313 if (usb_urb_dir_in(urb)) 3314 field |= TRB_ISP; 3315 3316 /* Set the TRB length, TD size, and interrupter fields. */ 3317 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, 3318 full_len, urb, more_trbs_coming); 3319 3320 length_field = TRB_LEN(trb_buff_len) | 3321 TRB_TD_SIZE(remainder) | 3322 TRB_INTR_TARGET(0); 3323 3324 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, 3325 lower_32_bits(send_addr), 3326 upper_32_bits(send_addr), 3327 length_field, 3328 field); 3329 3330 addr += trb_buff_len; 3331 sent_len = trb_buff_len; 3332 3333 while (sg && sent_len >= block_len) { 3334 /* New sg entry */ 3335 --num_sgs; 3336 sent_len -= block_len; 3337 if (num_sgs != 0) { 3338 sg = sg_next(sg); 3339 block_len = sg_dma_len(sg); 3340 addr = (u64) sg_dma_address(sg); 3341 addr += sent_len; 3342 } 3343 } 3344 block_len -= sent_len; 3345 send_addr = addr; 3346 } 3347 3348 if (need_zero_pkt) { 3349 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3350 ep_index, urb->stream_id, 3351 1, urb, 1, mem_flags); 3352 urb_priv->td[1].last_trb = ring->enqueue; 3353 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; 3354 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); 3355 } 3356 3357 check_trb_math(urb, enqd_len); 3358 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3359 start_cycle, start_trb); 3360 return 0; 3361 } 3362 3363 /* Caller must have locked xhci->lock */ 3364 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3365 struct urb *urb, int slot_id, unsigned int ep_index) 3366 { 3367 struct xhci_ring *ep_ring; 3368 int num_trbs; 3369 int ret; 3370 struct usb_ctrlrequest *setup; 3371 struct xhci_generic_trb *start_trb; 3372 int start_cycle; 3373 u32 field; 3374 struct urb_priv *urb_priv; 3375 struct xhci_td *td; 3376 3377 ep_ring = xhci_urb_to_transfer_ring(xhci, urb); 3378 if (!ep_ring) 3379 return -EINVAL; 3380 3381 /* 3382 * Need to copy setup packet into setup TRB, so we can't use the setup 3383 * DMA address. 3384 */ 3385 if (!urb->setup_packet) 3386 return -EINVAL; 3387 3388 /* 1 TRB for setup, 1 for status */ 3389 num_trbs = 2; 3390 /* 3391 * Don't need to check if we need additional event data and normal TRBs, 3392 * since data in control transfers will never get bigger than 16MB 3393 * XXX: can we get a buffer that crosses 64KB boundaries? 3394 */ 3395 if (urb->transfer_buffer_length > 0) 3396 num_trbs++; 3397 ret = prepare_transfer(xhci, xhci->devs[slot_id], 3398 ep_index, urb->stream_id, 3399 num_trbs, urb, 0, mem_flags); 3400 if (ret < 0) 3401 return ret; 3402 3403 urb_priv = urb->hcpriv; 3404 td = &urb_priv->td[0]; 3405 3406 /* 3407 * Don't give the first TRB to the hardware (by toggling the cycle bit) 3408 * until we've finished creating all the other TRBs. The ring's cycle 3409 * state may change as we enqueue the other TRBs, so save it too. 3410 */ 3411 start_trb = &ep_ring->enqueue->generic; 3412 start_cycle = ep_ring->cycle_state; 3413 3414 /* Queue setup TRB - see section 6.4.1.2.1 */ 3415 /* FIXME better way to translate setup_packet into two u32 fields? */ 3416 setup = (struct usb_ctrlrequest *) urb->setup_packet; 3417 field = 0; 3418 field |= TRB_IDT | TRB_TYPE(TRB_SETUP); 3419 if (start_cycle == 0) 3420 field |= 0x1; 3421 3422 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ 3423 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { 3424 if (urb->transfer_buffer_length > 0) { 3425 if (setup->bRequestType & USB_DIR_IN) 3426 field |= TRB_TX_TYPE(TRB_DATA_IN); 3427 else 3428 field |= TRB_TX_TYPE(TRB_DATA_OUT); 3429 } 3430 } 3431 3432 queue_trb(xhci, ep_ring, true, 3433 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, 3434 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, 3435 TRB_LEN(8) | TRB_INTR_TARGET(0), 3436 /* Immediate data in pointer */ 3437 field); 3438 3439 /* If there's data, queue data TRBs */ 3440 /* Only set interrupt on short packet for IN endpoints */ 3441 if (usb_urb_dir_in(urb)) 3442 field = TRB_ISP | TRB_TYPE(TRB_DATA); 3443 else 3444 field = TRB_TYPE(TRB_DATA); 3445 3446 if (urb->transfer_buffer_length > 0) { 3447 u32 length_field, remainder; 3448 u64 addr; 3449 3450 if (xhci_urb_suitable_for_idt(urb)) { 3451 memcpy(&addr, urb->transfer_buffer, 3452 urb->transfer_buffer_length); 3453 field |= TRB_IDT; 3454 } else { 3455 addr = (u64) urb->transfer_dma; 3456 } 3457 3458 remainder = xhci_td_remainder(xhci, 0, 3459 urb->transfer_buffer_length, 3460 urb->transfer_buffer_length, 3461 urb, 1); 3462 length_field = TRB_LEN(urb->transfer_buffer_length) | 3463 TRB_TD_SIZE(remainder) | 3464 TRB_INTR_TARGET(0); 3465 if (setup->bRequestType & USB_DIR_IN) 3466 field |= TRB_DIR_IN; 3467 queue_trb(xhci, ep_ring, true, 3468 lower_32_bits(addr), 3469 upper_32_bits(addr), 3470 length_field, 3471 field | ep_ring->cycle_state); 3472 } 3473 3474 /* Save the DMA address of the last TRB in the TD */ 3475 td->last_trb = ep_ring->enqueue; 3476 3477 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ 3478 /* If the device sent data, the status stage is an OUT transfer */ 3479 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) 3480 field = 0; 3481 else 3482 field = TRB_DIR_IN; 3483 queue_trb(xhci, ep_ring, false, 3484 0, 3485 0, 3486 TRB_INTR_TARGET(0), 3487 /* Event on completion */ 3488 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); 3489 3490 giveback_first_trb(xhci, slot_id, ep_index, 0, 3491 start_cycle, start_trb); 3492 return 0; 3493 } 3494 3495 /* 3496 * The transfer burst count field of the isochronous TRB defines the number of 3497 * bursts that are required to move all packets in this TD. Only SuperSpeed 3498 * devices can burst up to bMaxBurst number of packets per service interval. 3499 * This field is zero based, meaning a value of zero in the field means one 3500 * burst. Basically, for everything but SuperSpeed devices, this field will be 3501 * zero. Only xHCI 1.0 host controllers support this field. 3502 */ 3503 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, 3504 struct urb *urb, unsigned int total_packet_count) 3505 { 3506 unsigned int max_burst; 3507 3508 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) 3509 return 0; 3510 3511 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3512 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; 3513 } 3514 3515 /* 3516 * Returns the number of packets in the last "burst" of packets. This field is 3517 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so 3518 * the last burst packet count is equal to the total number of packets in the 3519 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst 3520 * must contain (bMaxBurst + 1) number of packets, but the last burst can 3521 * contain 1 to (bMaxBurst + 1) packets. 3522 */ 3523 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, 3524 struct urb *urb, unsigned int total_packet_count) 3525 { 3526 unsigned int max_burst; 3527 unsigned int residue; 3528 3529 if (xhci->hci_version < 0x100) 3530 return 0; 3531 3532 if (urb->dev->speed >= USB_SPEED_SUPER) { 3533 /* bMaxBurst is zero based: 0 means 1 packet per burst */ 3534 max_burst = urb->ep->ss_ep_comp.bMaxBurst; 3535 residue = total_packet_count % (max_burst + 1); 3536 /* If residue is zero, the last burst contains (max_burst + 1) 3537 * number of packets, but the TLBPC field is zero-based. 3538 */ 3539 if (residue == 0) 3540 return max_burst; 3541 return residue - 1; 3542 } 3543 if (total_packet_count == 0) 3544 return 0; 3545 return total_packet_count - 1; 3546 } 3547 3548 /* 3549 * Calculates Frame ID field of the isochronous TRB identifies the 3550 * target frame that the Interval associated with this Isochronous 3551 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. 3552 * 3553 * Returns actual frame id on success, negative value on error. 3554 */ 3555 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, 3556 struct urb *urb, int index) 3557 { 3558 int start_frame, ist, ret = 0; 3559 int start_frame_id, end_frame_id, current_frame_id; 3560 3561 if (urb->dev->speed == USB_SPEED_LOW || 3562 urb->dev->speed == USB_SPEED_FULL) 3563 start_frame = urb->start_frame + index * urb->interval; 3564 else 3565 start_frame = (urb->start_frame + index * urb->interval) >> 3; 3566 3567 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): 3568 * 3569 * If bit [3] of IST is cleared to '0', software can add a TRB no 3570 * later than IST[2:0] Microframes before that TRB is scheduled to 3571 * be executed. 3572 * If bit [3] of IST is set to '1', software can add a TRB no later 3573 * than IST[2:0] Frames before that TRB is scheduled to be executed. 3574 */ 3575 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3576 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3577 ist <<= 3; 3578 3579 /* Software shall not schedule an Isoch TD with a Frame ID value that 3580 * is less than the Start Frame ID or greater than the End Frame ID, 3581 * where: 3582 * 3583 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 3584 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 3585 * 3586 * Both the End Frame ID and Start Frame ID values are calculated 3587 * in microframes. When software determines the valid Frame ID value; 3588 * The End Frame ID value should be rounded down to the nearest Frame 3589 * boundary, and the Start Frame ID value should be rounded up to the 3590 * nearest Frame boundary. 3591 */ 3592 current_frame_id = readl(&xhci->run_regs->microframe_index); 3593 start_frame_id = roundup(current_frame_id + ist + 1, 8); 3594 end_frame_id = rounddown(current_frame_id + 895 * 8, 8); 3595 3596 start_frame &= 0x7ff; 3597 start_frame_id = (start_frame_id >> 3) & 0x7ff; 3598 end_frame_id = (end_frame_id >> 3) & 0x7ff; 3599 3600 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", 3601 __func__, index, readl(&xhci->run_regs->microframe_index), 3602 start_frame_id, end_frame_id, start_frame); 3603 3604 if (start_frame_id < end_frame_id) { 3605 if (start_frame > end_frame_id || 3606 start_frame < start_frame_id) 3607 ret = -EINVAL; 3608 } else if (start_frame_id > end_frame_id) { 3609 if ((start_frame > end_frame_id && 3610 start_frame < start_frame_id)) 3611 ret = -EINVAL; 3612 } else { 3613 ret = -EINVAL; 3614 } 3615 3616 if (index == 0) { 3617 if (ret == -EINVAL || start_frame == start_frame_id) { 3618 start_frame = start_frame_id + 1; 3619 if (urb->dev->speed == USB_SPEED_LOW || 3620 urb->dev->speed == USB_SPEED_FULL) 3621 urb->start_frame = start_frame; 3622 else 3623 urb->start_frame = start_frame << 3; 3624 ret = 0; 3625 } 3626 } 3627 3628 if (ret) { 3629 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", 3630 start_frame, current_frame_id, index, 3631 start_frame_id, end_frame_id); 3632 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); 3633 return ret; 3634 } 3635 3636 return start_frame; 3637 } 3638 3639 /* This is for isoc transfer */ 3640 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, 3641 struct urb *urb, int slot_id, unsigned int ep_index) 3642 { 3643 struct xhci_ring *ep_ring; 3644 struct urb_priv *urb_priv; 3645 struct xhci_td *td; 3646 int num_tds, trbs_per_td; 3647 struct xhci_generic_trb *start_trb; 3648 bool first_trb; 3649 int start_cycle; 3650 u32 field, length_field; 3651 int running_total, trb_buff_len, td_len, td_remain_len, ret; 3652 u64 start_addr, addr; 3653 int i, j; 3654 bool more_trbs_coming; 3655 struct xhci_virt_ep *xep; 3656 int frame_id; 3657 3658 xep = &xhci->devs[slot_id]->eps[ep_index]; 3659 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; 3660 3661 num_tds = urb->number_of_packets; 3662 if (num_tds < 1) { 3663 xhci_dbg(xhci, "Isoc URB with zero packets?\n"); 3664 return -EINVAL; 3665 } 3666 start_addr = (u64) urb->transfer_dma; 3667 start_trb = &ep_ring->enqueue->generic; 3668 start_cycle = ep_ring->cycle_state; 3669 3670 urb_priv = urb->hcpriv; 3671 /* Queue the TRBs for each TD, even if they are zero-length */ 3672 for (i = 0; i < num_tds; i++) { 3673 unsigned int total_pkt_count, max_pkt; 3674 unsigned int burst_count, last_burst_pkt_count; 3675 u32 sia_frame_id; 3676 3677 first_trb = true; 3678 running_total = 0; 3679 addr = start_addr + urb->iso_frame_desc[i].offset; 3680 td_len = urb->iso_frame_desc[i].length; 3681 td_remain_len = td_len; 3682 max_pkt = usb_endpoint_maxp(&urb->ep->desc); 3683 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); 3684 3685 /* A zero-length transfer still involves at least one packet. */ 3686 if (total_pkt_count == 0) 3687 total_pkt_count++; 3688 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); 3689 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, 3690 urb, total_pkt_count); 3691 3692 trbs_per_td = count_isoc_trbs_needed(urb, i); 3693 3694 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, 3695 urb->stream_id, trbs_per_td, urb, i, mem_flags); 3696 if (ret < 0) { 3697 if (i == 0) 3698 return ret; 3699 goto cleanup; 3700 } 3701 td = &urb_priv->td[i]; 3702 3703 /* use SIA as default, if frame id is used overwrite it */ 3704 sia_frame_id = TRB_SIA; 3705 if (!(urb->transfer_flags & URB_ISO_ASAP) && 3706 HCC_CFC(xhci->hcc_params)) { 3707 frame_id = xhci_get_isoc_frame_id(xhci, urb, i); 3708 if (frame_id >= 0) 3709 sia_frame_id = TRB_FRAME_ID(frame_id); 3710 } 3711 /* 3712 * Set isoc specific data for the first TRB in a TD. 3713 * Prevent HW from getting the TRBs by keeping the cycle state 3714 * inverted in the first TDs isoc TRB. 3715 */ 3716 field = TRB_TYPE(TRB_ISOC) | 3717 TRB_TLBPC(last_burst_pkt_count) | 3718 sia_frame_id | 3719 (i ? ep_ring->cycle_state : !start_cycle); 3720 3721 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ 3722 if (!xep->use_extended_tbc) 3723 field |= TRB_TBC(burst_count); 3724 3725 /* fill the rest of the TRB fields, and remaining normal TRBs */ 3726 for (j = 0; j < trbs_per_td; j++) { 3727 u32 remainder = 0; 3728 3729 /* only first TRB is isoc, overwrite otherwise */ 3730 if (!first_trb) 3731 field = TRB_TYPE(TRB_NORMAL) | 3732 ep_ring->cycle_state; 3733 3734 /* Only set interrupt on short packet for IN EPs */ 3735 if (usb_urb_dir_in(urb)) 3736 field |= TRB_ISP; 3737 3738 /* Set the chain bit for all except the last TRB */ 3739 if (j < trbs_per_td - 1) { 3740 more_trbs_coming = true; 3741 field |= TRB_CHAIN; 3742 } else { 3743 more_trbs_coming = false; 3744 td->last_trb = ep_ring->enqueue; 3745 field |= TRB_IOC; 3746 /* set BEI, except for the last TD */ 3747 if (xhci->hci_version >= 0x100 && 3748 !(xhci->quirks & XHCI_AVOID_BEI) && 3749 i < num_tds - 1) 3750 field |= TRB_BEI; 3751 } 3752 /* Calculate TRB length */ 3753 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); 3754 if (trb_buff_len > td_remain_len) 3755 trb_buff_len = td_remain_len; 3756 3757 /* Set the TRB length, TD size, & interrupter fields. */ 3758 remainder = xhci_td_remainder(xhci, running_total, 3759 trb_buff_len, td_len, 3760 urb, more_trbs_coming); 3761 3762 length_field = TRB_LEN(trb_buff_len) | 3763 TRB_INTR_TARGET(0); 3764 3765 /* xhci 1.1 with ETE uses TD Size field for TBC */ 3766 if (first_trb && xep->use_extended_tbc) 3767 length_field |= TRB_TD_SIZE_TBC(burst_count); 3768 else 3769 length_field |= TRB_TD_SIZE(remainder); 3770 first_trb = false; 3771 3772 queue_trb(xhci, ep_ring, more_trbs_coming, 3773 lower_32_bits(addr), 3774 upper_32_bits(addr), 3775 length_field, 3776 field); 3777 running_total += trb_buff_len; 3778 3779 addr += trb_buff_len; 3780 td_remain_len -= trb_buff_len; 3781 } 3782 3783 /* Check TD length */ 3784 if (running_total != td_len) { 3785 xhci_err(xhci, "ISOC TD length unmatch\n"); 3786 ret = -EINVAL; 3787 goto cleanup; 3788 } 3789 } 3790 3791 /* store the next frame id */ 3792 if (HCC_CFC(xhci->hcc_params)) 3793 xep->next_frame_id = urb->start_frame + num_tds * urb->interval; 3794 3795 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { 3796 if (xhci->quirks & XHCI_AMD_PLL_FIX) 3797 usb_amd_quirk_pll_disable(); 3798 } 3799 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; 3800 3801 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, 3802 start_cycle, start_trb); 3803 return 0; 3804 cleanup: 3805 /* Clean up a partially enqueued isoc transfer. */ 3806 3807 for (i--; i >= 0; i--) 3808 list_del_init(&urb_priv->td[i].td_list); 3809 3810 /* Use the first TD as a temporary variable to turn the TDs we've queued 3811 * into No-ops with a software-owned cycle bit. That way the hardware 3812 * won't accidentally start executing bogus TDs when we partially 3813 * overwrite them. td->first_trb and td->start_seg are already set. 3814 */ 3815 urb_priv->td[0].last_trb = ep_ring->enqueue; 3816 /* Every TRB except the first & last will have its cycle bit flipped. */ 3817 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); 3818 3819 /* Reset the ring enqueue back to the first TRB and its cycle bit. */ 3820 ep_ring->enqueue = urb_priv->td[0].first_trb; 3821 ep_ring->enq_seg = urb_priv->td[0].start_seg; 3822 ep_ring->cycle_state = start_cycle; 3823 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; 3824 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); 3825 return ret; 3826 } 3827 3828 /* 3829 * Check transfer ring to guarantee there is enough room for the urb. 3830 * Update ISO URB start_frame and interval. 3831 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to 3832 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or 3833 * Contiguous Frame ID is not supported by HC. 3834 */ 3835 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 3836 struct urb *urb, int slot_id, unsigned int ep_index) 3837 { 3838 struct xhci_virt_device *xdev; 3839 struct xhci_ring *ep_ring; 3840 struct xhci_ep_ctx *ep_ctx; 3841 int start_frame; 3842 int num_tds, num_trbs, i; 3843 int ret; 3844 struct xhci_virt_ep *xep; 3845 int ist; 3846 3847 xdev = xhci->devs[slot_id]; 3848 xep = &xhci->devs[slot_id]->eps[ep_index]; 3849 ep_ring = xdev->eps[ep_index].ring; 3850 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); 3851 3852 num_trbs = 0; 3853 num_tds = urb->number_of_packets; 3854 for (i = 0; i < num_tds; i++) 3855 num_trbs += count_isoc_trbs_needed(urb, i); 3856 3857 /* Check the ring to guarantee there is enough room for the whole urb. 3858 * Do not insert any td of the urb to the ring if the check failed. 3859 */ 3860 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), 3861 num_trbs, mem_flags); 3862 if (ret) 3863 return ret; 3864 3865 /* 3866 * Check interval value. This should be done before we start to 3867 * calculate the start frame value. 3868 */ 3869 check_interval(xhci, urb, ep_ctx); 3870 3871 /* Calculate the start frame and put it in urb->start_frame. */ 3872 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { 3873 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { 3874 urb->start_frame = xep->next_frame_id; 3875 goto skip_start_over; 3876 } 3877 } 3878 3879 start_frame = readl(&xhci->run_regs->microframe_index); 3880 start_frame &= 0x3fff; 3881 /* 3882 * Round up to the next frame and consider the time before trb really 3883 * gets scheduled by hardare. 3884 */ 3885 ist = HCS_IST(xhci->hcs_params2) & 0x7; 3886 if (HCS_IST(xhci->hcs_params2) & (1 << 3)) 3887 ist <<= 3; 3888 start_frame += ist + XHCI_CFC_DELAY; 3889 start_frame = roundup(start_frame, 8); 3890 3891 /* 3892 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT 3893 * is greate than 8 microframes. 3894 */ 3895 if (urb->dev->speed == USB_SPEED_LOW || 3896 urb->dev->speed == USB_SPEED_FULL) { 3897 start_frame = roundup(start_frame, urb->interval << 3); 3898 urb->start_frame = start_frame >> 3; 3899 } else { 3900 start_frame = roundup(start_frame, urb->interval); 3901 urb->start_frame = start_frame; 3902 } 3903 3904 skip_start_over: 3905 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; 3906 3907 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); 3908 } 3909 3910 /**** Command Ring Operations ****/ 3911 3912 /* Generic function for queueing a command TRB on the command ring. 3913 * Check to make sure there's room on the command ring for one command TRB. 3914 * Also check that there's room reserved for commands that must not fail. 3915 * If this is a command that must not fail, meaning command_must_succeed = TRUE, 3916 * then only check for the number of reserved spots. 3917 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB 3918 * because the command event handler may want to resubmit a failed command. 3919 */ 3920 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3921 u32 field1, u32 field2, 3922 u32 field3, u32 field4, bool command_must_succeed) 3923 { 3924 int reserved_trbs = xhci->cmd_ring_reserved_trbs; 3925 int ret; 3926 3927 if ((xhci->xhc_state & XHCI_STATE_DYING) || 3928 (xhci->xhc_state & XHCI_STATE_HALTED)) { 3929 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); 3930 return -ESHUTDOWN; 3931 } 3932 3933 if (!command_must_succeed) 3934 reserved_trbs++; 3935 3936 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, 3937 reserved_trbs, GFP_ATOMIC); 3938 if (ret < 0) { 3939 xhci_err(xhci, "ERR: No room for command on command ring\n"); 3940 if (command_must_succeed) 3941 xhci_err(xhci, "ERR: Reserved TRB counting for " 3942 "unfailable commands failed.\n"); 3943 return ret; 3944 } 3945 3946 cmd->command_trb = xhci->cmd_ring->enqueue; 3947 3948 /* if there are no other commands queued we start the timeout timer */ 3949 if (list_empty(&xhci->cmd_list)) { 3950 xhci->current_cmd = cmd; 3951 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); 3952 } 3953 3954 list_add_tail(&cmd->cmd_list, &xhci->cmd_list); 3955 3956 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, 3957 field4 | xhci->cmd_ring->cycle_state); 3958 return 0; 3959 } 3960 3961 /* Queue a slot enable or disable request on the command ring */ 3962 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 3963 u32 trb_type, u32 slot_id) 3964 { 3965 return queue_command(xhci, cmd, 0, 0, 0, 3966 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); 3967 } 3968 3969 /* Queue an address device command TRB */ 3970 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3971 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) 3972 { 3973 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 3974 upper_32_bits(in_ctx_ptr), 0, 3975 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) 3976 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); 3977 } 3978 3979 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 3980 u32 field1, u32 field2, u32 field3, u32 field4) 3981 { 3982 return queue_command(xhci, cmd, field1, field2, field3, field4, false); 3983 } 3984 3985 /* Queue a reset device command TRB */ 3986 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 3987 u32 slot_id) 3988 { 3989 return queue_command(xhci, cmd, 0, 0, 0, 3990 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), 3991 false); 3992 } 3993 3994 /* Queue a configure endpoint command TRB */ 3995 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 3996 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, 3997 u32 slot_id, bool command_must_succeed) 3998 { 3999 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4000 upper_32_bits(in_ctx_ptr), 0, 4001 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), 4002 command_must_succeed); 4003 } 4004 4005 /* Queue an evaluate context command TRB */ 4006 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 4007 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) 4008 { 4009 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), 4010 upper_32_bits(in_ctx_ptr), 0, 4011 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), 4012 command_must_succeed); 4013 } 4014 4015 /* 4016 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop 4017 * activity on an endpoint that is about to be suspended. 4018 */ 4019 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 4020 int slot_id, unsigned int ep_index, int suspend) 4021 { 4022 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4023 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4024 u32 type = TRB_TYPE(TRB_STOP_RING); 4025 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); 4026 4027 return queue_command(xhci, cmd, 0, 0, 0, 4028 trb_slot_id | trb_ep_index | type | trb_suspend, false); 4029 } 4030 4031 /* Set Transfer Ring Dequeue Pointer command */ 4032 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 4033 unsigned int slot_id, unsigned int ep_index, 4034 struct xhci_dequeue_state *deq_state) 4035 { 4036 dma_addr_t addr; 4037 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4038 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4039 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id); 4040 u32 trb_sct = 0; 4041 u32 type = TRB_TYPE(TRB_SET_DEQ); 4042 struct xhci_virt_ep *ep; 4043 struct xhci_command *cmd; 4044 int ret; 4045 4046 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, 4047 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", 4048 deq_state->new_deq_seg, 4049 (unsigned long long)deq_state->new_deq_seg->dma, 4050 deq_state->new_deq_ptr, 4051 (unsigned long long)xhci_trb_virt_to_dma( 4052 deq_state->new_deq_seg, deq_state->new_deq_ptr), 4053 deq_state->new_cycle_state); 4054 4055 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, 4056 deq_state->new_deq_ptr); 4057 if (addr == 0) { 4058 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4059 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", 4060 deq_state->new_deq_seg, deq_state->new_deq_ptr); 4061 return; 4062 } 4063 ep = &xhci->devs[slot_id]->eps[ep_index]; 4064 if ((ep->ep_state & SET_DEQ_PENDING)) { 4065 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); 4066 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); 4067 return; 4068 } 4069 4070 /* This function gets called from contexts where it cannot sleep */ 4071 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); 4072 if (!cmd) 4073 return; 4074 4075 ep->queued_deq_seg = deq_state->new_deq_seg; 4076 ep->queued_deq_ptr = deq_state->new_deq_ptr; 4077 if (deq_state->stream_id) 4078 trb_sct = SCT_FOR_TRB(SCT_PRI_TR); 4079 ret = queue_command(xhci, cmd, 4080 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, 4081 upper_32_bits(addr), trb_stream_id, 4082 trb_slot_id | trb_ep_index | type, false); 4083 if (ret < 0) { 4084 xhci_free_command(xhci, cmd); 4085 return; 4086 } 4087 4088 /* Stop the TD queueing code from ringing the doorbell until 4089 * this command completes. The HC won't set the dequeue pointer 4090 * if the ring is running, and ringing the doorbell starts the 4091 * ring running. 4092 */ 4093 ep->ep_state |= SET_DEQ_PENDING; 4094 } 4095 4096 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 4097 int slot_id, unsigned int ep_index, 4098 enum xhci_ep_reset_type reset_type) 4099 { 4100 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); 4101 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); 4102 u32 type = TRB_TYPE(TRB_RESET_EP); 4103 4104 if (reset_type == EP_SOFT_RESET) 4105 type |= TRB_TSP; 4106 4107 return queue_command(xhci, cmd, 0, 0, 0, 4108 trb_slot_id | trb_ep_index | type, false); 4109 } 4110