1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *dummy; /* For AMD quirk use */ 77 struct ehci_qh *reclaim; 78 unsigned scanning : 1; 79 80 /* periodic schedule support */ 81 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 82 unsigned periodic_size; 83 __hc32 *periodic; /* hw periodic table */ 84 dma_addr_t periodic_dma; 85 unsigned i_thresh; /* uframes HC might cache */ 86 87 union ehci_shadow *pshadow; /* mirror hw periodic table */ 88 int next_uframe; /* scan periodic, start here */ 89 unsigned periodic_sched; /* periodic activity count */ 90 91 /* list of itds & sitds completed while clock_frame was still active */ 92 struct list_head cached_itd_list; 93 struct list_head cached_sitd_list; 94 unsigned clock_frame; 95 96 /* per root hub port */ 97 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 98 99 /* bit vectors (one bit per port) */ 100 unsigned long bus_suspended; /* which ports were 101 already suspended at the start of a bus suspend */ 102 unsigned long companion_ports; /* which ports are 103 dedicated to the companion controller */ 104 unsigned long owned_ports; /* which ports are 105 owned by the companion during a bus suspend */ 106 unsigned long port_c_suspend; /* which ports have 107 the change-suspend feature turned on */ 108 unsigned long suspended_ports; /* which ports are 109 suspended */ 110 111 /* per-HC memory pools (could be per-bus, but ...) */ 112 struct dma_pool *qh_pool; /* qh per active urb */ 113 struct dma_pool *qtd_pool; /* one or more per qh */ 114 struct dma_pool *itd_pool; /* itd per iso urb */ 115 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 116 117 struct timer_list iaa_watchdog; 118 struct timer_list watchdog; 119 unsigned long actions; 120 unsigned stamp; 121 unsigned periodic_stamp; 122 unsigned random_frame; 123 unsigned long next_statechange; 124 ktime_t last_periodic_enable; 125 u32 command; 126 127 /* SILICON QUIRKS */ 128 unsigned no_selective_suspend:1; 129 unsigned has_fsl_port_bug:1; /* FreeScale */ 130 unsigned big_endian_mmio:1; 131 unsigned big_endian_desc:1; 132 unsigned big_endian_capbase:1; 133 unsigned has_amcc_usb23:1; 134 unsigned need_io_watchdog:1; 135 unsigned broken_periodic:1; 136 unsigned amd_pll_fix:1; 137 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 138 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 139 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 140 141 /* required for usb32 quirk */ 142 #define OHCI_CTRL_HCFS (3 << 6) 143 #define OHCI_USB_OPER (2 << 6) 144 #define OHCI_USB_SUSPEND (3 << 6) 145 146 #define OHCI_HCCTRL_OFFSET 0x4 147 #define OHCI_HCCTRL_LEN 0x4 148 __hc32 *ohci_hcctrl_reg; 149 unsigned has_hostpc:1; 150 unsigned has_lpm:1; /* support link power management */ 151 unsigned has_ppcd:1; /* support per-port change bits */ 152 u8 sbrn; /* packed release number */ 153 154 /* irq statistics */ 155 #ifdef EHCI_STATS 156 struct ehci_stats stats; 157 # define COUNT(x) do { (x)++; } while (0) 158 #else 159 # define COUNT(x) do {} while (0) 160 #endif 161 162 /* debug files */ 163 #ifdef DEBUG 164 struct dentry *debug_dir; 165 #endif 166 /* 167 * OTG controllers and transceivers need software interaction 168 */ 169 struct otg_transceiver *transceiver; 170 }; 171 172 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 173 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 174 { 175 return (struct ehci_hcd *) (hcd->hcd_priv); 176 } 177 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 178 { 179 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 180 } 181 182 183 static inline void 184 iaa_watchdog_start(struct ehci_hcd *ehci) 185 { 186 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 187 mod_timer(&ehci->iaa_watchdog, 188 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 189 } 190 191 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 192 { 193 del_timer(&ehci->iaa_watchdog); 194 } 195 196 enum ehci_timer_action { 197 TIMER_IO_WATCHDOG, 198 TIMER_ASYNC_SHRINK, 199 TIMER_ASYNC_OFF, 200 }; 201 202 static inline void 203 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 204 { 205 clear_bit (action, &ehci->actions); 206 } 207 208 static void free_cached_lists(struct ehci_hcd *ehci); 209 210 /*-------------------------------------------------------------------------*/ 211 212 #include <linux/usb/ehci_def.h> 213 214 /*-------------------------------------------------------------------------*/ 215 216 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 217 218 /* 219 * EHCI Specification 0.95 Section 3.5 220 * QTD: describe data transfer components (buffer, direction, ...) 221 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 222 * 223 * These are associated only with "QH" (Queue Head) structures, 224 * used with control, bulk, and interrupt transfers. 225 */ 226 struct ehci_qtd { 227 /* first part defined by EHCI spec */ 228 __hc32 hw_next; /* see EHCI 3.5.1 */ 229 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 230 __hc32 hw_token; /* see EHCI 3.5.3 */ 231 #define QTD_TOGGLE (1 << 31) /* data toggle */ 232 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 233 #define QTD_IOC (1 << 15) /* interrupt on complete */ 234 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 235 #define QTD_PID(tok) (((tok)>>8) & 0x3) 236 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 237 #define QTD_STS_HALT (1 << 6) /* halted on error */ 238 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 239 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 240 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 241 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 242 #define QTD_STS_STS (1 << 1) /* split transaction state */ 243 #define QTD_STS_PING (1 << 0) /* issue PING? */ 244 245 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 246 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 247 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 248 249 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 250 __hc32 hw_buf_hi [5]; /* Appendix B */ 251 252 /* the rest is HCD-private */ 253 dma_addr_t qtd_dma; /* qtd address */ 254 struct list_head qtd_list; /* sw qtd list */ 255 struct urb *urb; /* qtd's urb */ 256 size_t length; /* length of buffer */ 257 } __attribute__ ((aligned (32))); 258 259 /* mask NakCnt+T in qh->hw_alt_next */ 260 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 261 262 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 263 264 /*-------------------------------------------------------------------------*/ 265 266 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 267 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 268 269 /* 270 * Now the following defines are not converted using the 271 * cpu_to_le32() macro anymore, since we have to support 272 * "dynamic" switching between be and le support, so that the driver 273 * can be used on one system with SoC EHCI controller using big-endian 274 * descriptors as well as a normal little-endian PCI EHCI controller. 275 */ 276 /* values for that type tag */ 277 #define Q_TYPE_ITD (0 << 1) 278 #define Q_TYPE_QH (1 << 1) 279 #define Q_TYPE_SITD (2 << 1) 280 #define Q_TYPE_FSTN (3 << 1) 281 282 /* next async queue entry, or pointer to interrupt/periodic QH */ 283 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 284 285 /* for periodic/async schedules and qtd lists, mark end of list */ 286 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 287 288 /* 289 * Entries in periodic shadow table are pointers to one of four kinds 290 * of data structure. That's dictated by the hardware; a type tag is 291 * encoded in the low bits of the hardware's periodic schedule. Use 292 * Q_NEXT_TYPE to get the tag. 293 * 294 * For entries in the async schedule, the type tag always says "qh". 295 */ 296 union ehci_shadow { 297 struct ehci_qh *qh; /* Q_TYPE_QH */ 298 struct ehci_itd *itd; /* Q_TYPE_ITD */ 299 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 300 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 301 __hc32 *hw_next; /* (all types) */ 302 void *ptr; 303 }; 304 305 /*-------------------------------------------------------------------------*/ 306 307 /* 308 * EHCI Specification 0.95 Section 3.6 309 * QH: describes control/bulk/interrupt endpoints 310 * See Fig 3-7 "Queue Head Structure Layout". 311 * 312 * These appear in both the async and (for interrupt) periodic schedules. 313 */ 314 315 /* first part defined by EHCI spec */ 316 struct ehci_qh_hw { 317 __hc32 hw_next; /* see EHCI 3.6.1 */ 318 __hc32 hw_info1; /* see EHCI 3.6.2 */ 319 #define QH_HEAD 0x00008000 320 __hc32 hw_info2; /* see EHCI 3.6.2 */ 321 #define QH_SMASK 0x000000ff 322 #define QH_CMASK 0x0000ff00 323 #define QH_HUBADDR 0x007f0000 324 #define QH_HUBPORT 0x3f800000 325 #define QH_MULT 0xc0000000 326 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 327 328 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 329 __hc32 hw_qtd_next; 330 __hc32 hw_alt_next; 331 __hc32 hw_token; 332 __hc32 hw_buf [5]; 333 __hc32 hw_buf_hi [5]; 334 } __attribute__ ((aligned(32))); 335 336 struct ehci_qh { 337 struct ehci_qh_hw *hw; 338 /* the rest is HCD-private */ 339 dma_addr_t qh_dma; /* address of qh */ 340 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 341 struct list_head qtd_list; /* sw qtd list */ 342 struct ehci_qtd *dummy; 343 struct ehci_qh *reclaim; /* next to reclaim */ 344 345 struct ehci_hcd *ehci; 346 347 /* 348 * Do NOT use atomic operations for QH refcounting. On some CPUs 349 * (PPC7448 for example), atomic operations cannot be performed on 350 * memory that is cache-inhibited (i.e. being used for DMA). 351 * Spinlocks are used to protect all QH fields. 352 */ 353 u32 refcount; 354 unsigned stamp; 355 356 u8 needs_rescan; /* Dequeue during giveback */ 357 u8 qh_state; 358 #define QH_STATE_LINKED 1 /* HC sees this */ 359 #define QH_STATE_UNLINK 2 /* HC may still see this */ 360 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 361 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 362 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 363 364 u8 xacterrs; /* XactErr retry counter */ 365 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 366 367 /* periodic schedule info */ 368 u8 usecs; /* intr bandwidth */ 369 u8 gap_uf; /* uframes split/csplit gap */ 370 u8 c_usecs; /* ... split completion bw */ 371 u16 tt_usecs; /* tt downstream bandwidth */ 372 unsigned short period; /* polling interval */ 373 unsigned short start; /* where polling starts */ 374 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 375 376 struct usb_device *dev; /* access to TT */ 377 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 378 }; 379 380 /*-------------------------------------------------------------------------*/ 381 382 /* description of one iso transaction (up to 3 KB data if highspeed) */ 383 struct ehci_iso_packet { 384 /* These will be copied to iTD when scheduling */ 385 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 386 __hc32 transaction; /* itd->hw_transaction[i] |= */ 387 u8 cross; /* buf crosses pages */ 388 /* for full speed OUT splits */ 389 u32 buf1; 390 }; 391 392 /* temporary schedule data for packets from iso urbs (both speeds) 393 * each packet is one logical usb transaction to the device (not TT), 394 * beginning at stream->next_uframe 395 */ 396 struct ehci_iso_sched { 397 struct list_head td_list; 398 unsigned span; 399 struct ehci_iso_packet packet [0]; 400 }; 401 402 /* 403 * ehci_iso_stream - groups all (s)itds for this endpoint. 404 * acts like a qh would, if EHCI had them for ISO. 405 */ 406 struct ehci_iso_stream { 407 /* first field matches ehci_hq, but is NULL */ 408 struct ehci_qh_hw *hw; 409 410 u32 refcount; 411 u8 bEndpointAddress; 412 u8 highspeed; 413 struct list_head td_list; /* queued itds/sitds */ 414 struct list_head free_list; /* list of unused itds/sitds */ 415 struct usb_device *udev; 416 struct usb_host_endpoint *ep; 417 418 /* output of (re)scheduling */ 419 int next_uframe; 420 __hc32 splits; 421 422 /* the rest is derived from the endpoint descriptor, 423 * trusting urb->interval == f(epdesc->bInterval) and 424 * including the extra info for hw_bufp[0..2] 425 */ 426 u8 usecs, c_usecs; 427 u16 interval; 428 u16 tt_usecs; 429 u16 maxp; 430 u16 raw_mask; 431 unsigned bandwidth; 432 433 /* This is used to initialize iTD's hw_bufp fields */ 434 __hc32 buf0; 435 __hc32 buf1; 436 __hc32 buf2; 437 438 /* this is used to initialize sITD's tt info */ 439 __hc32 address; 440 }; 441 442 /*-------------------------------------------------------------------------*/ 443 444 /* 445 * EHCI Specification 0.95 Section 3.3 446 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 447 * 448 * Schedule records for high speed iso xfers 449 */ 450 struct ehci_itd { 451 /* first part defined by EHCI spec */ 452 __hc32 hw_next; /* see EHCI 3.3.1 */ 453 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 454 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 455 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 456 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 457 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 458 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 459 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 460 461 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 462 463 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 464 __hc32 hw_bufp_hi [7]; /* Appendix B */ 465 466 /* the rest is HCD-private */ 467 dma_addr_t itd_dma; /* for this itd */ 468 union ehci_shadow itd_next; /* ptr to periodic q entry */ 469 470 struct urb *urb; 471 struct ehci_iso_stream *stream; /* endpoint's queue */ 472 struct list_head itd_list; /* list of stream's itds */ 473 474 /* any/all hw_transactions here may be used by that urb */ 475 unsigned frame; /* where scheduled */ 476 unsigned pg; 477 unsigned index[8]; /* in urb->iso_frame_desc */ 478 } __attribute__ ((aligned (32))); 479 480 /*-------------------------------------------------------------------------*/ 481 482 /* 483 * EHCI Specification 0.95 Section 3.4 484 * siTD, aka split-transaction isochronous Transfer Descriptor 485 * ... describe full speed iso xfers through TT in hubs 486 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 487 */ 488 struct ehci_sitd { 489 /* first part defined by EHCI spec */ 490 __hc32 hw_next; 491 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 492 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 493 __hc32 hw_uframe; /* EHCI table 3-10 */ 494 __hc32 hw_results; /* EHCI table 3-11 */ 495 #define SITD_IOC (1 << 31) /* interrupt on completion */ 496 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 497 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 498 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 499 #define SITD_STS_ERR (1 << 6) /* error from TT */ 500 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 501 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 502 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 503 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 504 #define SITD_STS_STS (1 << 1) /* split transaction state */ 505 506 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 507 508 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 509 __hc32 hw_backpointer; /* EHCI table 3-13 */ 510 __hc32 hw_buf_hi [2]; /* Appendix B */ 511 512 /* the rest is HCD-private */ 513 dma_addr_t sitd_dma; 514 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 515 516 struct urb *urb; 517 struct ehci_iso_stream *stream; /* endpoint's queue */ 518 struct list_head sitd_list; /* list of stream's sitds */ 519 unsigned frame; 520 unsigned index; 521 } __attribute__ ((aligned (32))); 522 523 /*-------------------------------------------------------------------------*/ 524 525 /* 526 * EHCI Specification 0.96 Section 3.7 527 * Periodic Frame Span Traversal Node (FSTN) 528 * 529 * Manages split interrupt transactions (using TT) that span frame boundaries 530 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 531 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 532 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 533 */ 534 struct ehci_fstn { 535 __hc32 hw_next; /* any periodic q entry */ 536 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 537 538 /* the rest is HCD-private */ 539 dma_addr_t fstn_dma; 540 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 541 } __attribute__ ((aligned (32))); 542 543 /*-------------------------------------------------------------------------*/ 544 545 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 546 547 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 548 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 549 550 #define ehci_prepare_ports_for_controller_resume(ehci) \ 551 ehci_adjust_port_wakeup_flags(ehci, false, false); 552 553 /*-------------------------------------------------------------------------*/ 554 555 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 556 557 /* 558 * Some EHCI controllers have a Transaction Translator built into the 559 * root hub. This is a non-standard feature. Each controller will need 560 * to add code to the following inline functions, and call them as 561 * needed (mostly in root hub code). 562 */ 563 564 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 565 566 /* Returns the speed of a device attached to a port on the root hub. */ 567 static inline unsigned int 568 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 569 { 570 if (ehci_is_TDI(ehci)) { 571 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 572 case 0: 573 return 0; 574 case 1: 575 return USB_PORT_STAT_LOW_SPEED; 576 case 2: 577 default: 578 return USB_PORT_STAT_HIGH_SPEED; 579 } 580 } 581 return USB_PORT_STAT_HIGH_SPEED; 582 } 583 584 #else 585 586 #define ehci_is_TDI(e) (0) 587 588 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 589 #endif 590 591 /*-------------------------------------------------------------------------*/ 592 593 #ifdef CONFIG_PPC_83xx 594 /* Some Freescale processors have an erratum in which the TT 595 * port number in the queue head was 0..N-1 instead of 1..N. 596 */ 597 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 598 #else 599 #define ehci_has_fsl_portno_bug(e) (0) 600 #endif 601 602 /* 603 * While most USB host controllers implement their registers in 604 * little-endian format, a minority (celleb companion chip) implement 605 * them in big endian format. 606 * 607 * This attempts to support either format at compile time without a 608 * runtime penalty, or both formats with the additional overhead 609 * of checking a flag bit. 610 * 611 * ehci_big_endian_capbase is a special quirk for controllers that 612 * implement the HC capability registers as separate registers and not 613 * as fields of a 32-bit register. 614 */ 615 616 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 617 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 618 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 619 #else 620 #define ehci_big_endian_mmio(e) 0 621 #define ehci_big_endian_capbase(e) 0 622 #endif 623 624 /* 625 * Big-endian read/write functions are arch-specific. 626 * Other arches can be added if/when they're needed. 627 */ 628 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 629 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 630 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 631 #endif 632 633 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 634 __u32 __iomem * regs) 635 { 636 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 637 return ehci_big_endian_mmio(ehci) ? 638 readl_be(regs) : 639 readl(regs); 640 #else 641 return readl(regs); 642 #endif 643 } 644 645 static inline void ehci_writel(const struct ehci_hcd *ehci, 646 const unsigned int val, __u32 __iomem *regs) 647 { 648 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 649 ehci_big_endian_mmio(ehci) ? 650 writel_be(val, regs) : 651 writel(val, regs); 652 #else 653 writel(val, regs); 654 #endif 655 } 656 657 /* 658 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 659 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 660 * Other common bits are dependent on has_amcc_usb23 quirk flag. 661 */ 662 #ifdef CONFIG_44x 663 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 664 { 665 u32 hc_control; 666 667 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 668 if (operational) 669 hc_control |= OHCI_USB_OPER; 670 else 671 hc_control |= OHCI_USB_SUSPEND; 672 673 writel_be(hc_control, ehci->ohci_hcctrl_reg); 674 (void) readl_be(ehci->ohci_hcctrl_reg); 675 } 676 #else 677 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 678 { } 679 #endif 680 681 /*-------------------------------------------------------------------------*/ 682 683 /* 684 * The AMCC 440EPx not only implements its EHCI registers in big-endian 685 * format, but also its DMA data structures (descriptors). 686 * 687 * EHCI controllers accessed through PCI work normally (little-endian 688 * everywhere), so we won't bother supporting a BE-only mode for now. 689 */ 690 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 691 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 692 693 /* cpu to ehci */ 694 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 695 { 696 return ehci_big_endian_desc(ehci) 697 ? (__force __hc32)cpu_to_be32(x) 698 : (__force __hc32)cpu_to_le32(x); 699 } 700 701 /* ehci to cpu */ 702 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 703 { 704 return ehci_big_endian_desc(ehci) 705 ? be32_to_cpu((__force __be32)x) 706 : le32_to_cpu((__force __le32)x); 707 } 708 709 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 710 { 711 return ehci_big_endian_desc(ehci) 712 ? be32_to_cpup((__force __be32 *)x) 713 : le32_to_cpup((__force __le32 *)x); 714 } 715 716 #else 717 718 /* cpu to ehci */ 719 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 720 { 721 return cpu_to_le32(x); 722 } 723 724 /* ehci to cpu */ 725 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 726 { 727 return le32_to_cpu(x); 728 } 729 730 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 731 { 732 return le32_to_cpup(x); 733 } 734 735 #endif 736 737 /*-------------------------------------------------------------------------*/ 738 739 #ifndef DEBUG 740 #define STUB_DEBUG_FILES 741 #endif /* DEBUG */ 742 743 /*-------------------------------------------------------------------------*/ 744 745 #endif /* __LINUX_EHCI_HCD_H */ 746