1 /* 2 * Device driver for Microgate SyncLink GT serial adapters. 3 * 4 * written by Paul Fulghum for Microgate Corporation 5 * paulkf@microgate.com 6 * 7 * Microgate and SyncLink are trademarks of Microgate Corporation 8 * 9 * This code is released under the GNU General Public License (GPL) 10 * 11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 21 * OF THE POSSIBILITY OF SUCH DAMAGE. 22 */ 23 24 /* 25 * DEBUG OUTPUT DEFINITIONS 26 * 27 * uncomment lines below to enable specific types of debug output 28 * 29 * DBGINFO information - most verbose output 30 * DBGERR serious errors 31 * DBGBH bottom half service routine debugging 32 * DBGISR interrupt service routine debugging 33 * DBGDATA output receive and transmit data 34 * DBGTBUF output transmit DMA buffers and registers 35 * DBGRBUF output receive DMA buffers and registers 36 */ 37 38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt 39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt 40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt 41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt 42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label)) 43 /*#define DBGTBUF(info) dump_tbufs(info)*/ 44 /*#define DBGRBUF(info) dump_rbufs(info)*/ 45 46 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/signal.h> 50 #include <linux/sched.h> 51 #include <linux/timer.h> 52 #include <linux/interrupt.h> 53 #include <linux/pci.h> 54 #include <linux/tty.h> 55 #include <linux/tty_flip.h> 56 #include <linux/serial.h> 57 #include <linux/major.h> 58 #include <linux/string.h> 59 #include <linux/fcntl.h> 60 #include <linux/ptrace.h> 61 #include <linux/ioport.h> 62 #include <linux/mm.h> 63 #include <linux/seq_file.h> 64 #include <linux/slab.h> 65 #include <linux/netdevice.h> 66 #include <linux/vmalloc.h> 67 #include <linux/init.h> 68 #include <linux/delay.h> 69 #include <linux/ioctl.h> 70 #include <linux/termios.h> 71 #include <linux/bitops.h> 72 #include <linux/workqueue.h> 73 #include <linux/hdlc.h> 74 #include <linux/synclink.h> 75 76 #include <asm/io.h> 77 #include <asm/irq.h> 78 #include <asm/dma.h> 79 #include <asm/types.h> 80 #include <asm/uaccess.h> 81 82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE)) 83 #define SYNCLINK_GENERIC_HDLC 1 84 #else 85 #define SYNCLINK_GENERIC_HDLC 0 86 #endif 87 88 /* 89 * module identification 90 */ 91 static char *driver_name = "SyncLink GT"; 92 static char *tty_driver_name = "synclink_gt"; 93 static char *tty_dev_prefix = "ttySLG"; 94 MODULE_LICENSE("GPL"); 95 #define MGSL_MAGIC 0x5401 96 #define MAX_DEVICES 32 97 98 static struct pci_device_id pci_table[] = { 99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,}, 103 {0,}, /* terminate list */ 104 }; 105 MODULE_DEVICE_TABLE(pci, pci_table); 106 107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent); 108 static void remove_one(struct pci_dev *dev); 109 static struct pci_driver pci_driver = { 110 .name = "synclink_gt", 111 .id_table = pci_table, 112 .probe = init_one, 113 .remove = remove_one, 114 }; 115 116 static bool pci_registered; 117 118 /* 119 * module configuration and status 120 */ 121 static struct slgt_info *slgt_device_list; 122 static int slgt_device_count; 123 124 static int ttymajor; 125 static int debug_level; 126 static int maxframe[MAX_DEVICES]; 127 128 module_param(ttymajor, int, 0); 129 module_param(debug_level, int, 0); 130 module_param_array(maxframe, int, NULL, 0); 131 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned"); 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail"); 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)"); 135 136 /* 137 * tty support and callbacks 138 */ 139 static struct tty_driver *serial_driver; 140 141 static int open(struct tty_struct *tty, struct file * filp); 142 static void close(struct tty_struct *tty, struct file * filp); 143 static void hangup(struct tty_struct *tty); 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); 145 146 static int write(struct tty_struct *tty, const unsigned char *buf, int count); 147 static int put_char(struct tty_struct *tty, unsigned char ch); 148 static void send_xchar(struct tty_struct *tty, char ch); 149 static void wait_until_sent(struct tty_struct *tty, int timeout); 150 static int write_room(struct tty_struct *tty); 151 static void flush_chars(struct tty_struct *tty); 152 static void flush_buffer(struct tty_struct *tty); 153 static void tx_hold(struct tty_struct *tty); 154 static void tx_release(struct tty_struct *tty); 155 156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); 157 static int chars_in_buffer(struct tty_struct *tty); 158 static void throttle(struct tty_struct * tty); 159 static void unthrottle(struct tty_struct * tty); 160 static int set_break(struct tty_struct *tty, int break_state); 161 162 /* 163 * generic HDLC support and callbacks 164 */ 165 #if SYNCLINK_GENERIC_HDLC 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv) 167 static void hdlcdev_tx_done(struct slgt_info *info); 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size); 169 static int hdlcdev_init(struct slgt_info *info); 170 static void hdlcdev_exit(struct slgt_info *info); 171 #endif 172 173 174 /* 175 * device specific structures, macros and functions 176 */ 177 178 #define SLGT_MAX_PORTS 4 179 #define SLGT_REG_SIZE 256 180 181 /* 182 * conditional wait facility 183 */ 184 struct cond_wait { 185 struct cond_wait *next; 186 wait_queue_head_t q; 187 wait_queue_t wait; 188 unsigned int data; 189 }; 190 static void init_cond_wait(struct cond_wait *w, unsigned int data); 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w); 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w); 193 static void flush_cond_wait(struct cond_wait **head); 194 195 /* 196 * DMA buffer descriptor and access macros 197 */ 198 struct slgt_desc 199 { 200 __le16 count; 201 __le16 status; 202 __le32 pbuf; /* physical address of data buffer */ 203 __le32 next; /* physical address of next descriptor */ 204 205 /* driver book keeping */ 206 char *buf; /* virtual address of data buffer */ 207 unsigned int pdesc; /* physical address of this descriptor */ 208 dma_addr_t buf_dma_addr; 209 unsigned short buf_count; 210 }; 211 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b)) 213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b)) 214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b)) 215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0)) 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b)) 217 #define desc_count(a) (le16_to_cpu((a).count)) 218 #define desc_status(a) (le16_to_cpu((a).status)) 219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15) 220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0) 223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3) 224 225 struct _input_signal_events { 226 int ri_up; 227 int ri_down; 228 int dsr_up; 229 int dsr_down; 230 int dcd_up; 231 int dcd_down; 232 int cts_up; 233 int cts_down; 234 }; 235 236 /* 237 * device instance data structure 238 */ 239 struct slgt_info { 240 void *if_ptr; /* General purpose pointer (used by SPPP) */ 241 struct tty_port port; 242 243 struct slgt_info *next_device; /* device list link */ 244 245 int magic; 246 247 char device_name[25]; 248 struct pci_dev *pdev; 249 250 int port_count; /* count of ports on adapter */ 251 int adapter_num; /* adapter instance number */ 252 int port_num; /* port instance number */ 253 254 /* array of pointers to port contexts on this adapter */ 255 struct slgt_info *port_array[SLGT_MAX_PORTS]; 256 257 int line; /* tty line instance number */ 258 259 struct mgsl_icount icount; 260 261 int timeout; 262 int x_char; /* xon/xoff character */ 263 unsigned int read_status_mask; 264 unsigned int ignore_status_mask; 265 266 wait_queue_head_t status_event_wait_q; 267 wait_queue_head_t event_wait_q; 268 struct timer_list tx_timer; 269 struct timer_list rx_timer; 270 271 unsigned int gpio_present; 272 struct cond_wait *gpio_wait_q; 273 274 spinlock_t lock; /* spinlock for synchronizing with ISR */ 275 276 struct work_struct task; 277 u32 pending_bh; 278 bool bh_requested; 279 bool bh_running; 280 281 int isr_overflow; 282 bool irq_requested; /* true if IRQ requested */ 283 bool irq_occurred; /* for diagnostics use */ 284 285 /* device configuration */ 286 287 unsigned int bus_type; 288 unsigned int irq_level; 289 unsigned long irq_flags; 290 291 unsigned char __iomem * reg_addr; /* memory mapped registers address */ 292 u32 phys_reg_addr; 293 bool reg_addr_requested; 294 295 MGSL_PARAMS params; /* communications parameters */ 296 u32 idle_mode; 297 u32 max_frame_size; /* as set by device config */ 298 299 unsigned int rbuf_fill_level; 300 unsigned int rx_pio; 301 unsigned int if_mode; 302 unsigned int base_clock; 303 unsigned int xsync; 304 unsigned int xctrl; 305 306 /* device status */ 307 308 bool rx_enabled; 309 bool rx_restart; 310 311 bool tx_enabled; 312 bool tx_active; 313 314 unsigned char signals; /* serial signal states */ 315 int init_error; /* initialization error */ 316 317 unsigned char *tx_buf; 318 int tx_count; 319 320 char *flag_buf; 321 bool drop_rts_on_tx_done; 322 struct _input_signal_events input_signal_events; 323 324 int dcd_chkcount; /* check counts to prevent */ 325 int cts_chkcount; /* too many IRQs if a signal */ 326 int dsr_chkcount; /* is floating */ 327 int ri_chkcount; 328 329 char *bufs; /* virtual address of DMA buffer lists */ 330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */ 331 332 unsigned int rbuf_count; 333 struct slgt_desc *rbufs; 334 unsigned int rbuf_current; 335 unsigned int rbuf_index; 336 unsigned int rbuf_fill_index; 337 unsigned short rbuf_fill_count; 338 339 unsigned int tbuf_count; 340 struct slgt_desc *tbufs; 341 unsigned int tbuf_current; 342 unsigned int tbuf_start; 343 344 unsigned char *tmp_rbuf; 345 unsigned int tmp_rbuf_count; 346 347 /* SPPP/Cisco HDLC device parts */ 348 349 int netcount; 350 spinlock_t netlock; 351 #if SYNCLINK_GENERIC_HDLC 352 struct net_device *netdev; 353 #endif 354 355 }; 356 357 static MGSL_PARAMS default_params = { 358 .mode = MGSL_MODE_HDLC, 359 .loopback = 0, 360 .flags = HDLC_FLAG_UNDERRUN_ABORT15, 361 .encoding = HDLC_ENCODING_NRZI_SPACE, 362 .clock_speed = 0, 363 .addr_filter = 0xff, 364 .crc_type = HDLC_CRC_16_CCITT, 365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS, 366 .preamble = HDLC_PREAMBLE_PATTERN_NONE, 367 .data_rate = 9600, 368 .data_bits = 8, 369 .stop_bits = 1, 370 .parity = ASYNC_PARITY_NONE 371 }; 372 373 374 #define BH_RECEIVE 1 375 #define BH_TRANSMIT 2 376 #define BH_STATUS 4 377 #define IO_PIN_SHUTDOWN_LIMIT 100 378 379 #define DMABUFSIZE 256 380 #define DESC_LIST_SIZE 4096 381 382 #define MASK_PARITY BIT1 383 #define MASK_FRAMING BIT0 384 #define MASK_BREAK BIT14 385 #define MASK_OVERRUN BIT4 386 387 #define GSR 0x00 /* global status */ 388 #define JCR 0x04 /* JTAG control */ 389 #define IODR 0x08 /* GPIO direction */ 390 #define IOER 0x0c /* GPIO interrupt enable */ 391 #define IOVR 0x10 /* GPIO value */ 392 #define IOSR 0x14 /* GPIO interrupt status */ 393 #define TDR 0x80 /* tx data */ 394 #define RDR 0x80 /* rx data */ 395 #define TCR 0x82 /* tx control */ 396 #define TIR 0x84 /* tx idle */ 397 #define TPR 0x85 /* tx preamble */ 398 #define RCR 0x86 /* rx control */ 399 #define VCR 0x88 /* V.24 control */ 400 #define CCR 0x89 /* clock control */ 401 #define BDR 0x8a /* baud divisor */ 402 #define SCR 0x8c /* serial control */ 403 #define SSR 0x8e /* serial status */ 404 #define RDCSR 0x90 /* rx DMA control/status */ 405 #define TDCSR 0x94 /* tx DMA control/status */ 406 #define RDDAR 0x98 /* rx DMA descriptor address */ 407 #define TDDAR 0x9c /* tx DMA descriptor address */ 408 #define XSR 0x40 /* extended sync pattern */ 409 #define XCR 0x44 /* extended control */ 410 411 #define RXIDLE BIT14 412 #define RXBREAK BIT14 413 #define IRQ_TXDATA BIT13 414 #define IRQ_TXIDLE BIT12 415 #define IRQ_TXUNDER BIT11 /* HDLC */ 416 #define IRQ_RXDATA BIT10 417 #define IRQ_RXIDLE BIT9 /* HDLC */ 418 #define IRQ_RXBREAK BIT9 /* async */ 419 #define IRQ_RXOVER BIT8 420 #define IRQ_DSR BIT7 421 #define IRQ_CTS BIT6 422 #define IRQ_DCD BIT5 423 #define IRQ_RI BIT4 424 #define IRQ_ALL 0x3ff0 425 #define IRQ_MASTER BIT0 426 427 #define slgt_irq_on(info, mask) \ 428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask))) 429 #define slgt_irq_off(info, mask) \ 430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask))) 431 432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr); 433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value); 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr); 435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value); 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr); 437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 438 439 static void msc_set_vcr(struct slgt_info *info); 440 441 static int startup(struct slgt_info *info); 442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info); 443 static void shutdown(struct slgt_info *info); 444 static void program_hw(struct slgt_info *info); 445 static void change_params(struct slgt_info *info); 446 447 static int register_test(struct slgt_info *info); 448 static int irq_test(struct slgt_info *info); 449 static int loopback_test(struct slgt_info *info); 450 static int adapter_test(struct slgt_info *info); 451 452 static void reset_adapter(struct slgt_info *info); 453 static void reset_port(struct slgt_info *info); 454 static void async_mode(struct slgt_info *info); 455 static void sync_mode(struct slgt_info *info); 456 457 static void rx_stop(struct slgt_info *info); 458 static void rx_start(struct slgt_info *info); 459 static void reset_rbufs(struct slgt_info *info); 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last); 461 static void rdma_reset(struct slgt_info *info); 462 static bool rx_get_frame(struct slgt_info *info); 463 static bool rx_get_buf(struct slgt_info *info); 464 465 static void tx_start(struct slgt_info *info); 466 static void tx_stop(struct slgt_info *info); 467 static void tx_set_idle(struct slgt_info *info); 468 static unsigned int free_tbuf_count(struct slgt_info *info); 469 static unsigned int tbuf_bytes(struct slgt_info *info); 470 static void reset_tbufs(struct slgt_info *info); 471 static void tdma_reset(struct slgt_info *info); 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count); 473 474 static void get_signals(struct slgt_info *info); 475 static void set_signals(struct slgt_info *info); 476 static void enable_loopback(struct slgt_info *info); 477 static void set_rate(struct slgt_info *info, u32 data_rate); 478 479 static int bh_action(struct slgt_info *info); 480 static void bh_handler(struct work_struct *work); 481 static void bh_transmit(struct slgt_info *info); 482 static void isr_serial(struct slgt_info *info); 483 static void isr_rdma(struct slgt_info *info); 484 static void isr_txeom(struct slgt_info *info, unsigned short status); 485 static void isr_tdma(struct slgt_info *info); 486 487 static int alloc_dma_bufs(struct slgt_info *info); 488 static void free_dma_bufs(struct slgt_info *info); 489 static int alloc_desc(struct slgt_info *info); 490 static void free_desc(struct slgt_info *info); 491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count); 493 494 static int alloc_tmp_rbuf(struct slgt_info *info); 495 static void free_tmp_rbuf(struct slgt_info *info); 496 497 static void tx_timeout(unsigned long context); 498 static void rx_timeout(unsigned long context); 499 500 /* 501 * ioctl handlers 502 */ 503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount); 504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params); 505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params); 506 static int get_txidle(struct slgt_info *info, int __user *idle_mode); 507 static int set_txidle(struct slgt_info *info, int idle_mode); 508 static int tx_enable(struct slgt_info *info, int enable); 509 static int tx_abort(struct slgt_info *info); 510 static int rx_enable(struct slgt_info *info, int enable); 511 static int modem_input_wait(struct slgt_info *info,int arg); 512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr); 513 static int tiocmget(struct tty_struct *tty); 514 static int tiocmset(struct tty_struct *tty, 515 unsigned int set, unsigned int clear); 516 static int set_break(struct tty_struct *tty, int break_state); 517 static int get_interface(struct slgt_info *info, int __user *if_mode); 518 static int set_interface(struct slgt_info *info, int if_mode); 519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio); 522 static int get_xsync(struct slgt_info *info, int __user *if_mode); 523 static int set_xsync(struct slgt_info *info, int if_mode); 524 static int get_xctrl(struct slgt_info *info, int __user *if_mode); 525 static int set_xctrl(struct slgt_info *info, int if_mode); 526 527 /* 528 * driver functions 529 */ 530 static void add_device(struct slgt_info *info); 531 static void device_init(int adapter_num, struct pci_dev *pdev); 532 static int claim_resources(struct slgt_info *info); 533 static void release_resources(struct slgt_info *info); 534 535 /* 536 * DEBUG OUTPUT CODE 537 */ 538 #ifndef DBGINFO 539 #define DBGINFO(fmt) 540 #endif 541 #ifndef DBGERR 542 #define DBGERR(fmt) 543 #endif 544 #ifndef DBGBH 545 #define DBGBH(fmt) 546 #endif 547 #ifndef DBGISR 548 #define DBGISR(fmt) 549 #endif 550 551 #ifdef DBGDATA 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label) 553 { 554 int i; 555 int linecount; 556 printk("%s %s data:\n",info->device_name, label); 557 while(count) { 558 linecount = (count > 16) ? 16 : count; 559 for(i=0; i < linecount; i++) 560 printk("%02X ",(unsigned char)data[i]); 561 for(;i<17;i++) 562 printk(" "); 563 for(i=0;i<linecount;i++) { 564 if (data[i]>=040 && data[i]<=0176) 565 printk("%c",data[i]); 566 else 567 printk("."); 568 } 569 printk("\n"); 570 data += linecount; 571 count -= linecount; 572 } 573 } 574 #else 575 #define DBGDATA(info, buf, size, label) 576 #endif 577 578 #ifdef DBGTBUF 579 static void dump_tbufs(struct slgt_info *info) 580 { 581 int i; 582 printk("tbuf_current=%d\n", info->tbuf_current); 583 for (i=0 ; i < info->tbuf_count ; i++) { 584 printk("%d: count=%04X status=%04X\n", 585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status)); 586 } 587 } 588 #else 589 #define DBGTBUF(info) 590 #endif 591 592 #ifdef DBGRBUF 593 static void dump_rbufs(struct slgt_info *info) 594 { 595 int i; 596 printk("rbuf_current=%d\n", info->rbuf_current); 597 for (i=0 ; i < info->rbuf_count ; i++) { 598 printk("%d: count=%04X status=%04X\n", 599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status)); 600 } 601 } 602 #else 603 #define DBGRBUF(info) 604 #endif 605 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name) 607 { 608 #ifdef SANITY_CHECK 609 if (!info) { 610 printk("null struct slgt_info for (%s) in %s\n", devname, name); 611 return 1; 612 } 613 if (info->magic != MGSL_MAGIC) { 614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name); 615 return 1; 616 } 617 #else 618 if (!info) 619 return 1; 620 #endif 621 return 0; 622 } 623 624 /** 625 * line discipline callback wrappers 626 * 627 * The wrappers maintain line discipline references 628 * while calling into the line discipline. 629 * 630 * ldisc_receive_buf - pass receive data to line discipline 631 */ 632 static void ldisc_receive_buf(struct tty_struct *tty, 633 const __u8 *data, char *flags, int count) 634 { 635 struct tty_ldisc *ld; 636 if (!tty) 637 return; 638 ld = tty_ldisc_ref(tty); 639 if (ld) { 640 if (ld->ops->receive_buf) 641 ld->ops->receive_buf(tty, data, flags, count); 642 tty_ldisc_deref(ld); 643 } 644 } 645 646 /* tty callbacks */ 647 648 static int open(struct tty_struct *tty, struct file *filp) 649 { 650 struct slgt_info *info; 651 int retval, line; 652 unsigned long flags; 653 654 line = tty->index; 655 if (line >= slgt_device_count) { 656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line)); 657 return -ENODEV; 658 } 659 660 info = slgt_device_list; 661 while(info && info->line != line) 662 info = info->next_device; 663 if (sanity_check(info, tty->name, "open")) 664 return -ENODEV; 665 if (info->init_error) { 666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error)); 667 return -ENODEV; 668 } 669 670 tty->driver_data = info; 671 info->port.tty = tty; 672 673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count)); 674 675 /* If port is closing, signal caller to try again */ 676 if (info->port.flags & ASYNC_CLOSING){ 677 wait_event_interruptible_tty(tty, info->port.close_wait, 678 !(info->port.flags & ASYNC_CLOSING)); 679 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ? 680 -EAGAIN : -ERESTARTSYS); 681 goto cleanup; 682 } 683 684 mutex_lock(&info->port.mutex); 685 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; 686 687 spin_lock_irqsave(&info->netlock, flags); 688 if (info->netcount) { 689 retval = -EBUSY; 690 spin_unlock_irqrestore(&info->netlock, flags); 691 mutex_unlock(&info->port.mutex); 692 goto cleanup; 693 } 694 info->port.count++; 695 spin_unlock_irqrestore(&info->netlock, flags); 696 697 if (info->port.count == 1) { 698 /* 1st open on this device, init hardware */ 699 retval = startup(info); 700 if (retval < 0) { 701 mutex_unlock(&info->port.mutex); 702 goto cleanup; 703 } 704 } 705 mutex_unlock(&info->port.mutex); 706 retval = block_til_ready(tty, filp, info); 707 if (retval) { 708 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval)); 709 goto cleanup; 710 } 711 712 retval = 0; 713 714 cleanup: 715 if (retval) { 716 if (tty->count == 1) 717 info->port.tty = NULL; /* tty layer will release tty struct */ 718 if(info->port.count) 719 info->port.count--; 720 } 721 722 DBGINFO(("%s open rc=%d\n", info->device_name, retval)); 723 return retval; 724 } 725 726 static void close(struct tty_struct *tty, struct file *filp) 727 { 728 struct slgt_info *info = tty->driver_data; 729 730 if (sanity_check(info, tty->name, "close")) 731 return; 732 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count)); 733 734 if (tty_port_close_start(&info->port, tty, filp) == 0) 735 goto cleanup; 736 737 mutex_lock(&info->port.mutex); 738 if (info->port.flags & ASYNC_INITIALIZED) 739 wait_until_sent(tty, info->timeout); 740 flush_buffer(tty); 741 tty_ldisc_flush(tty); 742 743 shutdown(info); 744 mutex_unlock(&info->port.mutex); 745 746 tty_port_close_end(&info->port, tty); 747 info->port.tty = NULL; 748 cleanup: 749 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count)); 750 } 751 752 static void hangup(struct tty_struct *tty) 753 { 754 struct slgt_info *info = tty->driver_data; 755 unsigned long flags; 756 757 if (sanity_check(info, tty->name, "hangup")) 758 return; 759 DBGINFO(("%s hangup\n", info->device_name)); 760 761 flush_buffer(tty); 762 763 mutex_lock(&info->port.mutex); 764 shutdown(info); 765 766 spin_lock_irqsave(&info->port.lock, flags); 767 info->port.count = 0; 768 info->port.flags &= ~ASYNC_NORMAL_ACTIVE; 769 info->port.tty = NULL; 770 spin_unlock_irqrestore(&info->port.lock, flags); 771 mutex_unlock(&info->port.mutex); 772 773 wake_up_interruptible(&info->port.open_wait); 774 } 775 776 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) 777 { 778 struct slgt_info *info = tty->driver_data; 779 unsigned long flags; 780 781 DBGINFO(("%s set_termios\n", tty->driver->name)); 782 783 change_params(info); 784 785 /* Handle transition to B0 status */ 786 if (old_termios->c_cflag & CBAUD && 787 !(tty->termios.c_cflag & CBAUD)) { 788 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 789 spin_lock_irqsave(&info->lock,flags); 790 set_signals(info); 791 spin_unlock_irqrestore(&info->lock,flags); 792 } 793 794 /* Handle transition away from B0 status */ 795 if (!(old_termios->c_cflag & CBAUD) && 796 tty->termios.c_cflag & CBAUD) { 797 info->signals |= SerialSignal_DTR; 798 if (!(tty->termios.c_cflag & CRTSCTS) || 799 !test_bit(TTY_THROTTLED, &tty->flags)) { 800 info->signals |= SerialSignal_RTS; 801 } 802 spin_lock_irqsave(&info->lock,flags); 803 set_signals(info); 804 spin_unlock_irqrestore(&info->lock,flags); 805 } 806 807 /* Handle turning off CRTSCTS */ 808 if (old_termios->c_cflag & CRTSCTS && 809 !(tty->termios.c_cflag & CRTSCTS)) { 810 tty->hw_stopped = 0; 811 tx_release(tty); 812 } 813 } 814 815 static void update_tx_timer(struct slgt_info *info) 816 { 817 /* 818 * use worst case speed of 1200bps to calculate transmit timeout 819 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes) 820 */ 821 if (info->params.mode == MGSL_MODE_HDLC) { 822 int timeout = (tbuf_bytes(info) * 7) + 1000; 823 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout)); 824 } 825 } 826 827 static int write(struct tty_struct *tty, 828 const unsigned char *buf, int count) 829 { 830 int ret = 0; 831 struct slgt_info *info = tty->driver_data; 832 unsigned long flags; 833 834 if (sanity_check(info, tty->name, "write")) 835 return -EIO; 836 837 DBGINFO(("%s write count=%d\n", info->device_name, count)); 838 839 if (!info->tx_buf || (count > info->max_frame_size)) 840 return -EIO; 841 842 if (!count || tty->stopped || tty->hw_stopped) 843 return 0; 844 845 spin_lock_irqsave(&info->lock, flags); 846 847 if (info->tx_count) { 848 /* send accumulated data from send_char() */ 849 if (!tx_load(info, info->tx_buf, info->tx_count)) 850 goto cleanup; 851 info->tx_count = 0; 852 } 853 854 if (tx_load(info, buf, count)) 855 ret = count; 856 857 cleanup: 858 spin_unlock_irqrestore(&info->lock, flags); 859 DBGINFO(("%s write rc=%d\n", info->device_name, ret)); 860 return ret; 861 } 862 863 static int put_char(struct tty_struct *tty, unsigned char ch) 864 { 865 struct slgt_info *info = tty->driver_data; 866 unsigned long flags; 867 int ret = 0; 868 869 if (sanity_check(info, tty->name, "put_char")) 870 return 0; 871 DBGINFO(("%s put_char(%d)\n", info->device_name, ch)); 872 if (!info->tx_buf) 873 return 0; 874 spin_lock_irqsave(&info->lock,flags); 875 if (info->tx_count < info->max_frame_size) { 876 info->tx_buf[info->tx_count++] = ch; 877 ret = 1; 878 } 879 spin_unlock_irqrestore(&info->lock,flags); 880 return ret; 881 } 882 883 static void send_xchar(struct tty_struct *tty, char ch) 884 { 885 struct slgt_info *info = tty->driver_data; 886 unsigned long flags; 887 888 if (sanity_check(info, tty->name, "send_xchar")) 889 return; 890 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch)); 891 info->x_char = ch; 892 if (ch) { 893 spin_lock_irqsave(&info->lock,flags); 894 if (!info->tx_enabled) 895 tx_start(info); 896 spin_unlock_irqrestore(&info->lock,flags); 897 } 898 } 899 900 static void wait_until_sent(struct tty_struct *tty, int timeout) 901 { 902 struct slgt_info *info = tty->driver_data; 903 unsigned long orig_jiffies, char_time; 904 905 if (!info ) 906 return; 907 if (sanity_check(info, tty->name, "wait_until_sent")) 908 return; 909 DBGINFO(("%s wait_until_sent entry\n", info->device_name)); 910 if (!(info->port.flags & ASYNC_INITIALIZED)) 911 goto exit; 912 913 orig_jiffies = jiffies; 914 915 /* Set check interval to 1/5 of estimated time to 916 * send a character, and make it at least 1. The check 917 * interval should also be less than the timeout. 918 * Note: use tight timings here to satisfy the NIST-PCTS. 919 */ 920 921 if (info->params.data_rate) { 922 char_time = info->timeout/(32 * 5); 923 if (!char_time) 924 char_time++; 925 } else 926 char_time = 1; 927 928 if (timeout) 929 char_time = min_t(unsigned long, char_time, timeout); 930 931 while (info->tx_active) { 932 msleep_interruptible(jiffies_to_msecs(char_time)); 933 if (signal_pending(current)) 934 break; 935 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 936 break; 937 } 938 exit: 939 DBGINFO(("%s wait_until_sent exit\n", info->device_name)); 940 } 941 942 static int write_room(struct tty_struct *tty) 943 { 944 struct slgt_info *info = tty->driver_data; 945 int ret; 946 947 if (sanity_check(info, tty->name, "write_room")) 948 return 0; 949 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; 950 DBGINFO(("%s write_room=%d\n", info->device_name, ret)); 951 return ret; 952 } 953 954 static void flush_chars(struct tty_struct *tty) 955 { 956 struct slgt_info *info = tty->driver_data; 957 unsigned long flags; 958 959 if (sanity_check(info, tty->name, "flush_chars")) 960 return; 961 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count)); 962 963 if (info->tx_count <= 0 || tty->stopped || 964 tty->hw_stopped || !info->tx_buf) 965 return; 966 967 DBGINFO(("%s flush_chars start transmit\n", info->device_name)); 968 969 spin_lock_irqsave(&info->lock,flags); 970 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 971 info->tx_count = 0; 972 spin_unlock_irqrestore(&info->lock,flags); 973 } 974 975 static void flush_buffer(struct tty_struct *tty) 976 { 977 struct slgt_info *info = tty->driver_data; 978 unsigned long flags; 979 980 if (sanity_check(info, tty->name, "flush_buffer")) 981 return; 982 DBGINFO(("%s flush_buffer\n", info->device_name)); 983 984 spin_lock_irqsave(&info->lock, flags); 985 info->tx_count = 0; 986 spin_unlock_irqrestore(&info->lock, flags); 987 988 tty_wakeup(tty); 989 } 990 991 /* 992 * throttle (stop) transmitter 993 */ 994 static void tx_hold(struct tty_struct *tty) 995 { 996 struct slgt_info *info = tty->driver_data; 997 unsigned long flags; 998 999 if (sanity_check(info, tty->name, "tx_hold")) 1000 return; 1001 DBGINFO(("%s tx_hold\n", info->device_name)); 1002 spin_lock_irqsave(&info->lock,flags); 1003 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC) 1004 tx_stop(info); 1005 spin_unlock_irqrestore(&info->lock,flags); 1006 } 1007 1008 /* 1009 * release (start) transmitter 1010 */ 1011 static void tx_release(struct tty_struct *tty) 1012 { 1013 struct slgt_info *info = tty->driver_data; 1014 unsigned long flags; 1015 1016 if (sanity_check(info, tty->name, "tx_release")) 1017 return; 1018 DBGINFO(("%s tx_release\n", info->device_name)); 1019 spin_lock_irqsave(&info->lock, flags); 1020 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count)) 1021 info->tx_count = 0; 1022 spin_unlock_irqrestore(&info->lock, flags); 1023 } 1024 1025 /* 1026 * Service an IOCTL request 1027 * 1028 * Arguments 1029 * 1030 * tty pointer to tty instance data 1031 * cmd IOCTL command code 1032 * arg command argument/context 1033 * 1034 * Return 0 if success, otherwise error code 1035 */ 1036 static int ioctl(struct tty_struct *tty, 1037 unsigned int cmd, unsigned long arg) 1038 { 1039 struct slgt_info *info = tty->driver_data; 1040 void __user *argp = (void __user *)arg; 1041 int ret; 1042 1043 if (sanity_check(info, tty->name, "ioctl")) 1044 return -ENODEV; 1045 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd)); 1046 1047 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && 1048 (cmd != TIOCMIWAIT)) { 1049 if (tty->flags & (1 << TTY_IO_ERROR)) 1050 return -EIO; 1051 } 1052 1053 switch (cmd) { 1054 case MGSL_IOCWAITEVENT: 1055 return wait_mgsl_event(info, argp); 1056 case TIOCMIWAIT: 1057 return modem_input_wait(info,(int)arg); 1058 case MGSL_IOCSGPIO: 1059 return set_gpio(info, argp); 1060 case MGSL_IOCGGPIO: 1061 return get_gpio(info, argp); 1062 case MGSL_IOCWAITGPIO: 1063 return wait_gpio(info, argp); 1064 case MGSL_IOCGXSYNC: 1065 return get_xsync(info, argp); 1066 case MGSL_IOCSXSYNC: 1067 return set_xsync(info, (int)arg); 1068 case MGSL_IOCGXCTRL: 1069 return get_xctrl(info, argp); 1070 case MGSL_IOCSXCTRL: 1071 return set_xctrl(info, (int)arg); 1072 } 1073 mutex_lock(&info->port.mutex); 1074 switch (cmd) { 1075 case MGSL_IOCGPARAMS: 1076 ret = get_params(info, argp); 1077 break; 1078 case MGSL_IOCSPARAMS: 1079 ret = set_params(info, argp); 1080 break; 1081 case MGSL_IOCGTXIDLE: 1082 ret = get_txidle(info, argp); 1083 break; 1084 case MGSL_IOCSTXIDLE: 1085 ret = set_txidle(info, (int)arg); 1086 break; 1087 case MGSL_IOCTXENABLE: 1088 ret = tx_enable(info, (int)arg); 1089 break; 1090 case MGSL_IOCRXENABLE: 1091 ret = rx_enable(info, (int)arg); 1092 break; 1093 case MGSL_IOCTXABORT: 1094 ret = tx_abort(info); 1095 break; 1096 case MGSL_IOCGSTATS: 1097 ret = get_stats(info, argp); 1098 break; 1099 case MGSL_IOCGIF: 1100 ret = get_interface(info, argp); 1101 break; 1102 case MGSL_IOCSIF: 1103 ret = set_interface(info,(int)arg); 1104 break; 1105 default: 1106 ret = -ENOIOCTLCMD; 1107 } 1108 mutex_unlock(&info->port.mutex); 1109 return ret; 1110 } 1111 1112 static int get_icount(struct tty_struct *tty, 1113 struct serial_icounter_struct *icount) 1114 1115 { 1116 struct slgt_info *info = tty->driver_data; 1117 struct mgsl_icount cnow; /* kernel counter temps */ 1118 unsigned long flags; 1119 1120 spin_lock_irqsave(&info->lock,flags); 1121 cnow = info->icount; 1122 spin_unlock_irqrestore(&info->lock,flags); 1123 1124 icount->cts = cnow.cts; 1125 icount->dsr = cnow.dsr; 1126 icount->rng = cnow.rng; 1127 icount->dcd = cnow.dcd; 1128 icount->rx = cnow.rx; 1129 icount->tx = cnow.tx; 1130 icount->frame = cnow.frame; 1131 icount->overrun = cnow.overrun; 1132 icount->parity = cnow.parity; 1133 icount->brk = cnow.brk; 1134 icount->buf_overrun = cnow.buf_overrun; 1135 1136 return 0; 1137 } 1138 1139 /* 1140 * support for 32 bit ioctl calls on 64 bit systems 1141 */ 1142 #ifdef CONFIG_COMPAT 1143 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params) 1144 { 1145 struct MGSL_PARAMS32 tmp_params; 1146 1147 DBGINFO(("%s get_params32\n", info->device_name)); 1148 memset(&tmp_params, 0, sizeof(tmp_params)); 1149 tmp_params.mode = (compat_ulong_t)info->params.mode; 1150 tmp_params.loopback = info->params.loopback; 1151 tmp_params.flags = info->params.flags; 1152 tmp_params.encoding = info->params.encoding; 1153 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed; 1154 tmp_params.addr_filter = info->params.addr_filter; 1155 tmp_params.crc_type = info->params.crc_type; 1156 tmp_params.preamble_length = info->params.preamble_length; 1157 tmp_params.preamble = info->params.preamble; 1158 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate; 1159 tmp_params.data_bits = info->params.data_bits; 1160 tmp_params.stop_bits = info->params.stop_bits; 1161 tmp_params.parity = info->params.parity; 1162 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32))) 1163 return -EFAULT; 1164 return 0; 1165 } 1166 1167 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params) 1168 { 1169 struct MGSL_PARAMS32 tmp_params; 1170 1171 DBGINFO(("%s set_params32\n", info->device_name)); 1172 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32))) 1173 return -EFAULT; 1174 1175 spin_lock(&info->lock); 1176 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) { 1177 info->base_clock = tmp_params.clock_speed; 1178 } else { 1179 info->params.mode = tmp_params.mode; 1180 info->params.loopback = tmp_params.loopback; 1181 info->params.flags = tmp_params.flags; 1182 info->params.encoding = tmp_params.encoding; 1183 info->params.clock_speed = tmp_params.clock_speed; 1184 info->params.addr_filter = tmp_params.addr_filter; 1185 info->params.crc_type = tmp_params.crc_type; 1186 info->params.preamble_length = tmp_params.preamble_length; 1187 info->params.preamble = tmp_params.preamble; 1188 info->params.data_rate = tmp_params.data_rate; 1189 info->params.data_bits = tmp_params.data_bits; 1190 info->params.stop_bits = tmp_params.stop_bits; 1191 info->params.parity = tmp_params.parity; 1192 } 1193 spin_unlock(&info->lock); 1194 1195 program_hw(info); 1196 1197 return 0; 1198 } 1199 1200 static long slgt_compat_ioctl(struct tty_struct *tty, 1201 unsigned int cmd, unsigned long arg) 1202 { 1203 struct slgt_info *info = tty->driver_data; 1204 int rc = -ENOIOCTLCMD; 1205 1206 if (sanity_check(info, tty->name, "compat_ioctl")) 1207 return -ENODEV; 1208 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd)); 1209 1210 switch (cmd) { 1211 1212 case MGSL_IOCSPARAMS32: 1213 rc = set_params32(info, compat_ptr(arg)); 1214 break; 1215 1216 case MGSL_IOCGPARAMS32: 1217 rc = get_params32(info, compat_ptr(arg)); 1218 break; 1219 1220 case MGSL_IOCGPARAMS: 1221 case MGSL_IOCSPARAMS: 1222 case MGSL_IOCGTXIDLE: 1223 case MGSL_IOCGSTATS: 1224 case MGSL_IOCWAITEVENT: 1225 case MGSL_IOCGIF: 1226 case MGSL_IOCSGPIO: 1227 case MGSL_IOCGGPIO: 1228 case MGSL_IOCWAITGPIO: 1229 case MGSL_IOCGXSYNC: 1230 case MGSL_IOCGXCTRL: 1231 case MGSL_IOCSTXIDLE: 1232 case MGSL_IOCTXENABLE: 1233 case MGSL_IOCRXENABLE: 1234 case MGSL_IOCTXABORT: 1235 case TIOCMIWAIT: 1236 case MGSL_IOCSIF: 1237 case MGSL_IOCSXSYNC: 1238 case MGSL_IOCSXCTRL: 1239 rc = ioctl(tty, cmd, arg); 1240 break; 1241 } 1242 1243 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc)); 1244 return rc; 1245 } 1246 #else 1247 #define slgt_compat_ioctl NULL 1248 #endif /* ifdef CONFIG_COMPAT */ 1249 1250 /* 1251 * proc fs support 1252 */ 1253 static inline void line_info(struct seq_file *m, struct slgt_info *info) 1254 { 1255 char stat_buf[30]; 1256 unsigned long flags; 1257 1258 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n", 1259 info->device_name, info->phys_reg_addr, 1260 info->irq_level, info->max_frame_size); 1261 1262 /* output current serial signal states */ 1263 spin_lock_irqsave(&info->lock,flags); 1264 get_signals(info); 1265 spin_unlock_irqrestore(&info->lock,flags); 1266 1267 stat_buf[0] = 0; 1268 stat_buf[1] = 0; 1269 if (info->signals & SerialSignal_RTS) 1270 strcat(stat_buf, "|RTS"); 1271 if (info->signals & SerialSignal_CTS) 1272 strcat(stat_buf, "|CTS"); 1273 if (info->signals & SerialSignal_DTR) 1274 strcat(stat_buf, "|DTR"); 1275 if (info->signals & SerialSignal_DSR) 1276 strcat(stat_buf, "|DSR"); 1277 if (info->signals & SerialSignal_DCD) 1278 strcat(stat_buf, "|CD"); 1279 if (info->signals & SerialSignal_RI) 1280 strcat(stat_buf, "|RI"); 1281 1282 if (info->params.mode != MGSL_MODE_ASYNC) { 1283 seq_printf(m, "\tHDLC txok:%d rxok:%d", 1284 info->icount.txok, info->icount.rxok); 1285 if (info->icount.txunder) 1286 seq_printf(m, " txunder:%d", info->icount.txunder); 1287 if (info->icount.txabort) 1288 seq_printf(m, " txabort:%d", info->icount.txabort); 1289 if (info->icount.rxshort) 1290 seq_printf(m, " rxshort:%d", info->icount.rxshort); 1291 if (info->icount.rxlong) 1292 seq_printf(m, " rxlong:%d", info->icount.rxlong); 1293 if (info->icount.rxover) 1294 seq_printf(m, " rxover:%d", info->icount.rxover); 1295 if (info->icount.rxcrc) 1296 seq_printf(m, " rxcrc:%d", info->icount.rxcrc); 1297 } else { 1298 seq_printf(m, "\tASYNC tx:%d rx:%d", 1299 info->icount.tx, info->icount.rx); 1300 if (info->icount.frame) 1301 seq_printf(m, " fe:%d", info->icount.frame); 1302 if (info->icount.parity) 1303 seq_printf(m, " pe:%d", info->icount.parity); 1304 if (info->icount.brk) 1305 seq_printf(m, " brk:%d", info->icount.brk); 1306 if (info->icount.overrun) 1307 seq_printf(m, " oe:%d", info->icount.overrun); 1308 } 1309 1310 /* Append serial signal status to end */ 1311 seq_printf(m, " %s\n", stat_buf+1); 1312 1313 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", 1314 info->tx_active,info->bh_requested,info->bh_running, 1315 info->pending_bh); 1316 } 1317 1318 /* Called to print information about devices 1319 */ 1320 static int synclink_gt_proc_show(struct seq_file *m, void *v) 1321 { 1322 struct slgt_info *info; 1323 1324 seq_puts(m, "synclink_gt driver\n"); 1325 1326 info = slgt_device_list; 1327 while( info ) { 1328 line_info(m, info); 1329 info = info->next_device; 1330 } 1331 return 0; 1332 } 1333 1334 static int synclink_gt_proc_open(struct inode *inode, struct file *file) 1335 { 1336 return single_open(file, synclink_gt_proc_show, NULL); 1337 } 1338 1339 static const struct file_operations synclink_gt_proc_fops = { 1340 .owner = THIS_MODULE, 1341 .open = synclink_gt_proc_open, 1342 .read = seq_read, 1343 .llseek = seq_lseek, 1344 .release = single_release, 1345 }; 1346 1347 /* 1348 * return count of bytes in transmit buffer 1349 */ 1350 static int chars_in_buffer(struct tty_struct *tty) 1351 { 1352 struct slgt_info *info = tty->driver_data; 1353 int count; 1354 if (sanity_check(info, tty->name, "chars_in_buffer")) 1355 return 0; 1356 count = tbuf_bytes(info); 1357 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count)); 1358 return count; 1359 } 1360 1361 /* 1362 * signal remote device to throttle send data (our receive data) 1363 */ 1364 static void throttle(struct tty_struct * tty) 1365 { 1366 struct slgt_info *info = tty->driver_data; 1367 unsigned long flags; 1368 1369 if (sanity_check(info, tty->name, "throttle")) 1370 return; 1371 DBGINFO(("%s throttle\n", info->device_name)); 1372 if (I_IXOFF(tty)) 1373 send_xchar(tty, STOP_CHAR(tty)); 1374 if (tty->termios.c_cflag & CRTSCTS) { 1375 spin_lock_irqsave(&info->lock,flags); 1376 info->signals &= ~SerialSignal_RTS; 1377 set_signals(info); 1378 spin_unlock_irqrestore(&info->lock,flags); 1379 } 1380 } 1381 1382 /* 1383 * signal remote device to stop throttling send data (our receive data) 1384 */ 1385 static void unthrottle(struct tty_struct * tty) 1386 { 1387 struct slgt_info *info = tty->driver_data; 1388 unsigned long flags; 1389 1390 if (sanity_check(info, tty->name, "unthrottle")) 1391 return; 1392 DBGINFO(("%s unthrottle\n", info->device_name)); 1393 if (I_IXOFF(tty)) { 1394 if (info->x_char) 1395 info->x_char = 0; 1396 else 1397 send_xchar(tty, START_CHAR(tty)); 1398 } 1399 if (tty->termios.c_cflag & CRTSCTS) { 1400 spin_lock_irqsave(&info->lock,flags); 1401 info->signals |= SerialSignal_RTS; 1402 set_signals(info); 1403 spin_unlock_irqrestore(&info->lock,flags); 1404 } 1405 } 1406 1407 /* 1408 * set or clear transmit break condition 1409 * break_state -1=set break condition, 0=clear 1410 */ 1411 static int set_break(struct tty_struct *tty, int break_state) 1412 { 1413 struct slgt_info *info = tty->driver_data; 1414 unsigned short value; 1415 unsigned long flags; 1416 1417 if (sanity_check(info, tty->name, "set_break")) 1418 return -EINVAL; 1419 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state)); 1420 1421 spin_lock_irqsave(&info->lock,flags); 1422 value = rd_reg16(info, TCR); 1423 if (break_state == -1) 1424 value |= BIT6; 1425 else 1426 value &= ~BIT6; 1427 wr_reg16(info, TCR, value); 1428 spin_unlock_irqrestore(&info->lock,flags); 1429 return 0; 1430 } 1431 1432 #if SYNCLINK_GENERIC_HDLC 1433 1434 /** 1435 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) 1436 * set encoding and frame check sequence (FCS) options 1437 * 1438 * dev pointer to network device structure 1439 * encoding serial encoding setting 1440 * parity FCS setting 1441 * 1442 * returns 0 if success, otherwise error code 1443 */ 1444 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, 1445 unsigned short parity) 1446 { 1447 struct slgt_info *info = dev_to_port(dev); 1448 unsigned char new_encoding; 1449 unsigned short new_crctype; 1450 1451 /* return error if TTY interface open */ 1452 if (info->port.count) 1453 return -EBUSY; 1454 1455 DBGINFO(("%s hdlcdev_attach\n", info->device_name)); 1456 1457 switch (encoding) 1458 { 1459 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; 1460 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; 1461 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; 1462 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; 1463 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; 1464 default: return -EINVAL; 1465 } 1466 1467 switch (parity) 1468 { 1469 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; 1470 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; 1471 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; 1472 default: return -EINVAL; 1473 } 1474 1475 info->params.encoding = new_encoding; 1476 info->params.crc_type = new_crctype; 1477 1478 /* if network interface up, reprogram hardware */ 1479 if (info->netcount) 1480 program_hw(info); 1481 1482 return 0; 1483 } 1484 1485 /** 1486 * called by generic HDLC layer to send frame 1487 * 1488 * skb socket buffer containing HDLC frame 1489 * dev pointer to network device structure 1490 */ 1491 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, 1492 struct net_device *dev) 1493 { 1494 struct slgt_info *info = dev_to_port(dev); 1495 unsigned long flags; 1496 1497 DBGINFO(("%s hdlc_xmit\n", dev->name)); 1498 1499 if (!skb->len) 1500 return NETDEV_TX_OK; 1501 1502 /* stop sending until this frame completes */ 1503 netif_stop_queue(dev); 1504 1505 /* update network statistics */ 1506 dev->stats.tx_packets++; 1507 dev->stats.tx_bytes += skb->len; 1508 1509 /* save start time for transmit timeout detection */ 1510 dev->trans_start = jiffies; 1511 1512 spin_lock_irqsave(&info->lock, flags); 1513 tx_load(info, skb->data, skb->len); 1514 spin_unlock_irqrestore(&info->lock, flags); 1515 1516 /* done with socket buffer, so free it */ 1517 dev_kfree_skb(skb); 1518 1519 return NETDEV_TX_OK; 1520 } 1521 1522 /** 1523 * called by network layer when interface enabled 1524 * claim resources and initialize hardware 1525 * 1526 * dev pointer to network device structure 1527 * 1528 * returns 0 if success, otherwise error code 1529 */ 1530 static int hdlcdev_open(struct net_device *dev) 1531 { 1532 struct slgt_info *info = dev_to_port(dev); 1533 int rc; 1534 unsigned long flags; 1535 1536 if (!try_module_get(THIS_MODULE)) 1537 return -EBUSY; 1538 1539 DBGINFO(("%s hdlcdev_open\n", dev->name)); 1540 1541 /* generic HDLC layer open processing */ 1542 rc = hdlc_open(dev); 1543 if (rc) 1544 return rc; 1545 1546 /* arbitrate between network and tty opens */ 1547 spin_lock_irqsave(&info->netlock, flags); 1548 if (info->port.count != 0 || info->netcount != 0) { 1549 DBGINFO(("%s hdlc_open busy\n", dev->name)); 1550 spin_unlock_irqrestore(&info->netlock, flags); 1551 return -EBUSY; 1552 } 1553 info->netcount=1; 1554 spin_unlock_irqrestore(&info->netlock, flags); 1555 1556 /* claim resources and init adapter */ 1557 if ((rc = startup(info)) != 0) { 1558 spin_lock_irqsave(&info->netlock, flags); 1559 info->netcount=0; 1560 spin_unlock_irqrestore(&info->netlock, flags); 1561 return rc; 1562 } 1563 1564 /* assert RTS and DTR, apply hardware settings */ 1565 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 1566 program_hw(info); 1567 1568 /* enable network layer transmit */ 1569 dev->trans_start = jiffies; 1570 netif_start_queue(dev); 1571 1572 /* inform generic HDLC layer of current DCD status */ 1573 spin_lock_irqsave(&info->lock, flags); 1574 get_signals(info); 1575 spin_unlock_irqrestore(&info->lock, flags); 1576 if (info->signals & SerialSignal_DCD) 1577 netif_carrier_on(dev); 1578 else 1579 netif_carrier_off(dev); 1580 return 0; 1581 } 1582 1583 /** 1584 * called by network layer when interface is disabled 1585 * shutdown hardware and release resources 1586 * 1587 * dev pointer to network device structure 1588 * 1589 * returns 0 if success, otherwise error code 1590 */ 1591 static int hdlcdev_close(struct net_device *dev) 1592 { 1593 struct slgt_info *info = dev_to_port(dev); 1594 unsigned long flags; 1595 1596 DBGINFO(("%s hdlcdev_close\n", dev->name)); 1597 1598 netif_stop_queue(dev); 1599 1600 /* shutdown adapter and release resources */ 1601 shutdown(info); 1602 1603 hdlc_close(dev); 1604 1605 spin_lock_irqsave(&info->netlock, flags); 1606 info->netcount=0; 1607 spin_unlock_irqrestore(&info->netlock, flags); 1608 1609 module_put(THIS_MODULE); 1610 return 0; 1611 } 1612 1613 /** 1614 * called by network layer to process IOCTL call to network device 1615 * 1616 * dev pointer to network device structure 1617 * ifr pointer to network interface request structure 1618 * cmd IOCTL command code 1619 * 1620 * returns 0 if success, otherwise error code 1621 */ 1622 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1623 { 1624 const size_t size = sizeof(sync_serial_settings); 1625 sync_serial_settings new_line; 1626 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; 1627 struct slgt_info *info = dev_to_port(dev); 1628 unsigned int flags; 1629 1630 DBGINFO(("%s hdlcdev_ioctl\n", dev->name)); 1631 1632 /* return error if TTY interface open */ 1633 if (info->port.count) 1634 return -EBUSY; 1635 1636 if (cmd != SIOCWANDEV) 1637 return hdlc_ioctl(dev, ifr, cmd); 1638 1639 memset(&new_line, 0, sizeof(new_line)); 1640 1641 switch(ifr->ifr_settings.type) { 1642 case IF_GET_IFACE: /* return current sync_serial_settings */ 1643 1644 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 1645 if (ifr->ifr_settings.size < size) { 1646 ifr->ifr_settings.size = size; /* data size wanted */ 1647 return -ENOBUFS; 1648 } 1649 1650 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1651 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1652 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1653 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1654 1655 switch (flags){ 1656 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; 1657 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; 1658 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; 1659 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; 1660 default: new_line.clock_type = CLOCK_DEFAULT; 1661 } 1662 1663 new_line.clock_rate = info->params.clock_speed; 1664 new_line.loopback = info->params.loopback ? 1:0; 1665 1666 if (copy_to_user(line, &new_line, size)) 1667 return -EFAULT; 1668 return 0; 1669 1670 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ 1671 1672 if(!capable(CAP_NET_ADMIN)) 1673 return -EPERM; 1674 if (copy_from_user(&new_line, line, size)) 1675 return -EFAULT; 1676 1677 switch (new_line.clock_type) 1678 { 1679 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; 1680 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; 1681 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; 1682 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; 1683 case CLOCK_DEFAULT: flags = info->params.flags & 1684 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1685 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1686 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1687 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; 1688 default: return -EINVAL; 1689 } 1690 1691 if (new_line.loopback != 0 && new_line.loopback != 1) 1692 return -EINVAL; 1693 1694 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | 1695 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | 1696 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | 1697 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); 1698 info->params.flags |= flags; 1699 1700 info->params.loopback = new_line.loopback; 1701 1702 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) 1703 info->params.clock_speed = new_line.clock_rate; 1704 else 1705 info->params.clock_speed = 0; 1706 1707 /* if network interface up, reprogram hardware */ 1708 if (info->netcount) 1709 program_hw(info); 1710 return 0; 1711 1712 default: 1713 return hdlc_ioctl(dev, ifr, cmd); 1714 } 1715 } 1716 1717 /** 1718 * called by network layer when transmit timeout is detected 1719 * 1720 * dev pointer to network device structure 1721 */ 1722 static void hdlcdev_tx_timeout(struct net_device *dev) 1723 { 1724 struct slgt_info *info = dev_to_port(dev); 1725 unsigned long flags; 1726 1727 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name)); 1728 1729 dev->stats.tx_errors++; 1730 dev->stats.tx_aborted_errors++; 1731 1732 spin_lock_irqsave(&info->lock,flags); 1733 tx_stop(info); 1734 spin_unlock_irqrestore(&info->lock,flags); 1735 1736 netif_wake_queue(dev); 1737 } 1738 1739 /** 1740 * called by device driver when transmit completes 1741 * reenable network layer transmit if stopped 1742 * 1743 * info pointer to device instance information 1744 */ 1745 static void hdlcdev_tx_done(struct slgt_info *info) 1746 { 1747 if (netif_queue_stopped(info->netdev)) 1748 netif_wake_queue(info->netdev); 1749 } 1750 1751 /** 1752 * called by device driver when frame received 1753 * pass frame to network layer 1754 * 1755 * info pointer to device instance information 1756 * buf pointer to buffer contianing frame data 1757 * size count of data bytes in buf 1758 */ 1759 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size) 1760 { 1761 struct sk_buff *skb = dev_alloc_skb(size); 1762 struct net_device *dev = info->netdev; 1763 1764 DBGINFO(("%s hdlcdev_rx\n", dev->name)); 1765 1766 if (skb == NULL) { 1767 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name)); 1768 dev->stats.rx_dropped++; 1769 return; 1770 } 1771 1772 memcpy(skb_put(skb, size), buf, size); 1773 1774 skb->protocol = hdlc_type_trans(skb, dev); 1775 1776 dev->stats.rx_packets++; 1777 dev->stats.rx_bytes += size; 1778 1779 netif_rx(skb); 1780 } 1781 1782 static const struct net_device_ops hdlcdev_ops = { 1783 .ndo_open = hdlcdev_open, 1784 .ndo_stop = hdlcdev_close, 1785 .ndo_change_mtu = hdlc_change_mtu, 1786 .ndo_start_xmit = hdlc_start_xmit, 1787 .ndo_do_ioctl = hdlcdev_ioctl, 1788 .ndo_tx_timeout = hdlcdev_tx_timeout, 1789 }; 1790 1791 /** 1792 * called by device driver when adding device instance 1793 * do generic HDLC initialization 1794 * 1795 * info pointer to device instance information 1796 * 1797 * returns 0 if success, otherwise error code 1798 */ 1799 static int hdlcdev_init(struct slgt_info *info) 1800 { 1801 int rc; 1802 struct net_device *dev; 1803 hdlc_device *hdlc; 1804 1805 /* allocate and initialize network and HDLC layer objects */ 1806 1807 dev = alloc_hdlcdev(info); 1808 if (!dev) { 1809 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name); 1810 return -ENOMEM; 1811 } 1812 1813 /* for network layer reporting purposes only */ 1814 dev->mem_start = info->phys_reg_addr; 1815 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1; 1816 dev->irq = info->irq_level; 1817 1818 /* network layer callbacks and settings */ 1819 dev->netdev_ops = &hdlcdev_ops; 1820 dev->watchdog_timeo = 10 * HZ; 1821 dev->tx_queue_len = 50; 1822 1823 /* generic HDLC layer callbacks and settings */ 1824 hdlc = dev_to_hdlc(dev); 1825 hdlc->attach = hdlcdev_attach; 1826 hdlc->xmit = hdlcdev_xmit; 1827 1828 /* register objects with HDLC layer */ 1829 rc = register_hdlc_device(dev); 1830 if (rc) { 1831 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); 1832 free_netdev(dev); 1833 return rc; 1834 } 1835 1836 info->netdev = dev; 1837 return 0; 1838 } 1839 1840 /** 1841 * called by device driver when removing device instance 1842 * do generic HDLC cleanup 1843 * 1844 * info pointer to device instance information 1845 */ 1846 static void hdlcdev_exit(struct slgt_info *info) 1847 { 1848 unregister_hdlc_device(info->netdev); 1849 free_netdev(info->netdev); 1850 info->netdev = NULL; 1851 } 1852 1853 #endif /* ifdef CONFIG_HDLC */ 1854 1855 /* 1856 * get async data from rx DMA buffers 1857 */ 1858 static void rx_async(struct slgt_info *info) 1859 { 1860 struct mgsl_icount *icount = &info->icount; 1861 unsigned int start, end; 1862 unsigned char *p; 1863 unsigned char status; 1864 struct slgt_desc *bufs = info->rbufs; 1865 int i, count; 1866 int chars = 0; 1867 int stat; 1868 unsigned char ch; 1869 1870 start = end = info->rbuf_current; 1871 1872 while(desc_complete(bufs[end])) { 1873 count = desc_count(bufs[end]) - info->rbuf_index; 1874 p = bufs[end].buf + info->rbuf_index; 1875 1876 DBGISR(("%s rx_async count=%d\n", info->device_name, count)); 1877 DBGDATA(info, p, count, "rx"); 1878 1879 for(i=0 ; i < count; i+=2, p+=2) { 1880 ch = *p; 1881 icount->rx++; 1882 1883 stat = 0; 1884 1885 status = *(p + 1) & (BIT1 + BIT0); 1886 if (status) { 1887 if (status & BIT1) 1888 icount->parity++; 1889 else if (status & BIT0) 1890 icount->frame++; 1891 /* discard char if tty control flags say so */ 1892 if (status & info->ignore_status_mask) 1893 continue; 1894 if (status & BIT1) 1895 stat = TTY_PARITY; 1896 else if (status & BIT0) 1897 stat = TTY_FRAME; 1898 } 1899 tty_insert_flip_char(&info->port, ch, stat); 1900 chars++; 1901 } 1902 1903 if (i < count) { 1904 /* receive buffer not completed */ 1905 info->rbuf_index += i; 1906 mod_timer(&info->rx_timer, jiffies + 1); 1907 break; 1908 } 1909 1910 info->rbuf_index = 0; 1911 free_rbufs(info, end, end); 1912 1913 if (++end == info->rbuf_count) 1914 end = 0; 1915 1916 /* if entire list searched then no frame available */ 1917 if (end == start) 1918 break; 1919 } 1920 1921 if (chars) 1922 tty_flip_buffer_push(&info->port); 1923 } 1924 1925 /* 1926 * return next bottom half action to perform 1927 */ 1928 static int bh_action(struct slgt_info *info) 1929 { 1930 unsigned long flags; 1931 int rc; 1932 1933 spin_lock_irqsave(&info->lock,flags); 1934 1935 if (info->pending_bh & BH_RECEIVE) { 1936 info->pending_bh &= ~BH_RECEIVE; 1937 rc = BH_RECEIVE; 1938 } else if (info->pending_bh & BH_TRANSMIT) { 1939 info->pending_bh &= ~BH_TRANSMIT; 1940 rc = BH_TRANSMIT; 1941 } else if (info->pending_bh & BH_STATUS) { 1942 info->pending_bh &= ~BH_STATUS; 1943 rc = BH_STATUS; 1944 } else { 1945 /* Mark BH routine as complete */ 1946 info->bh_running = false; 1947 info->bh_requested = false; 1948 rc = 0; 1949 } 1950 1951 spin_unlock_irqrestore(&info->lock,flags); 1952 1953 return rc; 1954 } 1955 1956 /* 1957 * perform bottom half processing 1958 */ 1959 static void bh_handler(struct work_struct *work) 1960 { 1961 struct slgt_info *info = container_of(work, struct slgt_info, task); 1962 int action; 1963 1964 info->bh_running = true; 1965 1966 while((action = bh_action(info))) { 1967 switch (action) { 1968 case BH_RECEIVE: 1969 DBGBH(("%s bh receive\n", info->device_name)); 1970 switch(info->params.mode) { 1971 case MGSL_MODE_ASYNC: 1972 rx_async(info); 1973 break; 1974 case MGSL_MODE_HDLC: 1975 while(rx_get_frame(info)); 1976 break; 1977 case MGSL_MODE_RAW: 1978 case MGSL_MODE_MONOSYNC: 1979 case MGSL_MODE_BISYNC: 1980 case MGSL_MODE_XSYNC: 1981 while(rx_get_buf(info)); 1982 break; 1983 } 1984 /* restart receiver if rx DMA buffers exhausted */ 1985 if (info->rx_restart) 1986 rx_start(info); 1987 break; 1988 case BH_TRANSMIT: 1989 bh_transmit(info); 1990 break; 1991 case BH_STATUS: 1992 DBGBH(("%s bh status\n", info->device_name)); 1993 info->ri_chkcount = 0; 1994 info->dsr_chkcount = 0; 1995 info->dcd_chkcount = 0; 1996 info->cts_chkcount = 0; 1997 break; 1998 default: 1999 DBGBH(("%s unknown action\n", info->device_name)); 2000 break; 2001 } 2002 } 2003 DBGBH(("%s bh_handler exit\n", info->device_name)); 2004 } 2005 2006 static void bh_transmit(struct slgt_info *info) 2007 { 2008 struct tty_struct *tty = info->port.tty; 2009 2010 DBGBH(("%s bh_transmit\n", info->device_name)); 2011 if (tty) 2012 tty_wakeup(tty); 2013 } 2014 2015 static void dsr_change(struct slgt_info *info, unsigned short status) 2016 { 2017 if (status & BIT3) { 2018 info->signals |= SerialSignal_DSR; 2019 info->input_signal_events.dsr_up++; 2020 } else { 2021 info->signals &= ~SerialSignal_DSR; 2022 info->input_signal_events.dsr_down++; 2023 } 2024 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals)); 2025 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2026 slgt_irq_off(info, IRQ_DSR); 2027 return; 2028 } 2029 info->icount.dsr++; 2030 wake_up_interruptible(&info->status_event_wait_q); 2031 wake_up_interruptible(&info->event_wait_q); 2032 info->pending_bh |= BH_STATUS; 2033 } 2034 2035 static void cts_change(struct slgt_info *info, unsigned short status) 2036 { 2037 if (status & BIT2) { 2038 info->signals |= SerialSignal_CTS; 2039 info->input_signal_events.cts_up++; 2040 } else { 2041 info->signals &= ~SerialSignal_CTS; 2042 info->input_signal_events.cts_down++; 2043 } 2044 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals)); 2045 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2046 slgt_irq_off(info, IRQ_CTS); 2047 return; 2048 } 2049 info->icount.cts++; 2050 wake_up_interruptible(&info->status_event_wait_q); 2051 wake_up_interruptible(&info->event_wait_q); 2052 info->pending_bh |= BH_STATUS; 2053 2054 if (tty_port_cts_enabled(&info->port)) { 2055 if (info->port.tty) { 2056 if (info->port.tty->hw_stopped) { 2057 if (info->signals & SerialSignal_CTS) { 2058 info->port.tty->hw_stopped = 0; 2059 info->pending_bh |= BH_TRANSMIT; 2060 return; 2061 } 2062 } else { 2063 if (!(info->signals & SerialSignal_CTS)) 2064 info->port.tty->hw_stopped = 1; 2065 } 2066 } 2067 } 2068 } 2069 2070 static void dcd_change(struct slgt_info *info, unsigned short status) 2071 { 2072 if (status & BIT1) { 2073 info->signals |= SerialSignal_DCD; 2074 info->input_signal_events.dcd_up++; 2075 } else { 2076 info->signals &= ~SerialSignal_DCD; 2077 info->input_signal_events.dcd_down++; 2078 } 2079 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals)); 2080 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2081 slgt_irq_off(info, IRQ_DCD); 2082 return; 2083 } 2084 info->icount.dcd++; 2085 #if SYNCLINK_GENERIC_HDLC 2086 if (info->netcount) { 2087 if (info->signals & SerialSignal_DCD) 2088 netif_carrier_on(info->netdev); 2089 else 2090 netif_carrier_off(info->netdev); 2091 } 2092 #endif 2093 wake_up_interruptible(&info->status_event_wait_q); 2094 wake_up_interruptible(&info->event_wait_q); 2095 info->pending_bh |= BH_STATUS; 2096 2097 if (info->port.flags & ASYNC_CHECK_CD) { 2098 if (info->signals & SerialSignal_DCD) 2099 wake_up_interruptible(&info->port.open_wait); 2100 else { 2101 if (info->port.tty) 2102 tty_hangup(info->port.tty); 2103 } 2104 } 2105 } 2106 2107 static void ri_change(struct slgt_info *info, unsigned short status) 2108 { 2109 if (status & BIT0) { 2110 info->signals |= SerialSignal_RI; 2111 info->input_signal_events.ri_up++; 2112 } else { 2113 info->signals &= ~SerialSignal_RI; 2114 info->input_signal_events.ri_down++; 2115 } 2116 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals)); 2117 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) { 2118 slgt_irq_off(info, IRQ_RI); 2119 return; 2120 } 2121 info->icount.rng++; 2122 wake_up_interruptible(&info->status_event_wait_q); 2123 wake_up_interruptible(&info->event_wait_q); 2124 info->pending_bh |= BH_STATUS; 2125 } 2126 2127 static void isr_rxdata(struct slgt_info *info) 2128 { 2129 unsigned int count = info->rbuf_fill_count; 2130 unsigned int i = info->rbuf_fill_index; 2131 unsigned short reg; 2132 2133 while (rd_reg16(info, SSR) & IRQ_RXDATA) { 2134 reg = rd_reg16(info, RDR); 2135 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg)); 2136 if (desc_complete(info->rbufs[i])) { 2137 /* all buffers full */ 2138 rx_stop(info); 2139 info->rx_restart = 1; 2140 continue; 2141 } 2142 info->rbufs[i].buf[count++] = (unsigned char)reg; 2143 /* async mode saves status byte to buffer for each data byte */ 2144 if (info->params.mode == MGSL_MODE_ASYNC) 2145 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8); 2146 if (count == info->rbuf_fill_level || (reg & BIT10)) { 2147 /* buffer full or end of frame */ 2148 set_desc_count(info->rbufs[i], count); 2149 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); 2150 info->rbuf_fill_count = count = 0; 2151 if (++i == info->rbuf_count) 2152 i = 0; 2153 info->pending_bh |= BH_RECEIVE; 2154 } 2155 } 2156 2157 info->rbuf_fill_index = i; 2158 info->rbuf_fill_count = count; 2159 } 2160 2161 static void isr_serial(struct slgt_info *info) 2162 { 2163 unsigned short status = rd_reg16(info, SSR); 2164 2165 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status)); 2166 2167 wr_reg16(info, SSR, status); /* clear pending */ 2168 2169 info->irq_occurred = true; 2170 2171 if (info->params.mode == MGSL_MODE_ASYNC) { 2172 if (status & IRQ_TXIDLE) { 2173 if (info->tx_active) 2174 isr_txeom(info, status); 2175 } 2176 if (info->rx_pio && (status & IRQ_RXDATA)) 2177 isr_rxdata(info); 2178 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) { 2179 info->icount.brk++; 2180 /* process break detection if tty control allows */ 2181 if (info->port.tty) { 2182 if (!(status & info->ignore_status_mask)) { 2183 if (info->read_status_mask & MASK_BREAK) { 2184 tty_insert_flip_char(&info->port, 0, TTY_BREAK); 2185 if (info->port.flags & ASYNC_SAK) 2186 do_SAK(info->port.tty); 2187 } 2188 } 2189 } 2190 } 2191 } else { 2192 if (status & (IRQ_TXIDLE + IRQ_TXUNDER)) 2193 isr_txeom(info, status); 2194 if (info->rx_pio && (status & IRQ_RXDATA)) 2195 isr_rxdata(info); 2196 if (status & IRQ_RXIDLE) { 2197 if (status & RXIDLE) 2198 info->icount.rxidle++; 2199 else 2200 info->icount.exithunt++; 2201 wake_up_interruptible(&info->event_wait_q); 2202 } 2203 2204 if (status & IRQ_RXOVER) 2205 rx_start(info); 2206 } 2207 2208 if (status & IRQ_DSR) 2209 dsr_change(info, status); 2210 if (status & IRQ_CTS) 2211 cts_change(info, status); 2212 if (status & IRQ_DCD) 2213 dcd_change(info, status); 2214 if (status & IRQ_RI) 2215 ri_change(info, status); 2216 } 2217 2218 static void isr_rdma(struct slgt_info *info) 2219 { 2220 unsigned int status = rd_reg32(info, RDCSR); 2221 2222 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status)); 2223 2224 /* RDCSR (rx DMA control/status) 2225 * 2226 * 31..07 reserved 2227 * 06 save status byte to DMA buffer 2228 * 05 error 2229 * 04 eol (end of list) 2230 * 03 eob (end of buffer) 2231 * 02 IRQ enable 2232 * 01 reset 2233 * 00 enable 2234 */ 2235 wr_reg32(info, RDCSR, status); /* clear pending */ 2236 2237 if (status & (BIT5 + BIT4)) { 2238 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name)); 2239 info->rx_restart = true; 2240 } 2241 info->pending_bh |= BH_RECEIVE; 2242 } 2243 2244 static void isr_tdma(struct slgt_info *info) 2245 { 2246 unsigned int status = rd_reg32(info, TDCSR); 2247 2248 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status)); 2249 2250 /* TDCSR (tx DMA control/status) 2251 * 2252 * 31..06 reserved 2253 * 05 error 2254 * 04 eol (end of list) 2255 * 03 eob (end of buffer) 2256 * 02 IRQ enable 2257 * 01 reset 2258 * 00 enable 2259 */ 2260 wr_reg32(info, TDCSR, status); /* clear pending */ 2261 2262 if (status & (BIT5 + BIT4 + BIT3)) { 2263 // another transmit buffer has completed 2264 // run bottom half to get more send data from user 2265 info->pending_bh |= BH_TRANSMIT; 2266 } 2267 } 2268 2269 /* 2270 * return true if there are unsent tx DMA buffers, otherwise false 2271 * 2272 * if there are unsent buffers then info->tbuf_start 2273 * is set to index of first unsent buffer 2274 */ 2275 static bool unsent_tbufs(struct slgt_info *info) 2276 { 2277 unsigned int i = info->tbuf_current; 2278 bool rc = false; 2279 2280 /* 2281 * search backwards from last loaded buffer (precedes tbuf_current) 2282 * for first unsent buffer (desc_count > 0) 2283 */ 2284 2285 do { 2286 if (i) 2287 i--; 2288 else 2289 i = info->tbuf_count - 1; 2290 if (!desc_count(info->tbufs[i])) 2291 break; 2292 info->tbuf_start = i; 2293 rc = true; 2294 } while (i != info->tbuf_current); 2295 2296 return rc; 2297 } 2298 2299 static void isr_txeom(struct slgt_info *info, unsigned short status) 2300 { 2301 DBGISR(("%s txeom status=%04x\n", info->device_name, status)); 2302 2303 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 2304 tdma_reset(info); 2305 if (status & IRQ_TXUNDER) { 2306 unsigned short val = rd_reg16(info, TCR); 2307 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 2308 wr_reg16(info, TCR, val); /* clear reset bit */ 2309 } 2310 2311 if (info->tx_active) { 2312 if (info->params.mode != MGSL_MODE_ASYNC) { 2313 if (status & IRQ_TXUNDER) 2314 info->icount.txunder++; 2315 else if (status & IRQ_TXIDLE) 2316 info->icount.txok++; 2317 } 2318 2319 if (unsent_tbufs(info)) { 2320 tx_start(info); 2321 update_tx_timer(info); 2322 return; 2323 } 2324 info->tx_active = false; 2325 2326 del_timer(&info->tx_timer); 2327 2328 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) { 2329 info->signals &= ~SerialSignal_RTS; 2330 info->drop_rts_on_tx_done = false; 2331 set_signals(info); 2332 } 2333 2334 #if SYNCLINK_GENERIC_HDLC 2335 if (info->netcount) 2336 hdlcdev_tx_done(info); 2337 else 2338 #endif 2339 { 2340 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { 2341 tx_stop(info); 2342 return; 2343 } 2344 info->pending_bh |= BH_TRANSMIT; 2345 } 2346 } 2347 } 2348 2349 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state) 2350 { 2351 struct cond_wait *w, *prev; 2352 2353 /* wake processes waiting for specific transitions */ 2354 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) { 2355 if (w->data & changed) { 2356 w->data = state; 2357 wake_up_interruptible(&w->q); 2358 if (prev != NULL) 2359 prev->next = w->next; 2360 else 2361 info->gpio_wait_q = w->next; 2362 } else 2363 prev = w; 2364 } 2365 } 2366 2367 /* interrupt service routine 2368 * 2369 * irq interrupt number 2370 * dev_id device ID supplied during interrupt registration 2371 */ 2372 static irqreturn_t slgt_interrupt(int dummy, void *dev_id) 2373 { 2374 struct slgt_info *info = dev_id; 2375 unsigned int gsr; 2376 unsigned int i; 2377 2378 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level)); 2379 2380 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) { 2381 DBGISR(("%s gsr=%08x\n", info->device_name, gsr)); 2382 info->irq_occurred = true; 2383 for(i=0; i < info->port_count ; i++) { 2384 if (info->port_array[i] == NULL) 2385 continue; 2386 spin_lock(&info->port_array[i]->lock); 2387 if (gsr & (BIT8 << i)) 2388 isr_serial(info->port_array[i]); 2389 if (gsr & (BIT16 << (i*2))) 2390 isr_rdma(info->port_array[i]); 2391 if (gsr & (BIT17 << (i*2))) 2392 isr_tdma(info->port_array[i]); 2393 spin_unlock(&info->port_array[i]->lock); 2394 } 2395 } 2396 2397 if (info->gpio_present) { 2398 unsigned int state; 2399 unsigned int changed; 2400 spin_lock(&info->lock); 2401 while ((changed = rd_reg32(info, IOSR)) != 0) { 2402 DBGISR(("%s iosr=%08x\n", info->device_name, changed)); 2403 /* read latched state of GPIO signals */ 2404 state = rd_reg32(info, IOVR); 2405 /* clear pending GPIO interrupt bits */ 2406 wr_reg32(info, IOSR, changed); 2407 for (i=0 ; i < info->port_count ; i++) { 2408 if (info->port_array[i] != NULL) 2409 isr_gpio(info->port_array[i], changed, state); 2410 } 2411 } 2412 spin_unlock(&info->lock); 2413 } 2414 2415 for(i=0; i < info->port_count ; i++) { 2416 struct slgt_info *port = info->port_array[i]; 2417 if (port == NULL) 2418 continue; 2419 spin_lock(&port->lock); 2420 if ((port->port.count || port->netcount) && 2421 port->pending_bh && !port->bh_running && 2422 !port->bh_requested) { 2423 DBGISR(("%s bh queued\n", port->device_name)); 2424 schedule_work(&port->task); 2425 port->bh_requested = true; 2426 } 2427 spin_unlock(&port->lock); 2428 } 2429 2430 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level)); 2431 return IRQ_HANDLED; 2432 } 2433 2434 static int startup(struct slgt_info *info) 2435 { 2436 DBGINFO(("%s startup\n", info->device_name)); 2437 2438 if (info->port.flags & ASYNC_INITIALIZED) 2439 return 0; 2440 2441 if (!info->tx_buf) { 2442 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); 2443 if (!info->tx_buf) { 2444 DBGERR(("%s can't allocate tx buffer\n", info->device_name)); 2445 return -ENOMEM; 2446 } 2447 } 2448 2449 info->pending_bh = 0; 2450 2451 memset(&info->icount, 0, sizeof(info->icount)); 2452 2453 /* program hardware for current parameters */ 2454 change_params(info); 2455 2456 if (info->port.tty) 2457 clear_bit(TTY_IO_ERROR, &info->port.tty->flags); 2458 2459 info->port.flags |= ASYNC_INITIALIZED; 2460 2461 return 0; 2462 } 2463 2464 /* 2465 * called by close() and hangup() to shutdown hardware 2466 */ 2467 static void shutdown(struct slgt_info *info) 2468 { 2469 unsigned long flags; 2470 2471 if (!(info->port.flags & ASYNC_INITIALIZED)) 2472 return; 2473 2474 DBGINFO(("%s shutdown\n", info->device_name)); 2475 2476 /* clear status wait queue because status changes */ 2477 /* can't happen after shutting down the hardware */ 2478 wake_up_interruptible(&info->status_event_wait_q); 2479 wake_up_interruptible(&info->event_wait_q); 2480 2481 del_timer_sync(&info->tx_timer); 2482 del_timer_sync(&info->rx_timer); 2483 2484 kfree(info->tx_buf); 2485 info->tx_buf = NULL; 2486 2487 spin_lock_irqsave(&info->lock,flags); 2488 2489 tx_stop(info); 2490 rx_stop(info); 2491 2492 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 2493 2494 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { 2495 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2496 set_signals(info); 2497 } 2498 2499 flush_cond_wait(&info->gpio_wait_q); 2500 2501 spin_unlock_irqrestore(&info->lock,flags); 2502 2503 if (info->port.tty) 2504 set_bit(TTY_IO_ERROR, &info->port.tty->flags); 2505 2506 info->port.flags &= ~ASYNC_INITIALIZED; 2507 } 2508 2509 static void program_hw(struct slgt_info *info) 2510 { 2511 unsigned long flags; 2512 2513 spin_lock_irqsave(&info->lock,flags); 2514 2515 rx_stop(info); 2516 tx_stop(info); 2517 2518 if (info->params.mode != MGSL_MODE_ASYNC || 2519 info->netcount) 2520 sync_mode(info); 2521 else 2522 async_mode(info); 2523 2524 set_signals(info); 2525 2526 info->dcd_chkcount = 0; 2527 info->cts_chkcount = 0; 2528 info->ri_chkcount = 0; 2529 info->dsr_chkcount = 0; 2530 2531 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI); 2532 get_signals(info); 2533 2534 if (info->netcount || 2535 (info->port.tty && info->port.tty->termios.c_cflag & CREAD)) 2536 rx_start(info); 2537 2538 spin_unlock_irqrestore(&info->lock,flags); 2539 } 2540 2541 /* 2542 * reconfigure adapter based on new parameters 2543 */ 2544 static void change_params(struct slgt_info *info) 2545 { 2546 unsigned cflag; 2547 int bits_per_char; 2548 2549 if (!info->port.tty) 2550 return; 2551 DBGINFO(("%s change_params\n", info->device_name)); 2552 2553 cflag = info->port.tty->termios.c_cflag; 2554 2555 /* if B0 rate (hangup) specified then negate RTS and DTR */ 2556 /* otherwise assert RTS and DTR */ 2557 if (cflag & CBAUD) 2558 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 2559 else 2560 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 2561 2562 /* byte size and parity */ 2563 2564 switch (cflag & CSIZE) { 2565 case CS5: info->params.data_bits = 5; break; 2566 case CS6: info->params.data_bits = 6; break; 2567 case CS7: info->params.data_bits = 7; break; 2568 case CS8: info->params.data_bits = 8; break; 2569 default: info->params.data_bits = 7; break; 2570 } 2571 2572 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1; 2573 2574 if (cflag & PARENB) 2575 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN; 2576 else 2577 info->params.parity = ASYNC_PARITY_NONE; 2578 2579 /* calculate number of jiffies to transmit a full 2580 * FIFO (32 bytes) at specified data rate 2581 */ 2582 bits_per_char = info->params.data_bits + 2583 info->params.stop_bits + 1; 2584 2585 info->params.data_rate = tty_get_baud_rate(info->port.tty); 2586 2587 if (info->params.data_rate) { 2588 info->timeout = (32*HZ*bits_per_char) / 2589 info->params.data_rate; 2590 } 2591 info->timeout += HZ/50; /* Add .02 seconds of slop */ 2592 2593 if (cflag & CRTSCTS) 2594 info->port.flags |= ASYNC_CTS_FLOW; 2595 else 2596 info->port.flags &= ~ASYNC_CTS_FLOW; 2597 2598 if (cflag & CLOCAL) 2599 info->port.flags &= ~ASYNC_CHECK_CD; 2600 else 2601 info->port.flags |= ASYNC_CHECK_CD; 2602 2603 /* process tty input control flags */ 2604 2605 info->read_status_mask = IRQ_RXOVER; 2606 if (I_INPCK(info->port.tty)) 2607 info->read_status_mask |= MASK_PARITY | MASK_FRAMING; 2608 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) 2609 info->read_status_mask |= MASK_BREAK; 2610 if (I_IGNPAR(info->port.tty)) 2611 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING; 2612 if (I_IGNBRK(info->port.tty)) { 2613 info->ignore_status_mask |= MASK_BREAK; 2614 /* If ignoring parity and break indicators, ignore 2615 * overruns too. (For real raw support). 2616 */ 2617 if (I_IGNPAR(info->port.tty)) 2618 info->ignore_status_mask |= MASK_OVERRUN; 2619 } 2620 2621 program_hw(info); 2622 } 2623 2624 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount) 2625 { 2626 DBGINFO(("%s get_stats\n", info->device_name)); 2627 if (!user_icount) { 2628 memset(&info->icount, 0, sizeof(info->icount)); 2629 } else { 2630 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount))) 2631 return -EFAULT; 2632 } 2633 return 0; 2634 } 2635 2636 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params) 2637 { 2638 DBGINFO(("%s get_params\n", info->device_name)); 2639 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS))) 2640 return -EFAULT; 2641 return 0; 2642 } 2643 2644 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params) 2645 { 2646 unsigned long flags; 2647 MGSL_PARAMS tmp_params; 2648 2649 DBGINFO(("%s set_params\n", info->device_name)); 2650 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS))) 2651 return -EFAULT; 2652 2653 spin_lock_irqsave(&info->lock, flags); 2654 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) 2655 info->base_clock = tmp_params.clock_speed; 2656 else 2657 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS)); 2658 spin_unlock_irqrestore(&info->lock, flags); 2659 2660 program_hw(info); 2661 2662 return 0; 2663 } 2664 2665 static int get_txidle(struct slgt_info *info, int __user *idle_mode) 2666 { 2667 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode)); 2668 if (put_user(info->idle_mode, idle_mode)) 2669 return -EFAULT; 2670 return 0; 2671 } 2672 2673 static int set_txidle(struct slgt_info *info, int idle_mode) 2674 { 2675 unsigned long flags; 2676 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode)); 2677 spin_lock_irqsave(&info->lock,flags); 2678 info->idle_mode = idle_mode; 2679 if (info->params.mode != MGSL_MODE_ASYNC) 2680 tx_set_idle(info); 2681 spin_unlock_irqrestore(&info->lock,flags); 2682 return 0; 2683 } 2684 2685 static int tx_enable(struct slgt_info *info, int enable) 2686 { 2687 unsigned long flags; 2688 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable)); 2689 spin_lock_irqsave(&info->lock,flags); 2690 if (enable) { 2691 if (!info->tx_enabled) 2692 tx_start(info); 2693 } else { 2694 if (info->tx_enabled) 2695 tx_stop(info); 2696 } 2697 spin_unlock_irqrestore(&info->lock,flags); 2698 return 0; 2699 } 2700 2701 /* 2702 * abort transmit HDLC frame 2703 */ 2704 static int tx_abort(struct slgt_info *info) 2705 { 2706 unsigned long flags; 2707 DBGINFO(("%s tx_abort\n", info->device_name)); 2708 spin_lock_irqsave(&info->lock,flags); 2709 tdma_reset(info); 2710 spin_unlock_irqrestore(&info->lock,flags); 2711 return 0; 2712 } 2713 2714 static int rx_enable(struct slgt_info *info, int enable) 2715 { 2716 unsigned long flags; 2717 unsigned int rbuf_fill_level; 2718 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable)); 2719 spin_lock_irqsave(&info->lock,flags); 2720 /* 2721 * enable[31..16] = receive DMA buffer fill level 2722 * 0 = noop (leave fill level unchanged) 2723 * fill level must be multiple of 4 and <= buffer size 2724 */ 2725 rbuf_fill_level = ((unsigned int)enable) >> 16; 2726 if (rbuf_fill_level) { 2727 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) { 2728 spin_unlock_irqrestore(&info->lock, flags); 2729 return -EINVAL; 2730 } 2731 info->rbuf_fill_level = rbuf_fill_level; 2732 if (rbuf_fill_level < 128) 2733 info->rx_pio = 1; /* PIO mode */ 2734 else 2735 info->rx_pio = 0; /* DMA mode */ 2736 rx_stop(info); /* restart receiver to use new fill level */ 2737 } 2738 2739 /* 2740 * enable[1..0] = receiver enable command 2741 * 0 = disable 2742 * 1 = enable 2743 * 2 = enable or force hunt mode if already enabled 2744 */ 2745 enable &= 3; 2746 if (enable) { 2747 if (!info->rx_enabled) 2748 rx_start(info); 2749 else if (enable == 2) { 2750 /* force hunt mode (write 1 to RCR[3]) */ 2751 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); 2752 } 2753 } else { 2754 if (info->rx_enabled) 2755 rx_stop(info); 2756 } 2757 spin_unlock_irqrestore(&info->lock,flags); 2758 return 0; 2759 } 2760 2761 /* 2762 * wait for specified event to occur 2763 */ 2764 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr) 2765 { 2766 unsigned long flags; 2767 int s; 2768 int rc=0; 2769 struct mgsl_icount cprev, cnow; 2770 int events; 2771 int mask; 2772 struct _input_signal_events oldsigs, newsigs; 2773 DECLARE_WAITQUEUE(wait, current); 2774 2775 if (get_user(mask, mask_ptr)) 2776 return -EFAULT; 2777 2778 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask)); 2779 2780 spin_lock_irqsave(&info->lock,flags); 2781 2782 /* return immediately if state matches requested events */ 2783 get_signals(info); 2784 s = info->signals; 2785 2786 events = mask & 2787 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + 2788 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + 2789 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + 2790 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); 2791 if (events) { 2792 spin_unlock_irqrestore(&info->lock,flags); 2793 goto exit; 2794 } 2795 2796 /* save current irq counts */ 2797 cprev = info->icount; 2798 oldsigs = info->input_signal_events; 2799 2800 /* enable hunt and idle irqs if needed */ 2801 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { 2802 unsigned short val = rd_reg16(info, SCR); 2803 if (!(val & IRQ_RXIDLE)) 2804 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); 2805 } 2806 2807 set_current_state(TASK_INTERRUPTIBLE); 2808 add_wait_queue(&info->event_wait_q, &wait); 2809 2810 spin_unlock_irqrestore(&info->lock,flags); 2811 2812 for(;;) { 2813 schedule(); 2814 if (signal_pending(current)) { 2815 rc = -ERESTARTSYS; 2816 break; 2817 } 2818 2819 /* get current irq counts */ 2820 spin_lock_irqsave(&info->lock,flags); 2821 cnow = info->icount; 2822 newsigs = info->input_signal_events; 2823 set_current_state(TASK_INTERRUPTIBLE); 2824 spin_unlock_irqrestore(&info->lock,flags); 2825 2826 /* if no change, wait aborted for some reason */ 2827 if (newsigs.dsr_up == oldsigs.dsr_up && 2828 newsigs.dsr_down == oldsigs.dsr_down && 2829 newsigs.dcd_up == oldsigs.dcd_up && 2830 newsigs.dcd_down == oldsigs.dcd_down && 2831 newsigs.cts_up == oldsigs.cts_up && 2832 newsigs.cts_down == oldsigs.cts_down && 2833 newsigs.ri_up == oldsigs.ri_up && 2834 newsigs.ri_down == oldsigs.ri_down && 2835 cnow.exithunt == cprev.exithunt && 2836 cnow.rxidle == cprev.rxidle) { 2837 rc = -EIO; 2838 break; 2839 } 2840 2841 events = mask & 2842 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + 2843 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + 2844 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + 2845 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + 2846 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + 2847 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + 2848 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + 2849 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + 2850 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + 2851 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); 2852 if (events) 2853 break; 2854 2855 cprev = cnow; 2856 oldsigs = newsigs; 2857 } 2858 2859 remove_wait_queue(&info->event_wait_q, &wait); 2860 set_current_state(TASK_RUNNING); 2861 2862 2863 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { 2864 spin_lock_irqsave(&info->lock,flags); 2865 if (!waitqueue_active(&info->event_wait_q)) { 2866 /* disable enable exit hunt mode/idle rcvd IRQs */ 2867 wr_reg16(info, SCR, 2868 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE)); 2869 } 2870 spin_unlock_irqrestore(&info->lock,flags); 2871 } 2872 exit: 2873 if (rc == 0) 2874 rc = put_user(events, mask_ptr); 2875 return rc; 2876 } 2877 2878 static int get_interface(struct slgt_info *info, int __user *if_mode) 2879 { 2880 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode)); 2881 if (put_user(info->if_mode, if_mode)) 2882 return -EFAULT; 2883 return 0; 2884 } 2885 2886 static int set_interface(struct slgt_info *info, int if_mode) 2887 { 2888 unsigned long flags; 2889 unsigned short val; 2890 2891 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode)); 2892 spin_lock_irqsave(&info->lock,flags); 2893 info->if_mode = if_mode; 2894 2895 msc_set_vcr(info); 2896 2897 /* TCR (tx control) 07 1=RTS driver control */ 2898 val = rd_reg16(info, TCR); 2899 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 2900 val |= BIT7; 2901 else 2902 val &= ~BIT7; 2903 wr_reg16(info, TCR, val); 2904 2905 spin_unlock_irqrestore(&info->lock,flags); 2906 return 0; 2907 } 2908 2909 static int get_xsync(struct slgt_info *info, int __user *xsync) 2910 { 2911 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync)); 2912 if (put_user(info->xsync, xsync)) 2913 return -EFAULT; 2914 return 0; 2915 } 2916 2917 /* 2918 * set extended sync pattern (1 to 4 bytes) for extended sync mode 2919 * 2920 * sync pattern is contained in least significant bytes of value 2921 * most significant byte of sync pattern is oldest (1st sent/detected) 2922 */ 2923 static int set_xsync(struct slgt_info *info, int xsync) 2924 { 2925 unsigned long flags; 2926 2927 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync)); 2928 spin_lock_irqsave(&info->lock, flags); 2929 info->xsync = xsync; 2930 wr_reg32(info, XSR, xsync); 2931 spin_unlock_irqrestore(&info->lock, flags); 2932 return 0; 2933 } 2934 2935 static int get_xctrl(struct slgt_info *info, int __user *xctrl) 2936 { 2937 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl)); 2938 if (put_user(info->xctrl, xctrl)) 2939 return -EFAULT; 2940 return 0; 2941 } 2942 2943 /* 2944 * set extended control options 2945 * 2946 * xctrl[31:19] reserved, must be zero 2947 * xctrl[18:17] extended sync pattern length in bytes 2948 * 00 = 1 byte in xsr[7:0] 2949 * 01 = 2 bytes in xsr[15:0] 2950 * 10 = 3 bytes in xsr[23:0] 2951 * 11 = 4 bytes in xsr[31:0] 2952 * xctrl[16] 1 = enable terminal count, 0=disabled 2953 * xctrl[15:0] receive terminal count for fixed length packets 2954 * value is count minus one (0 = 1 byte packet) 2955 * when terminal count is reached, receiver 2956 * automatically returns to hunt mode and receive 2957 * FIFO contents are flushed to DMA buffers with 2958 * end of frame (EOF) status 2959 */ 2960 static int set_xctrl(struct slgt_info *info, int xctrl) 2961 { 2962 unsigned long flags; 2963 2964 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl)); 2965 spin_lock_irqsave(&info->lock, flags); 2966 info->xctrl = xctrl; 2967 wr_reg32(info, XCR, xctrl); 2968 spin_unlock_irqrestore(&info->lock, flags); 2969 return 0; 2970 } 2971 2972 /* 2973 * set general purpose IO pin state and direction 2974 * 2975 * user_gpio fields: 2976 * state each bit indicates a pin state 2977 * smask set bit indicates pin state to set 2978 * dir each bit indicates a pin direction (0=input, 1=output) 2979 * dmask set bit indicates pin direction to set 2980 */ 2981 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 2982 { 2983 unsigned long flags; 2984 struct gpio_desc gpio; 2985 __u32 data; 2986 2987 if (!info->gpio_present) 2988 return -EINVAL; 2989 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 2990 return -EFAULT; 2991 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n", 2992 info->device_name, gpio.state, gpio.smask, 2993 gpio.dir, gpio.dmask)); 2994 2995 spin_lock_irqsave(&info->port_array[0]->lock, flags); 2996 if (gpio.dmask) { 2997 data = rd_reg32(info, IODR); 2998 data |= gpio.dmask & gpio.dir; 2999 data &= ~(gpio.dmask & ~gpio.dir); 3000 wr_reg32(info, IODR, data); 3001 } 3002 if (gpio.smask) { 3003 data = rd_reg32(info, IOVR); 3004 data |= gpio.smask & gpio.state; 3005 data &= ~(gpio.smask & ~gpio.state); 3006 wr_reg32(info, IOVR, data); 3007 } 3008 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3009 3010 return 0; 3011 } 3012 3013 /* 3014 * get general purpose IO pin state and direction 3015 */ 3016 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3017 { 3018 struct gpio_desc gpio; 3019 if (!info->gpio_present) 3020 return -EINVAL; 3021 gpio.state = rd_reg32(info, IOVR); 3022 gpio.smask = 0xffffffff; 3023 gpio.dir = rd_reg32(info, IODR); 3024 gpio.dmask = 0xffffffff; 3025 if (copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3026 return -EFAULT; 3027 DBGINFO(("%s get_gpio state=%08x dir=%08x\n", 3028 info->device_name, gpio.state, gpio.dir)); 3029 return 0; 3030 } 3031 3032 /* 3033 * conditional wait facility 3034 */ 3035 static void init_cond_wait(struct cond_wait *w, unsigned int data) 3036 { 3037 init_waitqueue_head(&w->q); 3038 init_waitqueue_entry(&w->wait, current); 3039 w->data = data; 3040 } 3041 3042 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w) 3043 { 3044 set_current_state(TASK_INTERRUPTIBLE); 3045 add_wait_queue(&w->q, &w->wait); 3046 w->next = *head; 3047 *head = w; 3048 } 3049 3050 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw) 3051 { 3052 struct cond_wait *w, *prev; 3053 remove_wait_queue(&cw->q, &cw->wait); 3054 set_current_state(TASK_RUNNING); 3055 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) { 3056 if (w == cw) { 3057 if (prev != NULL) 3058 prev->next = w->next; 3059 else 3060 *head = w->next; 3061 break; 3062 } 3063 } 3064 } 3065 3066 static void flush_cond_wait(struct cond_wait **head) 3067 { 3068 while (*head != NULL) { 3069 wake_up_interruptible(&(*head)->q); 3070 *head = (*head)->next; 3071 } 3072 } 3073 3074 /* 3075 * wait for general purpose I/O pin(s) to enter specified state 3076 * 3077 * user_gpio fields: 3078 * state - bit indicates target pin state 3079 * smask - set bit indicates watched pin 3080 * 3081 * The wait ends when at least one watched pin enters the specified 3082 * state. When 0 (no error) is returned, user_gpio->state is set to the 3083 * state of all GPIO pins when the wait ends. 3084 * 3085 * Note: Each pin may be a dedicated input, dedicated output, or 3086 * configurable input/output. The number and configuration of pins 3087 * varies with the specific adapter model. Only input pins (dedicated 3088 * or configured) can be monitored with this function. 3089 */ 3090 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio) 3091 { 3092 unsigned long flags; 3093 int rc = 0; 3094 struct gpio_desc gpio; 3095 struct cond_wait wait; 3096 u32 state; 3097 3098 if (!info->gpio_present) 3099 return -EINVAL; 3100 if (copy_from_user(&gpio, user_gpio, sizeof(gpio))) 3101 return -EFAULT; 3102 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n", 3103 info->device_name, gpio.state, gpio.smask)); 3104 /* ignore output pins identified by set IODR bit */ 3105 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0) 3106 return -EINVAL; 3107 init_cond_wait(&wait, gpio.smask); 3108 3109 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3110 /* enable interrupts for watched pins */ 3111 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); 3112 /* get current pin states */ 3113 state = rd_reg32(info, IOVR); 3114 3115 if (gpio.smask & ~(state ^ gpio.state)) { 3116 /* already in target state */ 3117 gpio.state = state; 3118 } else { 3119 /* wait for target state */ 3120 add_cond_wait(&info->gpio_wait_q, &wait); 3121 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3122 schedule(); 3123 if (signal_pending(current)) 3124 rc = -ERESTARTSYS; 3125 else 3126 gpio.state = wait.data; 3127 spin_lock_irqsave(&info->port_array[0]->lock, flags); 3128 remove_cond_wait(&info->gpio_wait_q, &wait); 3129 } 3130 3131 /* disable all GPIO interrupts if no waiting processes */ 3132 if (info->gpio_wait_q == NULL) 3133 wr_reg32(info, IOER, 0); 3134 spin_unlock_irqrestore(&info->port_array[0]->lock, flags); 3135 3136 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio))) 3137 rc = -EFAULT; 3138 return rc; 3139 } 3140 3141 static int modem_input_wait(struct slgt_info *info,int arg) 3142 { 3143 unsigned long flags; 3144 int rc; 3145 struct mgsl_icount cprev, cnow; 3146 DECLARE_WAITQUEUE(wait, current); 3147 3148 /* save current irq counts */ 3149 spin_lock_irqsave(&info->lock,flags); 3150 cprev = info->icount; 3151 add_wait_queue(&info->status_event_wait_q, &wait); 3152 set_current_state(TASK_INTERRUPTIBLE); 3153 spin_unlock_irqrestore(&info->lock,flags); 3154 3155 for(;;) { 3156 schedule(); 3157 if (signal_pending(current)) { 3158 rc = -ERESTARTSYS; 3159 break; 3160 } 3161 3162 /* get new irq counts */ 3163 spin_lock_irqsave(&info->lock,flags); 3164 cnow = info->icount; 3165 set_current_state(TASK_INTERRUPTIBLE); 3166 spin_unlock_irqrestore(&info->lock,flags); 3167 3168 /* if no change, wait aborted for some reason */ 3169 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 3170 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { 3171 rc = -EIO; 3172 break; 3173 } 3174 3175 /* check for change in caller specified modem input */ 3176 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || 3177 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || 3178 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || 3179 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { 3180 rc = 0; 3181 break; 3182 } 3183 3184 cprev = cnow; 3185 } 3186 remove_wait_queue(&info->status_event_wait_q, &wait); 3187 set_current_state(TASK_RUNNING); 3188 return rc; 3189 } 3190 3191 /* 3192 * return state of serial control and status signals 3193 */ 3194 static int tiocmget(struct tty_struct *tty) 3195 { 3196 struct slgt_info *info = tty->driver_data; 3197 unsigned int result; 3198 unsigned long flags; 3199 3200 spin_lock_irqsave(&info->lock,flags); 3201 get_signals(info); 3202 spin_unlock_irqrestore(&info->lock,flags); 3203 3204 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) + 3205 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) + 3206 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) + 3207 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) + 3208 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) + 3209 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0); 3210 3211 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result)); 3212 return result; 3213 } 3214 3215 /* 3216 * set modem control signals (DTR/RTS) 3217 * 3218 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit 3219 * TIOCMSET = set/clear signal values 3220 * value bit mask for command 3221 */ 3222 static int tiocmset(struct tty_struct *tty, 3223 unsigned int set, unsigned int clear) 3224 { 3225 struct slgt_info *info = tty->driver_data; 3226 unsigned long flags; 3227 3228 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear)); 3229 3230 if (set & TIOCM_RTS) 3231 info->signals |= SerialSignal_RTS; 3232 if (set & TIOCM_DTR) 3233 info->signals |= SerialSignal_DTR; 3234 if (clear & TIOCM_RTS) 3235 info->signals &= ~SerialSignal_RTS; 3236 if (clear & TIOCM_DTR) 3237 info->signals &= ~SerialSignal_DTR; 3238 3239 spin_lock_irqsave(&info->lock,flags); 3240 set_signals(info); 3241 spin_unlock_irqrestore(&info->lock,flags); 3242 return 0; 3243 } 3244 3245 static int carrier_raised(struct tty_port *port) 3246 { 3247 unsigned long flags; 3248 struct slgt_info *info = container_of(port, struct slgt_info, port); 3249 3250 spin_lock_irqsave(&info->lock,flags); 3251 get_signals(info); 3252 spin_unlock_irqrestore(&info->lock,flags); 3253 return (info->signals & SerialSignal_DCD) ? 1 : 0; 3254 } 3255 3256 static void dtr_rts(struct tty_port *port, int on) 3257 { 3258 unsigned long flags; 3259 struct slgt_info *info = container_of(port, struct slgt_info, port); 3260 3261 spin_lock_irqsave(&info->lock,flags); 3262 if (on) 3263 info->signals |= SerialSignal_RTS | SerialSignal_DTR; 3264 else 3265 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 3266 set_signals(info); 3267 spin_unlock_irqrestore(&info->lock,flags); 3268 } 3269 3270 3271 /* 3272 * block current process until the device is ready to open 3273 */ 3274 static int block_til_ready(struct tty_struct *tty, struct file *filp, 3275 struct slgt_info *info) 3276 { 3277 DECLARE_WAITQUEUE(wait, current); 3278 int retval; 3279 bool do_clocal = false; 3280 unsigned long flags; 3281 int cd; 3282 struct tty_port *port = &info->port; 3283 3284 DBGINFO(("%s block_til_ready\n", tty->driver->name)); 3285 3286 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ 3287 /* nonblock mode is set or port is not enabled */ 3288 port->flags |= ASYNC_NORMAL_ACTIVE; 3289 return 0; 3290 } 3291 3292 if (tty->termios.c_cflag & CLOCAL) 3293 do_clocal = true; 3294 3295 /* Wait for carrier detect and the line to become 3296 * free (i.e., not in use by the callout). While we are in 3297 * this loop, port->count is dropped by one, so that 3298 * close() knows when to free things. We restore it upon 3299 * exit, either normal or abnormal. 3300 */ 3301 3302 retval = 0; 3303 add_wait_queue(&port->open_wait, &wait); 3304 3305 spin_lock_irqsave(&info->lock, flags); 3306 port->count--; 3307 spin_unlock_irqrestore(&info->lock, flags); 3308 port->blocked_open++; 3309 3310 while (1) { 3311 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) 3312 tty_port_raise_dtr_rts(port); 3313 3314 set_current_state(TASK_INTERRUPTIBLE); 3315 3316 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ 3317 retval = (port->flags & ASYNC_HUP_NOTIFY) ? 3318 -EAGAIN : -ERESTARTSYS; 3319 break; 3320 } 3321 3322 cd = tty_port_carrier_raised(port); 3323 3324 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd )) 3325 break; 3326 3327 if (signal_pending(current)) { 3328 retval = -ERESTARTSYS; 3329 break; 3330 } 3331 3332 DBGINFO(("%s block_til_ready wait\n", tty->driver->name)); 3333 tty_unlock(tty); 3334 schedule(); 3335 tty_lock(tty); 3336 } 3337 3338 set_current_state(TASK_RUNNING); 3339 remove_wait_queue(&port->open_wait, &wait); 3340 3341 if (!tty_hung_up_p(filp)) 3342 port->count++; 3343 port->blocked_open--; 3344 3345 if (!retval) 3346 port->flags |= ASYNC_NORMAL_ACTIVE; 3347 3348 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); 3349 return retval; 3350 } 3351 3352 /* 3353 * allocate buffers used for calling line discipline receive_buf 3354 * directly in synchronous mode 3355 * note: add 5 bytes to max frame size to allow appending 3356 * 32-bit CRC and status byte when configured to do so 3357 */ 3358 static int alloc_tmp_rbuf(struct slgt_info *info) 3359 { 3360 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL); 3361 if (info->tmp_rbuf == NULL) 3362 return -ENOMEM; 3363 /* unused flag buffer to satisfy receive_buf calling interface */ 3364 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL); 3365 if (!info->flag_buf) { 3366 kfree(info->tmp_rbuf); 3367 info->tmp_rbuf = NULL; 3368 return -ENOMEM; 3369 } 3370 return 0; 3371 } 3372 3373 static void free_tmp_rbuf(struct slgt_info *info) 3374 { 3375 kfree(info->tmp_rbuf); 3376 info->tmp_rbuf = NULL; 3377 kfree(info->flag_buf); 3378 info->flag_buf = NULL; 3379 } 3380 3381 /* 3382 * allocate DMA descriptor lists. 3383 */ 3384 static int alloc_desc(struct slgt_info *info) 3385 { 3386 unsigned int i; 3387 unsigned int pbufs; 3388 3389 /* allocate memory to hold descriptor lists */ 3390 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE, 3391 &info->bufs_dma_addr); 3392 if (info->bufs == NULL) 3393 return -ENOMEM; 3394 3395 info->rbufs = (struct slgt_desc*)info->bufs; 3396 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count; 3397 3398 pbufs = (unsigned int)info->bufs_dma_addr; 3399 3400 /* 3401 * Build circular lists of descriptors 3402 */ 3403 3404 for (i=0; i < info->rbuf_count; i++) { 3405 /* physical address of this descriptor */ 3406 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc)); 3407 3408 /* physical address of next descriptor */ 3409 if (i == info->rbuf_count - 1) 3410 info->rbufs[i].next = cpu_to_le32(pbufs); 3411 else 3412 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc))); 3413 set_desc_count(info->rbufs[i], DMABUFSIZE); 3414 } 3415 3416 for (i=0; i < info->tbuf_count; i++) { 3417 /* physical address of this descriptor */ 3418 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc)); 3419 3420 /* physical address of next descriptor */ 3421 if (i == info->tbuf_count - 1) 3422 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc)); 3423 else 3424 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc))); 3425 } 3426 3427 return 0; 3428 } 3429 3430 static void free_desc(struct slgt_info *info) 3431 { 3432 if (info->bufs != NULL) { 3433 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr); 3434 info->bufs = NULL; 3435 info->rbufs = NULL; 3436 info->tbufs = NULL; 3437 } 3438 } 3439 3440 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3441 { 3442 int i; 3443 for (i=0; i < count; i++) { 3444 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL) 3445 return -ENOMEM; 3446 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr); 3447 } 3448 return 0; 3449 } 3450 3451 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count) 3452 { 3453 int i; 3454 for (i=0; i < count; i++) { 3455 if (bufs[i].buf == NULL) 3456 continue; 3457 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr); 3458 bufs[i].buf = NULL; 3459 } 3460 } 3461 3462 static int alloc_dma_bufs(struct slgt_info *info) 3463 { 3464 info->rbuf_count = 32; 3465 info->tbuf_count = 32; 3466 3467 if (alloc_desc(info) < 0 || 3468 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 || 3469 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 || 3470 alloc_tmp_rbuf(info) < 0) { 3471 DBGERR(("%s DMA buffer alloc fail\n", info->device_name)); 3472 return -ENOMEM; 3473 } 3474 reset_rbufs(info); 3475 return 0; 3476 } 3477 3478 static void free_dma_bufs(struct slgt_info *info) 3479 { 3480 if (info->bufs) { 3481 free_bufs(info, info->rbufs, info->rbuf_count); 3482 free_bufs(info, info->tbufs, info->tbuf_count); 3483 free_desc(info); 3484 } 3485 free_tmp_rbuf(info); 3486 } 3487 3488 static int claim_resources(struct slgt_info *info) 3489 { 3490 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) { 3491 DBGERR(("%s reg addr conflict, addr=%08X\n", 3492 info->device_name, info->phys_reg_addr)); 3493 info->init_error = DiagStatus_AddressConflict; 3494 goto errout; 3495 } 3496 else 3497 info->reg_addr_requested = true; 3498 3499 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE); 3500 if (!info->reg_addr) { 3501 DBGERR(("%s can't map device registers, addr=%08X\n", 3502 info->device_name, info->phys_reg_addr)); 3503 info->init_error = DiagStatus_CantAssignPciResources; 3504 goto errout; 3505 } 3506 return 0; 3507 3508 errout: 3509 release_resources(info); 3510 return -ENODEV; 3511 } 3512 3513 static void release_resources(struct slgt_info *info) 3514 { 3515 if (info->irq_requested) { 3516 free_irq(info->irq_level, info); 3517 info->irq_requested = false; 3518 } 3519 3520 if (info->reg_addr_requested) { 3521 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE); 3522 info->reg_addr_requested = false; 3523 } 3524 3525 if (info->reg_addr) { 3526 iounmap(info->reg_addr); 3527 info->reg_addr = NULL; 3528 } 3529 } 3530 3531 /* Add the specified device instance data structure to the 3532 * global linked list of devices and increment the device count. 3533 */ 3534 static void add_device(struct slgt_info *info) 3535 { 3536 char *devstr; 3537 3538 info->next_device = NULL; 3539 info->line = slgt_device_count; 3540 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line); 3541 3542 if (info->line < MAX_DEVICES) { 3543 if (maxframe[info->line]) 3544 info->max_frame_size = maxframe[info->line]; 3545 } 3546 3547 slgt_device_count++; 3548 3549 if (!slgt_device_list) 3550 slgt_device_list = info; 3551 else { 3552 struct slgt_info *current_dev = slgt_device_list; 3553 while(current_dev->next_device) 3554 current_dev = current_dev->next_device; 3555 current_dev->next_device = info; 3556 } 3557 3558 if (info->max_frame_size < 4096) 3559 info->max_frame_size = 4096; 3560 else if (info->max_frame_size > 65535) 3561 info->max_frame_size = 65535; 3562 3563 switch(info->pdev->device) { 3564 case SYNCLINK_GT_DEVICE_ID: 3565 devstr = "GT"; 3566 break; 3567 case SYNCLINK_GT2_DEVICE_ID: 3568 devstr = "GT2"; 3569 break; 3570 case SYNCLINK_GT4_DEVICE_ID: 3571 devstr = "GT4"; 3572 break; 3573 case SYNCLINK_AC_DEVICE_ID: 3574 devstr = "AC"; 3575 info->params.mode = MGSL_MODE_ASYNC; 3576 break; 3577 default: 3578 devstr = "(unknown model)"; 3579 } 3580 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n", 3581 devstr, info->device_name, info->phys_reg_addr, 3582 info->irq_level, info->max_frame_size); 3583 3584 #if SYNCLINK_GENERIC_HDLC 3585 hdlcdev_init(info); 3586 #endif 3587 } 3588 3589 static const struct tty_port_operations slgt_port_ops = { 3590 .carrier_raised = carrier_raised, 3591 .dtr_rts = dtr_rts, 3592 }; 3593 3594 /* 3595 * allocate device instance structure, return NULL on failure 3596 */ 3597 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) 3598 { 3599 struct slgt_info *info; 3600 3601 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL); 3602 3603 if (!info) { 3604 DBGERR(("%s device alloc failed adapter=%d port=%d\n", 3605 driver_name, adapter_num, port_num)); 3606 } else { 3607 tty_port_init(&info->port); 3608 info->port.ops = &slgt_port_ops; 3609 info->magic = MGSL_MAGIC; 3610 INIT_WORK(&info->task, bh_handler); 3611 info->max_frame_size = 4096; 3612 info->base_clock = 14745600; 3613 info->rbuf_fill_level = DMABUFSIZE; 3614 info->port.close_delay = 5*HZ/10; 3615 info->port.closing_wait = 30*HZ; 3616 init_waitqueue_head(&info->status_event_wait_q); 3617 init_waitqueue_head(&info->event_wait_q); 3618 spin_lock_init(&info->netlock); 3619 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); 3620 info->idle_mode = HDLC_TXIDLE_FLAGS; 3621 info->adapter_num = adapter_num; 3622 info->port_num = port_num; 3623 3624 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); 3625 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info); 3626 3627 /* Copy configuration info to device instance data */ 3628 info->pdev = pdev; 3629 info->irq_level = pdev->irq; 3630 info->phys_reg_addr = pci_resource_start(pdev,0); 3631 3632 info->bus_type = MGSL_BUS_TYPE_PCI; 3633 info->irq_flags = IRQF_SHARED; 3634 3635 info->init_error = -1; /* assume error, set to 0 on successful init */ 3636 } 3637 3638 return info; 3639 } 3640 3641 static void device_init(int adapter_num, struct pci_dev *pdev) 3642 { 3643 struct slgt_info *port_array[SLGT_MAX_PORTS]; 3644 int i; 3645 int port_count = 1; 3646 3647 if (pdev->device == SYNCLINK_GT2_DEVICE_ID) 3648 port_count = 2; 3649 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID) 3650 port_count = 4; 3651 3652 /* allocate device instances for all ports */ 3653 for (i=0; i < port_count; ++i) { 3654 port_array[i] = alloc_dev(adapter_num, i, pdev); 3655 if (port_array[i] == NULL) { 3656 for (--i; i >= 0; --i) { 3657 tty_port_destroy(&port_array[i]->port); 3658 kfree(port_array[i]); 3659 } 3660 return; 3661 } 3662 } 3663 3664 /* give copy of port_array to all ports and add to device list */ 3665 for (i=0; i < port_count; ++i) { 3666 memcpy(port_array[i]->port_array, port_array, sizeof(port_array)); 3667 add_device(port_array[i]); 3668 port_array[i]->port_count = port_count; 3669 spin_lock_init(&port_array[i]->lock); 3670 } 3671 3672 /* Allocate and claim adapter resources */ 3673 if (!claim_resources(port_array[0])) { 3674 3675 alloc_dma_bufs(port_array[0]); 3676 3677 /* copy resource information from first port to others */ 3678 for (i = 1; i < port_count; ++i) { 3679 port_array[i]->irq_level = port_array[0]->irq_level; 3680 port_array[i]->reg_addr = port_array[0]->reg_addr; 3681 alloc_dma_bufs(port_array[i]); 3682 } 3683 3684 if (request_irq(port_array[0]->irq_level, 3685 slgt_interrupt, 3686 port_array[0]->irq_flags, 3687 port_array[0]->device_name, 3688 port_array[0]) < 0) { 3689 DBGERR(("%s request_irq failed IRQ=%d\n", 3690 port_array[0]->device_name, 3691 port_array[0]->irq_level)); 3692 } else { 3693 port_array[0]->irq_requested = true; 3694 adapter_test(port_array[0]); 3695 for (i=1 ; i < port_count ; i++) { 3696 port_array[i]->init_error = port_array[0]->init_error; 3697 port_array[i]->gpio_present = port_array[0]->gpio_present; 3698 } 3699 } 3700 } 3701 3702 for (i = 0; i < port_count; ++i) { 3703 struct slgt_info *info = port_array[i]; 3704 tty_port_register_device(&info->port, serial_driver, info->line, 3705 &info->pdev->dev); 3706 } 3707 } 3708 3709 static int init_one(struct pci_dev *dev, 3710 const struct pci_device_id *ent) 3711 { 3712 if (pci_enable_device(dev)) { 3713 printk("error enabling pci device %p\n", dev); 3714 return -EIO; 3715 } 3716 pci_set_master(dev); 3717 device_init(slgt_device_count, dev); 3718 return 0; 3719 } 3720 3721 static void remove_one(struct pci_dev *dev) 3722 { 3723 } 3724 3725 static const struct tty_operations ops = { 3726 .open = open, 3727 .close = close, 3728 .write = write, 3729 .put_char = put_char, 3730 .flush_chars = flush_chars, 3731 .write_room = write_room, 3732 .chars_in_buffer = chars_in_buffer, 3733 .flush_buffer = flush_buffer, 3734 .ioctl = ioctl, 3735 .compat_ioctl = slgt_compat_ioctl, 3736 .throttle = throttle, 3737 .unthrottle = unthrottle, 3738 .send_xchar = send_xchar, 3739 .break_ctl = set_break, 3740 .wait_until_sent = wait_until_sent, 3741 .set_termios = set_termios, 3742 .stop = tx_hold, 3743 .start = tx_release, 3744 .hangup = hangup, 3745 .tiocmget = tiocmget, 3746 .tiocmset = tiocmset, 3747 .get_icount = get_icount, 3748 .proc_fops = &synclink_gt_proc_fops, 3749 }; 3750 3751 static void slgt_cleanup(void) 3752 { 3753 int rc; 3754 struct slgt_info *info; 3755 struct slgt_info *tmp; 3756 3757 printk(KERN_INFO "unload %s\n", driver_name); 3758 3759 if (serial_driver) { 3760 for (info=slgt_device_list ; info != NULL ; info=info->next_device) 3761 tty_unregister_device(serial_driver, info->line); 3762 rc = tty_unregister_driver(serial_driver); 3763 if (rc) 3764 DBGERR(("tty_unregister_driver error=%d\n", rc)); 3765 put_tty_driver(serial_driver); 3766 } 3767 3768 /* reset devices */ 3769 info = slgt_device_list; 3770 while(info) { 3771 reset_port(info); 3772 info = info->next_device; 3773 } 3774 3775 /* release devices */ 3776 info = slgt_device_list; 3777 while(info) { 3778 #if SYNCLINK_GENERIC_HDLC 3779 hdlcdev_exit(info); 3780 #endif 3781 free_dma_bufs(info); 3782 free_tmp_rbuf(info); 3783 if (info->port_num == 0) 3784 release_resources(info); 3785 tmp = info; 3786 info = info->next_device; 3787 tty_port_destroy(&tmp->port); 3788 kfree(tmp); 3789 } 3790 3791 if (pci_registered) 3792 pci_unregister_driver(&pci_driver); 3793 } 3794 3795 /* 3796 * Driver initialization entry point. 3797 */ 3798 static int __init slgt_init(void) 3799 { 3800 int rc; 3801 3802 printk(KERN_INFO "%s\n", driver_name); 3803 3804 serial_driver = alloc_tty_driver(MAX_DEVICES); 3805 if (!serial_driver) { 3806 printk("%s can't allocate tty driver\n", driver_name); 3807 return -ENOMEM; 3808 } 3809 3810 /* Initialize the tty_driver structure */ 3811 3812 serial_driver->driver_name = tty_driver_name; 3813 serial_driver->name = tty_dev_prefix; 3814 serial_driver->major = ttymajor; 3815 serial_driver->minor_start = 64; 3816 serial_driver->type = TTY_DRIVER_TYPE_SERIAL; 3817 serial_driver->subtype = SERIAL_TYPE_NORMAL; 3818 serial_driver->init_termios = tty_std_termios; 3819 serial_driver->init_termios.c_cflag = 3820 B9600 | CS8 | CREAD | HUPCL | CLOCAL; 3821 serial_driver->init_termios.c_ispeed = 9600; 3822 serial_driver->init_termios.c_ospeed = 9600; 3823 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV; 3824 tty_set_operations(serial_driver, &ops); 3825 if ((rc = tty_register_driver(serial_driver)) < 0) { 3826 DBGERR(("%s can't register serial driver\n", driver_name)); 3827 put_tty_driver(serial_driver); 3828 serial_driver = NULL; 3829 goto error; 3830 } 3831 3832 printk(KERN_INFO "%s, tty major#%d\n", 3833 driver_name, serial_driver->major); 3834 3835 slgt_device_count = 0; 3836 if ((rc = pci_register_driver(&pci_driver)) < 0) { 3837 printk("%s pci_register_driver error=%d\n", driver_name, rc); 3838 goto error; 3839 } 3840 pci_registered = true; 3841 3842 if (!slgt_device_list) 3843 printk("%s no devices found\n",driver_name); 3844 3845 return 0; 3846 3847 error: 3848 slgt_cleanup(); 3849 return rc; 3850 } 3851 3852 static void __exit slgt_exit(void) 3853 { 3854 slgt_cleanup(); 3855 } 3856 3857 module_init(slgt_init); 3858 module_exit(slgt_exit); 3859 3860 /* 3861 * register access routines 3862 */ 3863 3864 #define CALC_REGADDR() \ 3865 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \ 3866 if (addr >= 0x80) \ 3867 reg_addr += (info->port_num) * 32; \ 3868 else if (addr >= 0x40) \ 3869 reg_addr += (info->port_num) * 16; 3870 3871 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr) 3872 { 3873 CALC_REGADDR(); 3874 return readb((void __iomem *)reg_addr); 3875 } 3876 3877 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value) 3878 { 3879 CALC_REGADDR(); 3880 writeb(value, (void __iomem *)reg_addr); 3881 } 3882 3883 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr) 3884 { 3885 CALC_REGADDR(); 3886 return readw((void __iomem *)reg_addr); 3887 } 3888 3889 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) 3890 { 3891 CALC_REGADDR(); 3892 writew(value, (void __iomem *)reg_addr); 3893 } 3894 3895 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr) 3896 { 3897 CALC_REGADDR(); 3898 return readl((void __iomem *)reg_addr); 3899 } 3900 3901 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) 3902 { 3903 CALC_REGADDR(); 3904 writel(value, (void __iomem *)reg_addr); 3905 } 3906 3907 static void rdma_reset(struct slgt_info *info) 3908 { 3909 unsigned int i; 3910 3911 /* set reset bit */ 3912 wr_reg32(info, RDCSR, BIT1); 3913 3914 /* wait for enable bit cleared */ 3915 for(i=0 ; i < 1000 ; i++) 3916 if (!(rd_reg32(info, RDCSR) & BIT0)) 3917 break; 3918 } 3919 3920 static void tdma_reset(struct slgt_info *info) 3921 { 3922 unsigned int i; 3923 3924 /* set reset bit */ 3925 wr_reg32(info, TDCSR, BIT1); 3926 3927 /* wait for enable bit cleared */ 3928 for(i=0 ; i < 1000 ; i++) 3929 if (!(rd_reg32(info, TDCSR) & BIT0)) 3930 break; 3931 } 3932 3933 /* 3934 * enable internal loopback 3935 * TxCLK and RxCLK are generated from BRG 3936 * and TxD is looped back to RxD internally. 3937 */ 3938 static void enable_loopback(struct slgt_info *info) 3939 { 3940 /* SCR (serial control) BIT2=loopback enable */ 3941 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3942 3943 if (info->params.mode != MGSL_MODE_ASYNC) { 3944 /* CCR (clock control) 3945 * 07..05 tx clock source (010 = BRG) 3946 * 04..02 rx clock source (010 = BRG) 3947 * 01 auxclk enable (0 = disable) 3948 * 00 BRG enable (1 = enable) 3949 * 3950 * 0100 1001 3951 */ 3952 wr_reg8(info, CCR, 0x49); 3953 3954 /* set speed if available, otherwise use default */ 3955 if (info->params.clock_speed) 3956 set_rate(info, info->params.clock_speed); 3957 else 3958 set_rate(info, 3686400); 3959 } 3960 } 3961 3962 /* 3963 * set baud rate generator to specified rate 3964 */ 3965 static void set_rate(struct slgt_info *info, u32 rate) 3966 { 3967 unsigned int div; 3968 unsigned int osc = info->base_clock; 3969 3970 /* div = osc/rate - 1 3971 * 3972 * Round div up if osc/rate is not integer to 3973 * force to next slowest rate. 3974 */ 3975 3976 if (rate) { 3977 div = osc/rate; 3978 if (!(osc % rate) && div) 3979 div--; 3980 wr_reg16(info, BDR, (unsigned short)div); 3981 } 3982 } 3983 3984 static void rx_stop(struct slgt_info *info) 3985 { 3986 unsigned short val; 3987 3988 /* disable and reset receiver */ 3989 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 3990 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3991 wr_reg16(info, RCR, val); /* clear reset bit */ 3992 3993 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE); 3994 3995 /* clear pending rx interrupts */ 3996 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); 3997 3998 rdma_reset(info); 3999 4000 info->rx_enabled = false; 4001 info->rx_restart = false; 4002 } 4003 4004 static void rx_start(struct slgt_info *info) 4005 { 4006 unsigned short val; 4007 4008 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA); 4009 4010 /* clear pending rx overrun IRQ */ 4011 wr_reg16(info, SSR, IRQ_RXOVER); 4012 4013 /* reset and disable receiver */ 4014 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ 4015 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4016 wr_reg16(info, RCR, val); /* clear reset bit */ 4017 4018 rdma_reset(info); 4019 reset_rbufs(info); 4020 4021 if (info->rx_pio) { 4022 /* rx request when rx FIFO not empty */ 4023 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); 4024 slgt_irq_on(info, IRQ_RXDATA); 4025 if (info->params.mode == MGSL_MODE_ASYNC) { 4026 /* enable saving of rx status */ 4027 wr_reg32(info, RDCSR, BIT6); 4028 } 4029 } else { 4030 /* rx request when rx FIFO half full */ 4031 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); 4032 /* set 1st descriptor address */ 4033 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); 4034 4035 if (info->params.mode != MGSL_MODE_ASYNC) { 4036 /* enable rx DMA and DMA interrupt */ 4037 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 4038 } else { 4039 /* enable saving of rx status, rx DMA and DMA interrupt */ 4040 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 4041 } 4042 } 4043 4044 slgt_irq_on(info, IRQ_RXOVER); 4045 4046 /* enable receiver */ 4047 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); 4048 4049 info->rx_restart = false; 4050 info->rx_enabled = true; 4051 } 4052 4053 static void tx_start(struct slgt_info *info) 4054 { 4055 if (!info->tx_enabled) { 4056 wr_reg16(info, TCR, 4057 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); 4058 info->tx_enabled = true; 4059 } 4060 4061 if (desc_count(info->tbufs[info->tbuf_start])) { 4062 info->drop_rts_on_tx_done = false; 4063 4064 if (info->params.mode != MGSL_MODE_ASYNC) { 4065 if (info->params.flags & HDLC_FLAG_AUTO_RTS) { 4066 get_signals(info); 4067 if (!(info->signals & SerialSignal_RTS)) { 4068 info->signals |= SerialSignal_RTS; 4069 set_signals(info); 4070 info->drop_rts_on_tx_done = true; 4071 } 4072 } 4073 4074 slgt_irq_off(info, IRQ_TXDATA); 4075 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE); 4076 /* clear tx idle and underrun status bits */ 4077 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4078 } else { 4079 slgt_irq_off(info, IRQ_TXDATA); 4080 slgt_irq_on(info, IRQ_TXIDLE); 4081 /* clear tx idle status bit */ 4082 wr_reg16(info, SSR, IRQ_TXIDLE); 4083 } 4084 /* set 1st descriptor address and start DMA */ 4085 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); 4086 wr_reg32(info, TDCSR, BIT2 + BIT0); 4087 info->tx_active = true; 4088 } 4089 } 4090 4091 static void tx_stop(struct slgt_info *info) 4092 { 4093 unsigned short val; 4094 4095 del_timer(&info->tx_timer); 4096 4097 tdma_reset(info); 4098 4099 /* reset and disable transmitter */ 4100 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ 4101 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 4102 4103 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER); 4104 4105 /* clear tx idle and underrun status bit */ 4106 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); 4107 4108 reset_tbufs(info); 4109 4110 info->tx_enabled = false; 4111 info->tx_active = false; 4112 } 4113 4114 static void reset_port(struct slgt_info *info) 4115 { 4116 if (!info->reg_addr) 4117 return; 4118 4119 tx_stop(info); 4120 rx_stop(info); 4121 4122 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); 4123 set_signals(info); 4124 4125 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4126 } 4127 4128 static void reset_adapter(struct slgt_info *info) 4129 { 4130 int i; 4131 for (i=0; i < info->port_count; ++i) { 4132 if (info->port_array[i]) 4133 reset_port(info->port_array[i]); 4134 } 4135 } 4136 4137 static void async_mode(struct slgt_info *info) 4138 { 4139 unsigned short val; 4140 4141 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4142 tx_stop(info); 4143 rx_stop(info); 4144 4145 /* TCR (tx control) 4146 * 4147 * 15..13 mode, 010=async 4148 * 12..10 encoding, 000=NRZ 4149 * 09 parity enable 4150 * 08 1=odd parity, 0=even parity 4151 * 07 1=RTS driver control 4152 * 06 1=break enable 4153 * 05..04 character length 4154 * 00=5 bits 4155 * 01=6 bits 4156 * 10=7 bits 4157 * 11=8 bits 4158 * 03 0=1 stop bit, 1=2 stop bits 4159 * 02 reset 4160 * 01 enable 4161 * 00 auto-CTS enable 4162 */ 4163 val = 0x4000; 4164 4165 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4166 val |= BIT7; 4167 4168 if (info->params.parity != ASYNC_PARITY_NONE) { 4169 val |= BIT9; 4170 if (info->params.parity == ASYNC_PARITY_ODD) 4171 val |= BIT8; 4172 } 4173 4174 switch (info->params.data_bits) 4175 { 4176 case 6: val |= BIT4; break; 4177 case 7: val |= BIT5; break; 4178 case 8: val |= BIT5 + BIT4; break; 4179 } 4180 4181 if (info->params.stop_bits != 1) 4182 val |= BIT3; 4183 4184 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4185 val |= BIT0; 4186 4187 wr_reg16(info, TCR, val); 4188 4189 /* RCR (rx control) 4190 * 4191 * 15..13 mode, 010=async 4192 * 12..10 encoding, 000=NRZ 4193 * 09 parity enable 4194 * 08 1=odd parity, 0=even parity 4195 * 07..06 reserved, must be 0 4196 * 05..04 character length 4197 * 00=5 bits 4198 * 01=6 bits 4199 * 10=7 bits 4200 * 11=8 bits 4201 * 03 reserved, must be zero 4202 * 02 reset 4203 * 01 enable 4204 * 00 auto-DCD enable 4205 */ 4206 val = 0x4000; 4207 4208 if (info->params.parity != ASYNC_PARITY_NONE) { 4209 val |= BIT9; 4210 if (info->params.parity == ASYNC_PARITY_ODD) 4211 val |= BIT8; 4212 } 4213 4214 switch (info->params.data_bits) 4215 { 4216 case 6: val |= BIT4; break; 4217 case 7: val |= BIT5; break; 4218 case 8: val |= BIT5 + BIT4; break; 4219 } 4220 4221 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4222 val |= BIT0; 4223 4224 wr_reg16(info, RCR, val); 4225 4226 /* CCR (clock control) 4227 * 4228 * 07..05 011 = tx clock source is BRG/16 4229 * 04..02 010 = rx clock source is BRG 4230 * 01 0 = auxclk disabled 4231 * 00 1 = BRG enabled 4232 * 4233 * 0110 1001 4234 */ 4235 wr_reg8(info, CCR, 0x69); 4236 4237 msc_set_vcr(info); 4238 4239 /* SCR (serial control) 4240 * 4241 * 15 1=tx req on FIFO half empty 4242 * 14 1=rx req on FIFO half full 4243 * 13 tx data IRQ enable 4244 * 12 tx idle IRQ enable 4245 * 11 rx break on IRQ enable 4246 * 10 rx data IRQ enable 4247 * 09 rx break off IRQ enable 4248 * 08 overrun IRQ enable 4249 * 07 DSR IRQ enable 4250 * 06 CTS IRQ enable 4251 * 05 DCD IRQ enable 4252 * 04 RI IRQ enable 4253 * 03 0=16x sampling, 1=8x sampling 4254 * 02 1=txd->rxd internal loopback enable 4255 * 01 reserved, must be zero 4256 * 00 1=master IRQ enable 4257 */ 4258 val = BIT15 + BIT14 + BIT0; 4259 /* JCR[8] : 1 = x8 async mode feature available */ 4260 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && 4261 ((info->base_clock < (info->params.data_rate * 16)) || 4262 (info->base_clock % (info->params.data_rate * 16)))) { 4263 /* use 8x sampling */ 4264 val |= BIT3; 4265 set_rate(info, info->params.data_rate * 8); 4266 } else { 4267 /* use 16x sampling */ 4268 set_rate(info, info->params.data_rate * 16); 4269 } 4270 wr_reg16(info, SCR, val); 4271 4272 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER); 4273 4274 if (info->params.loopback) 4275 enable_loopback(info); 4276 } 4277 4278 static void sync_mode(struct slgt_info *info) 4279 { 4280 unsigned short val; 4281 4282 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER); 4283 tx_stop(info); 4284 rx_stop(info); 4285 4286 /* TCR (tx control) 4287 * 4288 * 15..13 mode 4289 * 000=HDLC/SDLC 4290 * 001=raw bit synchronous 4291 * 010=asynchronous/isochronous 4292 * 011=monosync byte synchronous 4293 * 100=bisync byte synchronous 4294 * 101=xsync byte synchronous 4295 * 12..10 encoding 4296 * 09 CRC enable 4297 * 08 CRC32 4298 * 07 1=RTS driver control 4299 * 06 preamble enable 4300 * 05..04 preamble length 4301 * 03 share open/close flag 4302 * 02 reset 4303 * 01 enable 4304 * 00 auto-CTS enable 4305 */ 4306 val = BIT2; 4307 4308 switch(info->params.mode) { 4309 case MGSL_MODE_XSYNC: 4310 val |= BIT15 + BIT13; 4311 break; 4312 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4313 case MGSL_MODE_BISYNC: val |= BIT15; break; 4314 case MGSL_MODE_RAW: val |= BIT13; break; 4315 } 4316 if (info->if_mode & MGSL_INTERFACE_RTS_EN) 4317 val |= BIT7; 4318 4319 switch(info->params.encoding) 4320 { 4321 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4322 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4323 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4324 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4325 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4326 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4327 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4328 } 4329 4330 switch (info->params.crc_type & HDLC_CRC_MASK) 4331 { 4332 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4333 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4334 } 4335 4336 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE) 4337 val |= BIT6; 4338 4339 switch (info->params.preamble_length) 4340 { 4341 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break; 4342 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; 4343 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; 4344 } 4345 4346 if (info->params.flags & HDLC_FLAG_AUTO_CTS) 4347 val |= BIT0; 4348 4349 wr_reg16(info, TCR, val); 4350 4351 /* TPR (transmit preamble) */ 4352 4353 switch (info->params.preamble) 4354 { 4355 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break; 4356 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break; 4357 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break; 4358 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break; 4359 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break; 4360 default: val = 0x7e; break; 4361 } 4362 wr_reg8(info, TPR, (unsigned char)val); 4363 4364 /* RCR (rx control) 4365 * 4366 * 15..13 mode 4367 * 000=HDLC/SDLC 4368 * 001=raw bit synchronous 4369 * 010=asynchronous/isochronous 4370 * 011=monosync byte synchronous 4371 * 100=bisync byte synchronous 4372 * 101=xsync byte synchronous 4373 * 12..10 encoding 4374 * 09 CRC enable 4375 * 08 CRC32 4376 * 07..03 reserved, must be 0 4377 * 02 reset 4378 * 01 enable 4379 * 00 auto-DCD enable 4380 */ 4381 val = 0; 4382 4383 switch(info->params.mode) { 4384 case MGSL_MODE_XSYNC: 4385 val |= BIT15 + BIT13; 4386 break; 4387 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break; 4388 case MGSL_MODE_BISYNC: val |= BIT15; break; 4389 case MGSL_MODE_RAW: val |= BIT13; break; 4390 } 4391 4392 switch(info->params.encoding) 4393 { 4394 case HDLC_ENCODING_NRZB: val |= BIT10; break; 4395 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; 4396 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; 4397 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; 4398 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; 4399 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; 4400 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; 4401 } 4402 4403 switch (info->params.crc_type & HDLC_CRC_MASK) 4404 { 4405 case HDLC_CRC_16_CCITT: val |= BIT9; break; 4406 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; 4407 } 4408 4409 if (info->params.flags & HDLC_FLAG_AUTO_DCD) 4410 val |= BIT0; 4411 4412 wr_reg16(info, RCR, val); 4413 4414 /* CCR (clock control) 4415 * 4416 * 07..05 tx clock source 4417 * 04..02 rx clock source 4418 * 01 auxclk enable 4419 * 00 BRG enable 4420 */ 4421 val = 0; 4422 4423 if (info->params.flags & HDLC_FLAG_TXC_BRG) 4424 { 4425 // when RxC source is DPLL, BRG generates 16X DPLL 4426 // reference clock, so take TxC from BRG/16 to get 4427 // transmit clock at actual data rate 4428 if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4429 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ 4430 else 4431 val |= BIT6; /* 010, txclk = BRG */ 4432 } 4433 else if (info->params.flags & HDLC_FLAG_TXC_DPLL) 4434 val |= BIT7; /* 100, txclk = DPLL Input */ 4435 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN) 4436 val |= BIT5; /* 001, txclk = RXC Input */ 4437 4438 if (info->params.flags & HDLC_FLAG_RXC_BRG) 4439 val |= BIT3; /* 010, rxclk = BRG */ 4440 else if (info->params.flags & HDLC_FLAG_RXC_DPLL) 4441 val |= BIT4; /* 100, rxclk = DPLL */ 4442 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN) 4443 val |= BIT2; /* 001, rxclk = TXC Input */ 4444 4445 if (info->params.clock_speed) 4446 val |= BIT1 + BIT0; 4447 4448 wr_reg8(info, CCR, (unsigned char)val); 4449 4450 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL)) 4451 { 4452 // program DPLL mode 4453 switch(info->params.encoding) 4454 { 4455 case HDLC_ENCODING_BIPHASE_MARK: 4456 case HDLC_ENCODING_BIPHASE_SPACE: 4457 val = BIT7; break; 4458 case HDLC_ENCODING_BIPHASE_LEVEL: 4459 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: 4460 val = BIT7 + BIT6; break; 4461 default: val = BIT6; // NRZ encodings 4462 } 4463 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); 4464 4465 // DPLL requires a 16X reference clock from BRG 4466 set_rate(info, info->params.clock_speed * 16); 4467 } 4468 else 4469 set_rate(info, info->params.clock_speed); 4470 4471 tx_set_idle(info); 4472 4473 msc_set_vcr(info); 4474 4475 /* SCR (serial control) 4476 * 4477 * 15 1=tx req on FIFO half empty 4478 * 14 1=rx req on FIFO half full 4479 * 13 tx data IRQ enable 4480 * 12 tx idle IRQ enable 4481 * 11 underrun IRQ enable 4482 * 10 rx data IRQ enable 4483 * 09 rx idle IRQ enable 4484 * 08 overrun IRQ enable 4485 * 07 DSR IRQ enable 4486 * 06 CTS IRQ enable 4487 * 05 DCD IRQ enable 4488 * 04 RI IRQ enable 4489 * 03 reserved, must be zero 4490 * 02 1=txd->rxd internal loopback enable 4491 * 01 reserved, must be zero 4492 * 00 1=master IRQ enable 4493 */ 4494 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); 4495 4496 if (info->params.loopback) 4497 enable_loopback(info); 4498 } 4499 4500 /* 4501 * set transmit idle mode 4502 */ 4503 static void tx_set_idle(struct slgt_info *info) 4504 { 4505 unsigned char val; 4506 unsigned short tcr; 4507 4508 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits 4509 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits 4510 */ 4511 tcr = rd_reg16(info, TCR); 4512 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) { 4513 /* disable preamble, set idle size to 16 bits */ 4514 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; 4515 /* MSB of 16 bit idle specified in tx preamble register (TPR) */ 4516 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff)); 4517 } else if (!(tcr & BIT6)) { 4518 /* preamble is disabled, set idle size to 8 bits */ 4519 tcr &= ~(BIT5 + BIT4); 4520 } 4521 wr_reg16(info, TCR, tcr); 4522 4523 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) { 4524 /* LSB of custom tx idle specified in tx idle register */ 4525 val = (unsigned char)(info->idle_mode & 0xff); 4526 } else { 4527 /* standard 8 bit idle patterns */ 4528 switch(info->idle_mode) 4529 { 4530 case HDLC_TXIDLE_FLAGS: val = 0x7e; break; 4531 case HDLC_TXIDLE_ALT_ZEROS_ONES: 4532 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break; 4533 case HDLC_TXIDLE_ZEROS: 4534 case HDLC_TXIDLE_SPACE: val = 0x00; break; 4535 default: val = 0xff; 4536 } 4537 } 4538 4539 wr_reg8(info, TIR, val); 4540 } 4541 4542 /* 4543 * get state of V24 status (input) signals 4544 */ 4545 static void get_signals(struct slgt_info *info) 4546 { 4547 unsigned short status = rd_reg16(info, SSR); 4548 4549 /* clear all serial signals except RTS and DTR */ 4550 info->signals &= SerialSignal_RTS | SerialSignal_DTR; 4551 4552 if (status & BIT3) 4553 info->signals |= SerialSignal_DSR; 4554 if (status & BIT2) 4555 info->signals |= SerialSignal_CTS; 4556 if (status & BIT1) 4557 info->signals |= SerialSignal_DCD; 4558 if (status & BIT0) 4559 info->signals |= SerialSignal_RI; 4560 } 4561 4562 /* 4563 * set V.24 Control Register based on current configuration 4564 */ 4565 static void msc_set_vcr(struct slgt_info *info) 4566 { 4567 unsigned char val = 0; 4568 4569 /* VCR (V.24 control) 4570 * 4571 * 07..04 serial IF select 4572 * 03 DTR 4573 * 02 RTS 4574 * 01 LL 4575 * 00 RL 4576 */ 4577 4578 switch(info->if_mode & MGSL_INTERFACE_MASK) 4579 { 4580 case MGSL_INTERFACE_RS232: 4581 val |= BIT5; /* 0010 */ 4582 break; 4583 case MGSL_INTERFACE_V35: 4584 val |= BIT7 + BIT6 + BIT5; /* 1110 */ 4585 break; 4586 case MGSL_INTERFACE_RS422: 4587 val |= BIT6; /* 0100 */ 4588 break; 4589 } 4590 4591 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST) 4592 val |= BIT4; 4593 if (info->signals & SerialSignal_DTR) 4594 val |= BIT3; 4595 if (info->signals & SerialSignal_RTS) 4596 val |= BIT2; 4597 if (info->if_mode & MGSL_INTERFACE_LL) 4598 val |= BIT1; 4599 if (info->if_mode & MGSL_INTERFACE_RL) 4600 val |= BIT0; 4601 wr_reg8(info, VCR, val); 4602 } 4603 4604 /* 4605 * set state of V24 control (output) signals 4606 */ 4607 static void set_signals(struct slgt_info *info) 4608 { 4609 unsigned char val = rd_reg8(info, VCR); 4610 if (info->signals & SerialSignal_DTR) 4611 val |= BIT3; 4612 else 4613 val &= ~BIT3; 4614 if (info->signals & SerialSignal_RTS) 4615 val |= BIT2; 4616 else 4617 val &= ~BIT2; 4618 wr_reg8(info, VCR, val); 4619 } 4620 4621 /* 4622 * free range of receive DMA buffers (i to last) 4623 */ 4624 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last) 4625 { 4626 int done = 0; 4627 4628 while(!done) { 4629 /* reset current buffer for reuse */ 4630 info->rbufs[i].status = 0; 4631 set_desc_count(info->rbufs[i], info->rbuf_fill_level); 4632 if (i == last) 4633 done = 1; 4634 if (++i == info->rbuf_count) 4635 i = 0; 4636 } 4637 info->rbuf_current = i; 4638 } 4639 4640 /* 4641 * mark all receive DMA buffers as free 4642 */ 4643 static void reset_rbufs(struct slgt_info *info) 4644 { 4645 free_rbufs(info, 0, info->rbuf_count - 1); 4646 info->rbuf_fill_index = 0; 4647 info->rbuf_fill_count = 0; 4648 } 4649 4650 /* 4651 * pass receive HDLC frame to upper layer 4652 * 4653 * return true if frame available, otherwise false 4654 */ 4655 static bool rx_get_frame(struct slgt_info *info) 4656 { 4657 unsigned int start, end; 4658 unsigned short status; 4659 unsigned int framesize = 0; 4660 unsigned long flags; 4661 struct tty_struct *tty = info->port.tty; 4662 unsigned char addr_field = 0xff; 4663 unsigned int crc_size = 0; 4664 4665 switch (info->params.crc_type & HDLC_CRC_MASK) { 4666 case HDLC_CRC_16_CCITT: crc_size = 2; break; 4667 case HDLC_CRC_32_CCITT: crc_size = 4; break; 4668 } 4669 4670 check_again: 4671 4672 framesize = 0; 4673 addr_field = 0xff; 4674 start = end = info->rbuf_current; 4675 4676 for (;;) { 4677 if (!desc_complete(info->rbufs[end])) 4678 goto cleanup; 4679 4680 if (framesize == 0 && info->params.addr_filter != 0xff) 4681 addr_field = info->rbufs[end].buf[0]; 4682 4683 framesize += desc_count(info->rbufs[end]); 4684 4685 if (desc_eof(info->rbufs[end])) 4686 break; 4687 4688 if (++end == info->rbuf_count) 4689 end = 0; 4690 4691 if (end == info->rbuf_current) { 4692 if (info->rx_enabled){ 4693 spin_lock_irqsave(&info->lock,flags); 4694 rx_start(info); 4695 spin_unlock_irqrestore(&info->lock,flags); 4696 } 4697 goto cleanup; 4698 } 4699 } 4700 4701 /* status 4702 * 4703 * 15 buffer complete 4704 * 14..06 reserved 4705 * 05..04 residue 4706 * 02 eof (end of frame) 4707 * 01 CRC error 4708 * 00 abort 4709 */ 4710 status = desc_status(info->rbufs[end]); 4711 4712 /* ignore CRC bit if not using CRC (bit is undefined) */ 4713 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE) 4714 status &= ~BIT1; 4715 4716 if (framesize == 0 || 4717 (addr_field != 0xff && addr_field != info->params.addr_filter)) { 4718 free_rbufs(info, start, end); 4719 goto check_again; 4720 } 4721 4722 if (framesize < (2 + crc_size) || status & BIT0) { 4723 info->icount.rxshort++; 4724 framesize = 0; 4725 } else if (status & BIT1) { 4726 info->icount.rxcrc++; 4727 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) 4728 framesize = 0; 4729 } 4730 4731 #if SYNCLINK_GENERIC_HDLC 4732 if (framesize == 0) { 4733 info->netdev->stats.rx_errors++; 4734 info->netdev->stats.rx_frame_errors++; 4735 } 4736 #endif 4737 4738 DBGBH(("%s rx frame status=%04X size=%d\n", 4739 info->device_name, status, framesize)); 4740 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx"); 4741 4742 if (framesize) { 4743 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) { 4744 framesize -= crc_size; 4745 crc_size = 0; 4746 } 4747 4748 if (framesize > info->max_frame_size + crc_size) 4749 info->icount.rxlong++; 4750 else { 4751 /* copy dma buffer(s) to contiguous temp buffer */ 4752 int copy_count = framesize; 4753 int i = start; 4754 unsigned char *p = info->tmp_rbuf; 4755 info->tmp_rbuf_count = framesize; 4756 4757 info->icount.rxok++; 4758 4759 while(copy_count) { 4760 int partial_count = min_t(int, copy_count, info->rbuf_fill_level); 4761 memcpy(p, info->rbufs[i].buf, partial_count); 4762 p += partial_count; 4763 copy_count -= partial_count; 4764 if (++i == info->rbuf_count) 4765 i = 0; 4766 } 4767 4768 if (info->params.crc_type & HDLC_CRC_RETURN_EX) { 4769 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK; 4770 framesize++; 4771 } 4772 4773 #if SYNCLINK_GENERIC_HDLC 4774 if (info->netcount) 4775 hdlcdev_rx(info,info->tmp_rbuf, framesize); 4776 else 4777 #endif 4778 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize); 4779 } 4780 } 4781 free_rbufs(info, start, end); 4782 return true; 4783 4784 cleanup: 4785 return false; 4786 } 4787 4788 /* 4789 * pass receive buffer (RAW synchronous mode) to tty layer 4790 * return true if buffer available, otherwise false 4791 */ 4792 static bool rx_get_buf(struct slgt_info *info) 4793 { 4794 unsigned int i = info->rbuf_current; 4795 unsigned int count; 4796 4797 if (!desc_complete(info->rbufs[i])) 4798 return false; 4799 count = desc_count(info->rbufs[i]); 4800 switch(info->params.mode) { 4801 case MGSL_MODE_MONOSYNC: 4802 case MGSL_MODE_BISYNC: 4803 case MGSL_MODE_XSYNC: 4804 /* ignore residue in byte synchronous modes */ 4805 if (desc_residue(info->rbufs[i])) 4806 count--; 4807 break; 4808 } 4809 DBGDATA(info, info->rbufs[i].buf, count, "rx"); 4810 DBGINFO(("rx_get_buf size=%d\n", count)); 4811 if (count) 4812 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, 4813 info->flag_buf, count); 4814 free_rbufs(info, i, i); 4815 return true; 4816 } 4817 4818 static void reset_tbufs(struct slgt_info *info) 4819 { 4820 unsigned int i; 4821 info->tbuf_current = 0; 4822 for (i=0 ; i < info->tbuf_count ; i++) { 4823 info->tbufs[i].status = 0; 4824 info->tbufs[i].count = 0; 4825 } 4826 } 4827 4828 /* 4829 * return number of free transmit DMA buffers 4830 */ 4831 static unsigned int free_tbuf_count(struct slgt_info *info) 4832 { 4833 unsigned int count = 0; 4834 unsigned int i = info->tbuf_current; 4835 4836 do 4837 { 4838 if (desc_count(info->tbufs[i])) 4839 break; /* buffer in use */ 4840 ++count; 4841 if (++i == info->tbuf_count) 4842 i=0; 4843 } while (i != info->tbuf_current); 4844 4845 /* if tx DMA active, last zero count buffer is in use */ 4846 if (count && (rd_reg32(info, TDCSR) & BIT0)) 4847 --count; 4848 4849 return count; 4850 } 4851 4852 /* 4853 * return number of bytes in unsent transmit DMA buffers 4854 * and the serial controller tx FIFO 4855 */ 4856 static unsigned int tbuf_bytes(struct slgt_info *info) 4857 { 4858 unsigned int total_count = 0; 4859 unsigned int i = info->tbuf_current; 4860 unsigned int reg_value; 4861 unsigned int count; 4862 unsigned int active_buf_count = 0; 4863 4864 /* 4865 * Add descriptor counts for all tx DMA buffers. 4866 * If count is zero (cleared by DMA controller after read), 4867 * the buffer is complete or is actively being read from. 4868 * 4869 * Record buf_count of last buffer with zero count starting 4870 * from current ring position. buf_count is mirror 4871 * copy of count and is not cleared by serial controller. 4872 * If DMA controller is active, that buffer is actively 4873 * being read so add to total. 4874 */ 4875 do { 4876 count = desc_count(info->tbufs[i]); 4877 if (count) 4878 total_count += count; 4879 else if (!total_count) 4880 active_buf_count = info->tbufs[i].buf_count; 4881 if (++i == info->tbuf_count) 4882 i = 0; 4883 } while (i != info->tbuf_current); 4884 4885 /* read tx DMA status register */ 4886 reg_value = rd_reg32(info, TDCSR); 4887 4888 /* if tx DMA active, last zero count buffer is in use */ 4889 if (reg_value & BIT0) 4890 total_count += active_buf_count; 4891 4892 /* add tx FIFO count = reg_value[15..8] */ 4893 total_count += (reg_value >> 8) & 0xff; 4894 4895 /* if transmitter active add one byte for shift register */ 4896 if (info->tx_active) 4897 total_count++; 4898 4899 return total_count; 4900 } 4901 4902 /* 4903 * load data into transmit DMA buffer ring and start transmitter if needed 4904 * return true if data accepted, otherwise false (buffers full) 4905 */ 4906 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size) 4907 { 4908 unsigned short count; 4909 unsigned int i; 4910 struct slgt_desc *d; 4911 4912 /* check required buffer space */ 4913 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info)) 4914 return false; 4915 4916 DBGDATA(info, buf, size, "tx"); 4917 4918 /* 4919 * copy data to one or more DMA buffers in circular ring 4920 * tbuf_start = first buffer for this data 4921 * tbuf_current = next free buffer 4922 * 4923 * Copy all data before making data visible to DMA controller by 4924 * setting descriptor count of the first buffer. 4925 * This prevents an active DMA controller from reading the first DMA 4926 * buffers of a frame and stopping before the final buffers are filled. 4927 */ 4928 4929 info->tbuf_start = i = info->tbuf_current; 4930 4931 while (size) { 4932 d = &info->tbufs[i]; 4933 4934 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size); 4935 memcpy(d->buf, buf, count); 4936 4937 size -= count; 4938 buf += count; 4939 4940 /* 4941 * set EOF bit for last buffer of HDLC frame or 4942 * for every buffer in raw mode 4943 */ 4944 if ((!size && info->params.mode == MGSL_MODE_HDLC) || 4945 info->params.mode == MGSL_MODE_RAW) 4946 set_desc_eof(*d, 1); 4947 else 4948 set_desc_eof(*d, 0); 4949 4950 /* set descriptor count for all but first buffer */ 4951 if (i != info->tbuf_start) 4952 set_desc_count(*d, count); 4953 d->buf_count = count; 4954 4955 if (++i == info->tbuf_count) 4956 i = 0; 4957 } 4958 4959 info->tbuf_current = i; 4960 4961 /* set first buffer count to make new data visible to DMA controller */ 4962 d = &info->tbufs[info->tbuf_start]; 4963 set_desc_count(*d, d->buf_count); 4964 4965 /* start transmitter if needed and update transmit timeout */ 4966 if (!info->tx_active) 4967 tx_start(info); 4968 update_tx_timer(info); 4969 4970 return true; 4971 } 4972 4973 static int register_test(struct slgt_info *info) 4974 { 4975 static unsigned short patterns[] = 4976 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696}; 4977 static unsigned int count = ARRAY_SIZE(patterns); 4978 unsigned int i; 4979 int rc = 0; 4980 4981 for (i=0 ; i < count ; i++) { 4982 wr_reg16(info, TIR, patterns[i]); 4983 wr_reg16(info, BDR, patterns[(i+1)%count]); 4984 if ((rd_reg16(info, TIR) != patterns[i]) || 4985 (rd_reg16(info, BDR) != patterns[(i+1)%count])) { 4986 rc = -ENODEV; 4987 break; 4988 } 4989 } 4990 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0; 4991 info->init_error = rc ? 0 : DiagStatus_AddressFailure; 4992 return rc; 4993 } 4994 4995 static int irq_test(struct slgt_info *info) 4996 { 4997 unsigned long timeout; 4998 unsigned long flags; 4999 struct tty_struct *oldtty = info->port.tty; 5000 u32 speed = info->params.data_rate; 5001 5002 info->params.data_rate = 921600; 5003 info->port.tty = NULL; 5004 5005 spin_lock_irqsave(&info->lock, flags); 5006 async_mode(info); 5007 slgt_irq_on(info, IRQ_TXIDLE); 5008 5009 /* enable transmitter */ 5010 wr_reg16(info, TCR, 5011 (unsigned short)(rd_reg16(info, TCR) | BIT1)); 5012 5013 /* write one byte and wait for tx idle */ 5014 wr_reg16(info, TDR, 0); 5015 5016 /* assume failure */ 5017 info->init_error = DiagStatus_IrqFailure; 5018 info->irq_occurred = false; 5019 5020 spin_unlock_irqrestore(&info->lock, flags); 5021 5022 timeout=100; 5023 while(timeout-- && !info->irq_occurred) 5024 msleep_interruptible(10); 5025 5026 spin_lock_irqsave(&info->lock,flags); 5027 reset_port(info); 5028 spin_unlock_irqrestore(&info->lock,flags); 5029 5030 info->params.data_rate = speed; 5031 info->port.tty = oldtty; 5032 5033 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure; 5034 return info->irq_occurred ? 0 : -ENODEV; 5035 } 5036 5037 static int loopback_test_rx(struct slgt_info *info) 5038 { 5039 unsigned char *src, *dest; 5040 int count; 5041 5042 if (desc_complete(info->rbufs[0])) { 5043 count = desc_count(info->rbufs[0]); 5044 src = info->rbufs[0].buf; 5045 dest = info->tmp_rbuf; 5046 5047 for( ; count ; count-=2, src+=2) { 5048 /* src=data byte (src+1)=status byte */ 5049 if (!(*(src+1) & (BIT9 + BIT8))) { 5050 *dest = *src; 5051 dest++; 5052 info->tmp_rbuf_count++; 5053 } 5054 } 5055 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx"); 5056 return 1; 5057 } 5058 return 0; 5059 } 5060 5061 static int loopback_test(struct slgt_info *info) 5062 { 5063 #define TESTFRAMESIZE 20 5064 5065 unsigned long timeout; 5066 u16 count = TESTFRAMESIZE; 5067 unsigned char buf[TESTFRAMESIZE]; 5068 int rc = -ENODEV; 5069 unsigned long flags; 5070 5071 struct tty_struct *oldtty = info->port.tty; 5072 MGSL_PARAMS params; 5073 5074 memcpy(¶ms, &info->params, sizeof(params)); 5075 5076 info->params.mode = MGSL_MODE_ASYNC; 5077 info->params.data_rate = 921600; 5078 info->params.loopback = 1; 5079 info->port.tty = NULL; 5080 5081 /* build and send transmit frame */ 5082 for (count = 0; count < TESTFRAMESIZE; ++count) 5083 buf[count] = (unsigned char)count; 5084 5085 info->tmp_rbuf_count = 0; 5086 memset(info->tmp_rbuf, 0, TESTFRAMESIZE); 5087 5088 /* program hardware for HDLC and enabled receiver */ 5089 spin_lock_irqsave(&info->lock,flags); 5090 async_mode(info); 5091 rx_start(info); 5092 tx_load(info, buf, count); 5093 spin_unlock_irqrestore(&info->lock, flags); 5094 5095 /* wait for receive complete */ 5096 for (timeout = 100; timeout; --timeout) { 5097 msleep_interruptible(10); 5098 if (loopback_test_rx(info)) { 5099 rc = 0; 5100 break; 5101 } 5102 } 5103 5104 /* verify received frame length and contents */ 5105 if (!rc && (info->tmp_rbuf_count != count || 5106 memcmp(buf, info->tmp_rbuf, count))) { 5107 rc = -ENODEV; 5108 } 5109 5110 spin_lock_irqsave(&info->lock,flags); 5111 reset_adapter(info); 5112 spin_unlock_irqrestore(&info->lock,flags); 5113 5114 memcpy(&info->params, ¶ms, sizeof(info->params)); 5115 info->port.tty = oldtty; 5116 5117 info->init_error = rc ? DiagStatus_DmaFailure : 0; 5118 return rc; 5119 } 5120 5121 static int adapter_test(struct slgt_info *info) 5122 { 5123 DBGINFO(("testing %s\n", info->device_name)); 5124 if (register_test(info) < 0) { 5125 printk("register test failure %s addr=%08X\n", 5126 info->device_name, info->phys_reg_addr); 5127 } else if (irq_test(info) < 0) { 5128 printk("IRQ test failure %s IRQ=%d\n", 5129 info->device_name, info->irq_level); 5130 } else if (loopback_test(info) < 0) { 5131 printk("loopback test failure %s\n", info->device_name); 5132 } 5133 return info->init_error; 5134 } 5135 5136 /* 5137 * transmit timeout handler 5138 */ 5139 static void tx_timeout(unsigned long context) 5140 { 5141 struct slgt_info *info = (struct slgt_info*)context; 5142 unsigned long flags; 5143 5144 DBGINFO(("%s tx_timeout\n", info->device_name)); 5145 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { 5146 info->icount.txtimeout++; 5147 } 5148 spin_lock_irqsave(&info->lock,flags); 5149 tx_stop(info); 5150 spin_unlock_irqrestore(&info->lock,flags); 5151 5152 #if SYNCLINK_GENERIC_HDLC 5153 if (info->netcount) 5154 hdlcdev_tx_done(info); 5155 else 5156 #endif 5157 bh_transmit(info); 5158 } 5159 5160 /* 5161 * receive buffer polling timer 5162 */ 5163 static void rx_timeout(unsigned long context) 5164 { 5165 struct slgt_info *info = (struct slgt_info*)context; 5166 unsigned long flags; 5167 5168 DBGINFO(("%s rx_timeout\n", info->device_name)); 5169 spin_lock_irqsave(&info->lock, flags); 5170 info->pending_bh |= BH_RECEIVE; 5171 spin_unlock_irqrestore(&info->lock, flags); 5172 bh_handler(&info->task); 5173 } 5174 5175