1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18 #undef DEBUG 19 20 #include <linux/clk.h> 21 #include <linux/console.h> 22 #include <linux/ctype.h> 23 #include <linux/cpufreq.h> 24 #include <linux/delay.h> 25 #include <linux/dmaengine.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/err.h> 28 #include <linux/errno.h> 29 #include <linux/init.h> 30 #include <linux/interrupt.h> 31 #include <linux/ioport.h> 32 #include <linux/ktime.h> 33 #include <linux/major.h> 34 #include <linux/module.h> 35 #include <linux/mm.h> 36 #include <linux/of.h> 37 #include <linux/of_device.h> 38 #include <linux/platform_device.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/scatterlist.h> 41 #include <linux/serial.h> 42 #include <linux/serial_sci.h> 43 #include <linux/sh_dma.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/sysrq.h> 47 #include <linux/timer.h> 48 #include <linux/tty.h> 49 #include <linux/tty_flip.h> 50 51 #ifdef CONFIG_SUPERH 52 #include <asm/sh_bios.h> 53 #include <asm/platform_early.h> 54 #endif 55 56 #include "serial_mctrl_gpio.h" 57 #include "sh-sci.h" 58 59 /* Offsets into the sci_port->irqs array */ 60 enum { 61 SCIx_ERI_IRQ, 62 SCIx_RXI_IRQ, 63 SCIx_TXI_IRQ, 64 SCIx_BRI_IRQ, 65 SCIx_DRI_IRQ, 66 SCIx_TEI_IRQ, 67 SCIx_NR_IRQS, 68 69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 70 }; 71 72 #define SCIx_IRQ_IS_MUXED(port) \ 73 ((port)->irqs[SCIx_ERI_IRQ] == \ 74 (port)->irqs[SCIx_RXI_IRQ]) || \ 75 ((port)->irqs[SCIx_ERI_IRQ] && \ 76 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 77 78 enum SCI_CLKS { 79 SCI_FCK, /* Functional Clock */ 80 SCI_SCK, /* Optional External Clock */ 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 83 SCI_NUM_CLKS 84 }; 85 86 /* Bit x set means sampling rate x + 1 is supported */ 87 #define SCI_SR(x) BIT((x) - 1) 88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 89 90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 92 SCI_SR(19) | SCI_SR(27) 93 94 #define min_sr(_port) ffs((_port)->sampling_rate_mask) 95 #define max_sr(_port) fls((_port)->sampling_rate_mask) 96 97 /* Iterate over all supported sampling rates, from high to low */ 98 #define for_each_sr(_sr, _port) \ 99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 100 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 101 102 struct plat_sci_reg { 103 u8 offset, size; 104 }; 105 106 struct sci_port_params { 107 const struct plat_sci_reg regs[SCIx_NR_REGS]; 108 unsigned int fifosize; 109 unsigned int overrun_reg; 110 unsigned int overrun_mask; 111 unsigned int sampling_rate_mask; 112 unsigned int error_mask; 113 unsigned int error_clear; 114 }; 115 116 struct sci_port { 117 struct uart_port port; 118 119 /* Platform configuration */ 120 const struct sci_port_params *params; 121 const struct plat_sci_port *cfg; 122 unsigned int sampling_rate_mask; 123 resource_size_t reg_size; 124 struct mctrl_gpios *gpios; 125 126 /* Clocks */ 127 struct clk *clks[SCI_NUM_CLKS]; 128 unsigned long clk_rates[SCI_NUM_CLKS]; 129 130 int irqs[SCIx_NR_IRQS]; 131 char *irqstr[SCIx_NR_IRQS]; 132 133 struct dma_chan *chan_tx; 134 struct dma_chan *chan_rx; 135 136 #ifdef CONFIG_SERIAL_SH_SCI_DMA 137 struct dma_chan *chan_tx_saved; 138 struct dma_chan *chan_rx_saved; 139 dma_cookie_t cookie_tx; 140 dma_cookie_t cookie_rx[2]; 141 dma_cookie_t active_rx; 142 dma_addr_t tx_dma_addr; 143 unsigned int tx_dma_len; 144 struct scatterlist sg_rx[2]; 145 void *rx_buf[2]; 146 size_t buf_len_rx; 147 struct work_struct work_tx; 148 struct hrtimer rx_timer; 149 unsigned int rx_timeout; /* microseconds */ 150 #endif 151 unsigned int rx_frame; 152 int rx_trigger; 153 struct timer_list rx_fifo_timer; 154 int rx_fifo_timeout; 155 u16 hscif_tot; 156 157 bool has_rtscts; 158 bool autorts; 159 }; 160 161 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 162 163 static struct sci_port sci_ports[SCI_NPORTS]; 164 static unsigned long sci_ports_in_use; 165 static struct uart_driver sci_uart_driver; 166 167 static inline struct sci_port * 168 to_sci_port(struct uart_port *uart) 169 { 170 return container_of(uart, struct sci_port, port); 171 } 172 173 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 174 /* 175 * Common SCI definitions, dependent on the port's regshift 176 * value. 177 */ 178 [SCIx_SCI_REGTYPE] = { 179 .regs = { 180 [SCSMR] = { 0x00, 8 }, 181 [SCBRR] = { 0x01, 8 }, 182 [SCSCR] = { 0x02, 8 }, 183 [SCxTDR] = { 0x03, 8 }, 184 [SCxSR] = { 0x04, 8 }, 185 [SCxRDR] = { 0x05, 8 }, 186 }, 187 .fifosize = 1, 188 .overrun_reg = SCxSR, 189 .overrun_mask = SCI_ORER, 190 .sampling_rate_mask = SCI_SR(32), 191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 193 }, 194 195 /* 196 * Common definitions for legacy IrDA ports. 197 */ 198 [SCIx_IRDA_REGTYPE] = { 199 .regs = { 200 [SCSMR] = { 0x00, 8 }, 201 [SCBRR] = { 0x02, 8 }, 202 [SCSCR] = { 0x04, 8 }, 203 [SCxTDR] = { 0x06, 8 }, 204 [SCxSR] = { 0x08, 16 }, 205 [SCxRDR] = { 0x0a, 8 }, 206 [SCFCR] = { 0x0c, 8 }, 207 [SCFDR] = { 0x0e, 16 }, 208 }, 209 .fifosize = 1, 210 .overrun_reg = SCxSR, 211 .overrun_mask = SCI_ORER, 212 .sampling_rate_mask = SCI_SR(32), 213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 215 }, 216 217 /* 218 * Common SCIFA definitions. 219 */ 220 [SCIx_SCIFA_REGTYPE] = { 221 .regs = { 222 [SCSMR] = { 0x00, 16 }, 223 [SCBRR] = { 0x04, 8 }, 224 [SCSCR] = { 0x08, 16 }, 225 [SCxTDR] = { 0x20, 8 }, 226 [SCxSR] = { 0x14, 16 }, 227 [SCxRDR] = { 0x24, 8 }, 228 [SCFCR] = { 0x18, 16 }, 229 [SCFDR] = { 0x1c, 16 }, 230 [SCPCR] = { 0x30, 16 }, 231 [SCPDR] = { 0x34, 16 }, 232 }, 233 .fifosize = 64, 234 .overrun_reg = SCxSR, 235 .overrun_mask = SCIFA_ORER, 236 .sampling_rate_mask = SCI_SR_SCIFAB, 237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 239 }, 240 241 /* 242 * Common SCIFB definitions. 243 */ 244 [SCIx_SCIFB_REGTYPE] = { 245 .regs = { 246 [SCSMR] = { 0x00, 16 }, 247 [SCBRR] = { 0x04, 8 }, 248 [SCSCR] = { 0x08, 16 }, 249 [SCxTDR] = { 0x40, 8 }, 250 [SCxSR] = { 0x14, 16 }, 251 [SCxRDR] = { 0x60, 8 }, 252 [SCFCR] = { 0x18, 16 }, 253 [SCTFDR] = { 0x38, 16 }, 254 [SCRFDR] = { 0x3c, 16 }, 255 [SCPCR] = { 0x30, 16 }, 256 [SCPDR] = { 0x34, 16 }, 257 }, 258 .fifosize = 256, 259 .overrun_reg = SCxSR, 260 .overrun_mask = SCIFA_ORER, 261 .sampling_rate_mask = SCI_SR_SCIFAB, 262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 264 }, 265 266 /* 267 * Common SH-2(A) SCIF definitions for ports with FIFO data 268 * count registers. 269 */ 270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 271 .regs = { 272 [SCSMR] = { 0x00, 16 }, 273 [SCBRR] = { 0x04, 8 }, 274 [SCSCR] = { 0x08, 16 }, 275 [SCxTDR] = { 0x0c, 8 }, 276 [SCxSR] = { 0x10, 16 }, 277 [SCxRDR] = { 0x14, 8 }, 278 [SCFCR] = { 0x18, 16 }, 279 [SCFDR] = { 0x1c, 16 }, 280 [SCSPTR] = { 0x20, 16 }, 281 [SCLSR] = { 0x24, 16 }, 282 }, 283 .fifosize = 16, 284 .overrun_reg = SCLSR, 285 .overrun_mask = SCLSR_ORER, 286 .sampling_rate_mask = SCI_SR(32), 287 .error_mask = SCIF_DEFAULT_ERROR_MASK, 288 .error_clear = SCIF_ERROR_CLEAR, 289 }, 290 291 /* 292 * The "SCIFA" that is in RZ/T and RZ/A2. 293 * It looks like a normal SCIF with FIFO data, but with a 294 * compressed address space. Also, the break out of interrupts 295 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 296 */ 297 [SCIx_RZ_SCIFA_REGTYPE] = { 298 .regs = { 299 [SCSMR] = { 0x00, 16 }, 300 [SCBRR] = { 0x02, 8 }, 301 [SCSCR] = { 0x04, 16 }, 302 [SCxTDR] = { 0x06, 8 }, 303 [SCxSR] = { 0x08, 16 }, 304 [SCxRDR] = { 0x0A, 8 }, 305 [SCFCR] = { 0x0C, 16 }, 306 [SCFDR] = { 0x0E, 16 }, 307 [SCSPTR] = { 0x10, 16 }, 308 [SCLSR] = { 0x12, 16 }, 309 }, 310 .fifosize = 16, 311 .overrun_reg = SCLSR, 312 .overrun_mask = SCLSR_ORER, 313 .sampling_rate_mask = SCI_SR(32), 314 .error_mask = SCIF_DEFAULT_ERROR_MASK, 315 .error_clear = SCIF_ERROR_CLEAR, 316 }, 317 318 /* 319 * Common SH-3 SCIF definitions. 320 */ 321 [SCIx_SH3_SCIF_REGTYPE] = { 322 .regs = { 323 [SCSMR] = { 0x00, 8 }, 324 [SCBRR] = { 0x02, 8 }, 325 [SCSCR] = { 0x04, 8 }, 326 [SCxTDR] = { 0x06, 8 }, 327 [SCxSR] = { 0x08, 16 }, 328 [SCxRDR] = { 0x0a, 8 }, 329 [SCFCR] = { 0x0c, 8 }, 330 [SCFDR] = { 0x0e, 16 }, 331 }, 332 .fifosize = 16, 333 .overrun_reg = SCLSR, 334 .overrun_mask = SCLSR_ORER, 335 .sampling_rate_mask = SCI_SR(32), 336 .error_mask = SCIF_DEFAULT_ERROR_MASK, 337 .error_clear = SCIF_ERROR_CLEAR, 338 }, 339 340 /* 341 * Common SH-4(A) SCIF(B) definitions. 342 */ 343 [SCIx_SH4_SCIF_REGTYPE] = { 344 .regs = { 345 [SCSMR] = { 0x00, 16 }, 346 [SCBRR] = { 0x04, 8 }, 347 [SCSCR] = { 0x08, 16 }, 348 [SCxTDR] = { 0x0c, 8 }, 349 [SCxSR] = { 0x10, 16 }, 350 [SCxRDR] = { 0x14, 8 }, 351 [SCFCR] = { 0x18, 16 }, 352 [SCFDR] = { 0x1c, 16 }, 353 [SCSPTR] = { 0x20, 16 }, 354 [SCLSR] = { 0x24, 16 }, 355 }, 356 .fifosize = 16, 357 .overrun_reg = SCLSR, 358 .overrun_mask = SCLSR_ORER, 359 .sampling_rate_mask = SCI_SR(32), 360 .error_mask = SCIF_DEFAULT_ERROR_MASK, 361 .error_clear = SCIF_ERROR_CLEAR, 362 }, 363 364 /* 365 * Common SCIF definitions for ports with a Baud Rate Generator for 366 * External Clock (BRG). 367 */ 368 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 369 .regs = { 370 [SCSMR] = { 0x00, 16 }, 371 [SCBRR] = { 0x04, 8 }, 372 [SCSCR] = { 0x08, 16 }, 373 [SCxTDR] = { 0x0c, 8 }, 374 [SCxSR] = { 0x10, 16 }, 375 [SCxRDR] = { 0x14, 8 }, 376 [SCFCR] = { 0x18, 16 }, 377 [SCFDR] = { 0x1c, 16 }, 378 [SCSPTR] = { 0x20, 16 }, 379 [SCLSR] = { 0x24, 16 }, 380 [SCDL] = { 0x30, 16 }, 381 [SCCKS] = { 0x34, 16 }, 382 }, 383 .fifosize = 16, 384 .overrun_reg = SCLSR, 385 .overrun_mask = SCLSR_ORER, 386 .sampling_rate_mask = SCI_SR(32), 387 .error_mask = SCIF_DEFAULT_ERROR_MASK, 388 .error_clear = SCIF_ERROR_CLEAR, 389 }, 390 391 /* 392 * Common HSCIF definitions. 393 */ 394 [SCIx_HSCIF_REGTYPE] = { 395 .regs = { 396 [SCSMR] = { 0x00, 16 }, 397 [SCBRR] = { 0x04, 8 }, 398 [SCSCR] = { 0x08, 16 }, 399 [SCxTDR] = { 0x0c, 8 }, 400 [SCxSR] = { 0x10, 16 }, 401 [SCxRDR] = { 0x14, 8 }, 402 [SCFCR] = { 0x18, 16 }, 403 [SCFDR] = { 0x1c, 16 }, 404 [SCSPTR] = { 0x20, 16 }, 405 [SCLSR] = { 0x24, 16 }, 406 [HSSRR] = { 0x40, 16 }, 407 [SCDL] = { 0x30, 16 }, 408 [SCCKS] = { 0x34, 16 }, 409 [HSRTRGR] = { 0x54, 16 }, 410 [HSTTRGR] = { 0x58, 16 }, 411 }, 412 .fifosize = 128, 413 .overrun_reg = SCLSR, 414 .overrun_mask = SCLSR_ORER, 415 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 416 .error_mask = SCIF_DEFAULT_ERROR_MASK, 417 .error_clear = SCIF_ERROR_CLEAR, 418 }, 419 420 /* 421 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 422 * register. 423 */ 424 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 425 .regs = { 426 [SCSMR] = { 0x00, 16 }, 427 [SCBRR] = { 0x04, 8 }, 428 [SCSCR] = { 0x08, 16 }, 429 [SCxTDR] = { 0x0c, 8 }, 430 [SCxSR] = { 0x10, 16 }, 431 [SCxRDR] = { 0x14, 8 }, 432 [SCFCR] = { 0x18, 16 }, 433 [SCFDR] = { 0x1c, 16 }, 434 [SCLSR] = { 0x24, 16 }, 435 }, 436 .fifosize = 16, 437 .overrun_reg = SCLSR, 438 .overrun_mask = SCLSR_ORER, 439 .sampling_rate_mask = SCI_SR(32), 440 .error_mask = SCIF_DEFAULT_ERROR_MASK, 441 .error_clear = SCIF_ERROR_CLEAR, 442 }, 443 444 /* 445 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 446 * count registers. 447 */ 448 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 449 .regs = { 450 [SCSMR] = { 0x00, 16 }, 451 [SCBRR] = { 0x04, 8 }, 452 [SCSCR] = { 0x08, 16 }, 453 [SCxTDR] = { 0x0c, 8 }, 454 [SCxSR] = { 0x10, 16 }, 455 [SCxRDR] = { 0x14, 8 }, 456 [SCFCR] = { 0x18, 16 }, 457 [SCFDR] = { 0x1c, 16 }, 458 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 459 [SCRFDR] = { 0x20, 16 }, 460 [SCSPTR] = { 0x24, 16 }, 461 [SCLSR] = { 0x28, 16 }, 462 }, 463 .fifosize = 16, 464 .overrun_reg = SCLSR, 465 .overrun_mask = SCLSR_ORER, 466 .sampling_rate_mask = SCI_SR(32), 467 .error_mask = SCIF_DEFAULT_ERROR_MASK, 468 .error_clear = SCIF_ERROR_CLEAR, 469 }, 470 471 /* 472 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 473 * registers. 474 */ 475 [SCIx_SH7705_SCIF_REGTYPE] = { 476 .regs = { 477 [SCSMR] = { 0x00, 16 }, 478 [SCBRR] = { 0x04, 8 }, 479 [SCSCR] = { 0x08, 16 }, 480 [SCxTDR] = { 0x20, 8 }, 481 [SCxSR] = { 0x14, 16 }, 482 [SCxRDR] = { 0x24, 8 }, 483 [SCFCR] = { 0x18, 16 }, 484 [SCFDR] = { 0x1c, 16 }, 485 }, 486 .fifosize = 64, 487 .overrun_reg = SCxSR, 488 .overrun_mask = SCIFA_ORER, 489 .sampling_rate_mask = SCI_SR(16), 490 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 491 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 492 }, 493 }; 494 495 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 496 497 /* 498 * The "offset" here is rather misleading, in that it refers to an enum 499 * value relative to the port mapping rather than the fixed offset 500 * itself, which needs to be manually retrieved from the platform's 501 * register map for the given port. 502 */ 503 static unsigned int sci_serial_in(struct uart_port *p, int offset) 504 { 505 const struct plat_sci_reg *reg = sci_getreg(p, offset); 506 507 if (reg->size == 8) 508 return ioread8(p->membase + (reg->offset << p->regshift)); 509 else if (reg->size == 16) 510 return ioread16(p->membase + (reg->offset << p->regshift)); 511 else 512 WARN(1, "Invalid register access\n"); 513 514 return 0; 515 } 516 517 static void sci_serial_out(struct uart_port *p, int offset, int value) 518 { 519 const struct plat_sci_reg *reg = sci_getreg(p, offset); 520 521 if (reg->size == 8) 522 iowrite8(value, p->membase + (reg->offset << p->regshift)); 523 else if (reg->size == 16) 524 iowrite16(value, p->membase + (reg->offset << p->regshift)); 525 else 526 WARN(1, "Invalid register access\n"); 527 } 528 529 static void sci_port_enable(struct sci_port *sci_port) 530 { 531 unsigned int i; 532 533 if (!sci_port->port.dev) 534 return; 535 536 pm_runtime_get_sync(sci_port->port.dev); 537 538 for (i = 0; i < SCI_NUM_CLKS; i++) { 539 clk_prepare_enable(sci_port->clks[i]); 540 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 541 } 542 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 543 } 544 545 static void sci_port_disable(struct sci_port *sci_port) 546 { 547 unsigned int i; 548 549 if (!sci_port->port.dev) 550 return; 551 552 for (i = SCI_NUM_CLKS; i-- > 0; ) 553 clk_disable_unprepare(sci_port->clks[i]); 554 555 pm_runtime_put_sync(sci_port->port.dev); 556 } 557 558 static inline unsigned long port_rx_irq_mask(struct uart_port *port) 559 { 560 /* 561 * Not all ports (such as SCIFA) will support REIE. Rather than 562 * special-casing the port type, we check the port initialization 563 * IRQ enable mask to see whether the IRQ is desired at all. If 564 * it's unset, it's logically inferred that there's no point in 565 * testing for it. 566 */ 567 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 568 } 569 570 static void sci_start_tx(struct uart_port *port) 571 { 572 struct sci_port *s = to_sci_port(port); 573 unsigned short ctrl; 574 575 #ifdef CONFIG_SERIAL_SH_SCI_DMA 576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 577 u16 new, scr = serial_port_in(port, SCSCR); 578 if (s->chan_tx) 579 new = scr | SCSCR_TDRQE; 580 else 581 new = scr & ~SCSCR_TDRQE; 582 if (new != scr) 583 serial_port_out(port, SCSCR, new); 584 } 585 586 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 587 dma_submit_error(s->cookie_tx)) { 588 s->cookie_tx = 0; 589 schedule_work(&s->work_tx); 590 } 591 #endif 592 593 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 594 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 595 ctrl = serial_port_in(port, SCSCR); 596 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 597 } 598 } 599 600 static void sci_stop_tx(struct uart_port *port) 601 { 602 unsigned short ctrl; 603 604 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 605 ctrl = serial_port_in(port, SCSCR); 606 607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 608 ctrl &= ~SCSCR_TDRQE; 609 610 ctrl &= ~SCSCR_TIE; 611 612 serial_port_out(port, SCSCR, ctrl); 613 } 614 615 static void sci_start_rx(struct uart_port *port) 616 { 617 unsigned short ctrl; 618 619 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 620 621 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 622 ctrl &= ~SCSCR_RDRQE; 623 624 serial_port_out(port, SCSCR, ctrl); 625 } 626 627 static void sci_stop_rx(struct uart_port *port) 628 { 629 unsigned short ctrl; 630 631 ctrl = serial_port_in(port, SCSCR); 632 633 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 634 ctrl &= ~SCSCR_RDRQE; 635 636 ctrl &= ~port_rx_irq_mask(port); 637 638 serial_port_out(port, SCSCR, ctrl); 639 } 640 641 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 642 { 643 if (port->type == PORT_SCI) { 644 /* Just store the mask */ 645 serial_port_out(port, SCxSR, mask); 646 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 647 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 648 /* Only clear the status bits we want to clear */ 649 serial_port_out(port, SCxSR, 650 serial_port_in(port, SCxSR) & mask); 651 } else { 652 /* Store the mask, clear parity/framing errors */ 653 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 654 } 655 } 656 657 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 658 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 659 660 #ifdef CONFIG_CONSOLE_POLL 661 static int sci_poll_get_char(struct uart_port *port) 662 { 663 unsigned short status; 664 int c; 665 666 do { 667 status = serial_port_in(port, SCxSR); 668 if (status & SCxSR_ERRORS(port)) { 669 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 670 continue; 671 } 672 break; 673 } while (1); 674 675 if (!(status & SCxSR_RDxF(port))) 676 return NO_POLL_CHAR; 677 678 c = serial_port_in(port, SCxRDR); 679 680 /* Dummy read */ 681 serial_port_in(port, SCxSR); 682 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 683 684 return c; 685 } 686 #endif 687 688 static void sci_poll_put_char(struct uart_port *port, unsigned char c) 689 { 690 unsigned short status; 691 692 do { 693 status = serial_port_in(port, SCxSR); 694 } while (!(status & SCxSR_TDxE(port))); 695 696 serial_port_out(port, SCxTDR, c); 697 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 698 } 699 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 700 CONFIG_SERIAL_SH_SCI_EARLYCON */ 701 702 static void sci_init_pins(struct uart_port *port, unsigned int cflag) 703 { 704 struct sci_port *s = to_sci_port(port); 705 706 /* 707 * Use port-specific handler if provided. 708 */ 709 if (s->cfg->ops && s->cfg->ops->init_pins) { 710 s->cfg->ops->init_pins(port, cflag); 711 return; 712 } 713 714 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 715 u16 data = serial_port_in(port, SCPDR); 716 u16 ctrl = serial_port_in(port, SCPCR); 717 718 /* Enable RXD and TXD pin functions */ 719 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 720 if (to_sci_port(port)->has_rtscts) { 721 /* RTS# is output, active low, unless autorts */ 722 if (!(port->mctrl & TIOCM_RTS)) { 723 ctrl |= SCPCR_RTSC; 724 data |= SCPDR_RTSD; 725 } else if (!s->autorts) { 726 ctrl |= SCPCR_RTSC; 727 data &= ~SCPDR_RTSD; 728 } else { 729 /* Enable RTS# pin function */ 730 ctrl &= ~SCPCR_RTSC; 731 } 732 /* Enable CTS# pin function */ 733 ctrl &= ~SCPCR_CTSC; 734 } 735 serial_port_out(port, SCPDR, data); 736 serial_port_out(port, SCPCR, ctrl); 737 } else if (sci_getreg(port, SCSPTR)->size) { 738 u16 status = serial_port_in(port, SCSPTR); 739 740 /* RTS# is always output; and active low, unless autorts */ 741 status |= SCSPTR_RTSIO; 742 if (!(port->mctrl & TIOCM_RTS)) 743 status |= SCSPTR_RTSDT; 744 else if (!s->autorts) 745 status &= ~SCSPTR_RTSDT; 746 /* CTS# and SCK are inputs */ 747 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 748 serial_port_out(port, SCSPTR, status); 749 } 750 } 751 752 static int sci_txfill(struct uart_port *port) 753 { 754 struct sci_port *s = to_sci_port(port); 755 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 756 const struct plat_sci_reg *reg; 757 758 reg = sci_getreg(port, SCTFDR); 759 if (reg->size) 760 return serial_port_in(port, SCTFDR) & fifo_mask; 761 762 reg = sci_getreg(port, SCFDR); 763 if (reg->size) 764 return serial_port_in(port, SCFDR) >> 8; 765 766 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 767 } 768 769 static int sci_txroom(struct uart_port *port) 770 { 771 return port->fifosize - sci_txfill(port); 772 } 773 774 static int sci_rxfill(struct uart_port *port) 775 { 776 struct sci_port *s = to_sci_port(port); 777 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 778 const struct plat_sci_reg *reg; 779 780 reg = sci_getreg(port, SCRFDR); 781 if (reg->size) 782 return serial_port_in(port, SCRFDR) & fifo_mask; 783 784 reg = sci_getreg(port, SCFDR); 785 if (reg->size) 786 return serial_port_in(port, SCFDR) & fifo_mask; 787 788 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 789 } 790 791 /* ********************************************************************** * 792 * the interrupt related routines * 793 * ********************************************************************** */ 794 795 static void sci_transmit_chars(struct uart_port *port) 796 { 797 struct circ_buf *xmit = &port->state->xmit; 798 unsigned int stopped = uart_tx_stopped(port); 799 unsigned short status; 800 unsigned short ctrl; 801 int count; 802 803 status = serial_port_in(port, SCxSR); 804 if (!(status & SCxSR_TDxE(port))) { 805 ctrl = serial_port_in(port, SCSCR); 806 if (uart_circ_empty(xmit)) 807 ctrl &= ~SCSCR_TIE; 808 else 809 ctrl |= SCSCR_TIE; 810 serial_port_out(port, SCSCR, ctrl); 811 return; 812 } 813 814 count = sci_txroom(port); 815 816 do { 817 unsigned char c; 818 819 if (port->x_char) { 820 c = port->x_char; 821 port->x_char = 0; 822 } else if (!uart_circ_empty(xmit) && !stopped) { 823 c = xmit->buf[xmit->tail]; 824 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 825 } else { 826 break; 827 } 828 829 serial_port_out(port, SCxTDR, c); 830 831 port->icount.tx++; 832 } while (--count > 0); 833 834 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 835 836 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 837 uart_write_wakeup(port); 838 if (uart_circ_empty(xmit)) 839 sci_stop_tx(port); 840 841 } 842 843 /* On SH3, SCIF may read end-of-break as a space->mark char */ 844 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) 845 846 static void sci_receive_chars(struct uart_port *port) 847 { 848 struct tty_port *tport = &port->state->port; 849 int i, count, copied = 0; 850 unsigned short status; 851 unsigned char flag; 852 853 status = serial_port_in(port, SCxSR); 854 if (!(status & SCxSR_RDxF(port))) 855 return; 856 857 while (1) { 858 /* Don't copy more bytes than there is room for in the buffer */ 859 count = tty_buffer_request_room(tport, sci_rxfill(port)); 860 861 /* If for any reason we can't copy more data, we're done! */ 862 if (count == 0) 863 break; 864 865 if (port->type == PORT_SCI) { 866 char c = serial_port_in(port, SCxRDR); 867 if (uart_handle_sysrq_char(port, c)) 868 count = 0; 869 else 870 tty_insert_flip_char(tport, c, TTY_NORMAL); 871 } else { 872 for (i = 0; i < count; i++) { 873 char c; 874 875 if (port->type == PORT_SCIF || 876 port->type == PORT_HSCIF) { 877 status = serial_port_in(port, SCxSR); 878 c = serial_port_in(port, SCxRDR); 879 } else { 880 c = serial_port_in(port, SCxRDR); 881 status = serial_port_in(port, SCxSR); 882 } 883 if (uart_handle_sysrq_char(port, c)) { 884 count--; i--; 885 continue; 886 } 887 888 /* Store data and status */ 889 if (status & SCxSR_FER(port)) { 890 flag = TTY_FRAME; 891 port->icount.frame++; 892 dev_notice(port->dev, "frame error\n"); 893 } else if (status & SCxSR_PER(port)) { 894 flag = TTY_PARITY; 895 port->icount.parity++; 896 dev_notice(port->dev, "parity error\n"); 897 } else 898 flag = TTY_NORMAL; 899 900 tty_insert_flip_char(tport, c, flag); 901 } 902 } 903 904 serial_port_in(port, SCxSR); /* dummy read */ 905 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 906 907 copied += count; 908 port->icount.rx += count; 909 } 910 911 if (copied) { 912 /* Tell the rest of the system the news. New characters! */ 913 tty_flip_buffer_push(tport); 914 } else { 915 /* TTY buffers full; read from RX reg to prevent lockup */ 916 serial_port_in(port, SCxRDR); 917 serial_port_in(port, SCxSR); /* dummy read */ 918 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 919 } 920 } 921 922 static int sci_handle_errors(struct uart_port *port) 923 { 924 int copied = 0; 925 unsigned short status = serial_port_in(port, SCxSR); 926 struct tty_port *tport = &port->state->port; 927 struct sci_port *s = to_sci_port(port); 928 929 /* Handle overruns */ 930 if (status & s->params->overrun_mask) { 931 port->icount.overrun++; 932 933 /* overrun error */ 934 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 935 copied++; 936 937 dev_notice(port->dev, "overrun error\n"); 938 } 939 940 if (status & SCxSR_FER(port)) { 941 /* frame error */ 942 port->icount.frame++; 943 944 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 945 copied++; 946 947 dev_notice(port->dev, "frame error\n"); 948 } 949 950 if (status & SCxSR_PER(port)) { 951 /* parity error */ 952 port->icount.parity++; 953 954 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 955 copied++; 956 957 dev_notice(port->dev, "parity error\n"); 958 } 959 960 if (copied) 961 tty_flip_buffer_push(tport); 962 963 return copied; 964 } 965 966 static int sci_handle_fifo_overrun(struct uart_port *port) 967 { 968 struct tty_port *tport = &port->state->port; 969 struct sci_port *s = to_sci_port(port); 970 const struct plat_sci_reg *reg; 971 int copied = 0; 972 u16 status; 973 974 reg = sci_getreg(port, s->params->overrun_reg); 975 if (!reg->size) 976 return 0; 977 978 status = serial_port_in(port, s->params->overrun_reg); 979 if (status & s->params->overrun_mask) { 980 status &= ~s->params->overrun_mask; 981 serial_port_out(port, s->params->overrun_reg, status); 982 983 port->icount.overrun++; 984 985 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 986 tty_flip_buffer_push(tport); 987 988 dev_dbg(port->dev, "overrun error\n"); 989 copied++; 990 } 991 992 return copied; 993 } 994 995 static int sci_handle_breaks(struct uart_port *port) 996 { 997 int copied = 0; 998 unsigned short status = serial_port_in(port, SCxSR); 999 struct tty_port *tport = &port->state->port; 1000 1001 if (uart_handle_break(port)) 1002 return 0; 1003 1004 if (status & SCxSR_BRK(port)) { 1005 port->icount.brk++; 1006 1007 /* Notify of BREAK */ 1008 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1009 copied++; 1010 1011 dev_dbg(port->dev, "BREAK detected\n"); 1012 } 1013 1014 if (copied) 1015 tty_flip_buffer_push(tport); 1016 1017 copied += sci_handle_fifo_overrun(port); 1018 1019 return copied; 1020 } 1021 1022 static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1023 { 1024 unsigned int bits; 1025 1026 if (rx_trig < 1) 1027 rx_trig = 1; 1028 if (rx_trig >= port->fifosize) 1029 rx_trig = port->fifosize; 1030 1031 /* HSCIF can be set to an arbitrary level. */ 1032 if (sci_getreg(port, HSRTRGR)->size) { 1033 serial_port_out(port, HSRTRGR, rx_trig); 1034 return rx_trig; 1035 } 1036 1037 switch (port->type) { 1038 case PORT_SCIF: 1039 if (rx_trig < 4) { 1040 bits = 0; 1041 rx_trig = 1; 1042 } else if (rx_trig < 8) { 1043 bits = SCFCR_RTRG0; 1044 rx_trig = 4; 1045 } else if (rx_trig < 14) { 1046 bits = SCFCR_RTRG1; 1047 rx_trig = 8; 1048 } else { 1049 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1050 rx_trig = 14; 1051 } 1052 break; 1053 case PORT_SCIFA: 1054 case PORT_SCIFB: 1055 if (rx_trig < 16) { 1056 bits = 0; 1057 rx_trig = 1; 1058 } else if (rx_trig < 32) { 1059 bits = SCFCR_RTRG0; 1060 rx_trig = 16; 1061 } else if (rx_trig < 48) { 1062 bits = SCFCR_RTRG1; 1063 rx_trig = 32; 1064 } else { 1065 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1066 rx_trig = 48; 1067 } 1068 break; 1069 default: 1070 WARN(1, "unknown FIFO configuration"); 1071 return 1; 1072 } 1073 1074 serial_port_out(port, SCFCR, 1075 (serial_port_in(port, SCFCR) & 1076 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1077 1078 return rx_trig; 1079 } 1080 1081 static int scif_rtrg_enabled(struct uart_port *port) 1082 { 1083 if (sci_getreg(port, HSRTRGR)->size) 1084 return serial_port_in(port, HSRTRGR) != 0; 1085 else 1086 return (serial_port_in(port, SCFCR) & 1087 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1088 } 1089 1090 static void rx_fifo_timer_fn(struct timer_list *t) 1091 { 1092 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1093 struct uart_port *port = &s->port; 1094 1095 dev_dbg(port->dev, "Rx timed out\n"); 1096 scif_set_rtrg(port, 1); 1097 } 1098 1099 static ssize_t rx_fifo_trigger_show(struct device *dev, 1100 struct device_attribute *attr, char *buf) 1101 { 1102 struct uart_port *port = dev_get_drvdata(dev); 1103 struct sci_port *sci = to_sci_port(port); 1104 1105 return sprintf(buf, "%d\n", sci->rx_trigger); 1106 } 1107 1108 static ssize_t rx_fifo_trigger_store(struct device *dev, 1109 struct device_attribute *attr, 1110 const char *buf, size_t count) 1111 { 1112 struct uart_port *port = dev_get_drvdata(dev); 1113 struct sci_port *sci = to_sci_port(port); 1114 int ret; 1115 long r; 1116 1117 ret = kstrtol(buf, 0, &r); 1118 if (ret) 1119 return ret; 1120 1121 sci->rx_trigger = scif_set_rtrg(port, r); 1122 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1123 scif_set_rtrg(port, 1); 1124 1125 return count; 1126 } 1127 1128 static DEVICE_ATTR_RW(rx_fifo_trigger); 1129 1130 static ssize_t rx_fifo_timeout_show(struct device *dev, 1131 struct device_attribute *attr, 1132 char *buf) 1133 { 1134 struct uart_port *port = dev_get_drvdata(dev); 1135 struct sci_port *sci = to_sci_port(port); 1136 int v; 1137 1138 if (port->type == PORT_HSCIF) 1139 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1140 else 1141 v = sci->rx_fifo_timeout; 1142 1143 return sprintf(buf, "%d\n", v); 1144 } 1145 1146 static ssize_t rx_fifo_timeout_store(struct device *dev, 1147 struct device_attribute *attr, 1148 const char *buf, 1149 size_t count) 1150 { 1151 struct uart_port *port = dev_get_drvdata(dev); 1152 struct sci_port *sci = to_sci_port(port); 1153 int ret; 1154 long r; 1155 1156 ret = kstrtol(buf, 0, &r); 1157 if (ret) 1158 return ret; 1159 1160 if (port->type == PORT_HSCIF) { 1161 if (r < 0 || r > 3) 1162 return -EINVAL; 1163 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1164 } else { 1165 sci->rx_fifo_timeout = r; 1166 scif_set_rtrg(port, 1); 1167 if (r > 0) 1168 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1169 } 1170 1171 return count; 1172 } 1173 1174 static DEVICE_ATTR_RW(rx_fifo_timeout); 1175 1176 1177 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1178 static void sci_dma_tx_complete(void *arg) 1179 { 1180 struct sci_port *s = arg; 1181 struct uart_port *port = &s->port; 1182 struct circ_buf *xmit = &port->state->xmit; 1183 unsigned long flags; 1184 1185 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1186 1187 spin_lock_irqsave(&port->lock, flags); 1188 1189 xmit->tail += s->tx_dma_len; 1190 xmit->tail &= UART_XMIT_SIZE - 1; 1191 1192 port->icount.tx += s->tx_dma_len; 1193 1194 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1195 uart_write_wakeup(port); 1196 1197 if (!uart_circ_empty(xmit)) { 1198 s->cookie_tx = 0; 1199 schedule_work(&s->work_tx); 1200 } else { 1201 s->cookie_tx = -EINVAL; 1202 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1203 u16 ctrl = serial_port_in(port, SCSCR); 1204 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1205 } 1206 } 1207 1208 spin_unlock_irqrestore(&port->lock, flags); 1209 } 1210 1211 /* Locking: called with port lock held */ 1212 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1213 { 1214 struct uart_port *port = &s->port; 1215 struct tty_port *tport = &port->state->port; 1216 int copied; 1217 1218 copied = tty_insert_flip_string(tport, buf, count); 1219 if (copied < count) 1220 port->icount.buf_overrun++; 1221 1222 port->icount.rx += copied; 1223 1224 return copied; 1225 } 1226 1227 static int sci_dma_rx_find_active(struct sci_port *s) 1228 { 1229 unsigned int i; 1230 1231 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1232 if (s->active_rx == s->cookie_rx[i]) 1233 return i; 1234 1235 return -1; 1236 } 1237 1238 static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1239 { 1240 unsigned int i; 1241 1242 s->chan_rx = NULL; 1243 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1244 s->cookie_rx[i] = -EINVAL; 1245 s->active_rx = 0; 1246 } 1247 1248 static void sci_dma_rx_release(struct sci_port *s) 1249 { 1250 struct dma_chan *chan = s->chan_rx_saved; 1251 1252 s->chan_rx_saved = NULL; 1253 sci_dma_rx_chan_invalidate(s); 1254 dmaengine_terminate_sync(chan); 1255 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1256 sg_dma_address(&s->sg_rx[0])); 1257 dma_release_channel(chan); 1258 } 1259 1260 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1261 { 1262 long sec = usec / 1000000; 1263 long nsec = (usec % 1000000) * 1000; 1264 ktime_t t = ktime_set(sec, nsec); 1265 1266 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1267 } 1268 1269 static void sci_dma_rx_reenable_irq(struct sci_port *s) 1270 { 1271 struct uart_port *port = &s->port; 1272 u16 scr; 1273 1274 /* Direct new serial port interrupts back to CPU */ 1275 scr = serial_port_in(port, SCSCR); 1276 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1277 scr &= ~SCSCR_RDRQE; 1278 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1279 } 1280 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1281 } 1282 1283 static void sci_dma_rx_complete(void *arg) 1284 { 1285 struct sci_port *s = arg; 1286 struct dma_chan *chan = s->chan_rx; 1287 struct uart_port *port = &s->port; 1288 struct dma_async_tx_descriptor *desc; 1289 unsigned long flags; 1290 int active, count = 0; 1291 1292 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1293 s->active_rx); 1294 1295 spin_lock_irqsave(&port->lock, flags); 1296 1297 active = sci_dma_rx_find_active(s); 1298 if (active >= 0) 1299 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1300 1301 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1302 1303 if (count) 1304 tty_flip_buffer_push(&port->state->port); 1305 1306 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1307 DMA_DEV_TO_MEM, 1308 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1309 if (!desc) 1310 goto fail; 1311 1312 desc->callback = sci_dma_rx_complete; 1313 desc->callback_param = s; 1314 s->cookie_rx[active] = dmaengine_submit(desc); 1315 if (dma_submit_error(s->cookie_rx[active])) 1316 goto fail; 1317 1318 s->active_rx = s->cookie_rx[!active]; 1319 1320 dma_async_issue_pending(chan); 1321 1322 spin_unlock_irqrestore(&port->lock, flags); 1323 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1324 __func__, s->cookie_rx[active], active, s->active_rx); 1325 return; 1326 1327 fail: 1328 spin_unlock_irqrestore(&port->lock, flags); 1329 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1330 /* Switch to PIO */ 1331 spin_lock_irqsave(&port->lock, flags); 1332 dmaengine_terminate_async(chan); 1333 sci_dma_rx_chan_invalidate(s); 1334 sci_dma_rx_reenable_irq(s); 1335 spin_unlock_irqrestore(&port->lock, flags); 1336 } 1337 1338 static void sci_dma_tx_release(struct sci_port *s) 1339 { 1340 struct dma_chan *chan = s->chan_tx_saved; 1341 1342 cancel_work_sync(&s->work_tx); 1343 s->chan_tx_saved = s->chan_tx = NULL; 1344 s->cookie_tx = -EINVAL; 1345 dmaengine_terminate_sync(chan); 1346 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1347 DMA_TO_DEVICE); 1348 dma_release_channel(chan); 1349 } 1350 1351 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1352 { 1353 struct dma_chan *chan = s->chan_rx; 1354 struct uart_port *port = &s->port; 1355 unsigned long flags; 1356 int i; 1357 1358 for (i = 0; i < 2; i++) { 1359 struct scatterlist *sg = &s->sg_rx[i]; 1360 struct dma_async_tx_descriptor *desc; 1361 1362 desc = dmaengine_prep_slave_sg(chan, 1363 sg, 1, DMA_DEV_TO_MEM, 1364 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1365 if (!desc) 1366 goto fail; 1367 1368 desc->callback = sci_dma_rx_complete; 1369 desc->callback_param = s; 1370 s->cookie_rx[i] = dmaengine_submit(desc); 1371 if (dma_submit_error(s->cookie_rx[i])) 1372 goto fail; 1373 1374 } 1375 1376 s->active_rx = s->cookie_rx[0]; 1377 1378 dma_async_issue_pending(chan); 1379 return 0; 1380 1381 fail: 1382 /* Switch to PIO */ 1383 if (!port_lock_held) 1384 spin_lock_irqsave(&port->lock, flags); 1385 if (i) 1386 dmaengine_terminate_async(chan); 1387 sci_dma_rx_chan_invalidate(s); 1388 sci_start_rx(port); 1389 if (!port_lock_held) 1390 spin_unlock_irqrestore(&port->lock, flags); 1391 return -EAGAIN; 1392 } 1393 1394 static void sci_dma_tx_work_fn(struct work_struct *work) 1395 { 1396 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1397 struct dma_async_tx_descriptor *desc; 1398 struct dma_chan *chan = s->chan_tx; 1399 struct uart_port *port = &s->port; 1400 struct circ_buf *xmit = &port->state->xmit; 1401 unsigned long flags; 1402 dma_addr_t buf; 1403 int head, tail; 1404 1405 /* 1406 * DMA is idle now. 1407 * Port xmit buffer is already mapped, and it is one page... Just adjust 1408 * offsets and lengths. Since it is a circular buffer, we have to 1409 * transmit till the end, and then the rest. Take the port lock to get a 1410 * consistent xmit buffer state. 1411 */ 1412 spin_lock_irq(&port->lock); 1413 head = xmit->head; 1414 tail = xmit->tail; 1415 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1)); 1416 s->tx_dma_len = min_t(unsigned int, 1417 CIRC_CNT(head, tail, UART_XMIT_SIZE), 1418 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE)); 1419 if (!s->tx_dma_len) { 1420 /* Transmit buffer has been flushed */ 1421 spin_unlock_irq(&port->lock); 1422 return; 1423 } 1424 1425 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1426 DMA_MEM_TO_DEV, 1427 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1428 if (!desc) { 1429 spin_unlock_irq(&port->lock); 1430 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1431 goto switch_to_pio; 1432 } 1433 1434 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1435 DMA_TO_DEVICE); 1436 1437 desc->callback = sci_dma_tx_complete; 1438 desc->callback_param = s; 1439 s->cookie_tx = dmaengine_submit(desc); 1440 if (dma_submit_error(s->cookie_tx)) { 1441 spin_unlock_irq(&port->lock); 1442 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1443 goto switch_to_pio; 1444 } 1445 1446 spin_unlock_irq(&port->lock); 1447 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1448 __func__, xmit->buf, tail, head, s->cookie_tx); 1449 1450 dma_async_issue_pending(chan); 1451 return; 1452 1453 switch_to_pio: 1454 spin_lock_irqsave(&port->lock, flags); 1455 s->chan_tx = NULL; 1456 sci_start_tx(port); 1457 spin_unlock_irqrestore(&port->lock, flags); 1458 return; 1459 } 1460 1461 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1462 { 1463 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1464 struct dma_chan *chan = s->chan_rx; 1465 struct uart_port *port = &s->port; 1466 struct dma_tx_state state; 1467 enum dma_status status; 1468 unsigned long flags; 1469 unsigned int read; 1470 int active, count; 1471 1472 dev_dbg(port->dev, "DMA Rx timed out\n"); 1473 1474 spin_lock_irqsave(&port->lock, flags); 1475 1476 active = sci_dma_rx_find_active(s); 1477 if (active < 0) { 1478 spin_unlock_irqrestore(&port->lock, flags); 1479 return HRTIMER_NORESTART; 1480 } 1481 1482 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1483 if (status == DMA_COMPLETE) { 1484 spin_unlock_irqrestore(&port->lock, flags); 1485 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1486 s->active_rx, active); 1487 1488 /* Let packet complete handler take care of the packet */ 1489 return HRTIMER_NORESTART; 1490 } 1491 1492 dmaengine_pause(chan); 1493 1494 /* 1495 * sometimes DMA transfer doesn't stop even if it is stopped and 1496 * data keeps on coming until transaction is complete so check 1497 * for DMA_COMPLETE again 1498 * Let packet complete handler take care of the packet 1499 */ 1500 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1501 if (status == DMA_COMPLETE) { 1502 spin_unlock_irqrestore(&port->lock, flags); 1503 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1504 return HRTIMER_NORESTART; 1505 } 1506 1507 /* Handle incomplete DMA receive */ 1508 dmaengine_terminate_async(s->chan_rx); 1509 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1510 1511 if (read) { 1512 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1513 if (count) 1514 tty_flip_buffer_push(&port->state->port); 1515 } 1516 1517 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1518 sci_dma_rx_submit(s, true); 1519 1520 sci_dma_rx_reenable_irq(s); 1521 1522 spin_unlock_irqrestore(&port->lock, flags); 1523 1524 return HRTIMER_NORESTART; 1525 } 1526 1527 static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1528 enum dma_transfer_direction dir) 1529 { 1530 struct dma_chan *chan; 1531 struct dma_slave_config cfg; 1532 int ret; 1533 1534 chan = dma_request_slave_channel(port->dev, 1535 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1536 if (!chan) { 1537 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1538 return NULL; 1539 } 1540 1541 memset(&cfg, 0, sizeof(cfg)); 1542 cfg.direction = dir; 1543 if (dir == DMA_MEM_TO_DEV) { 1544 cfg.dst_addr = port->mapbase + 1545 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1546 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1547 } else { 1548 cfg.src_addr = port->mapbase + 1549 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1550 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1551 } 1552 1553 ret = dmaengine_slave_config(chan, &cfg); 1554 if (ret) { 1555 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1556 dma_release_channel(chan); 1557 return NULL; 1558 } 1559 1560 return chan; 1561 } 1562 1563 static void sci_request_dma(struct uart_port *port) 1564 { 1565 struct sci_port *s = to_sci_port(port); 1566 struct dma_chan *chan; 1567 1568 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1569 1570 /* 1571 * DMA on console may interfere with Kernel log messages which use 1572 * plain putchar(). So, simply don't use it with a console. 1573 */ 1574 if (uart_console(port)) 1575 return; 1576 1577 if (!port->dev->of_node) 1578 return; 1579 1580 s->cookie_tx = -EINVAL; 1581 1582 /* 1583 * Don't request a dma channel if no channel was specified 1584 * in the device tree. 1585 */ 1586 if (!of_find_property(port->dev->of_node, "dmas", NULL)) 1587 return; 1588 1589 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1590 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1591 if (chan) { 1592 /* UART circular tx buffer is an aligned page. */ 1593 s->tx_dma_addr = dma_map_single(chan->device->dev, 1594 port->state->xmit.buf, 1595 UART_XMIT_SIZE, 1596 DMA_TO_DEVICE); 1597 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1598 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1599 dma_release_channel(chan); 1600 } else { 1601 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1602 __func__, UART_XMIT_SIZE, 1603 port->state->xmit.buf, &s->tx_dma_addr); 1604 1605 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1606 s->chan_tx_saved = s->chan_tx = chan; 1607 } 1608 } 1609 1610 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1611 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1612 if (chan) { 1613 unsigned int i; 1614 dma_addr_t dma; 1615 void *buf; 1616 1617 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1618 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1619 &dma, GFP_KERNEL); 1620 if (!buf) { 1621 dev_warn(port->dev, 1622 "Failed to allocate Rx dma buffer, using PIO\n"); 1623 dma_release_channel(chan); 1624 return; 1625 } 1626 1627 for (i = 0; i < 2; i++) { 1628 struct scatterlist *sg = &s->sg_rx[i]; 1629 1630 sg_init_table(sg, 1); 1631 s->rx_buf[i] = buf; 1632 sg_dma_address(sg) = dma; 1633 sg_dma_len(sg) = s->buf_len_rx; 1634 1635 buf += s->buf_len_rx; 1636 dma += s->buf_len_rx; 1637 } 1638 1639 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1640 s->rx_timer.function = sci_dma_rx_timer_fn; 1641 1642 s->chan_rx_saved = s->chan_rx = chan; 1643 1644 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1645 sci_dma_rx_submit(s, false); 1646 } 1647 } 1648 1649 static void sci_free_dma(struct uart_port *port) 1650 { 1651 struct sci_port *s = to_sci_port(port); 1652 1653 if (s->chan_tx_saved) 1654 sci_dma_tx_release(s); 1655 if (s->chan_rx_saved) 1656 sci_dma_rx_release(s); 1657 } 1658 1659 static void sci_flush_buffer(struct uart_port *port) 1660 { 1661 struct sci_port *s = to_sci_port(port); 1662 1663 /* 1664 * In uart_flush_buffer(), the xmit circular buffer has just been 1665 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1666 * pending transfers 1667 */ 1668 s->tx_dma_len = 0; 1669 if (s->chan_tx) { 1670 dmaengine_terminate_async(s->chan_tx); 1671 s->cookie_tx = -EINVAL; 1672 } 1673 } 1674 #else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1675 static inline void sci_request_dma(struct uart_port *port) 1676 { 1677 } 1678 1679 static inline void sci_free_dma(struct uart_port *port) 1680 { 1681 } 1682 1683 #define sci_flush_buffer NULL 1684 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1685 1686 static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1687 { 1688 struct uart_port *port = ptr; 1689 struct sci_port *s = to_sci_port(port); 1690 1691 #ifdef CONFIG_SERIAL_SH_SCI_DMA 1692 if (s->chan_rx) { 1693 u16 scr = serial_port_in(port, SCSCR); 1694 u16 ssr = serial_port_in(port, SCxSR); 1695 1696 /* Disable future Rx interrupts */ 1697 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1698 disable_irq_nosync(irq); 1699 scr |= SCSCR_RDRQE; 1700 } else { 1701 if (sci_dma_rx_submit(s, false) < 0) 1702 goto handle_pio; 1703 1704 scr &= ~SCSCR_RIE; 1705 } 1706 serial_port_out(port, SCSCR, scr); 1707 /* Clear current interrupt */ 1708 serial_port_out(port, SCxSR, 1709 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1710 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1711 jiffies, s->rx_timeout); 1712 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1713 1714 return IRQ_HANDLED; 1715 } 1716 1717 handle_pio: 1718 #endif 1719 1720 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1721 if (!scif_rtrg_enabled(port)) 1722 scif_set_rtrg(port, s->rx_trigger); 1723 1724 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1725 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1726 } 1727 1728 /* I think sci_receive_chars has to be called irrespective 1729 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1730 * to be disabled? 1731 */ 1732 sci_receive_chars(port); 1733 1734 return IRQ_HANDLED; 1735 } 1736 1737 static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1738 { 1739 struct uart_port *port = ptr; 1740 unsigned long flags; 1741 1742 spin_lock_irqsave(&port->lock, flags); 1743 sci_transmit_chars(port); 1744 spin_unlock_irqrestore(&port->lock, flags); 1745 1746 return IRQ_HANDLED; 1747 } 1748 1749 static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1750 { 1751 struct uart_port *port = ptr; 1752 1753 /* Handle BREAKs */ 1754 sci_handle_breaks(port); 1755 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1756 1757 return IRQ_HANDLED; 1758 } 1759 1760 static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1761 { 1762 struct uart_port *port = ptr; 1763 struct sci_port *s = to_sci_port(port); 1764 1765 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1766 /* Break and Error interrupts are muxed */ 1767 unsigned short ssr_status = serial_port_in(port, SCxSR); 1768 1769 /* Break Interrupt */ 1770 if (ssr_status & SCxSR_BRK(port)) 1771 sci_br_interrupt(irq, ptr); 1772 1773 /* Break only? */ 1774 if (!(ssr_status & SCxSR_ERRORS(port))) 1775 return IRQ_HANDLED; 1776 } 1777 1778 /* Handle errors */ 1779 if (port->type == PORT_SCI) { 1780 if (sci_handle_errors(port)) { 1781 /* discard character in rx buffer */ 1782 serial_port_in(port, SCxSR); 1783 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1784 } 1785 } else { 1786 sci_handle_fifo_overrun(port); 1787 if (!s->chan_rx) 1788 sci_receive_chars(port); 1789 } 1790 1791 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1792 1793 /* Kick the transmission */ 1794 if (!s->chan_tx) 1795 sci_tx_interrupt(irq, ptr); 1796 1797 return IRQ_HANDLED; 1798 } 1799 1800 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1801 { 1802 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1803 struct uart_port *port = ptr; 1804 struct sci_port *s = to_sci_port(port); 1805 irqreturn_t ret = IRQ_NONE; 1806 1807 ssr_status = serial_port_in(port, SCxSR); 1808 scr_status = serial_port_in(port, SCSCR); 1809 if (s->params->overrun_reg == SCxSR) 1810 orer_status = ssr_status; 1811 else if (sci_getreg(port, s->params->overrun_reg)->size) 1812 orer_status = serial_port_in(port, s->params->overrun_reg); 1813 1814 err_enabled = scr_status & port_rx_irq_mask(port); 1815 1816 /* Tx Interrupt */ 1817 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1818 !s->chan_tx) 1819 ret = sci_tx_interrupt(irq, ptr); 1820 1821 /* 1822 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1823 * DR flags 1824 */ 1825 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1826 (scr_status & SCSCR_RIE)) 1827 ret = sci_rx_interrupt(irq, ptr); 1828 1829 /* Error Interrupt */ 1830 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1831 ret = sci_er_interrupt(irq, ptr); 1832 1833 /* Break Interrupt */ 1834 if ((ssr_status & SCxSR_BRK(port)) && err_enabled) 1835 ret = sci_br_interrupt(irq, ptr); 1836 1837 /* Overrun Interrupt */ 1838 if (orer_status & s->params->overrun_mask) { 1839 sci_handle_fifo_overrun(port); 1840 ret = IRQ_HANDLED; 1841 } 1842 1843 return ret; 1844 } 1845 1846 static const struct sci_irq_desc { 1847 const char *desc; 1848 irq_handler_t handler; 1849 } sci_irq_desc[] = { 1850 /* 1851 * Split out handlers, the default case. 1852 */ 1853 [SCIx_ERI_IRQ] = { 1854 .desc = "rx err", 1855 .handler = sci_er_interrupt, 1856 }, 1857 1858 [SCIx_RXI_IRQ] = { 1859 .desc = "rx full", 1860 .handler = sci_rx_interrupt, 1861 }, 1862 1863 [SCIx_TXI_IRQ] = { 1864 .desc = "tx empty", 1865 .handler = sci_tx_interrupt, 1866 }, 1867 1868 [SCIx_BRI_IRQ] = { 1869 .desc = "break", 1870 .handler = sci_br_interrupt, 1871 }, 1872 1873 [SCIx_DRI_IRQ] = { 1874 .desc = "rx ready", 1875 .handler = sci_rx_interrupt, 1876 }, 1877 1878 [SCIx_TEI_IRQ] = { 1879 .desc = "tx end", 1880 .handler = sci_tx_interrupt, 1881 }, 1882 1883 /* 1884 * Special muxed handler. 1885 */ 1886 [SCIx_MUX_IRQ] = { 1887 .desc = "mux", 1888 .handler = sci_mpxed_interrupt, 1889 }, 1890 }; 1891 1892 static int sci_request_irq(struct sci_port *port) 1893 { 1894 struct uart_port *up = &port->port; 1895 int i, j, w, ret = 0; 1896 1897 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1898 const struct sci_irq_desc *desc; 1899 int irq; 1900 1901 /* Check if already registered (muxed) */ 1902 for (w = 0; w < i; w++) 1903 if (port->irqs[w] == port->irqs[i]) 1904 w = i + 1; 1905 if (w > i) 1906 continue; 1907 1908 if (SCIx_IRQ_IS_MUXED(port)) { 1909 i = SCIx_MUX_IRQ; 1910 irq = up->irq; 1911 } else { 1912 irq = port->irqs[i]; 1913 1914 /* 1915 * Certain port types won't support all of the 1916 * available interrupt sources. 1917 */ 1918 if (unlikely(irq < 0)) 1919 continue; 1920 } 1921 1922 desc = sci_irq_desc + i; 1923 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1924 dev_name(up->dev), desc->desc); 1925 if (!port->irqstr[j]) { 1926 ret = -ENOMEM; 1927 goto out_nomem; 1928 } 1929 1930 ret = request_irq(irq, desc->handler, up->irqflags, 1931 port->irqstr[j], port); 1932 if (unlikely(ret)) { 1933 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1934 goto out_noirq; 1935 } 1936 } 1937 1938 return 0; 1939 1940 out_noirq: 1941 while (--i >= 0) 1942 free_irq(port->irqs[i], port); 1943 1944 out_nomem: 1945 while (--j >= 0) 1946 kfree(port->irqstr[j]); 1947 1948 return ret; 1949 } 1950 1951 static void sci_free_irq(struct sci_port *port) 1952 { 1953 int i, j; 1954 1955 /* 1956 * Intentionally in reverse order so we iterate over the muxed 1957 * IRQ first. 1958 */ 1959 for (i = 0; i < SCIx_NR_IRQS; i++) { 1960 int irq = port->irqs[i]; 1961 1962 /* 1963 * Certain port types won't support all of the available 1964 * interrupt sources. 1965 */ 1966 if (unlikely(irq < 0)) 1967 continue; 1968 1969 /* Check if already freed (irq was muxed) */ 1970 for (j = 0; j < i; j++) 1971 if (port->irqs[j] == irq) 1972 j = i + 1; 1973 if (j > i) 1974 continue; 1975 1976 free_irq(port->irqs[i], port); 1977 kfree(port->irqstr[i]); 1978 1979 if (SCIx_IRQ_IS_MUXED(port)) { 1980 /* If there's only one IRQ, we're done. */ 1981 return; 1982 } 1983 } 1984 } 1985 1986 static unsigned int sci_tx_empty(struct uart_port *port) 1987 { 1988 unsigned short status = serial_port_in(port, SCxSR); 1989 unsigned short in_tx_fifo = sci_txfill(port); 1990 1991 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1992 } 1993 1994 static void sci_set_rts(struct uart_port *port, bool state) 1995 { 1996 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 1997 u16 data = serial_port_in(port, SCPDR); 1998 1999 /* Active low */ 2000 if (state) 2001 data &= ~SCPDR_RTSD; 2002 else 2003 data |= SCPDR_RTSD; 2004 serial_port_out(port, SCPDR, data); 2005 2006 /* RTS# is output */ 2007 serial_port_out(port, SCPCR, 2008 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2009 } else if (sci_getreg(port, SCSPTR)->size) { 2010 u16 ctrl = serial_port_in(port, SCSPTR); 2011 2012 /* Active low */ 2013 if (state) 2014 ctrl &= ~SCSPTR_RTSDT; 2015 else 2016 ctrl |= SCSPTR_RTSDT; 2017 serial_port_out(port, SCSPTR, ctrl); 2018 } 2019 } 2020 2021 static bool sci_get_cts(struct uart_port *port) 2022 { 2023 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2024 /* Active low */ 2025 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2026 } else if (sci_getreg(port, SCSPTR)->size) { 2027 /* Active low */ 2028 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2029 } 2030 2031 return true; 2032 } 2033 2034 /* 2035 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2036 * CTS/RTS is supported in hardware by at least one port and controlled 2037 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2038 * handled via the ->init_pins() op, which is a bit of a one-way street, 2039 * lacking any ability to defer pin control -- this will later be 2040 * converted over to the GPIO framework). 2041 * 2042 * Other modes (such as loopback) are supported generically on certain 2043 * port types, but not others. For these it's sufficient to test for the 2044 * existence of the support register and simply ignore the port type. 2045 */ 2046 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2047 { 2048 struct sci_port *s = to_sci_port(port); 2049 2050 if (mctrl & TIOCM_LOOP) { 2051 const struct plat_sci_reg *reg; 2052 2053 /* 2054 * Standard loopback mode for SCFCR ports. 2055 */ 2056 reg = sci_getreg(port, SCFCR); 2057 if (reg->size) 2058 serial_port_out(port, SCFCR, 2059 serial_port_in(port, SCFCR) | 2060 SCFCR_LOOP); 2061 } 2062 2063 mctrl_gpio_set(s->gpios, mctrl); 2064 2065 if (!s->has_rtscts) 2066 return; 2067 2068 if (!(mctrl & TIOCM_RTS)) { 2069 /* Disable Auto RTS */ 2070 serial_port_out(port, SCFCR, 2071 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2072 2073 /* Clear RTS */ 2074 sci_set_rts(port, 0); 2075 } else if (s->autorts) { 2076 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2077 /* Enable RTS# pin function */ 2078 serial_port_out(port, SCPCR, 2079 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2080 } 2081 2082 /* Enable Auto RTS */ 2083 serial_port_out(port, SCFCR, 2084 serial_port_in(port, SCFCR) | SCFCR_MCE); 2085 } else { 2086 /* Set RTS */ 2087 sci_set_rts(port, 1); 2088 } 2089 } 2090 2091 static unsigned int sci_get_mctrl(struct uart_port *port) 2092 { 2093 struct sci_port *s = to_sci_port(port); 2094 struct mctrl_gpios *gpios = s->gpios; 2095 unsigned int mctrl = 0; 2096 2097 mctrl_gpio_get(gpios, &mctrl); 2098 2099 /* 2100 * CTS/RTS is handled in hardware when supported, while nothing 2101 * else is wired up. 2102 */ 2103 if (s->autorts) { 2104 if (sci_get_cts(port)) 2105 mctrl |= TIOCM_CTS; 2106 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2107 mctrl |= TIOCM_CTS; 2108 } 2109 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2110 mctrl |= TIOCM_DSR; 2111 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2112 mctrl |= TIOCM_CAR; 2113 2114 return mctrl; 2115 } 2116 2117 static void sci_enable_ms(struct uart_port *port) 2118 { 2119 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2120 } 2121 2122 static void sci_break_ctl(struct uart_port *port, int break_state) 2123 { 2124 unsigned short scscr, scsptr; 2125 unsigned long flags; 2126 2127 /* check wheter the port has SCSPTR */ 2128 if (!sci_getreg(port, SCSPTR)->size) { 2129 /* 2130 * Not supported by hardware. Most parts couple break and rx 2131 * interrupts together, with break detection always enabled. 2132 */ 2133 return; 2134 } 2135 2136 spin_lock_irqsave(&port->lock, flags); 2137 scsptr = serial_port_in(port, SCSPTR); 2138 scscr = serial_port_in(port, SCSCR); 2139 2140 if (break_state == -1) { 2141 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2142 scscr &= ~SCSCR_TE; 2143 } else { 2144 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2145 scscr |= SCSCR_TE; 2146 } 2147 2148 serial_port_out(port, SCSPTR, scsptr); 2149 serial_port_out(port, SCSCR, scscr); 2150 spin_unlock_irqrestore(&port->lock, flags); 2151 } 2152 2153 static int sci_startup(struct uart_port *port) 2154 { 2155 struct sci_port *s = to_sci_port(port); 2156 int ret; 2157 2158 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2159 2160 sci_request_dma(port); 2161 2162 ret = sci_request_irq(s); 2163 if (unlikely(ret < 0)) { 2164 sci_free_dma(port); 2165 return ret; 2166 } 2167 2168 return 0; 2169 } 2170 2171 static void sci_shutdown(struct uart_port *port) 2172 { 2173 struct sci_port *s = to_sci_port(port); 2174 unsigned long flags; 2175 u16 scr; 2176 2177 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2178 2179 s->autorts = false; 2180 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2181 2182 spin_lock_irqsave(&port->lock, flags); 2183 sci_stop_rx(port); 2184 sci_stop_tx(port); 2185 /* 2186 * Stop RX and TX, disable related interrupts, keep clock source 2187 * and HSCIF TOT bits 2188 */ 2189 scr = serial_port_in(port, SCSCR); 2190 serial_port_out(port, SCSCR, scr & 2191 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2192 spin_unlock_irqrestore(&port->lock, flags); 2193 2194 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2195 if (s->chan_rx_saved) { 2196 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2197 port->line); 2198 hrtimer_cancel(&s->rx_timer); 2199 } 2200 #endif 2201 2202 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2203 del_timer_sync(&s->rx_fifo_timer); 2204 sci_free_irq(s); 2205 sci_free_dma(port); 2206 } 2207 2208 static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2209 unsigned int *srr) 2210 { 2211 unsigned long freq = s->clk_rates[SCI_SCK]; 2212 int err, min_err = INT_MAX; 2213 unsigned int sr; 2214 2215 if (s->port.type != PORT_HSCIF) 2216 freq *= 2; 2217 2218 for_each_sr(sr, s) { 2219 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2220 if (abs(err) >= abs(min_err)) 2221 continue; 2222 2223 min_err = err; 2224 *srr = sr - 1; 2225 2226 if (!err) 2227 break; 2228 } 2229 2230 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2231 *srr + 1); 2232 return min_err; 2233 } 2234 2235 static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2236 unsigned long freq, unsigned int *dlr, 2237 unsigned int *srr) 2238 { 2239 int err, min_err = INT_MAX; 2240 unsigned int sr, dl; 2241 2242 if (s->port.type != PORT_HSCIF) 2243 freq *= 2; 2244 2245 for_each_sr(sr, s) { 2246 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2247 dl = clamp(dl, 1U, 65535U); 2248 2249 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2250 if (abs(err) >= abs(min_err)) 2251 continue; 2252 2253 min_err = err; 2254 *dlr = dl; 2255 *srr = sr - 1; 2256 2257 if (!err) 2258 break; 2259 } 2260 2261 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2262 min_err, *dlr, *srr + 1); 2263 return min_err; 2264 } 2265 2266 /* calculate sample rate, BRR, and clock select */ 2267 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2268 unsigned int *brr, unsigned int *srr, 2269 unsigned int *cks) 2270 { 2271 unsigned long freq = s->clk_rates[SCI_FCK]; 2272 unsigned int sr, br, prediv, scrate, c; 2273 int err, min_err = INT_MAX; 2274 2275 if (s->port.type != PORT_HSCIF) 2276 freq *= 2; 2277 2278 /* 2279 * Find the combination of sample rate and clock select with the 2280 * smallest deviation from the desired baud rate. 2281 * Prefer high sample rates to maximise the receive margin. 2282 * 2283 * M: Receive margin (%) 2284 * N: Ratio of bit rate to clock (N = sampling rate) 2285 * D: Clock duty (D = 0 to 1.0) 2286 * L: Frame length (L = 9 to 12) 2287 * F: Absolute value of clock frequency deviation 2288 * 2289 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2290 * (|D - 0.5| / N * (1 + F))| 2291 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2292 */ 2293 for_each_sr(sr, s) { 2294 for (c = 0; c <= 3; c++) { 2295 /* integerized formulas from HSCIF documentation */ 2296 prediv = sr * (1 << (2 * c + 1)); 2297 2298 /* 2299 * We need to calculate: 2300 * 2301 * br = freq / (prediv * bps) clamped to [1..256] 2302 * err = freq / (br * prediv) - bps 2303 * 2304 * Watch out for overflow when calculating the desired 2305 * sampling clock rate! 2306 */ 2307 if (bps > UINT_MAX / prediv) 2308 break; 2309 2310 scrate = prediv * bps; 2311 br = DIV_ROUND_CLOSEST(freq, scrate); 2312 br = clamp(br, 1U, 256U); 2313 2314 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2315 if (abs(err) >= abs(min_err)) 2316 continue; 2317 2318 min_err = err; 2319 *brr = br - 1; 2320 *srr = sr - 1; 2321 *cks = c; 2322 2323 if (!err) 2324 goto found; 2325 } 2326 } 2327 2328 found: 2329 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2330 min_err, *brr, *srr + 1, *cks); 2331 return min_err; 2332 } 2333 2334 static void sci_reset(struct uart_port *port) 2335 { 2336 const struct plat_sci_reg *reg; 2337 unsigned int status; 2338 struct sci_port *s = to_sci_port(port); 2339 2340 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2341 2342 reg = sci_getreg(port, SCFCR); 2343 if (reg->size) 2344 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2345 2346 sci_clear_SCxSR(port, 2347 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2348 SCxSR_BREAK_CLEAR(port)); 2349 if (sci_getreg(port, SCLSR)->size) { 2350 status = serial_port_in(port, SCLSR); 2351 status &= ~(SCLSR_TO | SCLSR_ORER); 2352 serial_port_out(port, SCLSR, status); 2353 } 2354 2355 if (s->rx_trigger > 1) { 2356 if (s->rx_fifo_timeout) { 2357 scif_set_rtrg(port, 1); 2358 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2359 } else { 2360 if (port->type == PORT_SCIFA || 2361 port->type == PORT_SCIFB) 2362 scif_set_rtrg(port, 1); 2363 else 2364 scif_set_rtrg(port, s->rx_trigger); 2365 } 2366 } 2367 } 2368 2369 static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2370 struct ktermios *old) 2371 { 2372 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2373 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2374 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2375 struct sci_port *s = to_sci_port(port); 2376 const struct plat_sci_reg *reg; 2377 int min_err = INT_MAX, err; 2378 unsigned long max_freq = 0; 2379 int best_clk = -1; 2380 unsigned long flags; 2381 2382 if ((termios->c_cflag & CSIZE) == CS7) 2383 smr_val |= SCSMR_CHR; 2384 if (termios->c_cflag & PARENB) 2385 smr_val |= SCSMR_PE; 2386 if (termios->c_cflag & PARODD) 2387 smr_val |= SCSMR_PE | SCSMR_ODD; 2388 if (termios->c_cflag & CSTOPB) 2389 smr_val |= SCSMR_STOP; 2390 2391 /* 2392 * earlyprintk comes here early on with port->uartclk set to zero. 2393 * the clock framework is not up and running at this point so here 2394 * we assume that 115200 is the maximum baud rate. please note that 2395 * the baud rate is not programmed during earlyprintk - it is assumed 2396 * that the previous boot loader has enabled required clocks and 2397 * setup the baud rate generator hardware for us already. 2398 */ 2399 if (!port->uartclk) { 2400 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2401 goto done; 2402 } 2403 2404 for (i = 0; i < SCI_NUM_CLKS; i++) 2405 max_freq = max(max_freq, s->clk_rates[i]); 2406 2407 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2408 if (!baud) 2409 goto done; 2410 2411 /* 2412 * There can be multiple sources for the sampling clock. Find the one 2413 * that gives us the smallest deviation from the desired baud rate. 2414 */ 2415 2416 /* Optional Undivided External Clock */ 2417 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2418 port->type != PORT_SCIFB) { 2419 err = sci_sck_calc(s, baud, &srr1); 2420 if (abs(err) < abs(min_err)) { 2421 best_clk = SCI_SCK; 2422 scr_val = SCSCR_CKE1; 2423 sccks = SCCKS_CKS; 2424 min_err = err; 2425 srr = srr1; 2426 if (!err) 2427 goto done; 2428 } 2429 } 2430 2431 /* Optional BRG Frequency Divided External Clock */ 2432 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2433 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2434 &srr1); 2435 if (abs(err) < abs(min_err)) { 2436 best_clk = SCI_SCIF_CLK; 2437 scr_val = SCSCR_CKE1; 2438 sccks = 0; 2439 min_err = err; 2440 dl = dl1; 2441 srr = srr1; 2442 if (!err) 2443 goto done; 2444 } 2445 } 2446 2447 /* Optional BRG Frequency Divided Internal Clock */ 2448 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2449 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2450 &srr1); 2451 if (abs(err) < abs(min_err)) { 2452 best_clk = SCI_BRG_INT; 2453 scr_val = SCSCR_CKE1; 2454 sccks = SCCKS_XIN; 2455 min_err = err; 2456 dl = dl1; 2457 srr = srr1; 2458 if (!min_err) 2459 goto done; 2460 } 2461 } 2462 2463 /* Divided Functional Clock using standard Bit Rate Register */ 2464 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2465 if (abs(err) < abs(min_err)) { 2466 best_clk = SCI_FCK; 2467 scr_val = 0; 2468 min_err = err; 2469 brr = brr1; 2470 srr = srr1; 2471 cks = cks1; 2472 } 2473 2474 done: 2475 if (best_clk >= 0) 2476 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2477 s->clks[best_clk], baud, min_err); 2478 2479 sci_port_enable(s); 2480 2481 /* 2482 * Program the optional External Baud Rate Generator (BRG) first. 2483 * It controls the mux to select (H)SCK or frequency divided clock. 2484 */ 2485 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2486 serial_port_out(port, SCDL, dl); 2487 serial_port_out(port, SCCKS, sccks); 2488 } 2489 2490 spin_lock_irqsave(&port->lock, flags); 2491 2492 sci_reset(port); 2493 2494 uart_update_timeout(port, termios->c_cflag, baud); 2495 2496 /* byte size and parity */ 2497 switch (termios->c_cflag & CSIZE) { 2498 case CS5: 2499 bits = 7; 2500 break; 2501 case CS6: 2502 bits = 8; 2503 break; 2504 case CS7: 2505 bits = 9; 2506 break; 2507 default: 2508 bits = 10; 2509 break; 2510 } 2511 2512 if (termios->c_cflag & CSTOPB) 2513 bits++; 2514 if (termios->c_cflag & PARENB) 2515 bits++; 2516 2517 if (best_clk >= 0) { 2518 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2519 switch (srr + 1) { 2520 case 5: smr_val |= SCSMR_SRC_5; break; 2521 case 7: smr_val |= SCSMR_SRC_7; break; 2522 case 11: smr_val |= SCSMR_SRC_11; break; 2523 case 13: smr_val |= SCSMR_SRC_13; break; 2524 case 16: smr_val |= SCSMR_SRC_16; break; 2525 case 17: smr_val |= SCSMR_SRC_17; break; 2526 case 19: smr_val |= SCSMR_SRC_19; break; 2527 case 27: smr_val |= SCSMR_SRC_27; break; 2528 } 2529 smr_val |= cks; 2530 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2531 serial_port_out(port, SCSMR, smr_val); 2532 serial_port_out(port, SCBRR, brr); 2533 if (sci_getreg(port, HSSRR)->size) { 2534 unsigned int hssrr = srr | HSCIF_SRE; 2535 /* Calculate deviation from intended rate at the 2536 * center of the last stop bit in sampling clocks. 2537 */ 2538 int last_stop = bits * 2 - 1; 2539 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2540 (int)(srr + 1), 2541 2 * (int)baud); 2542 2543 if (abs(deviation) >= 2) { 2544 /* At least two sampling clocks off at the 2545 * last stop bit; we can increase the error 2546 * margin by shifting the sampling point. 2547 */ 2548 int shift = clamp(deviation / 2, -8, 7); 2549 2550 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2551 HSCIF_SRHP_MASK; 2552 hssrr |= HSCIF_SRDE; 2553 } 2554 serial_port_out(port, HSSRR, hssrr); 2555 } 2556 2557 /* Wait one bit interval */ 2558 udelay((1000000 + (baud - 1)) / baud); 2559 } else { 2560 /* Don't touch the bit rate configuration */ 2561 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2562 smr_val |= serial_port_in(port, SCSMR) & 2563 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2564 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2565 serial_port_out(port, SCSMR, smr_val); 2566 } 2567 2568 sci_init_pins(port, termios->c_cflag); 2569 2570 port->status &= ~UPSTAT_AUTOCTS; 2571 s->autorts = false; 2572 reg = sci_getreg(port, SCFCR); 2573 if (reg->size) { 2574 unsigned short ctrl = serial_port_in(port, SCFCR); 2575 2576 if ((port->flags & UPF_HARD_FLOW) && 2577 (termios->c_cflag & CRTSCTS)) { 2578 /* There is no CTS interrupt to restart the hardware */ 2579 port->status |= UPSTAT_AUTOCTS; 2580 /* MCE is enabled when RTS is raised */ 2581 s->autorts = true; 2582 } 2583 2584 /* 2585 * As we've done a sci_reset() above, ensure we don't 2586 * interfere with the FIFOs while toggling MCE. As the 2587 * reset values could still be set, simply mask them out. 2588 */ 2589 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2590 2591 serial_port_out(port, SCFCR, ctrl); 2592 } 2593 if (port->flags & UPF_HARD_FLOW) { 2594 /* Refresh (Auto) RTS */ 2595 sci_set_mctrl(port, port->mctrl); 2596 } 2597 2598 scr_val |= SCSCR_RE | SCSCR_TE | 2599 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2600 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2601 if ((srr + 1 == 5) && 2602 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2603 /* 2604 * In asynchronous mode, when the sampling rate is 1/5, first 2605 * received data may become invalid on some SCIFA and SCIFB. 2606 * To avoid this problem wait more than 1 serial data time (1 2607 * bit time x serial data number) after setting SCSCR.RE = 1. 2608 */ 2609 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2610 } 2611 2612 /* 2613 * Calculate delay for 2 DMA buffers (4 FIFO). 2614 * See serial_core.c::uart_update_timeout(). 2615 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above 2616 * function calculates 1 jiffie for the data plus 5 jiffies for the 2617 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA 2618 * buffers (4 FIFO sizes), but when performing a faster transfer, the 2619 * value obtained by this formula is too small. Therefore, if the value 2620 * is smaller than 20ms, use 20ms as the timeout value for DMA. 2621 */ 2622 s->rx_frame = (10000 * bits) / (baud / 100); 2623 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2624 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2625 if (s->rx_timeout < 20) 2626 s->rx_timeout = 20; 2627 #endif 2628 2629 if ((termios->c_cflag & CREAD) != 0) 2630 sci_start_rx(port); 2631 2632 spin_unlock_irqrestore(&port->lock, flags); 2633 2634 sci_port_disable(s); 2635 2636 if (UART_ENABLE_MS(port, termios->c_cflag)) 2637 sci_enable_ms(port); 2638 } 2639 2640 static void sci_pm(struct uart_port *port, unsigned int state, 2641 unsigned int oldstate) 2642 { 2643 struct sci_port *sci_port = to_sci_port(port); 2644 2645 switch (state) { 2646 case UART_PM_STATE_OFF: 2647 sci_port_disable(sci_port); 2648 break; 2649 default: 2650 sci_port_enable(sci_port); 2651 break; 2652 } 2653 } 2654 2655 static const char *sci_type(struct uart_port *port) 2656 { 2657 switch (port->type) { 2658 case PORT_IRDA: 2659 return "irda"; 2660 case PORT_SCI: 2661 return "sci"; 2662 case PORT_SCIF: 2663 return "scif"; 2664 case PORT_SCIFA: 2665 return "scifa"; 2666 case PORT_SCIFB: 2667 return "scifb"; 2668 case PORT_HSCIF: 2669 return "hscif"; 2670 } 2671 2672 return NULL; 2673 } 2674 2675 static int sci_remap_port(struct uart_port *port) 2676 { 2677 struct sci_port *sport = to_sci_port(port); 2678 2679 /* 2680 * Nothing to do if there's already an established membase. 2681 */ 2682 if (port->membase) 2683 return 0; 2684 2685 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2686 port->membase = ioremap(port->mapbase, sport->reg_size); 2687 if (unlikely(!port->membase)) { 2688 dev_err(port->dev, "can't remap port#%d\n", port->line); 2689 return -ENXIO; 2690 } 2691 } else { 2692 /* 2693 * For the simple (and majority of) cases where we don't 2694 * need to do any remapping, just cast the cookie 2695 * directly. 2696 */ 2697 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static void sci_release_port(struct uart_port *port) 2704 { 2705 struct sci_port *sport = to_sci_port(port); 2706 2707 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2708 iounmap(port->membase); 2709 port->membase = NULL; 2710 } 2711 2712 release_mem_region(port->mapbase, sport->reg_size); 2713 } 2714 2715 static int sci_request_port(struct uart_port *port) 2716 { 2717 struct resource *res; 2718 struct sci_port *sport = to_sci_port(port); 2719 int ret; 2720 2721 res = request_mem_region(port->mapbase, sport->reg_size, 2722 dev_name(port->dev)); 2723 if (unlikely(res == NULL)) { 2724 dev_err(port->dev, "request_mem_region failed."); 2725 return -EBUSY; 2726 } 2727 2728 ret = sci_remap_port(port); 2729 if (unlikely(ret != 0)) { 2730 release_resource(res); 2731 return ret; 2732 } 2733 2734 return 0; 2735 } 2736 2737 static void sci_config_port(struct uart_port *port, int flags) 2738 { 2739 if (flags & UART_CONFIG_TYPE) { 2740 struct sci_port *sport = to_sci_port(port); 2741 2742 port->type = sport->cfg->type; 2743 sci_request_port(port); 2744 } 2745 } 2746 2747 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2748 { 2749 if (ser->baud_base < 2400) 2750 /* No paper tape reader for Mitch.. */ 2751 return -EINVAL; 2752 2753 return 0; 2754 } 2755 2756 static const struct uart_ops sci_uart_ops = { 2757 .tx_empty = sci_tx_empty, 2758 .set_mctrl = sci_set_mctrl, 2759 .get_mctrl = sci_get_mctrl, 2760 .start_tx = sci_start_tx, 2761 .stop_tx = sci_stop_tx, 2762 .stop_rx = sci_stop_rx, 2763 .enable_ms = sci_enable_ms, 2764 .break_ctl = sci_break_ctl, 2765 .startup = sci_startup, 2766 .shutdown = sci_shutdown, 2767 .flush_buffer = sci_flush_buffer, 2768 .set_termios = sci_set_termios, 2769 .pm = sci_pm, 2770 .type = sci_type, 2771 .release_port = sci_release_port, 2772 .request_port = sci_request_port, 2773 .config_port = sci_config_port, 2774 .verify_port = sci_verify_port, 2775 #ifdef CONFIG_CONSOLE_POLL 2776 .poll_get_char = sci_poll_get_char, 2777 .poll_put_char = sci_poll_put_char, 2778 #endif 2779 }; 2780 2781 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2782 { 2783 const char *clk_names[] = { 2784 [SCI_FCK] = "fck", 2785 [SCI_SCK] = "sck", 2786 [SCI_BRG_INT] = "brg_int", 2787 [SCI_SCIF_CLK] = "scif_clk", 2788 }; 2789 struct clk *clk; 2790 unsigned int i; 2791 2792 if (sci_port->cfg->type == PORT_HSCIF) 2793 clk_names[SCI_SCK] = "hsck"; 2794 2795 for (i = 0; i < SCI_NUM_CLKS; i++) { 2796 clk = devm_clk_get(dev, clk_names[i]); 2797 if (PTR_ERR(clk) == -EPROBE_DEFER) 2798 return -EPROBE_DEFER; 2799 2800 if (IS_ERR(clk) && i == SCI_FCK) { 2801 /* 2802 * "fck" used to be called "sci_ick", and we need to 2803 * maintain DT backward compatibility. 2804 */ 2805 clk = devm_clk_get(dev, "sci_ick"); 2806 if (PTR_ERR(clk) == -EPROBE_DEFER) 2807 return -EPROBE_DEFER; 2808 2809 if (!IS_ERR(clk)) 2810 goto found; 2811 2812 /* 2813 * Not all SH platforms declare a clock lookup entry 2814 * for SCI devices, in which case we need to get the 2815 * global "peripheral_clk" clock. 2816 */ 2817 clk = devm_clk_get(dev, "peripheral_clk"); 2818 if (!IS_ERR(clk)) 2819 goto found; 2820 2821 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], 2822 PTR_ERR(clk)); 2823 return PTR_ERR(clk); 2824 } 2825 2826 found: 2827 if (IS_ERR(clk)) 2828 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], 2829 PTR_ERR(clk)); 2830 else 2831 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2832 clk, clk_get_rate(clk)); 2833 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; 2834 } 2835 return 0; 2836 } 2837 2838 static const struct sci_port_params * 2839 sci_probe_regmap(const struct plat_sci_port *cfg) 2840 { 2841 unsigned int regtype; 2842 2843 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2844 return &sci_port_params[cfg->regtype]; 2845 2846 switch (cfg->type) { 2847 case PORT_SCI: 2848 regtype = SCIx_SCI_REGTYPE; 2849 break; 2850 case PORT_IRDA: 2851 regtype = SCIx_IRDA_REGTYPE; 2852 break; 2853 case PORT_SCIFA: 2854 regtype = SCIx_SCIFA_REGTYPE; 2855 break; 2856 case PORT_SCIFB: 2857 regtype = SCIx_SCIFB_REGTYPE; 2858 break; 2859 case PORT_SCIF: 2860 /* 2861 * The SH-4 is a bit of a misnomer here, although that's 2862 * where this particular port layout originated. This 2863 * configuration (or some slight variation thereof) 2864 * remains the dominant model for all SCIFs. 2865 */ 2866 regtype = SCIx_SH4_SCIF_REGTYPE; 2867 break; 2868 case PORT_HSCIF: 2869 regtype = SCIx_HSCIF_REGTYPE; 2870 break; 2871 default: 2872 pr_err("Can't probe register map for given port\n"); 2873 return NULL; 2874 } 2875 2876 return &sci_port_params[regtype]; 2877 } 2878 2879 static int sci_init_single(struct platform_device *dev, 2880 struct sci_port *sci_port, unsigned int index, 2881 const struct plat_sci_port *p, bool early) 2882 { 2883 struct uart_port *port = &sci_port->port; 2884 const struct resource *res; 2885 unsigned int i; 2886 int ret; 2887 2888 sci_port->cfg = p; 2889 2890 port->ops = &sci_uart_ops; 2891 port->iotype = UPIO_MEM; 2892 port->line = index; 2893 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2894 2895 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2896 if (res == NULL) 2897 return -ENOMEM; 2898 2899 port->mapbase = res->start; 2900 sci_port->reg_size = resource_size(res); 2901 2902 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2903 if (i) 2904 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2905 else 2906 sci_port->irqs[i] = platform_get_irq(dev, i); 2907 } 2908 2909 /* The SCI generates several interrupts. They can be muxed together or 2910 * connected to different interrupt lines. In the muxed case only one 2911 * interrupt resource is specified as there is only one interrupt ID. 2912 * In the non-muxed case, up to 6 interrupt signals might be generated 2913 * from the SCI, however those signals might have their own individual 2914 * interrupt ID numbers, or muxed together with another interrupt. 2915 */ 2916 if (sci_port->irqs[0] < 0) 2917 return -ENXIO; 2918 2919 if (sci_port->irqs[1] < 0) 2920 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2921 sci_port->irqs[i] = sci_port->irqs[0]; 2922 2923 sci_port->params = sci_probe_regmap(p); 2924 if (unlikely(sci_port->params == NULL)) 2925 return -EINVAL; 2926 2927 switch (p->type) { 2928 case PORT_SCIFB: 2929 sci_port->rx_trigger = 48; 2930 break; 2931 case PORT_HSCIF: 2932 sci_port->rx_trigger = 64; 2933 break; 2934 case PORT_SCIFA: 2935 sci_port->rx_trigger = 32; 2936 break; 2937 case PORT_SCIF: 2938 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2939 /* RX triggering not implemented for this IP */ 2940 sci_port->rx_trigger = 1; 2941 else 2942 sci_port->rx_trigger = 8; 2943 break; 2944 default: 2945 sci_port->rx_trigger = 1; 2946 break; 2947 } 2948 2949 sci_port->rx_fifo_timeout = 0; 2950 sci_port->hscif_tot = 0; 2951 2952 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2953 * match the SoC datasheet, this should be investigated. Let platform 2954 * data override the sampling rate for now. 2955 */ 2956 sci_port->sampling_rate_mask = p->sampling_rate 2957 ? SCI_SR(p->sampling_rate) 2958 : sci_port->params->sampling_rate_mask; 2959 2960 if (!early) { 2961 ret = sci_init_clocks(sci_port, &dev->dev); 2962 if (ret < 0) 2963 return ret; 2964 2965 port->dev = &dev->dev; 2966 2967 pm_runtime_enable(&dev->dev); 2968 } 2969 2970 port->type = p->type; 2971 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 2972 port->fifosize = sci_port->params->fifosize; 2973 2974 if (port->type == PORT_SCI) { 2975 if (sci_port->reg_size >= 0x20) 2976 port->regshift = 2; 2977 else 2978 port->regshift = 1; 2979 } 2980 2981 /* 2982 * The UART port needs an IRQ value, so we peg this to the RX IRQ 2983 * for the multi-IRQ ports, which is where we are primarily 2984 * concerned with the shutdown path synchronization. 2985 * 2986 * For the muxed case there's nothing more to do. 2987 */ 2988 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 2989 port->irqflags = 0; 2990 2991 port->serial_in = sci_serial_in; 2992 port->serial_out = sci_serial_out; 2993 2994 return 0; 2995 } 2996 2997 static void sci_cleanup_single(struct sci_port *port) 2998 { 2999 pm_runtime_disable(port->port.dev); 3000 } 3001 3002 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3003 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3004 static void serial_console_putchar(struct uart_port *port, int ch) 3005 { 3006 sci_poll_put_char(port, ch); 3007 } 3008 3009 /* 3010 * Print a string to the serial port trying not to disturb 3011 * any possible real use of the port... 3012 */ 3013 static void serial_console_write(struct console *co, const char *s, 3014 unsigned count) 3015 { 3016 struct sci_port *sci_port = &sci_ports[co->index]; 3017 struct uart_port *port = &sci_port->port; 3018 unsigned short bits, ctrl, ctrl_temp; 3019 unsigned long flags; 3020 int locked = 1; 3021 3022 if (port->sysrq) 3023 locked = 0; 3024 else if (oops_in_progress) 3025 locked = spin_trylock_irqsave(&port->lock, flags); 3026 else 3027 spin_lock_irqsave(&port->lock, flags); 3028 3029 /* first save SCSCR then disable interrupts, keep clock source */ 3030 ctrl = serial_port_in(port, SCSCR); 3031 ctrl_temp = SCSCR_RE | SCSCR_TE | 3032 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3033 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3034 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3035 3036 uart_console_write(port, s, count, serial_console_putchar); 3037 3038 /* wait until fifo is empty and last bit has been transmitted */ 3039 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3040 while ((serial_port_in(port, SCxSR) & bits) != bits) 3041 cpu_relax(); 3042 3043 /* restore the SCSCR */ 3044 serial_port_out(port, SCSCR, ctrl); 3045 3046 if (locked) 3047 spin_unlock_irqrestore(&port->lock, flags); 3048 } 3049 3050 static int serial_console_setup(struct console *co, char *options) 3051 { 3052 struct sci_port *sci_port; 3053 struct uart_port *port; 3054 int baud = 115200; 3055 int bits = 8; 3056 int parity = 'n'; 3057 int flow = 'n'; 3058 int ret; 3059 3060 /* 3061 * Refuse to handle any bogus ports. 3062 */ 3063 if (co->index < 0 || co->index >= SCI_NPORTS) 3064 return -ENODEV; 3065 3066 sci_port = &sci_ports[co->index]; 3067 port = &sci_port->port; 3068 3069 /* 3070 * Refuse to handle uninitialized ports. 3071 */ 3072 if (!port->ops) 3073 return -ENODEV; 3074 3075 ret = sci_remap_port(port); 3076 if (unlikely(ret != 0)) 3077 return ret; 3078 3079 if (options) 3080 uart_parse_options(options, &baud, &parity, &bits, &flow); 3081 3082 return uart_set_options(port, co, baud, parity, bits, flow); 3083 } 3084 3085 static struct console serial_console = { 3086 .name = "ttySC", 3087 .device = uart_console_device, 3088 .write = serial_console_write, 3089 .setup = serial_console_setup, 3090 .flags = CON_PRINTBUFFER, 3091 .index = -1, 3092 .data = &sci_uart_driver, 3093 }; 3094 3095 #ifdef CONFIG_SUPERH 3096 static struct console early_serial_console = { 3097 .name = "early_ttySC", 3098 .write = serial_console_write, 3099 .flags = CON_PRINTBUFFER, 3100 .index = -1, 3101 }; 3102 3103 static char early_serial_buf[32]; 3104 3105 static int sci_probe_earlyprintk(struct platform_device *pdev) 3106 { 3107 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3108 3109 if (early_serial_console.data) 3110 return -EEXIST; 3111 3112 early_serial_console.index = pdev->id; 3113 3114 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3115 3116 serial_console_setup(&early_serial_console, early_serial_buf); 3117 3118 if (!strstr(early_serial_buf, "keep")) 3119 early_serial_console.flags |= CON_BOOT; 3120 3121 register_console(&early_serial_console); 3122 return 0; 3123 } 3124 #endif 3125 3126 #define SCI_CONSOLE (&serial_console) 3127 3128 #else 3129 static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3130 { 3131 return -EINVAL; 3132 } 3133 3134 #define SCI_CONSOLE NULL 3135 3136 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3137 3138 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3139 3140 static DEFINE_MUTEX(sci_uart_registration_lock); 3141 static struct uart_driver sci_uart_driver = { 3142 .owner = THIS_MODULE, 3143 .driver_name = "sci", 3144 .dev_name = "ttySC", 3145 .major = SCI_MAJOR, 3146 .minor = SCI_MINOR_START, 3147 .nr = SCI_NPORTS, 3148 .cons = SCI_CONSOLE, 3149 }; 3150 3151 static int sci_remove(struct platform_device *dev) 3152 { 3153 struct sci_port *port = platform_get_drvdata(dev); 3154 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3155 3156 sci_ports_in_use &= ~BIT(port->port.line); 3157 uart_remove_one_port(&sci_uart_driver, &port->port); 3158 3159 sci_cleanup_single(port); 3160 3161 if (port->port.fifosize > 1) 3162 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3163 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3164 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3165 3166 return 0; 3167 } 3168 3169 3170 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3171 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3172 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3173 3174 static const struct of_device_id of_sci_match[] = { 3175 /* SoC-specific types */ 3176 { 3177 .compatible = "renesas,scif-r7s72100", 3178 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3179 }, 3180 { 3181 .compatible = "renesas,scif-r7s9210", 3182 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3183 }, 3184 /* Family-specific types */ 3185 { 3186 .compatible = "renesas,rcar-gen1-scif", 3187 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3188 }, { 3189 .compatible = "renesas,rcar-gen2-scif", 3190 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3191 }, { 3192 .compatible = "renesas,rcar-gen3-scif", 3193 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3194 }, 3195 /* Generic types */ 3196 { 3197 .compatible = "renesas,scif", 3198 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3199 }, { 3200 .compatible = "renesas,scifa", 3201 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3202 }, { 3203 .compatible = "renesas,scifb", 3204 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3205 }, { 3206 .compatible = "renesas,hscif", 3207 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3208 }, { 3209 .compatible = "renesas,sci", 3210 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3211 }, { 3212 /* Terminator */ 3213 }, 3214 }; 3215 MODULE_DEVICE_TABLE(of, of_sci_match); 3216 3217 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3218 unsigned int *dev_id) 3219 { 3220 struct device_node *np = pdev->dev.of_node; 3221 struct plat_sci_port *p; 3222 struct sci_port *sp; 3223 const void *data; 3224 int id; 3225 3226 if (!IS_ENABLED(CONFIG_OF) || !np) 3227 return NULL; 3228 3229 data = of_device_get_match_data(&pdev->dev); 3230 3231 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3232 if (!p) 3233 return NULL; 3234 3235 /* Get the line number from the aliases node. */ 3236 id = of_alias_get_id(np, "serial"); 3237 if (id < 0 && ~sci_ports_in_use) 3238 id = ffz(sci_ports_in_use); 3239 if (id < 0) { 3240 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3241 return NULL; 3242 } 3243 if (id >= ARRAY_SIZE(sci_ports)) { 3244 dev_err(&pdev->dev, "serial%d out of range\n", id); 3245 return NULL; 3246 } 3247 3248 sp = &sci_ports[id]; 3249 *dev_id = id; 3250 3251 p->type = SCI_OF_TYPE(data); 3252 p->regtype = SCI_OF_REGTYPE(data); 3253 3254 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3255 3256 return p; 3257 } 3258 3259 static int sci_probe_single(struct platform_device *dev, 3260 unsigned int index, 3261 struct plat_sci_port *p, 3262 struct sci_port *sciport) 3263 { 3264 int ret; 3265 3266 /* Sanity check */ 3267 if (unlikely(index >= SCI_NPORTS)) { 3268 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3269 index+1, SCI_NPORTS); 3270 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3271 return -EINVAL; 3272 } 3273 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3274 if (sci_ports_in_use & BIT(index)) 3275 return -EBUSY; 3276 3277 mutex_lock(&sci_uart_registration_lock); 3278 if (!sci_uart_driver.state) { 3279 ret = uart_register_driver(&sci_uart_driver); 3280 if (ret) { 3281 mutex_unlock(&sci_uart_registration_lock); 3282 return ret; 3283 } 3284 } 3285 mutex_unlock(&sci_uart_registration_lock); 3286 3287 ret = sci_init_single(dev, sciport, index, p, false); 3288 if (ret) 3289 return ret; 3290 3291 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3292 if (IS_ERR(sciport->gpios)) 3293 return PTR_ERR(sciport->gpios); 3294 3295 if (sciport->has_rtscts) { 3296 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3297 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3298 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3299 return -EINVAL; 3300 } 3301 sciport->port.flags |= UPF_HARD_FLOW; 3302 } 3303 3304 if (sci_uart_driver.cons->index == sciport->port.line) 3305 spin_lock_init(&sciport->port.lock); 3306 3307 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3308 if (ret) { 3309 sci_cleanup_single(sciport); 3310 return ret; 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int sci_probe(struct platform_device *dev) 3317 { 3318 struct plat_sci_port *p; 3319 struct sci_port *sp; 3320 unsigned int dev_id; 3321 int ret; 3322 3323 /* 3324 * If we've come here via earlyprintk initialization, head off to 3325 * the special early probe. We don't have sufficient device state 3326 * to make it beyond this yet. 3327 */ 3328 #ifdef CONFIG_SUPERH 3329 if (is_sh_early_platform_device(dev)) 3330 return sci_probe_earlyprintk(dev); 3331 #endif 3332 3333 if (dev->dev.of_node) { 3334 p = sci_parse_dt(dev, &dev_id); 3335 if (p == NULL) 3336 return -EINVAL; 3337 } else { 3338 p = dev->dev.platform_data; 3339 if (p == NULL) { 3340 dev_err(&dev->dev, "no platform data supplied\n"); 3341 return -EINVAL; 3342 } 3343 3344 dev_id = dev->id; 3345 } 3346 3347 sp = &sci_ports[dev_id]; 3348 platform_set_drvdata(dev, sp); 3349 3350 ret = sci_probe_single(dev, dev_id, p, sp); 3351 if (ret) 3352 return ret; 3353 3354 if (sp->port.fifosize > 1) { 3355 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3356 if (ret) 3357 return ret; 3358 } 3359 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3360 sp->port.type == PORT_HSCIF) { 3361 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3362 if (ret) { 3363 if (sp->port.fifosize > 1) { 3364 device_remove_file(&dev->dev, 3365 &dev_attr_rx_fifo_trigger); 3366 } 3367 return ret; 3368 } 3369 } 3370 3371 #ifdef CONFIG_SH_STANDARD_BIOS 3372 sh_bios_gdb_detach(); 3373 #endif 3374 3375 sci_ports_in_use |= BIT(dev_id); 3376 return 0; 3377 } 3378 3379 static __maybe_unused int sci_suspend(struct device *dev) 3380 { 3381 struct sci_port *sport = dev_get_drvdata(dev); 3382 3383 if (sport) 3384 uart_suspend_port(&sci_uart_driver, &sport->port); 3385 3386 return 0; 3387 } 3388 3389 static __maybe_unused int sci_resume(struct device *dev) 3390 { 3391 struct sci_port *sport = dev_get_drvdata(dev); 3392 3393 if (sport) 3394 uart_resume_port(&sci_uart_driver, &sport->port); 3395 3396 return 0; 3397 } 3398 3399 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3400 3401 static struct platform_driver sci_driver = { 3402 .probe = sci_probe, 3403 .remove = sci_remove, 3404 .driver = { 3405 .name = "sh-sci", 3406 .pm = &sci_dev_pm_ops, 3407 .of_match_table = of_match_ptr(of_sci_match), 3408 }, 3409 }; 3410 3411 static int __init sci_init(void) 3412 { 3413 pr_info("%s\n", banner); 3414 3415 return platform_driver_register(&sci_driver); 3416 } 3417 3418 static void __exit sci_exit(void) 3419 { 3420 platform_driver_unregister(&sci_driver); 3421 3422 if (sci_uart_driver.state) 3423 uart_unregister_driver(&sci_uart_driver); 3424 } 3425 3426 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3427 sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3428 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3429 #endif 3430 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3431 static struct plat_sci_port port_cfg __initdata; 3432 3433 static int __init early_console_setup(struct earlycon_device *device, 3434 int type) 3435 { 3436 if (!device->port.membase) 3437 return -ENODEV; 3438 3439 device->port.serial_in = sci_serial_in; 3440 device->port.serial_out = sci_serial_out; 3441 device->port.type = type; 3442 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3443 port_cfg.type = type; 3444 sci_ports[0].cfg = &port_cfg; 3445 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3446 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3447 sci_serial_out(&sci_ports[0].port, SCSCR, 3448 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3449 3450 device->con->write = serial_console_write; 3451 return 0; 3452 } 3453 static int __init sci_early_console_setup(struct earlycon_device *device, 3454 const char *opt) 3455 { 3456 return early_console_setup(device, PORT_SCI); 3457 } 3458 static int __init scif_early_console_setup(struct earlycon_device *device, 3459 const char *opt) 3460 { 3461 return early_console_setup(device, PORT_SCIF); 3462 } 3463 static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3464 const char *opt) 3465 { 3466 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3467 return early_console_setup(device, PORT_SCIF); 3468 } 3469 static int __init scifa_early_console_setup(struct earlycon_device *device, 3470 const char *opt) 3471 { 3472 return early_console_setup(device, PORT_SCIFA); 3473 } 3474 static int __init scifb_early_console_setup(struct earlycon_device *device, 3475 const char *opt) 3476 { 3477 return early_console_setup(device, PORT_SCIFB); 3478 } 3479 static int __init hscif_early_console_setup(struct earlycon_device *device, 3480 const char *opt) 3481 { 3482 return early_console_setup(device, PORT_HSCIF); 3483 } 3484 3485 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3486 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3487 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3488 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3489 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3490 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3491 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3492 3493 module_init(sci_init); 3494 module_exit(sci_exit); 3495 3496 MODULE_LICENSE("GPL"); 3497 MODULE_ALIAS("platform:sh-sci"); 3498 MODULE_AUTHOR("Paul Mundt"); 3499 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3500