1 /* 2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * File: desc.h 20 * 21 * Purpose:The header file of descriptor 22 * 23 * Revision History: 24 * 25 * Author: Tevin Chen 26 * 27 * Date: May 21, 1996 28 * 29 */ 30 31 #ifndef __DESC_H__ 32 #define __DESC_H__ 33 34 #include <linux/types.h> 35 #include <linux/mm.h> 36 #include "linux/ieee80211.h" 37 38 #define B_OWNED_BY_CHIP 1 39 #define B_OWNED_BY_HOST 0 40 41 /* Bits in the RSR register */ 42 #define RSR_ADDRBROAD 0x80 43 #define RSR_ADDRMULTI 0x40 44 #define RSR_ADDRUNI 0x00 45 #define RSR_IVLDTYP 0x20 46 #define RSR_IVLDLEN 0x10 /* invalid len (> 2312 byte) */ 47 #define RSR_BSSIDOK 0x08 48 #define RSR_CRCOK 0x04 49 #define RSR_BCNSSIDOK 0x02 50 #define RSR_ADDROK 0x01 51 52 /* Bits in the new RSR register */ 53 #define NEWRSR_DECRYPTOK 0x10 54 #define NEWRSR_CFPIND 0x08 55 #define NEWRSR_HWUTSF 0x04 56 #define NEWRSR_BCNHITAID 0x02 57 #define NEWRSR_BCNHITAID0 0x01 58 59 /* Bits in the TSR0 register */ 60 #define TSR0_PWRSTS1_2 0xC0 61 #define TSR0_PWRSTS7 0x20 62 #define TSR0_NCR 0x1F 63 64 /* Bits in the TSR1 register */ 65 #define TSR1_TERR 0x80 66 #define TSR1_PWRSTS4_6 0x70 67 #define TSR1_RETRYTMO 0x08 68 #define TSR1_TMO 0x04 69 #define TSR1_PWRSTS3 0x02 70 #define ACK_DATA 0x01 71 72 /* Bits in the TCR register */ 73 #define EDMSDU 0x04 /* end of sdu */ 74 #define TCR_EDP 0x02 /* end of packet */ 75 #define TCR_STP 0x01 /* start of packet */ 76 77 /* max transmit or receive buffer size */ 78 #define CB_MAX_BUF_SIZE 2900U 79 /* NOTE: must be multiple of 4 */ 80 #define CB_MAX_TX_BUF_SIZE CB_MAX_BUF_SIZE 81 #define CB_MAX_RX_BUF_SIZE_NORMAL CB_MAX_BUF_SIZE 82 83 #define CB_BEACON_BUF_SIZE 512U 84 85 #define CB_MAX_RX_DESC 128 86 #define CB_MIN_RX_DESC 16 87 #define CB_MAX_TX_DESC 64 88 #define CB_MIN_TX_DESC 16 89 90 #define CB_MAX_RECEIVED_PACKETS 16 91 /* 92 * limit our receive routine to indicating 93 * this many at a time for 2 reasons: 94 * 1. driver flow control to protocol layer 95 * 2. limit the time used in ISR routine 96 */ 97 98 #define CB_EXTRA_RD_NUM 32 99 #define CB_RD_NUM 32 100 #define CB_TD_NUM 32 101 102 /* 103 * max number of physical segments in a single NDIS packet. Above this 104 * threshold, the packet is copied into a single physically contiguous buffer 105 */ 106 #define CB_MAX_SEGMENT 4 107 108 #define CB_MIN_MAP_REG_NUM 4 109 #define CB_MAX_MAP_REG_NUM CB_MAX_TX_DESC 110 111 #define CB_PROTOCOL_RESERVED_SECTION 16 112 113 /* 114 * if retrys excess 15 times , tx will abort, and if tx fifo underflow, 115 * tx will fail, we should try to resend it 116 */ 117 #define CB_MAX_TX_ABORT_RETRY 3 118 119 /* WMAC definition FIFO Control */ 120 #define FIFOCTL_AUTO_FB_1 0x1000 121 #define FIFOCTL_AUTO_FB_0 0x0800 122 #define FIFOCTL_GRPACK 0x0400 123 #define FIFOCTL_11GA 0x0300 124 #define FIFOCTL_11GB 0x0200 125 #define FIFOCTL_11B 0x0100 126 #define FIFOCTL_11A 0x0000 127 #define FIFOCTL_RTS 0x0080 128 #define FIFOCTL_ISDMA0 0x0040 129 #define FIFOCTL_GENINT 0x0020 130 #define FIFOCTL_TMOEN 0x0010 131 #define FIFOCTL_LRETRY 0x0008 132 #define FIFOCTL_CRCDIS 0x0004 133 #define FIFOCTL_NEEDACK 0x0002 134 #define FIFOCTL_LHEAD 0x0001 135 136 /* WMAC definition Frag Control */ 137 #define FRAGCTL_AES 0x0300 138 #define FRAGCTL_TKIP 0x0200 139 #define FRAGCTL_LEGACY 0x0100 140 #define FRAGCTL_NONENCRYPT 0x0000 141 #define FRAGCTL_ENDFRAG 0x0003 142 #define FRAGCTL_MIDFRAG 0x0002 143 #define FRAGCTL_STAFRAG 0x0001 144 #define FRAGCTL_NONFRAG 0x0000 145 146 #define TYPE_TXDMA0 0 147 #define TYPE_AC0DMA 1 148 #define TYPE_ATIMDMA 2 149 #define TYPE_SYNCDMA 3 150 #define TYPE_MAXTD 2 151 152 #define TYPE_BEACONDMA 4 153 154 #define TYPE_RXDMA0 0 155 #define TYPE_RXDMA1 1 156 #define TYPE_MAXRD 2 157 158 /* TD_INFO flags control bit */ 159 #define TD_FLAGS_NETIF_SKB 0x01 /* check if need release skb */ 160 #define TD_FLAGS_PRIV_SKB 0x02 /* check if called from private skb (hostap) */ 161 #define TD_FLAGS_PS_RETRY 0x04 /* check if PS STA frame re-transmit */ 162 163 /* 164 * ref_sk_buff is used for mapping the skb structure between pre-built 165 * driver-obj & running kernel. Since different kernel version (2.4x) may 166 * change skb structure, i.e. pre-built driver-obj may link to older skb that 167 * leads error. 168 */ 169 170 typedef struct tagDEVICE_RD_INFO { 171 struct sk_buff *skb; 172 dma_addr_t skb_dma; 173 } DEVICE_RD_INFO, *PDEVICE_RD_INFO; 174 175 #ifdef __BIG_ENDIAN 176 177 typedef struct tagRDES0 { 178 volatile __le16 wResCount; 179 union { 180 volatile u16 f15Reserved; 181 struct { 182 volatile u8 f8Reserved1; 183 volatile u8 f1Owner:1; 184 volatile u8 f7Reserved:7; 185 } __attribute__ ((__packed__)); 186 } __attribute__ ((__packed__)); 187 } __attribute__ ((__packed__)) 188 SRDES0, *PSRDES0; 189 190 #else 191 192 typedef struct tagRDES0 { 193 __le16 wResCount; 194 unsigned short f15Reserved:15; 195 unsigned short f1Owner:1; 196 } __attribute__ ((__packed__)) 197 SRDES0; 198 199 #endif 200 201 typedef struct tagRDES1 { 202 __le16 wReqCount; 203 unsigned short wReserved; 204 } __attribute__ ((__packed__)) 205 SRDES1; 206 207 /* Rx descriptor*/ 208 typedef struct tagSRxDesc { 209 volatile SRDES0 m_rd0RD0; 210 volatile SRDES1 m_rd1RD1; 211 volatile __le32 buff_addr; 212 volatile __le32 next_desc; 213 struct tagSRxDesc *next __aligned(8); 214 volatile PDEVICE_RD_INFO pRDInfo __aligned(8); 215 } __attribute__ ((__packed__)) 216 SRxDesc, *PSRxDesc; 217 typedef const SRxDesc *PCSRxDesc; 218 219 struct vnt_tdes0 { 220 volatile u8 tsr0; 221 volatile u8 tsr1; 222 #ifdef __BIG_ENDIAN 223 union { 224 volatile u16 f15_txtime; 225 struct { 226 volatile u8 f8_reserved; 227 volatile u8 owner:1; 228 volatile u8 f7_reserved:7; 229 } __packed; 230 } __packed; 231 #else 232 volatile u16 f15_txtime:15; 233 volatile u16 owner:1; 234 #endif 235 } __packed; 236 237 struct vnt_tdes1 { 238 volatile __le16 req_count; 239 volatile u8 tcr; 240 volatile u8 reserved; 241 } __packed; 242 243 struct vnt_td_info { 244 void *mic_hdr; 245 struct sk_buff *skb; 246 unsigned char *buf; 247 dma_addr_t buf_dma; 248 u16 req_count; 249 u8 flags; 250 }; 251 252 /* transmit descriptor */ 253 struct vnt_tx_desc { 254 volatile struct vnt_tdes0 td0; 255 volatile struct vnt_tdes1 td1; 256 volatile __le32 buff_addr; 257 volatile __le32 next_desc; 258 struct vnt_tx_desc *next __aligned(8); 259 struct vnt_td_info *td_info __aligned(8); 260 } __packed; 261 262 /* Length, Service, and Signal fields of Phy for Tx */ 263 struct vnt_phy_field { 264 u8 signal; 265 u8 service; 266 __le16 len; 267 } __packed; 268 269 union vnt_phy_field_swap { 270 struct vnt_phy_field field_read; 271 u16 swap[2]; 272 u32 field_write; 273 }; 274 275 #endif /* __DESC_H__ */ 276