1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for Realtek PCI-Express card reader 4 * 5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 * 7 * Author: 8 * Wei WANG (wei_wang@realsil.com.cn) 9 * Micky Ching (micky_ching@realsil.com.cn) 10 */ 11 12 #include <linux/blkdev.h> 13 #include <linux/kthread.h> 14 #include <linux/sched.h> 15 #include <linux/workqueue.h> 16 #include <linux/vmalloc.h> 17 18 #include "rtsx.h" 19 #include "sd.h" 20 #include "xd.h" 21 #include "ms.h" 22 23 static void rtsx_calibration(struct rtsx_chip *chip) 24 { 25 rtsx_write_phy_register(chip, 0x1B, 0x135E); 26 wait_timeout(10); 27 rtsx_write_phy_register(chip, 0x00, 0x0280); 28 rtsx_write_phy_register(chip, 0x01, 0x7112); 29 rtsx_write_phy_register(chip, 0x01, 0x7110); 30 rtsx_write_phy_register(chip, 0x01, 0x7112); 31 rtsx_write_phy_register(chip, 0x01, 0x7113); 32 rtsx_write_phy_register(chip, 0x00, 0x0288); 33 } 34 35 void rtsx_enable_card_int(struct rtsx_chip *chip) 36 { 37 u32 reg = rtsx_readl(chip, RTSX_BIER); 38 int i; 39 40 for (i = 0; i <= chip->max_lun; i++) { 41 if (chip->lun2card[i] & XD_CARD) 42 reg |= XD_INT_EN; 43 if (chip->lun2card[i] & SD_CARD) 44 reg |= SD_INT_EN; 45 if (chip->lun2card[i] & MS_CARD) 46 reg |= MS_INT_EN; 47 } 48 if (chip->hw_bypass_sd) 49 reg &= ~((u32)SD_INT_EN); 50 51 rtsx_writel(chip, RTSX_BIER, reg); 52 } 53 54 void rtsx_enable_bus_int(struct rtsx_chip *chip) 55 { 56 u32 reg = 0; 57 #ifndef DISABLE_CARD_INT 58 int i; 59 #endif 60 61 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN; 62 63 #ifndef DISABLE_CARD_INT 64 for (i = 0; i <= chip->max_lun; i++) { 65 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n", 66 i, chip->lun2card[i]); 67 68 if (chip->lun2card[i] & XD_CARD) 69 reg |= XD_INT_EN; 70 if (chip->lun2card[i] & SD_CARD) 71 reg |= SD_INT_EN; 72 if (chip->lun2card[i] & MS_CARD) 73 reg |= MS_INT_EN; 74 } 75 if (chip->hw_bypass_sd) 76 reg &= ~((u32)SD_INT_EN); 77 #endif 78 79 if (chip->ic_version >= IC_VER_C) 80 reg |= DELINK_INT_EN; 81 #ifdef SUPPORT_OCP 82 reg |= OC_INT_EN; 83 #endif 84 if (!chip->adma_mode) 85 reg |= DATA_DONE_INT_EN; 86 87 /* Enable Bus Interrupt */ 88 rtsx_writel(chip, RTSX_BIER, reg); 89 90 dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg); 91 } 92 93 void rtsx_disable_bus_int(struct rtsx_chip *chip) 94 { 95 rtsx_writel(chip, RTSX_BIER, 0); 96 } 97 98 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) 99 { 100 int retval; 101 102 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { 103 if (chip->asic_code) { 104 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 105 0xFF, 106 MS_INS_PU | SD_WP_PU | 107 SD_CD_PU | SD_CMD_PU); 108 if (retval) 109 return retval; 110 } else { 111 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 112 0xFF, 113 FPGA_SD_PULL_CTL_EN); 114 if (retval) 115 return retval; 116 } 117 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF, 118 CARD_SHARE_48_SD); 119 if (retval) 120 return retval; 121 122 /* Enable SDIO internal clock */ 123 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01); 124 if (retval) 125 return retval; 126 127 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF, 128 SDIO_BUS_CTRL | SDIO_CD_CTRL); 129 if (retval) 130 return retval; 131 132 chip->sd_int = 1; 133 chip->sd_io = 1; 134 } else { 135 chip->need_reset |= SD_CARD; 136 } 137 138 return STATUS_SUCCESS; 139 } 140 141 #ifdef HW_AUTO_SWITCH_SD_BUS 142 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) 143 { 144 u8 tmp; 145 bool sw_bypass_sd = false; 146 int retval; 147 148 if (chip->driver_first_load) { 149 if (CHECK_PID(chip, 0x5288)) { 150 retval = rtsx_read_register(chip, 0xFE5A, &tmp); 151 if (retval) 152 return retval; 153 if (tmp & 0x08) 154 sw_bypass_sd = true; 155 } else if (CHECK_PID(chip, 0x5208)) { 156 retval = rtsx_read_register(chip, 0xFE70, &tmp); 157 if (retval) 158 return retval; 159 if (tmp & 0x80) 160 sw_bypass_sd = true; 161 } 162 } else { 163 if (chip->sdio_in_charge) 164 sw_bypass_sd = true; 165 } 166 dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n", 167 chip->sdio_in_charge); 168 dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n", 169 chip->driver_first_load); 170 dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n", 171 sw_bypass_sd); 172 173 if (sw_bypass_sd) { 174 u8 cd_toggle_mask = 0; 175 176 retval = rtsx_read_register(chip, TLPTISTAT, &tmp); 177 if (retval) 178 return retval; 179 cd_toggle_mask = 0x08; 180 181 if (tmp & cd_toggle_mask) { 182 /* Disable sdio_bus_auto_switch */ 183 if (CHECK_PID(chip, 0x5288)) { 184 retval = rtsx_write_register(chip, 0xFE5A, 185 0x08, 0x00); 186 if (retval) 187 return retval; 188 } else if (CHECK_PID(chip, 0x5208)) { 189 retval = rtsx_write_register(chip, 0xFE70, 190 0x80, 0x00); 191 if (retval) 192 return retval; 193 } 194 195 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF, 196 tmp); 197 if (retval) 198 return retval; 199 200 chip->need_reset |= SD_CARD; 201 } else { 202 dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n"); 203 204 if (chip->asic_code) { 205 retval = sd_pull_ctl_enable(chip); 206 if (retval != STATUS_SUCCESS) 207 return STATUS_FAIL; 208 } else { 209 retval = rtsx_write_register 210 (chip, FPGA_PULL_CTL, 211 FPGA_SD_PULL_CTL_BIT | 0x20, 212 0); 213 if (retval) 214 return retval; 215 } 216 retval = card_share_mode(chip, SD_CARD); 217 if (retval != STATUS_SUCCESS) 218 return STATUS_FAIL; 219 220 /* Enable sdio_bus_auto_switch */ 221 if (CHECK_PID(chip, 0x5288)) { 222 retval = rtsx_write_register(chip, 0xFE5A, 223 0x08, 0x08); 224 if (retval) 225 return retval; 226 } else if (CHECK_PID(chip, 0x5208)) { 227 retval = rtsx_write_register(chip, 0xFE70, 228 0x80, 0x80); 229 if (retval) 230 return retval; 231 } 232 233 chip->chip_insert_with_sdio = 1; 234 chip->sd_io = 1; 235 } 236 } else { 237 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 238 if (retval) 239 return retval; 240 241 chip->need_reset |= SD_CARD; 242 } 243 244 return STATUS_SUCCESS; 245 } 246 #endif 247 248 static int rtsx_reset_aspm(struct rtsx_chip *chip) 249 { 250 int ret; 251 252 if (chip->dynamic_aspm) { 253 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288)) 254 return STATUS_SUCCESS; 255 256 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, 257 chip->aspm_l0s_l1_en); 258 if (ret != STATUS_SUCCESS) 259 return STATUS_FAIL; 260 261 return STATUS_SUCCESS; 262 } 263 264 if (CHECK_PID(chip, 0x5208)) { 265 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); 266 if (ret) 267 return ret; 268 } 269 ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); 270 if (ret != STATUS_SUCCESS) 271 return STATUS_FAIL; 272 273 chip->aspm_level[0] = chip->aspm_l0s_l1_en; 274 if (CHK_SDIO_EXIST(chip)) { 275 chip->aspm_level[1] = chip->aspm_l0s_l1_en; 276 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 277 0xC0, 0xFF, chip->aspm_l0s_l1_en); 278 if (ret != STATUS_SUCCESS) 279 return STATUS_FAIL; 280 } 281 282 chip->aspm_enabled = 1; 283 284 return STATUS_SUCCESS; 285 } 286 287 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip) 288 { 289 int ret; 290 291 if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) { 292 rtsx_enable_bus_int(chip); 293 return STATUS_SUCCESS; 294 } 295 296 if (chip->phy_debug_mode) { 297 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); 298 if (ret) 299 return ret; 300 rtsx_disable_bus_int(chip); 301 } else { 302 rtsx_enable_bus_int(chip); 303 } 304 305 if (chip->ic_version >= IC_VER_D) { 306 u16 reg; 307 308 ret = rtsx_read_phy_register(chip, 0x00, ®); 309 if (ret != STATUS_SUCCESS) 310 return STATUS_FAIL; 311 312 reg &= 0xFE7F; 313 reg |= 0x80; 314 ret = rtsx_write_phy_register(chip, 0x00, reg); 315 if (ret != STATUS_SUCCESS) 316 return STATUS_FAIL; 317 318 ret = rtsx_read_phy_register(chip, 0x1C, ®); 319 if (ret != STATUS_SUCCESS) 320 return STATUS_FAIL; 321 322 reg &= 0xFFF7; 323 ret = rtsx_write_phy_register(chip, 0x1C, reg); 324 if (ret != STATUS_SUCCESS) 325 return STATUS_FAIL; 326 } 327 328 if (chip->driver_first_load && (chip->ic_version < IC_VER_C)) 329 rtsx_calibration(chip); 330 331 return STATUS_SUCCESS; 332 } 333 334 int rtsx_reset_chip(struct rtsx_chip *chip) 335 { 336 int retval; 337 338 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); 339 340 rtsx_disable_aspm(chip); 341 342 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); 343 if (retval) 344 return retval; 345 346 /* Disable card clock */ 347 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0); 348 if (retval) 349 return retval; 350 351 #ifdef SUPPORT_OCP 352 /* SSC power on, OCD power on */ 353 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 354 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0); 355 if (retval) 356 return retval; 357 } else { 358 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 359 MS_OC_POWER_DOWN); 360 if (retval) 361 return retval; 362 } 363 364 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK, 365 OCP_TIME_800); 366 if (retval) 367 return retval; 368 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK, 369 OCP_THD_244_946); 370 if (retval) 371 return retval; 372 retval = rtsx_write_register(chip, OCPCTL, 0xFF, 373 CARD_OC_INT_EN | CARD_DETECT_EN); 374 if (retval) 375 return retval; 376 #else 377 /* OC power down */ 378 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 379 OC_POWER_DOWN); 380 if (retval) 381 return retval; 382 #endif 383 384 if (!CHECK_PID(chip, 0x5288)) { 385 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03); 386 if (retval) 387 return retval; 388 } 389 390 /* Turn off LED */ 391 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03); 392 if (retval) 393 return retval; 394 395 /* Reset delink mode */ 396 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0); 397 if (retval) 398 return retval; 399 400 /* Card driving select */ 401 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF, 402 chip->card_drive_sel); 403 if (retval) 404 return retval; 405 406 #ifdef LED_AUTO_BLINK 407 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF, 408 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); 409 if (retval) 410 return retval; 411 #endif 412 413 if (chip->asic_code) { 414 /* Enable SSC Clock */ 415 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF, 416 SSC_8X_EN | SSC_SEL_4M); 417 if (retval) 418 return retval; 419 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12); 420 if (retval) 421 return retval; 422 } 423 424 /* 425 * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) 426 * 0xFE5B 427 * bit[1] u_cd_rst_core_en rst_value = 0 428 * bit[2] u_force_rst_core_en rst_value = 0 429 * bit[5] u_mac_phy_rst_n_dbg rst_value = 1 430 * bit[4] u_non_sticky_rst_n_dbg rst_value = 0 431 */ 432 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10); 433 if (retval) 434 return retval; 435 436 /* Enable ASPM */ 437 if (chip->aspm_l0s_l1_en) { 438 retval = rtsx_reset_aspm(chip); 439 if (retval != STATUS_SUCCESS) 440 return STATUS_FAIL; 441 } else { 442 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 443 retval = rtsx_write_phy_register(chip, 0x07, 0x0129); 444 if (retval != STATUS_SUCCESS) 445 return STATUS_FAIL; 446 } 447 retval = rtsx_write_config_byte(chip, LCTLR, 448 chip->aspm_l0s_l1_en); 449 if (retval != STATUS_SUCCESS) 450 return STATUS_FAIL; 451 } 452 453 retval = rtsx_write_config_byte(chip, 0x81, 1); 454 if (retval != STATUS_SUCCESS) 455 return STATUS_FAIL; 456 457 if (CHK_SDIO_EXIST(chip)) { 458 retval = rtsx_write_cfg_dw(chip, 459 CHECK_PID(chip, 0x5288) ? 2 : 1, 460 0xC0, 0xFF00, 0x0100); 461 462 if (retval != STATUS_SUCCESS) 463 return STATUS_FAIL; 464 } 465 466 if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) { 467 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103); 468 if (retval != STATUS_SUCCESS) 469 return STATUS_FAIL; 470 471 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03); 472 if (retval != STATUS_SUCCESS) 473 return STATUS_FAIL; 474 } 475 476 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, 477 LINK_RDY_INT); 478 if (retval) 479 return retval; 480 481 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); 482 if (retval) 483 return retval; 484 485 retval = rtsx_enable_pcie_intr(chip); 486 if (retval != STATUS_SUCCESS) 487 return STATUS_FAIL; 488 489 chip->need_reset = 0; 490 491 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 492 493 if (chip->hw_bypass_sd) 494 goto nextcard; 495 dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__, 496 chip->int_reg); 497 if (chip->int_reg & SD_EXIST) { 498 #ifdef HW_AUTO_SWITCH_SD_BUS 499 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C)) 500 retval = rtsx_pre_handle_sdio_old(chip); 501 else 502 retval = rtsx_pre_handle_sdio_new(chip); 503 504 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (%s)\n", 505 (unsigned int)(chip->need_reset), __func__); 506 #else /* HW_AUTO_SWITCH_SD_BUS */ 507 retval = rtsx_pre_handle_sdio_old(chip); 508 #endif /* HW_AUTO_SWITCH_SD_BUS */ 509 if (retval != STATUS_SUCCESS) 510 return STATUS_FAIL; 511 512 } else { 513 chip->sd_io = 0; 514 retval = rtsx_write_register(chip, SDIO_CTRL, 515 SDIO_BUS_CTRL | SDIO_CD_CTRL, 0); 516 if (retval) 517 return retval; 518 } 519 520 nextcard: 521 if (chip->int_reg & XD_EXIST) 522 chip->need_reset |= XD_CARD; 523 if (chip->int_reg & MS_EXIST) 524 chip->need_reset |= MS_CARD; 525 if (chip->int_reg & CARD_EXIST) { 526 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB, 527 SSC_RSTB); 528 if (retval) 529 return retval; 530 } 531 532 dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__, 533 (unsigned int)(chip->need_reset)); 534 535 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00); 536 if (retval) 537 return retval; 538 539 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { 540 /* Turn off main power when entering S3/S4 state */ 541 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03, 542 0x03); 543 if (retval) 544 return retval; 545 } 546 547 if (chip->remote_wakeup_en && !chip->auto_delink_en) { 548 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07); 549 if (retval) 550 return retval; 551 if (chip->aux_pwr_exist) { 552 retval = rtsx_write_register(chip, PME_FORCE_CTL, 553 0xFF, 0x33); 554 if (retval) 555 return retval; 556 } 557 } else { 558 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04); 559 if (retval) 560 return retval; 561 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30); 562 if (retval) 563 return retval; 564 } 565 566 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { 567 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14); 568 if (retval) 569 return retval; 570 } 571 572 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 573 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); 574 if (retval != STATUS_SUCCESS) 575 return STATUS_FAIL; 576 } 577 578 if (chip->ft2_fast_mode) { 579 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, 580 MS_PARTIAL_POWER_ON | 581 SD_PARTIAL_POWER_ON); 582 if (retval) 583 return retval; 584 udelay(chip->pmos_pwr_on_interval); 585 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, 586 MS_POWER_ON | SD_POWER_ON); 587 if (retval) 588 return retval; 589 590 wait_timeout(200); 591 } 592 593 /* Reset card */ 594 rtsx_reset_detected_cards(chip, 0); 595 596 chip->driver_first_load = 0; 597 598 return STATUS_SUCCESS; 599 } 600 601 static inline int check_sd_speed_prior(u32 sd_speed_prior) 602 { 603 bool fake_para = false; 604 int i; 605 606 for (i = 0; i < 4; i++) { 607 u8 tmp = (u8)(sd_speed_prior >> (i * 8)); 608 609 if ((tmp < 0x01) || (tmp > 0x04)) { 610 fake_para = true; 611 break; 612 } 613 } 614 615 return !fake_para; 616 } 617 618 static inline int check_sd_current_prior(u32 sd_current_prior) 619 { 620 bool fake_para = false; 621 int i; 622 623 for (i = 0; i < 4; i++) { 624 u8 tmp = (u8)(sd_current_prior >> (i * 8)); 625 626 if (tmp > 0x03) { 627 fake_para = true; 628 break; 629 } 630 } 631 632 return !fake_para; 633 } 634 635 static int rts5208_init(struct rtsx_chip *chip) 636 { 637 int retval; 638 u16 reg = 0; 639 u8 val = 0; 640 641 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); 642 if (retval) 643 return retval; 644 retval = rtsx_read_register(chip, CLK_SEL, &val); 645 if (retval) 646 return retval; 647 chip->asic_code = val == 0 ? 1 : 0; 648 649 if (chip->asic_code) { 650 retval = rtsx_read_phy_register(chip, 0x1C, ®); 651 if (retval != STATUS_SUCCESS) 652 return STATUS_FAIL; 653 654 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n", 655 reg); 656 chip->ic_version = (reg >> 4) & 0x07; 657 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0; 658 659 } else { 660 retval = rtsx_read_register(chip, 0xFE80, &val); 661 if (retval) 662 return retval; 663 chip->ic_version = val; 664 chip->phy_debug_mode = 0; 665 } 666 667 retval = rtsx_read_register(chip, PDINFO, &val); 668 if (retval) 669 return retval; 670 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); 671 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; 672 673 retval = rtsx_read_register(chip, 0xFE50, &val); 674 if (retval) 675 return retval; 676 chip->hw_bypass_sd = val & 0x01 ? 1 : 0; 677 678 rtsx_read_config_byte(chip, 0x0E, &val); 679 if (val & 0x80) 680 SET_SDIO_EXIST(chip); 681 else 682 CLR_SDIO_EXIST(chip); 683 684 if (chip->use_hw_setting) { 685 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); 686 if (retval) 687 return retval; 688 chip->auto_delink_en = val & 0x80 ? 1 : 0; 689 } 690 691 return STATUS_SUCCESS; 692 } 693 694 static int rts5288_init(struct rtsx_chip *chip) 695 { 696 int retval; 697 u8 val = 0, max_func; 698 u32 lval = 0; 699 700 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); 701 if (retval) 702 return retval; 703 retval = rtsx_read_register(chip, CLK_SEL, &val); 704 if (retval) 705 return retval; 706 chip->asic_code = val == 0 ? 1 : 0; 707 708 chip->ic_version = 0; 709 chip->phy_debug_mode = 0; 710 711 retval = rtsx_read_register(chip, PDINFO, &val); 712 if (retval) 713 return retval; 714 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); 715 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; 716 717 retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val); 718 if (retval) 719 return retval; 720 dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val); 721 chip->baro_pkg = val & 0x04 ? QFN : LQFP; 722 723 retval = rtsx_read_register(chip, 0xFE5A, &val); 724 if (retval) 725 return retval; 726 chip->hw_bypass_sd = val & 0x10 ? 1 : 0; 727 728 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); 729 if (retval != STATUS_SUCCESS) 730 return STATUS_FAIL; 731 732 max_func = (u8)((lval >> 29) & 0x07); 733 dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func); 734 if (max_func == 0x02) 735 SET_SDIO_EXIST(chip); 736 else 737 CLR_SDIO_EXIST(chip); 738 739 if (chip->use_hw_setting) { 740 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); 741 if (retval) 742 return retval; 743 chip->auto_delink_en = val & 0x80 ? 1 : 0; 744 745 if (CHECK_BARO_PKG(chip, LQFP)) 746 chip->lun_mode = SD_MS_1LUN; 747 else 748 chip->lun_mode = DEFAULT_SINGLE; 749 } 750 751 return STATUS_SUCCESS; 752 } 753 754 int rtsx_init_chip(struct rtsx_chip *chip) 755 { 756 struct sd_info *sd_card = &chip->sd_card; 757 struct xd_info *xd_card = &chip->xd_card; 758 struct ms_info *ms_card = &chip->ms_card; 759 int retval; 760 unsigned int i; 761 762 dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n", 763 chip->vendor_id, chip->product_id); 764 765 chip->ic_version = 0; 766 767 memset(xd_card, 0, sizeof(struct xd_info)); 768 memset(sd_card, 0, sizeof(struct sd_info)); 769 memset(ms_card, 0, sizeof(struct ms_info)); 770 771 chip->xd_reset_counter = 0; 772 chip->sd_reset_counter = 0; 773 chip->ms_reset_counter = 0; 774 775 chip->xd_show_cnt = MAX_SHOW_CNT; 776 chip->sd_show_cnt = MAX_SHOW_CNT; 777 chip->ms_show_cnt = MAX_SHOW_CNT; 778 779 chip->sd_io = 0; 780 chip->auto_delink_cnt = 0; 781 chip->auto_delink_allowed = 1; 782 rtsx_set_stat(chip, RTSX_STAT_INIT); 783 784 chip->aspm_enabled = 0; 785 chip->chip_insert_with_sdio = 0; 786 chip->sdio_aspm = 0; 787 chip->sdio_idle = 0; 788 chip->sdio_counter = 0; 789 chip->cur_card = 0; 790 chip->phy_debug_mode = 0; 791 chip->sdio_func_exist = 0; 792 memset(chip->sdio_raw_data, 0, 12); 793 794 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) { 795 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE); 796 chip->rw_fail_cnt[i] = 0; 797 } 798 799 if (!check_sd_speed_prior(chip->sd_speed_prior)) 800 chip->sd_speed_prior = 0x01040203; 801 802 dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n", 803 chip->sd_speed_prior); 804 805 if (!check_sd_current_prior(chip->sd_current_prior)) 806 chip->sd_current_prior = 0x00010203; 807 808 dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n", 809 chip->sd_current_prior); 810 811 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0)) 812 chip->sd_ddr_tx_phase = 0; 813 814 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) 815 chip->mmc_ddr_tx_phase = 0; 816 817 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0); 818 if (retval) 819 return retval; 820 wait_timeout(200); 821 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); 822 if (retval) 823 return retval; 824 dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n", 825 chip->use_hw_setting); 826 827 if (CHECK_PID(chip, 0x5208)) { 828 retval = rts5208_init(chip); 829 if (retval != STATUS_SUCCESS) 830 return STATUS_FAIL; 831 832 } else if (CHECK_PID(chip, 0x5288)) { 833 retval = rts5288_init(chip); 834 if (retval != STATUS_SUCCESS) 835 return STATUS_FAIL; 836 } 837 838 if (chip->ss_en == 2) 839 chip->ss_en = 0; 840 841 dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code); 842 dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version); 843 dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n", 844 chip->phy_debug_mode); 845 dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n", 846 chip->aux_pwr_exist); 847 dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n", 848 chip->sdio_func_exist); 849 dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n", 850 chip->hw_bypass_sd); 851 dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n", 852 chip->aspm_l0s_l1_en); 853 dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode); 854 dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n", 855 chip->auto_delink_en); 856 dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en); 857 dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg); 858 859 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 860 chip->card2lun[SD_CARD] = 0; 861 chip->card2lun[MS_CARD] = 1; 862 chip->card2lun[XD_CARD] = 0xFF; 863 chip->lun2card[0] = SD_CARD; 864 chip->lun2card[1] = MS_CARD; 865 chip->max_lun = 1; 866 SET_SDIO_IGNORED(chip); 867 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) { 868 chip->card2lun[SD_CARD] = 0; 869 chip->card2lun[MS_CARD] = 0; 870 chip->card2lun[XD_CARD] = 0xFF; 871 chip->lun2card[0] = SD_CARD | MS_CARD; 872 chip->max_lun = 0; 873 } else { 874 chip->card2lun[XD_CARD] = 0; 875 chip->card2lun[SD_CARD] = 0; 876 chip->card2lun[MS_CARD] = 0; 877 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD; 878 chip->max_lun = 0; 879 } 880 881 retval = rtsx_reset_chip(chip); 882 if (retval != STATUS_SUCCESS) 883 return STATUS_FAIL; 884 885 return STATUS_SUCCESS; 886 } 887 888 void rtsx_release_chip(struct rtsx_chip *chip) 889 { 890 xd_free_l2p_tbl(chip); 891 ms_free_l2p_tbl(chip); 892 chip->card_exist = 0; 893 chip->card_ready = 0; 894 } 895 896 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 897 static inline void rtsx_blink_led(struct rtsx_chip *chip) 898 { 899 if (chip->card_exist && chip->blink_led) { 900 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) { 901 chip->led_toggle_counter++; 902 } else { 903 chip->led_toggle_counter = 0; 904 toggle_gpio(chip, LED_GPIO); 905 } 906 } 907 } 908 #endif 909 910 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip) 911 { 912 bool reg_changed, maybe_support_aspm; 913 u32 tmp = 0; 914 u8 reg0 = 0, reg1 = 0; 915 916 maybe_support_aspm = false; 917 reg_changed = false; 918 rtsx_read_config_byte(chip, LCTLR, ®0); 919 if (chip->aspm_level[0] != reg0) { 920 reg_changed = true; 921 chip->aspm_level[0] = reg0; 922 } 923 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 924 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp); 925 reg1 = (u8)tmp; 926 if (chip->aspm_level[1] != reg1) { 927 reg_changed = true; 928 chip->aspm_level[1] = reg1; 929 } 930 931 if ((reg0 & 0x03) && (reg1 & 0x03)) 932 maybe_support_aspm = true; 933 934 } else { 935 if (reg0 & 0x03) 936 maybe_support_aspm = true; 937 } 938 939 if (reg_changed) { 940 if (maybe_support_aspm) 941 chip->aspm_l0s_l1_en = 0x03; 942 943 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n", 944 chip->aspm_level[0], chip->aspm_level[1]); 945 946 if (chip->aspm_l0s_l1_en) { 947 chip->aspm_enabled = 1; 948 } else { 949 chip->aspm_enabled = 0; 950 chip->sdio_aspm = 0; 951 } 952 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 953 0x30 | chip->aspm_level[0] | 954 (chip->aspm_level[1] << 2)); 955 } 956 } 957 958 static void rtsx_manage_ocp(struct rtsx_chip *chip) 959 { 960 #ifdef SUPPORT_OCP 961 if (!chip->ocp_int) 962 return; 963 964 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat); 965 966 if (chip->card_exist & SD_CARD) 967 sd_power_off_card3v3(chip); 968 else if (chip->card_exist & MS_CARD) 969 ms_power_off_card3v3(chip); 970 else if (chip->card_exist & XD_CARD) 971 xd_power_off_card3v3(chip); 972 973 chip->ocp_int = 0; 974 #endif 975 } 976 977 static void rtsx_manage_sd_lock(struct rtsx_chip *chip) 978 { 979 #ifdef SUPPORT_SD_LOCK 980 struct sd_info *sd_card = &chip->sd_card; 981 u8 val; 982 983 if (!sd_card->sd_erase_status) 984 return; 985 986 if (chip->card_exist & SD_CARD) { 987 rtsx_read_register(chip, 0xFD30, &val); 988 if (val & 0x02) { 989 sd_card->sd_erase_status = SD_NOT_ERASE; 990 sd_card->sd_lock_notify = 1; 991 chip->need_reinit |= SD_CARD; 992 } 993 } else { 994 sd_card->sd_erase_status = SD_NOT_ERASE; 995 } 996 #endif 997 } 998 999 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip) 1000 { 1001 u32 val; 1002 1003 if (!chip->ss_en || CHECK_PID(chip, 0x5288)) 1004 return false; 1005 1006 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 1007 rtsx_read_cfg_dw(chip, 1, 0x04, &val); 1008 if (val & 0x07) 1009 return false; 1010 } 1011 1012 return true; 1013 } 1014 1015 static void rtsx_manage_ss(struct rtsx_chip *chip) 1016 { 1017 if (!rtsx_is_ss_allowed(chip) || chip->sd_io) 1018 return; 1019 1020 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { 1021 chip->ss_counter = 0; 1022 return; 1023 } 1024 1025 if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL)) 1026 chip->ss_counter++; 1027 else 1028 rtsx_exclusive_enter_ss(chip); 1029 } 1030 1031 static void rtsx_manage_aspm(struct rtsx_chip *chip) 1032 { 1033 u8 data; 1034 1035 if (!CHECK_PID(chip, 0x5208)) 1036 return; 1037 1038 rtsx_monitor_aspm_config(chip); 1039 1040 #ifdef SUPPORT_SDIO_ASPM 1041 if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) || 1042 !chip->aspm_l0s_l1_en || !chip->dynamic_aspm) 1043 return; 1044 1045 if (chip->sd_io) { 1046 dynamic_configure_sdio_aspm(chip); 1047 return; 1048 } 1049 1050 if (chip->sdio_aspm) 1051 return; 1052 1053 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n"); 1054 data = 0x30 | (chip->aspm_level[1] << 2); 1055 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data); 1056 chip->sdio_aspm = 1; 1057 #endif 1058 } 1059 1060 static void rtsx_manage_idle(struct rtsx_chip *chip) 1061 { 1062 if (chip->idle_counter < IDLE_MAX_COUNT) { 1063 chip->idle_counter++; 1064 return; 1065 } 1066 1067 if (rtsx_get_stat(chip) == RTSX_STAT_IDLE) 1068 return; 1069 1070 dev_dbg(rtsx_dev(chip), "Idle state!\n"); 1071 rtsx_set_stat(chip, RTSX_STAT_IDLE); 1072 1073 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1074 chip->led_toggle_counter = 0; 1075 #endif 1076 rtsx_force_power_on(chip, SSC_PDCTL); 1077 1078 turn_off_led(chip, LED_GPIO); 1079 1080 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io) 1081 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1082 } 1083 1084 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip) 1085 { 1086 #ifdef SUPPORT_OCP 1087 u8 sd_oc, ms_oc; 1088 1089 sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER); 1090 ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER); 1091 1092 if (sd_oc || ms_oc) 1093 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 1094 chip->ocp_stat); 1095 1096 if (sd_oc && (chip->card_exist & SD_CARD)) { 1097 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1098 card_power_off(chip, SD_CARD); 1099 chip->card_fail |= SD_CARD; 1100 } 1101 1102 if (ms_oc && (chip->card_exist & MS_CARD)) { 1103 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1104 card_power_off(chip, MS_CARD); 1105 chip->card_fail |= MS_CARD; 1106 } 1107 #endif 1108 } 1109 1110 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip) 1111 { 1112 #ifdef SUPPORT_OCP 1113 if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER))) 1114 return; 1115 1116 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 1117 chip->ocp_stat); 1118 1119 if (chip->card_exist & SD_CARD) { 1120 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1121 chip->card_fail |= SD_CARD; 1122 } else if (chip->card_exist & MS_CARD) { 1123 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1124 chip->card_fail |= MS_CARD; 1125 } else if (chip->card_exist & XD_CARD) { 1126 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 1127 chip->card_fail |= XD_CARD; 1128 } 1129 card_power_off(chip, SD_CARD); 1130 #endif 1131 } 1132 1133 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1, 1134 int stage3_cnt) 1135 { 1136 u8 val; 1137 1138 rtsx_set_stat(chip, RTSX_STAT_DELINK); 1139 1140 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1141 rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1142 1143 if (chip->card_exist) 1144 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n"); 1145 else 1146 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n"); 1147 1148 if (enter_L1) 1149 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); 1150 1151 if (chip->card_exist) 1152 val = 0x02; 1153 else 1154 val = 0x0A; 1155 1156 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val); 1157 1158 if (enter_L1) 1159 rtsx_enter_L1(chip); 1160 1161 if (chip->card_exist) 1162 chip->auto_delink_cnt = stage3_cnt + 1; 1163 } 1164 1165 static void rtsx_delink_stage(struct rtsx_chip *chip) 1166 { 1167 int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt; 1168 int enter_L1; 1169 1170 if (!chip->auto_delink_en || !chip->auto_delink_allowed || 1171 chip->card_ready || chip->card_ejected || chip->sd_io) { 1172 chip->auto_delink_cnt = 0; 1173 return; 1174 } 1175 1176 enter_L1 = chip->auto_delink_in_L1 && 1177 (chip->aspm_l0s_l1_en || chip->ss_en); 1178 1179 delink_stage1_cnt = chip->delink_stage1_step; 1180 delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step; 1181 delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step; 1182 1183 if (chip->auto_delink_cnt > delink_stage3_cnt) 1184 return; 1185 1186 if (chip->auto_delink_cnt == delink_stage1_cnt) 1187 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt); 1188 1189 if (chip->auto_delink_cnt == delink_stage2_cnt) { 1190 dev_dbg(rtsx_dev(chip), "Try to do force delink\n"); 1191 1192 if (enter_L1) 1193 rtsx_exit_L1(chip); 1194 1195 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1196 rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1197 1198 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A); 1199 } 1200 1201 chip->auto_delink_cnt++; 1202 } 1203 1204 void rtsx_polling_func(struct rtsx_chip *chip) 1205 { 1206 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND)) 1207 return; 1208 1209 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK)) 1210 goto delink_stage; 1211 1212 if (chip->polling_config) { 1213 u8 val; 1214 1215 rtsx_read_config_byte(chip, 0, &val); 1216 } 1217 1218 if (rtsx_chk_stat(chip, RTSX_STAT_SS)) 1219 return; 1220 1221 rtsx_manage_ocp(chip); 1222 1223 rtsx_manage_sd_lock(chip); 1224 1225 rtsx_init_cards(chip); 1226 1227 rtsx_manage_ss(chip); 1228 1229 rtsx_manage_aspm(chip); 1230 1231 rtsx_manage_idle(chip); 1232 1233 switch (rtsx_get_stat(chip)) { 1234 case RTSX_STAT_RUN: 1235 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1236 rtsx_blink_led(chip); 1237 #endif 1238 do_remaining_work(chip); 1239 break; 1240 1241 case RTSX_STAT_IDLE: 1242 if (chip->sd_io && !chip->sd_int) 1243 try_to_switch_sdio_ctrl(chip); 1244 1245 rtsx_enable_aspm(chip); 1246 break; 1247 1248 default: 1249 break; 1250 } 1251 1252 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 1253 rtsx_manage_2lun_mode(chip); 1254 else 1255 rtsx_manage_1lun_mode(chip); 1256 1257 delink_stage: 1258 rtsx_delink_stage(chip); 1259 } 1260 1261 /** 1262 * rtsx_stop_cmd - stop command transfer and DMA transfer 1263 * @chip: Realtek's card reader chip 1264 * @card: flash card type 1265 * 1266 * Stop command transfer and DMA transfer. 1267 * This function is called in error handler. 1268 */ 1269 void rtsx_stop_cmd(struct rtsx_chip *chip, int card) 1270 { 1271 int i; 1272 1273 for (i = 0; i <= 8; i++) { 1274 int addr = RTSX_HCBAR + i * 4; 1275 u32 reg; 1276 1277 reg = rtsx_readl(chip, addr); 1278 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg); 1279 } 1280 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD); 1281 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA); 1282 1283 for (i = 0; i < 16; i++) { 1284 u16 addr = 0xFE20 + (u16)i; 1285 u8 val; 1286 1287 rtsx_read_register(chip, addr, &val); 1288 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val); 1289 } 1290 1291 rtsx_write_register(chip, DMACTL, 0x80, 0x80); 1292 rtsx_write_register(chip, RBCTL, 0x80, 0x80); 1293 } 1294 1295 #define MAX_RW_REG_CNT 1024 1296 1297 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) 1298 { 1299 int i; 1300 u32 val = 3 << 30; 1301 1302 val |= (u32)(addr & 0x3FFF) << 16; 1303 val |= (u32)mask << 8; 1304 val |= (u32)data; 1305 1306 rtsx_writel(chip, RTSX_HAIMR, val); 1307 1308 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1309 val = rtsx_readl(chip, RTSX_HAIMR); 1310 if ((val & BIT(31)) == 0) { 1311 if (data != (u8)val) 1312 return STATUS_FAIL; 1313 1314 return STATUS_SUCCESS; 1315 } 1316 } 1317 1318 return STATUS_TIMEDOUT; 1319 } 1320 1321 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) 1322 { 1323 u32 val = 2 << 30; 1324 int i; 1325 1326 if (data) 1327 *data = 0; 1328 1329 val |= (u32)(addr & 0x3FFF) << 16; 1330 1331 rtsx_writel(chip, RTSX_HAIMR, val); 1332 1333 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1334 val = rtsx_readl(chip, RTSX_HAIMR); 1335 if ((val & BIT(31)) == 0) 1336 break; 1337 } 1338 1339 if (i >= MAX_RW_REG_CNT) 1340 return STATUS_TIMEDOUT; 1341 1342 if (data) 1343 *data = (u8)(val & 0xFF); 1344 1345 return STATUS_SUCCESS; 1346 } 1347 1348 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, 1349 u32 val) 1350 { 1351 int retval; 1352 u8 mode = 0, tmp; 1353 int i; 1354 1355 for (i = 0; i < 4; i++) { 1356 if (mask & 0xFF) { 1357 retval = rtsx_write_register(chip, CFGDATA0 + i, 1358 0xFF, 1359 (u8)(val & mask & 0xFF)); 1360 if (retval) 1361 return retval; 1362 mode |= (1 << i); 1363 } 1364 mask >>= 8; 1365 val >>= 8; 1366 } 1367 1368 if (mode) { 1369 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); 1370 if (retval) 1371 return retval; 1372 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, 1373 (u8)(addr >> 8)); 1374 if (retval) 1375 return retval; 1376 1377 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, 1378 0x80 | mode | 1379 ((func_no & 0x03) << 4)); 1380 if (retval) 1381 return retval; 1382 1383 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1384 retval = rtsx_read_register(chip, CFGRWCTL, &tmp); 1385 if (retval) 1386 return retval; 1387 if ((tmp & 0x80) == 0) 1388 break; 1389 } 1390 } 1391 1392 return STATUS_SUCCESS; 1393 } 1394 1395 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) 1396 { 1397 int retval; 1398 int i; 1399 u8 tmp; 1400 u32 data = 0; 1401 1402 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); 1403 if (retval) 1404 return retval; 1405 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); 1406 if (retval) 1407 return retval; 1408 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, 1409 0x80 | ((func_no & 0x03) << 4)); 1410 if (retval) 1411 return retval; 1412 1413 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1414 retval = rtsx_read_register(chip, CFGRWCTL, &tmp); 1415 if (retval) 1416 return retval; 1417 if ((tmp & 0x80) == 0) 1418 break; 1419 } 1420 1421 for (i = 0; i < 4; i++) { 1422 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp); 1423 if (retval) 1424 return retval; 1425 data |= (u32)tmp << (i * 8); 1426 } 1427 1428 if (val) 1429 *val = data; 1430 1431 return STATUS_SUCCESS; 1432 } 1433 1434 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, 1435 int len) 1436 { 1437 u32 *data, *mask; 1438 u16 offset = addr % 4; 1439 u16 aligned_addr = addr - offset; 1440 int dw_len, i, j; 1441 int retval; 1442 1443 if (!buf) 1444 return STATUS_NOMEM; 1445 1446 if ((len + offset) % 4) 1447 dw_len = (len + offset) / 4 + 1; 1448 else 1449 dw_len = (len + offset) / 4; 1450 1451 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len); 1452 1453 data = vzalloc(array_size(dw_len, 4)); 1454 if (!data) 1455 return STATUS_NOMEM; 1456 1457 mask = vzalloc(array_size(dw_len, 4)); 1458 if (!mask) { 1459 vfree(data); 1460 return STATUS_NOMEM; 1461 } 1462 1463 j = 0; 1464 for (i = 0; i < len; i++) { 1465 mask[j] |= 0xFF << (offset * 8); 1466 data[j] |= buf[i] << (offset * 8); 1467 if (++offset == 4) { 1468 j++; 1469 offset = 0; 1470 } 1471 } 1472 1473 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask, 1474 dw_len * 4); 1475 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data, 1476 dw_len * 4); 1477 1478 for (i = 0; i < dw_len; i++) { 1479 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, 1480 mask[i], data[i]); 1481 if (retval != STATUS_SUCCESS) { 1482 vfree(data); 1483 vfree(mask); 1484 return STATUS_FAIL; 1485 } 1486 } 1487 1488 vfree(data); 1489 vfree(mask); 1490 1491 return STATUS_SUCCESS; 1492 } 1493 1494 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, 1495 int len) 1496 { 1497 u32 *data; 1498 u16 offset = addr % 4; 1499 u16 aligned_addr = addr - offset; 1500 int dw_len, i, j; 1501 int retval; 1502 1503 if ((len + offset) % 4) 1504 dw_len = (len + offset) / 4 + 1; 1505 else 1506 dw_len = (len + offset) / 4; 1507 1508 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len); 1509 1510 data = vmalloc(array_size(dw_len, 4)); 1511 if (!data) 1512 return STATUS_NOMEM; 1513 1514 for (i = 0; i < dw_len; i++) { 1515 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, 1516 data + i); 1517 if (retval != STATUS_SUCCESS) { 1518 vfree(data); 1519 return STATUS_FAIL; 1520 } 1521 } 1522 1523 if (buf) { 1524 j = 0; 1525 1526 for (i = 0; i < len; i++) { 1527 buf[i] = (u8)(data[j] >> (offset * 8)); 1528 if (++offset == 4) { 1529 j++; 1530 offset = 0; 1531 } 1532 } 1533 } 1534 1535 vfree(data); 1536 1537 return STATUS_SUCCESS; 1538 } 1539 1540 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) 1541 { 1542 int retval; 1543 bool finished = false; 1544 int i; 1545 u8 tmp; 1546 1547 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); 1548 if (retval) 1549 return retval; 1550 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); 1551 if (retval) 1552 return retval; 1553 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); 1554 if (retval) 1555 return retval; 1556 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81); 1557 if (retval) 1558 return retval; 1559 1560 for (i = 0; i < 100000; i++) { 1561 retval = rtsx_read_register(chip, PHYRWCTL, &tmp); 1562 if (retval) 1563 return retval; 1564 if (!(tmp & 0x80)) { 1565 finished = true; 1566 break; 1567 } 1568 } 1569 1570 if (!finished) 1571 return STATUS_FAIL; 1572 1573 return STATUS_SUCCESS; 1574 } 1575 1576 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) 1577 { 1578 int retval; 1579 bool finished = false; 1580 int i; 1581 u16 data = 0; 1582 u8 tmp; 1583 1584 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); 1585 if (retval) 1586 return retval; 1587 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80); 1588 if (retval) 1589 return retval; 1590 1591 for (i = 0; i < 100000; i++) { 1592 retval = rtsx_read_register(chip, PHYRWCTL, &tmp); 1593 if (retval) 1594 return retval; 1595 if (!(tmp & 0x80)) { 1596 finished = true; 1597 break; 1598 } 1599 } 1600 1601 if (!finished) 1602 return STATUS_FAIL; 1603 1604 retval = rtsx_read_register(chip, PHYDATA0, &tmp); 1605 if (retval) 1606 return retval; 1607 data = tmp; 1608 retval = rtsx_read_register(chip, PHYDATA1, &tmp); 1609 if (retval) 1610 return retval; 1611 data |= (u16)tmp << 8; 1612 1613 if (val) 1614 *val = data; 1615 1616 return STATUS_SUCCESS; 1617 } 1618 1619 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) 1620 { 1621 int retval; 1622 int i; 1623 u8 data = 0; 1624 1625 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr); 1626 if (retval) 1627 return retval; 1628 1629 for (i = 0; i < 100; i++) { 1630 retval = rtsx_read_register(chip, EFUSE_CTRL, &data); 1631 if (retval) 1632 return retval; 1633 if (!(data & 0x80)) 1634 break; 1635 udelay(1); 1636 } 1637 1638 if (data & 0x80) 1639 return STATUS_TIMEDOUT; 1640 1641 retval = rtsx_read_register(chip, EFUSE_DATA, &data); 1642 if (retval) 1643 return retval; 1644 if (val) 1645 *val = data; 1646 1647 return STATUS_SUCCESS; 1648 } 1649 1650 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) 1651 { 1652 int retval; 1653 int i, j; 1654 u8 data = 0, tmp = 0xFF; 1655 1656 for (i = 0; i < 8; i++) { 1657 if (val & (u8)(1 << i)) 1658 continue; 1659 1660 tmp &= (~(u8)(1 << i)); 1661 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr); 1662 1663 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp); 1664 if (retval) 1665 return retval; 1666 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 1667 0xA0 | addr); 1668 if (retval) 1669 return retval; 1670 1671 for (j = 0; j < 100; j++) { 1672 retval = rtsx_read_register(chip, EFUSE_CTRL, &data); 1673 if (retval) 1674 return retval; 1675 if (!(data & 0x80)) 1676 break; 1677 wait_timeout(3); 1678 } 1679 1680 if (data & 0x80) 1681 return STATUS_TIMEDOUT; 1682 1683 wait_timeout(5); 1684 } 1685 1686 return STATUS_SUCCESS; 1687 } 1688 1689 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1690 { 1691 int retval; 1692 u16 value; 1693 1694 retval = rtsx_read_phy_register(chip, reg, &value); 1695 if (retval != STATUS_SUCCESS) 1696 return STATUS_FAIL; 1697 1698 if (value & (1 << bit)) { 1699 value &= ~(1 << bit); 1700 retval = rtsx_write_phy_register(chip, reg, value); 1701 if (retval != STATUS_SUCCESS) 1702 return STATUS_FAIL; 1703 } 1704 1705 return STATUS_SUCCESS; 1706 } 1707 1708 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1709 { 1710 int retval; 1711 u16 value; 1712 1713 retval = rtsx_read_phy_register(chip, reg, &value); 1714 if (retval != STATUS_SUCCESS) 1715 return STATUS_FAIL; 1716 1717 if ((value & (1 << bit)) == 0) { 1718 value |= (1 << bit); 1719 retval = rtsx_write_phy_register(chip, reg, value); 1720 if (retval != STATUS_SUCCESS) 1721 return STATUS_FAIL; 1722 } 1723 1724 return STATUS_SUCCESS; 1725 } 1726 1727 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate) 1728 { 1729 u32 ultmp; 1730 1731 dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n", 1732 chip->product_id, dstate); 1733 1734 if (CHK_SDIO_EXIST(chip)) { 1735 u8 func_no; 1736 1737 if (CHECK_PID(chip, 0x5288)) 1738 func_no = 2; 1739 else 1740 func_no = 1; 1741 1742 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp); 1743 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n", 1744 (int)func_no, ultmp); 1745 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate); 1746 } 1747 1748 rtsx_write_config_byte(chip, 0x44, dstate); 1749 rtsx_write_config_byte(chip, 0x45, 0); 1750 } 1751 1752 void rtsx_enter_L1(struct rtsx_chip *chip) 1753 { 1754 rtsx_handle_pm_dstate(chip, 2); 1755 } 1756 1757 void rtsx_exit_L1(struct rtsx_chip *chip) 1758 { 1759 rtsx_write_config_byte(chip, 0x44, 0); 1760 rtsx_write_config_byte(chip, 0x45, 0); 1761 } 1762 1763 void rtsx_enter_ss(struct rtsx_chip *chip) 1764 { 1765 dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n"); 1766 1767 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); 1768 1769 if (chip->power_down_in_ss) { 1770 rtsx_power_off_card(chip); 1771 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1772 } 1773 1774 if (CHK_SDIO_EXIST(chip)) 1775 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 1776 0xC0, 0xFF00, 0x0100); 1777 1778 if (chip->auto_delink_en) { 1779 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01); 1780 } else { 1781 if (!chip->phy_debug_mode) { 1782 u32 tmp; 1783 1784 tmp = rtsx_readl(chip, RTSX_BIER); 1785 tmp |= CARD_INT; 1786 rtsx_writel(chip, RTSX_BIER, tmp); 1787 } 1788 1789 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0); 1790 } 1791 1792 rtsx_enter_L1(chip); 1793 1794 RTSX_CLR_DELINK(chip); 1795 rtsx_set_stat(chip, RTSX_STAT_SS); 1796 } 1797 1798 void rtsx_exit_ss(struct rtsx_chip *chip) 1799 { 1800 dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n"); 1801 1802 rtsx_exit_L1(chip); 1803 1804 if (chip->power_down_in_ss) { 1805 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 1806 udelay(1000); 1807 } 1808 1809 if (RTSX_TST_DELINK(chip)) { 1810 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1811 rtsx_reinit_cards(chip, 1); 1812 RTSX_CLR_DELINK(chip); 1813 } else if (chip->power_down_in_ss) { 1814 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1815 rtsx_reinit_cards(chip, 0); 1816 } 1817 } 1818 1819 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip) 1820 { 1821 u32 status, int_enable; 1822 bool exit_ss = false; 1823 #ifdef SUPPORT_OCP 1824 u32 ocp_int = 0; 1825 1826 ocp_int = OC_INT; 1827 #endif 1828 1829 if (chip->ss_en) { 1830 chip->ss_counter = 0; 1831 if (rtsx_get_stat(chip) == RTSX_STAT_SS) { 1832 exit_ss = true; 1833 rtsx_exit_L1(chip); 1834 rtsx_set_stat(chip, RTSX_STAT_RUN); 1835 } 1836 } 1837 1838 int_enable = rtsx_readl(chip, RTSX_BIER); 1839 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 1840 1841 if (((chip->int_reg & int_enable) == 0) || 1842 (chip->int_reg == 0xFFFFFFFF)) 1843 return STATUS_FAIL; 1844 1845 status = chip->int_reg &= (int_enable | 0x7FFFFF); 1846 1847 if (status & CARD_INT) { 1848 chip->auto_delink_cnt = 0; 1849 1850 if (status & SD_INT) { 1851 if (status & SD_EXIST) { 1852 set_bit(SD_NR, &chip->need_reset); 1853 } else { 1854 set_bit(SD_NR, &chip->need_release); 1855 chip->sd_reset_counter = 0; 1856 chip->sd_show_cnt = 0; 1857 clear_bit(SD_NR, &chip->need_reset); 1858 } 1859 } else { 1860 /* 1861 * If multi-luns, it's possible that 1862 * when plugging/unplugging one card 1863 * there is another card which still 1864 * exists in the slot. In this case, 1865 * all existed cards should be reset. 1866 */ 1867 if (exit_ss && (status & SD_EXIST)) 1868 set_bit(SD_NR, &chip->need_reinit); 1869 } 1870 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) { 1871 if (status & XD_INT) { 1872 if (status & XD_EXIST) { 1873 set_bit(XD_NR, &chip->need_reset); 1874 } else { 1875 set_bit(XD_NR, &chip->need_release); 1876 chip->xd_reset_counter = 0; 1877 chip->xd_show_cnt = 0; 1878 clear_bit(XD_NR, &chip->need_reset); 1879 } 1880 } else { 1881 if (exit_ss && (status & XD_EXIST)) 1882 set_bit(XD_NR, &chip->need_reinit); 1883 } 1884 } 1885 if (status & MS_INT) { 1886 if (status & MS_EXIST) { 1887 set_bit(MS_NR, &chip->need_reset); 1888 } else { 1889 set_bit(MS_NR, &chip->need_release); 1890 chip->ms_reset_counter = 0; 1891 chip->ms_show_cnt = 0; 1892 clear_bit(MS_NR, &chip->need_reset); 1893 } 1894 } else { 1895 if (exit_ss && (status & MS_EXIST)) 1896 set_bit(MS_NR, &chip->need_reinit); 1897 } 1898 } 1899 1900 #ifdef SUPPORT_OCP 1901 chip->ocp_int = ocp_int & status; 1902 #endif 1903 1904 if (chip->sd_io && (chip->int_reg & DATA_DONE_INT)) 1905 chip->int_reg &= ~(u32)DATA_DONE_INT; 1906 1907 return STATUS_SUCCESS; 1908 } 1909 1910 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat) 1911 { 1912 int retval; 1913 1914 dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat); 1915 1916 rtsx_set_stat(chip, RTSX_STAT_SUSPEND); 1917 1918 retval = rtsx_force_power_on(chip, SSC_PDCTL); 1919 if (retval != STATUS_SUCCESS) 1920 return; 1921 1922 rtsx_release_cards(chip); 1923 rtsx_disable_bus_int(chip); 1924 turn_off_led(chip, LED_GPIO); 1925 1926 #ifdef HW_AUTO_SWITCH_SD_BUS 1927 if (chip->sd_io) { 1928 chip->sdio_in_charge = 1; 1929 if (CHECK_PID(chip, 0x5208)) { 1930 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 1931 /* Enable sdio_bus_auto_switch */ 1932 rtsx_write_register(chip, 0xFE70, 0x80, 0x80); 1933 } else if (CHECK_PID(chip, 0x5288)) { 1934 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 1935 /* Enable sdio_bus_auto_switch */ 1936 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08); 1937 } 1938 } 1939 #endif 1940 1941 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { 1942 /* u_force_clkreq_0 */ 1943 rtsx_write_register(chip, PETXCFG, 0x08, 0x08); 1944 } 1945 1946 if (pm_stat == PM_S1) { 1947 dev_dbg(rtsx_dev(chip), "Host enter S1\n"); 1948 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1949 HOST_ENTER_S1); 1950 } else if (pm_stat == PM_S3) { 1951 if (chip->s3_pwr_off_delay > 0) 1952 wait_timeout(chip->s3_pwr_off_delay); 1953 1954 dev_dbg(rtsx_dev(chip), "Host enter S3\n"); 1955 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1956 HOST_ENTER_S3); 1957 } 1958 1959 if (chip->do_delink_before_power_down && chip->auto_delink_en) 1960 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2); 1961 1962 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1963 1964 chip->cur_clk = 0; 1965 chip->cur_card = 0; 1966 chip->card_exist = 0; 1967 } 1968 1969 void rtsx_enable_aspm(struct rtsx_chip *chip) 1970 { 1971 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) { 1972 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n"); 1973 chip->aspm_enabled = 1; 1974 1975 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1976 rtsx_write_phy_register(chip, 0x07, 0); 1977 if (CHECK_PID(chip, 0x5208)) { 1978 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 1979 0x30 | chip->aspm_level[0]); 1980 } else { 1981 rtsx_write_config_byte(chip, LCTLR, 1982 chip->aspm_l0s_l1_en); 1983 } 1984 1985 if (CHK_SDIO_EXIST(chip)) { 1986 u16 val = chip->aspm_l0s_l1_en | 0x0100; 1987 1988 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 1989 0xC0, 0xFFF, val); 1990 } 1991 } 1992 } 1993 1994 void rtsx_disable_aspm(struct rtsx_chip *chip) 1995 { 1996 if (CHECK_PID(chip, 0x5208)) 1997 rtsx_monitor_aspm_config(chip); 1998 1999 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) { 2000 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n"); 2001 chip->aspm_enabled = 0; 2002 2003 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 2004 rtsx_write_phy_register(chip, 0x07, 0x0129); 2005 if (CHECK_PID(chip, 0x5208)) 2006 rtsx_write_register(chip, ASPM_FORCE_CTL, 2007 0xF3, 0x30); 2008 else 2009 rtsx_write_config_byte(chip, LCTLR, 0x00); 2010 2011 wait_timeout(1); 2012 } 2013 } 2014 2015 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2016 { 2017 int retval; 2018 int i, j; 2019 u16 reg_addr; 2020 u8 *ptr; 2021 2022 if (!buf) 2023 return STATUS_ERROR; 2024 2025 ptr = buf; 2026 reg_addr = PPBUF_BASE2; 2027 for (i = 0; i < buf_len / 256; i++) { 2028 rtsx_init_cmd(chip); 2029 2030 for (j = 0; j < 256; j++) 2031 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2032 2033 retval = rtsx_send_cmd(chip, 0, 250); 2034 if (retval < 0) 2035 return STATUS_FAIL; 2036 2037 memcpy(ptr, rtsx_get_cmd_data(chip), 256); 2038 ptr += 256; 2039 } 2040 2041 if (buf_len % 256) { 2042 rtsx_init_cmd(chip); 2043 2044 for (j = 0; j < buf_len % 256; j++) 2045 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2046 2047 retval = rtsx_send_cmd(chip, 0, 250); 2048 if (retval < 0) 2049 return STATUS_FAIL; 2050 } 2051 2052 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256); 2053 2054 return STATUS_SUCCESS; 2055 } 2056 2057 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2058 { 2059 int retval; 2060 int i, j; 2061 u16 reg_addr; 2062 u8 *ptr; 2063 2064 if (!buf) 2065 return STATUS_ERROR; 2066 2067 ptr = buf; 2068 reg_addr = PPBUF_BASE2; 2069 for (i = 0; i < buf_len / 256; i++) { 2070 rtsx_init_cmd(chip); 2071 2072 for (j = 0; j < 256; j++) { 2073 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, 2074 *ptr); 2075 ptr++; 2076 } 2077 2078 retval = rtsx_send_cmd(chip, 0, 250); 2079 if (retval < 0) 2080 return STATUS_FAIL; 2081 } 2082 2083 if (buf_len % 256) { 2084 rtsx_init_cmd(chip); 2085 2086 for (j = 0; j < buf_len % 256; j++) { 2087 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, 2088 *ptr); 2089 ptr++; 2090 } 2091 2092 retval = rtsx_send_cmd(chip, 0, 250); 2093 if (retval < 0) 2094 return STATUS_FAIL; 2095 } 2096 2097 return STATUS_SUCCESS; 2098 } 2099 2100 int rtsx_check_chip_exist(struct rtsx_chip *chip) 2101 { 2102 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) 2103 return STATUS_FAIL; 2104 2105 return STATUS_SUCCESS; 2106 } 2107 2108 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl) 2109 { 2110 int retval; 2111 u8 mask = 0; 2112 2113 if (ctl & SSC_PDCTL) 2114 mask |= SSC_POWER_DOWN; 2115 2116 #ifdef SUPPORT_OCP 2117 if (ctl & OC_PDCTL) { 2118 mask |= SD_OC_POWER_DOWN; 2119 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2120 mask |= MS_OC_POWER_DOWN; 2121 } 2122 #endif 2123 2124 if (mask) { 2125 retval = rtsx_write_register(chip, FPDCTL, mask, 0); 2126 if (retval != STATUS_SUCCESS) 2127 return STATUS_FAIL; 2128 2129 if (CHECK_PID(chip, 0x5288)) 2130 wait_timeout(200); 2131 } 2132 2133 return STATUS_SUCCESS; 2134 } 2135 2136 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl) 2137 { 2138 int retval; 2139 u8 mask = 0, val = 0; 2140 2141 if (ctl & SSC_PDCTL) 2142 mask |= SSC_POWER_DOWN; 2143 2144 #ifdef SUPPORT_OCP 2145 if (ctl & OC_PDCTL) { 2146 mask |= SD_OC_POWER_DOWN; 2147 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2148 mask |= MS_OC_POWER_DOWN; 2149 } 2150 #endif 2151 2152 if (mask) { 2153 val = mask; 2154 retval = rtsx_write_register(chip, FPDCTL, mask, val); 2155 if (retval != STATUS_SUCCESS) 2156 return STATUS_FAIL; 2157 } 2158 2159 return STATUS_SUCCESS; 2160 } 2161