xref: /linux/drivers/staging/rtl8192e/rtl819x_Qos.h (revision 307797159ac25fe5a2048bf5c6a5718298edca57)
1 /******************************************************************************
2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3  *
4  * This program is distributed in the hope that it will be useful, but WITHOUT
5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
7  * more details.
8  *
9  * The full GNU General Public License is included in this distribution in the
10  * file called LICENSE.
11  *
12  * Contact Information:
13  * wlanfae <wlanfae@realtek.com>
14  *****************************************************************************/
15 #ifndef __INC_QOS_TYPE_H
16 #define __INC_QOS_TYPE_H
17 
18 #define BIT0		    0x00000001
19 #define BIT1		    0x00000002
20 #define BIT2		    0x00000004
21 #define BIT3		    0x00000008
22 #define BIT4		    0x00000010
23 #define BIT5		    0x00000020
24 #define BIT6		    0x00000040
25 #define BIT7		    0x00000080
26 #define BIT8		    0x00000100
27 #define BIT9		    0x00000200
28 #define BIT10		   0x00000400
29 #define BIT11		   0x00000800
30 #define BIT12		   0x00001000
31 #define BIT13		   0x00002000
32 #define BIT14		   0x00004000
33 #define BIT15		   0x00008000
34 #define BIT16		   0x00010000
35 #define BIT17		   0x00020000
36 #define BIT18		   0x00040000
37 #define BIT19		   0x00080000
38 #define BIT20		   0x00100000
39 #define BIT21		   0x00200000
40 #define BIT22		   0x00400000
41 #define BIT23		   0x00800000
42 #define BIT24		   0x01000000
43 #define BIT25		   0x02000000
44 #define BIT26		   0x04000000
45 #define BIT27		   0x08000000
46 #define BIT28		   0x10000000
47 #define BIT29		   0x20000000
48 #define BIT30		   0x40000000
49 #define BIT31		   0x80000000
50 
51 union qos_tsinfo {
52 	u8		charData[3];
53 	struct {
54 		u8		ucTrafficType:1;
55 		u8		ucTSID:4;
56 		u8		ucDirection:2;
57 		u8		ucAccessPolicy:2;
58 		u8		ucAggregation:1;
59 		u8		ucPSB:1;
60 		u8		ucUP:3;
61 		u8		ucTSInfoAckPolicy:2;
62 		u8		ucSchedule:1;
63 		u8		ucReserved:7;
64 	} field;
65 };
66 
67 union tspec_body {
68 	u8		charData[55];
69 
70 	struct {
71 		union qos_tsinfo TSInfo;
72 		u16	NominalMSDUsize;
73 		u16	MaxMSDUsize;
74 		u32	MinServiceItv;
75 		u32	MaxServiceItv;
76 		u32	InactivityItv;
77 		u32	SuspenItv;
78 		u32	ServiceStartTime;
79 		u32	MinDataRate;
80 		u32	MeanDataRate;
81 		u32	PeakDataRate;
82 		u32	MaxBurstSize;
83 		u32	DelayBound;
84 		u32	MinPhyRate;
85 		u16	SurplusBandwidthAllowance;
86 		u16	MediumTime;
87 	} f;
88 };
89 
90 struct octet_string {
91 	u8 *Octet;
92 	u16 Length;
93 };
94 
95 #define AC0_BE	0
96 #define AC1_BK	1
97 #define AC2_VI	2
98 #define AC3_VO	3
99 #define AC_MAX	4
100 
101 enum direction_value {
102 	DIR_UP			= 0,
103 	DIR_DOWN		= 1,
104 	DIR_DIRECT		= 2,
105 	DIR_BI_DIR		= 3,
106 };
107 
108 enum acm_method {
109 	eAcmWay0_SwAndHw		= 0,
110 	eAcmWay1_HW			= 1,
111 	eAcmWay2_SW			= 2,
112 };
113 
114 
115 struct acm {
116 	u64		UsedTime;
117 	u64		MediumTime;
118 	u8		HwAcmCtl;
119 };
120 
121 union qos_tclas {
122 
123 	struct _TYPE_GENERAL {
124 		u8		Priority;
125 		u8		ClassifierType;
126 		u8		Mask;
127 	} TYPE_GENERAL;
128 
129 	struct _TYPE0_ETH {
130 		u8		Priority;
131 		u8		ClassifierType;
132 		u8		Mask;
133 		u8		SrcAddr[ETH_ALEN];
134 		u8		DstAddr[ETH_ALEN];
135 		u16		Type;
136 	} TYPE0_ETH;
137 
138 	struct _TYPE1_IPV4 {
139 		u8		Priority;
140 		u8		ClassifierType;
141 		u8		Mask;
142 		u8		Version;
143 		u8		SrcIP[4];
144 		u8		DstIP[4];
145 		u16		SrcPort;
146 		u16		DstPort;
147 		u8		DSCP;
148 		u8		Protocol;
149 		u8		Reserved;
150 	} TYPE1_IPV4;
151 
152 	struct _TYPE1_IPV6 {
153 		u8		Priority;
154 		u8		ClassifierType;
155 		u8		Mask;
156 		u8		Version;
157 		u8		SrcIP[16];
158 		u8		DstIP[16];
159 		u16		SrcPort;
160 		u16		DstPort;
161 		u8		FlowLabel[3];
162 	} TYPE1_IPV6;
163 
164 	struct _TYPE2_8021Q {
165 		u8		Priority;
166 		u8		ClassifierType;
167 		u8		Mask;
168 		u16		TagType;
169 	} TYPE2_8021Q;
170 };
171 
172 union aci_aifsn {
173 	u8	charData;
174 
175 	struct {
176 		u8	AIFSN:4;
177 		u8	acm:1;
178 		u8	ACI:2;
179 		u8	Reserved:1;
180 	} f;
181 };
182 
183 #endif
184