1 /* 2 * Sonics Silicon Backplane 3 * Broadcom ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/ssb/ssb_regs.h> 13 #include <linux/pci.h> 14 15 #include "ssb_private.h" 16 17 18 /* Clock sources */ 19 enum ssb_clksrc { 20 /* PCI clock */ 21 SSB_CHIPCO_CLKSRC_PCI, 22 /* Crystal slow clock oscillator */ 23 SSB_CHIPCO_CLKSRC_XTALOS, 24 /* Low power oscillator */ 25 SSB_CHIPCO_CLKSRC_LOPWROS, 26 }; 27 28 29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, 30 u32 mask, u32 value) 31 { 32 value &= mask; 33 value |= chipco_read32(cc, offset) & ~mask; 34 chipco_write32(cc, offset, value); 35 36 return value; 37 } 38 39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, 40 enum ssb_clkmode mode) 41 { 42 struct ssb_device *ccdev = cc->dev; 43 struct ssb_bus *bus; 44 u32 tmp; 45 46 if (!ccdev) 47 return; 48 bus = ccdev->bus; 49 50 /* We support SLOW only on 6..9 */ 51 if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW) 52 mode = SSB_CLKMODE_DYNAMIC; 53 54 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) 55 return; /* PMU controls clockmode, separated function needed */ 56 SSB_WARN_ON(ccdev->id.revision >= 20); 57 58 /* chipcommon cores prior to rev6 don't support dynamic clock control */ 59 if (ccdev->id.revision < 6) 60 return; 61 62 /* ChipCommon cores rev10+ need testing */ 63 if (ccdev->id.revision >= 10) 64 return; 65 66 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 67 return; 68 69 switch (mode) { 70 case SSB_CLKMODE_SLOW: /* For revs 6..9 only */ 71 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 72 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; 73 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 74 break; 75 case SSB_CLKMODE_FAST: 76 if (ccdev->id.revision < 10) { 77 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ 78 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 79 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 80 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; 81 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 82 } else { 83 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, 84 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) | 85 SSB_CHIPCO_SYSCLKCTL_FORCEHT)); 86 /* udelay(150); TODO: not available in early init */ 87 } 88 break; 89 case SSB_CLKMODE_DYNAMIC: 90 if (ccdev->id.revision < 10) { 91 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 92 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 93 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; 94 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 95 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != 96 SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) 97 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 98 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 99 100 /* For dynamic control, we have to release our xtal_pu 101 * "force on" */ 102 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) 103 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); 104 } else { 105 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, 106 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & 107 ~SSB_CHIPCO_SYSCLKCTL_FORCEHT)); 108 } 109 break; 110 default: 111 SSB_WARN_ON(1); 112 } 113 } 114 115 /* Get the Slow Clock Source */ 116 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) 117 { 118 struct ssb_bus *bus = cc->dev->bus; 119 u32 uninitialized_var(tmp); 120 121 if (cc->dev->id.revision < 6) { 122 if (bus->bustype == SSB_BUSTYPE_SSB || 123 bus->bustype == SSB_BUSTYPE_PCMCIA) 124 return SSB_CHIPCO_CLKSRC_XTALOS; 125 if (bus->bustype == SSB_BUSTYPE_PCI) { 126 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); 127 if (tmp & 0x10) 128 return SSB_CHIPCO_CLKSRC_PCI; 129 return SSB_CHIPCO_CLKSRC_XTALOS; 130 } 131 } 132 if (cc->dev->id.revision < 10) { 133 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 134 tmp &= 0x7; 135 if (tmp == 0) 136 return SSB_CHIPCO_CLKSRC_LOPWROS; 137 if (tmp == 1) 138 return SSB_CHIPCO_CLKSRC_XTALOS; 139 if (tmp == 2) 140 return SSB_CHIPCO_CLKSRC_PCI; 141 } 142 143 return SSB_CHIPCO_CLKSRC_XTALOS; 144 } 145 146 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ 147 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) 148 { 149 int uninitialized_var(limit); 150 enum ssb_clksrc clocksrc; 151 int divisor = 1; 152 u32 tmp; 153 154 clocksrc = chipco_pctl_get_slowclksrc(cc); 155 if (cc->dev->id.revision < 6) { 156 switch (clocksrc) { 157 case SSB_CHIPCO_CLKSRC_PCI: 158 divisor = 64; 159 break; 160 case SSB_CHIPCO_CLKSRC_XTALOS: 161 divisor = 32; 162 break; 163 default: 164 SSB_WARN_ON(1); 165 } 166 } else if (cc->dev->id.revision < 10) { 167 switch (clocksrc) { 168 case SSB_CHIPCO_CLKSRC_LOPWROS: 169 break; 170 case SSB_CHIPCO_CLKSRC_XTALOS: 171 case SSB_CHIPCO_CLKSRC_PCI: 172 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 173 divisor = (tmp >> 16) + 1; 174 divisor *= 4; 175 break; 176 } 177 } else { 178 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); 179 divisor = (tmp >> 16) + 1; 180 divisor *= 4; 181 } 182 183 switch (clocksrc) { 184 case SSB_CHIPCO_CLKSRC_LOPWROS: 185 if (get_max) 186 limit = 43000; 187 else 188 limit = 25000; 189 break; 190 case SSB_CHIPCO_CLKSRC_XTALOS: 191 if (get_max) 192 limit = 20200000; 193 else 194 limit = 19800000; 195 break; 196 case SSB_CHIPCO_CLKSRC_PCI: 197 if (get_max) 198 limit = 34000000; 199 else 200 limit = 25000000; 201 break; 202 } 203 limit /= divisor; 204 205 return limit; 206 } 207 208 static void chipco_powercontrol_init(struct ssb_chipcommon *cc) 209 { 210 struct ssb_bus *bus = cc->dev->bus; 211 212 if (bus->chip_id == 0x4321) { 213 if (bus->chip_rev == 0) 214 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); 215 else if (bus->chip_rev == 1) 216 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); 217 } 218 219 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 220 return; 221 222 if (cc->dev->id.revision >= 10) { 223 /* Set Idle Power clock rate to 1Mhz */ 224 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, 225 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & 226 0x0000FFFF) | 0x00040000); 227 } else { 228 int maxfreq; 229 230 maxfreq = chipco_pctl_clockfreqlimit(cc, 1); 231 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, 232 (maxfreq * 150 + 999999) / 1000000); 233 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, 234 (maxfreq * 15 + 999999) / 1000000); 235 } 236 } 237 238 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */ 239 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc) 240 { 241 struct ssb_bus *bus = cc->dev->bus; 242 243 switch (bus->chip_id) { 244 case 0x4312: 245 case 0x4322: 246 case 0x4328: 247 return 7000; 248 case 0x4325: 249 /* TODO: */ 250 default: 251 return 15000; 252 } 253 } 254 255 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */ 256 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) 257 { 258 struct ssb_bus *bus = cc->dev->bus; 259 int minfreq; 260 unsigned int tmp; 261 u32 pll_on_delay; 262 263 if (bus->bustype != SSB_BUSTYPE_PCI) 264 return; 265 266 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { 267 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc); 268 return; 269 } 270 271 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 272 return; 273 274 minfreq = chipco_pctl_clockfreqlimit(cc, 0); 275 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); 276 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; 277 SSB_WARN_ON(tmp & ~0xFFFF); 278 279 cc->fast_pwrup_delay = tmp; 280 } 281 282 void ssb_chipcommon_init(struct ssb_chipcommon *cc) 283 { 284 if (!cc->dev) 285 return; /* We don't have a ChipCommon */ 286 if (cc->dev->id.revision >= 11) 287 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); 288 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status); 289 290 if (cc->dev->id.revision >= 20) { 291 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0); 292 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0); 293 } 294 295 ssb_pmu_init(cc); 296 chipco_powercontrol_init(cc); 297 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 298 calc_fast_powerup_delay(cc); 299 } 300 301 void ssb_chipco_suspend(struct ssb_chipcommon *cc) 302 { 303 if (!cc->dev) 304 return; 305 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 306 } 307 308 void ssb_chipco_resume(struct ssb_chipcommon *cc) 309 { 310 if (!cc->dev) 311 return; 312 chipco_powercontrol_init(cc); 313 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 314 } 315 316 /* Get the processor clock */ 317 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, 318 u32 *plltype, u32 *n, u32 *m) 319 { 320 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 321 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 322 switch (*plltype) { 323 case SSB_PLLTYPE_2: 324 case SSB_PLLTYPE_4: 325 case SSB_PLLTYPE_6: 326 case SSB_PLLTYPE_7: 327 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 328 break; 329 case SSB_PLLTYPE_3: 330 /* 5350 uses m2 to control mips */ 331 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 332 break; 333 default: 334 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 335 break; 336 } 337 } 338 339 /* Get the bus clock */ 340 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, 341 u32 *plltype, u32 *n, u32 *m) 342 { 343 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 344 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 345 switch (*plltype) { 346 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 347 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 348 break; 349 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 350 if (cc->dev->bus->chip_id != 0x5365) { 351 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 352 break; 353 } 354 /* Fallthough */ 355 default: 356 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 357 } 358 } 359 360 void ssb_chipco_timing_init(struct ssb_chipcommon *cc, 361 unsigned long ns) 362 { 363 struct ssb_device *dev = cc->dev; 364 struct ssb_bus *bus = dev->bus; 365 u32 tmp; 366 367 /* set register for external IO to control LED. */ 368 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); 369 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 370 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ 371 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ 372 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 373 374 /* Set timing for the flash */ 375 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ 376 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ 377 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ 378 if ((bus->chip_id == 0x5365) || 379 (dev->id.revision < 9)) 380 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); 381 if ((bus->chip_id == 0x5365) || 382 (dev->id.revision < 9) || 383 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) 384 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); 385 386 if (bus->chip_id == 0x5350) { 387 /* Enable EXTIF */ 388 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 389 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ 390 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ 391 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ 392 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 393 } 394 } 395 396 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 397 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) 398 { 399 /* instant NMI */ 400 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); 401 } 402 403 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value) 404 { 405 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value); 406 } 407 408 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask) 409 { 410 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask; 411 } 412 413 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) 414 { 415 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; 416 } 417 418 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) 419 { 420 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); 421 } 422 423 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) 424 { 425 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); 426 } 427 428 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) 429 { 430 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); 431 } 432 EXPORT_SYMBOL(ssb_chipco_gpio_control); 433 434 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) 435 { 436 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); 437 } 438 439 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) 440 { 441 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); 442 } 443 444 #ifdef CONFIG_SSB_SERIAL 445 int ssb_chipco_serial_init(struct ssb_chipcommon *cc, 446 struct ssb_serial_port *ports) 447 { 448 struct ssb_bus *bus = cc->dev->bus; 449 int nr_ports = 0; 450 u32 plltype; 451 unsigned int irq; 452 u32 baud_base, div; 453 u32 i, n; 454 unsigned int ccrev = cc->dev->id.revision; 455 456 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 457 irq = ssb_mips_irq(cc->dev); 458 459 if (plltype == SSB_PLLTYPE_1) { 460 /* PLL clock */ 461 baud_base = ssb_calc_clock_rate(plltype, 462 chipco_read32(cc, SSB_CHIPCO_CLOCK_N), 463 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); 464 div = 1; 465 } else { 466 if (ccrev == 20) { 467 /* BCM5354 uses constant 25MHz clock */ 468 baud_base = 25000000; 469 div = 48; 470 /* Set the override bit so we don't divide it */ 471 chipco_write32(cc, SSB_CHIPCO_CORECTL, 472 chipco_read32(cc, SSB_CHIPCO_CORECTL) 473 | SSB_CHIPCO_CORECTL_UARTCLK0); 474 } else if ((ccrev >= 11) && (ccrev != 15)) { 475 /* Fixed ALP clock */ 476 baud_base = 20000000; 477 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { 478 /* FIXME: baud_base is different for devices with a PMU */ 479 SSB_WARN_ON(1); 480 } 481 div = 1; 482 if (ccrev >= 21) { 483 /* Turn off UART clock before switching clocksource. */ 484 chipco_write32(cc, SSB_CHIPCO_CORECTL, 485 chipco_read32(cc, SSB_CHIPCO_CORECTL) 486 & ~SSB_CHIPCO_CORECTL_UARTCLKEN); 487 } 488 /* Set the override bit so we don't divide it */ 489 chipco_write32(cc, SSB_CHIPCO_CORECTL, 490 chipco_read32(cc, SSB_CHIPCO_CORECTL) 491 | SSB_CHIPCO_CORECTL_UARTCLK0); 492 if (ccrev >= 21) { 493 /* Re-enable the UART clock. */ 494 chipco_write32(cc, SSB_CHIPCO_CORECTL, 495 chipco_read32(cc, SSB_CHIPCO_CORECTL) 496 | SSB_CHIPCO_CORECTL_UARTCLKEN); 497 } 498 } else if (ccrev >= 3) { 499 /* Internal backplane clock */ 500 baud_base = ssb_clockspeed(bus); 501 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) 502 & SSB_CHIPCO_CLKDIV_UART; 503 } else { 504 /* Fixed internal backplane clock */ 505 baud_base = 88000000; 506 div = 48; 507 } 508 509 /* Clock source depends on strapping if UartClkOverride is unset */ 510 if ((ccrev > 0) && 511 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { 512 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == 513 SSB_CHIPCO_CAP_UARTCLK_INT) { 514 /* Internal divided backplane clock */ 515 baud_base /= div; 516 } else { 517 /* Assume external clock of 1.8432 MHz */ 518 baud_base = 1843200; 519 } 520 } 521 } 522 523 /* Determine the registers of the UARTs */ 524 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); 525 for (i = 0; i < n; i++) { 526 void __iomem *cc_mmio; 527 void __iomem *uart_regs; 528 529 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); 530 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; 531 /* Offset changed at after rev 0 */ 532 if (ccrev == 0) 533 uart_regs += (i * 8); 534 else 535 uart_regs += (i * 256); 536 537 nr_ports++; 538 ports[i].regs = uart_regs; 539 ports[i].irq = irq; 540 ports[i].baud_base = baud_base; 541 ports[i].reg_shift = 0; 542 } 543 544 return nr_ports; 545 } 546 #endif /* CONFIG_SSB_SERIAL */ 547