1 /* 2 * SPI driver for Nvidia's Tegra20 Serial Flash Controller. 3 * 4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 5 * 6 * Author: Laxman Dewangan <ldewangan@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kernel.h> 29 #include <linux/kthread.h> 30 #include <linux/module.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/spi-tegra.h> 37 #include <linux/clk/tegra.h> 38 39 #define SPI_COMMAND 0x000 40 #define SPI_GO BIT(30) 41 #define SPI_M_S BIT(28) 42 #define SPI_ACTIVE_SCLK_MASK (0x3 << 26) 43 #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26) 44 #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26) 45 #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26) 46 #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26) 47 48 #define SPI_CK_SDA_FALLING (1 << 21) 49 #define SPI_CK_SDA_RISING (0 << 21) 50 #define SPI_CK_SDA_MASK (1 << 21) 51 #define SPI_ACTIVE_SDA (0x3 << 18) 52 #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18) 53 #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18) 54 #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18) 55 #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18) 56 57 #define SPI_CS_POL_INVERT BIT(16) 58 #define SPI_TX_EN BIT(15) 59 #define SPI_RX_EN BIT(14) 60 #define SPI_CS_VAL_HIGH BIT(13) 61 #define SPI_CS_VAL_LOW 0x0 62 #define SPI_CS_SW BIT(12) 63 #define SPI_CS_HW 0x0 64 #define SPI_CS_DELAY_MASK (7 << 9) 65 #define SPI_CS3_EN BIT(8) 66 #define SPI_CS2_EN BIT(7) 67 #define SPI_CS1_EN BIT(6) 68 #define SPI_CS0_EN BIT(5) 69 70 #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \ 71 SPI_CS1_EN | SPI_CS0_EN) 72 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) 73 74 #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK) 75 76 #define SPI_STATUS 0x004 77 #define SPI_BSY BIT(31) 78 #define SPI_RDY BIT(30) 79 #define SPI_TXF_FLUSH BIT(29) 80 #define SPI_RXF_FLUSH BIT(28) 81 #define SPI_RX_UNF BIT(27) 82 #define SPI_TX_OVF BIT(26) 83 #define SPI_RXF_EMPTY BIT(25) 84 #define SPI_RXF_FULL BIT(24) 85 #define SPI_TXF_EMPTY BIT(23) 86 #define SPI_TXF_FULL BIT(22) 87 #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1) 88 89 #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF) 90 #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY) 91 92 #define SPI_RX_CMP 0x8 93 #define SPI_DMA_CTL 0x0C 94 #define SPI_DMA_EN BIT(31) 95 #define SPI_IE_RXC BIT(27) 96 #define SPI_IE_TXC BIT(26) 97 #define SPI_PACKED BIT(20) 98 #define SPI_RX_TRIG_MASK (0x3 << 18) 99 #define SPI_RX_TRIG_1W (0x0 << 18) 100 #define SPI_RX_TRIG_4W (0x1 << 18) 101 #define SPI_TX_TRIG_MASK (0x3 << 16) 102 #define SPI_TX_TRIG_1W (0x0 << 16) 103 #define SPI_TX_TRIG_4W (0x1 << 16) 104 #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF); 105 106 #define SPI_TX_FIFO 0x10 107 #define SPI_RX_FIFO 0x20 108 109 #define DATA_DIR_TX (1 << 0) 110 #define DATA_DIR_RX (1 << 1) 111 112 #define MAX_CHIP_SELECT 4 113 #define SPI_FIFO_DEPTH 4 114 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 115 116 struct tegra_sflash_data { 117 struct device *dev; 118 struct spi_master *master; 119 spinlock_t lock; 120 121 struct clk *clk; 122 void __iomem *base; 123 unsigned irq; 124 u32 spi_max_frequency; 125 u32 cur_speed; 126 127 struct spi_device *cur_spi; 128 unsigned cur_pos; 129 unsigned cur_len; 130 unsigned bytes_per_word; 131 unsigned cur_direction; 132 unsigned curr_xfer_words; 133 134 unsigned cur_rx_pos; 135 unsigned cur_tx_pos; 136 137 u32 tx_status; 138 u32 rx_status; 139 u32 status_reg; 140 141 u32 def_command_reg; 142 u32 command_reg; 143 u32 dma_control_reg; 144 145 struct completion xfer_completion; 146 struct spi_transfer *curr_xfer; 147 }; 148 149 static int tegra_sflash_runtime_suspend(struct device *dev); 150 static int tegra_sflash_runtime_resume(struct device *dev); 151 152 static inline unsigned long tegra_sflash_readl(struct tegra_sflash_data *tsd, 153 unsigned long reg) 154 { 155 return readl(tsd->base + reg); 156 } 157 158 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd, 159 unsigned long val, unsigned long reg) 160 { 161 writel(val, tsd->base + reg); 162 } 163 164 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd) 165 { 166 /* Write 1 to clear status register */ 167 tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS); 168 } 169 170 static unsigned tegra_sflash_calculate_curr_xfer_param( 171 struct spi_device *spi, struct tegra_sflash_data *tsd, 172 struct spi_transfer *t) 173 { 174 unsigned remain_len = t->len - tsd->cur_pos; 175 unsigned max_word; 176 177 tsd->bytes_per_word = (t->bits_per_word - 1) / 8 + 1; 178 max_word = remain_len / tsd->bytes_per_word; 179 if (max_word > SPI_FIFO_DEPTH) 180 max_word = SPI_FIFO_DEPTH; 181 tsd->curr_xfer_words = max_word; 182 return max_word; 183 } 184 185 static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf( 186 struct tegra_sflash_data *tsd, struct spi_transfer *t) 187 { 188 unsigned nbytes; 189 unsigned long status; 190 unsigned max_n_32bit = tsd->curr_xfer_words; 191 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos; 192 193 if (max_n_32bit > SPI_FIFO_DEPTH) 194 max_n_32bit = SPI_FIFO_DEPTH; 195 nbytes = max_n_32bit * tsd->bytes_per_word; 196 197 status = tegra_sflash_readl(tsd, SPI_STATUS); 198 while (!(status & SPI_TXF_FULL)) { 199 int i; 200 unsigned int x = 0; 201 202 for (i = 0; nbytes && (i < tsd->bytes_per_word); 203 i++, nbytes--) 204 x |= ((*tx_buf++) << i*8); 205 tegra_sflash_writel(tsd, x, SPI_TX_FIFO); 206 if (!nbytes) 207 break; 208 209 status = tegra_sflash_readl(tsd, SPI_STATUS); 210 } 211 tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word; 212 return max_n_32bit; 213 } 214 215 static int tegra_sflash_read_rx_fifo_to_client_rxbuf( 216 struct tegra_sflash_data *tsd, struct spi_transfer *t) 217 { 218 unsigned long status; 219 unsigned int read_words = 0; 220 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos; 221 222 status = tegra_sflash_readl(tsd, SPI_STATUS); 223 while (!(status & SPI_RXF_EMPTY)) { 224 int i; 225 unsigned long x; 226 227 x = tegra_sflash_readl(tsd, SPI_RX_FIFO); 228 for (i = 0; (i < tsd->bytes_per_word); i++) 229 *rx_buf++ = (x >> (i*8)) & 0xFF; 230 read_words++; 231 status = tegra_sflash_readl(tsd, SPI_STATUS); 232 } 233 tsd->cur_rx_pos += read_words * tsd->bytes_per_word; 234 return 0; 235 } 236 237 static int tegra_sflash_start_cpu_based_transfer( 238 struct tegra_sflash_data *tsd, struct spi_transfer *t) 239 { 240 unsigned long val = 0; 241 unsigned cur_words; 242 243 if (tsd->cur_direction & DATA_DIR_TX) 244 val |= SPI_IE_TXC; 245 246 if (tsd->cur_direction & DATA_DIR_RX) 247 val |= SPI_IE_RXC; 248 249 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 250 tsd->dma_control_reg = val; 251 252 if (tsd->cur_direction & DATA_DIR_TX) 253 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t); 254 else 255 cur_words = tsd->curr_xfer_words; 256 val |= SPI_DMA_BLK_COUNT(cur_words); 257 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 258 tsd->dma_control_reg = val; 259 val |= SPI_DMA_EN; 260 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 261 return 0; 262 } 263 264 static int tegra_sflash_start_transfer_one(struct spi_device *spi, 265 struct spi_transfer *t, bool is_first_of_msg, 266 bool is_single_xfer) 267 { 268 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); 269 u32 speed; 270 unsigned long command; 271 272 speed = t->speed_hz; 273 if (speed != tsd->cur_speed) { 274 clk_set_rate(tsd->clk, speed); 275 tsd->cur_speed = speed; 276 } 277 278 tsd->cur_spi = spi; 279 tsd->cur_pos = 0; 280 tsd->cur_rx_pos = 0; 281 tsd->cur_tx_pos = 0; 282 tsd->curr_xfer = t; 283 tegra_sflash_calculate_curr_xfer_param(spi, tsd, t); 284 if (is_first_of_msg) { 285 command = tsd->def_command_reg; 286 command |= SPI_BIT_LENGTH(t->bits_per_word - 1); 287 command |= SPI_CS_VAL_HIGH; 288 289 command &= ~SPI_MODES; 290 if (spi->mode & SPI_CPHA) 291 command |= SPI_CK_SDA_FALLING; 292 293 if (spi->mode & SPI_CPOL) 294 command |= SPI_ACTIVE_SCLK_DRIVE_HIGH; 295 else 296 command |= SPI_ACTIVE_SCLK_DRIVE_LOW; 297 command |= SPI_CS0_EN << spi->chip_select; 298 } else { 299 command = tsd->command_reg; 300 command &= ~SPI_BIT_LENGTH(~0); 301 command |= SPI_BIT_LENGTH(t->bits_per_word - 1); 302 command &= ~(SPI_RX_EN | SPI_TX_EN); 303 } 304 305 tsd->cur_direction = 0; 306 if (t->rx_buf) { 307 command |= SPI_RX_EN; 308 tsd->cur_direction |= DATA_DIR_RX; 309 } 310 if (t->tx_buf) { 311 command |= SPI_TX_EN; 312 tsd->cur_direction |= DATA_DIR_TX; 313 } 314 tegra_sflash_writel(tsd, command, SPI_COMMAND); 315 tsd->command_reg = command; 316 317 return tegra_sflash_start_cpu_based_transfer(tsd, t); 318 } 319 320 static int tegra_sflash_setup(struct spi_device *spi) 321 { 322 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); 323 324 /* Set speed to the spi max fequency if spi device has not set */ 325 spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency; 326 return 0; 327 } 328 329 static int tegra_sflash_transfer_one_message(struct spi_master *master, 330 struct spi_message *msg) 331 { 332 bool is_first_msg = true; 333 int single_xfer; 334 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 335 struct spi_transfer *xfer; 336 struct spi_device *spi = msg->spi; 337 int ret; 338 339 ret = pm_runtime_get_sync(tsd->dev); 340 if (ret < 0) { 341 dev_err(tsd->dev, "pm_runtime_get() failed, err = %d\n", ret); 342 return ret; 343 } 344 345 msg->status = 0; 346 msg->actual_length = 0; 347 single_xfer = list_is_singular(&msg->transfers); 348 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 349 INIT_COMPLETION(tsd->xfer_completion); 350 ret = tegra_sflash_start_transfer_one(spi, xfer, 351 is_first_msg, single_xfer); 352 if (ret < 0) { 353 dev_err(tsd->dev, 354 "spi can not start transfer, err %d\n", ret); 355 goto exit; 356 } 357 is_first_msg = false; 358 ret = wait_for_completion_timeout(&tsd->xfer_completion, 359 SPI_DMA_TIMEOUT); 360 if (WARN_ON(ret == 0)) { 361 dev_err(tsd->dev, 362 "spi trasfer timeout, err %d\n", ret); 363 ret = -EIO; 364 goto exit; 365 } 366 367 if (tsd->tx_status || tsd->rx_status) { 368 dev_err(tsd->dev, "Error in Transfer\n"); 369 ret = -EIO; 370 goto exit; 371 } 372 msg->actual_length += xfer->len; 373 if (xfer->cs_change && xfer->delay_usecs) { 374 tegra_sflash_writel(tsd, tsd->def_command_reg, 375 SPI_COMMAND); 376 udelay(xfer->delay_usecs); 377 } 378 } 379 ret = 0; 380 exit: 381 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 382 msg->status = ret; 383 spi_finalize_current_message(master); 384 pm_runtime_put(tsd->dev); 385 return ret; 386 } 387 388 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd) 389 { 390 struct spi_transfer *t = tsd->curr_xfer; 391 unsigned long flags; 392 393 spin_lock_irqsave(&tsd->lock, flags); 394 if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) { 395 dev_err(tsd->dev, 396 "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg); 397 dev_err(tsd->dev, 398 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, 399 tsd->dma_control_reg); 400 tegra_periph_reset_assert(tsd->clk); 401 udelay(2); 402 tegra_periph_reset_deassert(tsd->clk); 403 complete(&tsd->xfer_completion); 404 goto exit; 405 } 406 407 if (tsd->cur_direction & DATA_DIR_RX) 408 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t); 409 410 if (tsd->cur_direction & DATA_DIR_TX) 411 tsd->cur_pos = tsd->cur_tx_pos; 412 else 413 tsd->cur_pos = tsd->cur_rx_pos; 414 415 if (tsd->cur_pos == t->len) { 416 complete(&tsd->xfer_completion); 417 goto exit; 418 } 419 420 tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t); 421 tegra_sflash_start_cpu_based_transfer(tsd, t); 422 exit: 423 spin_unlock_irqrestore(&tsd->lock, flags); 424 return IRQ_HANDLED; 425 } 426 427 static irqreturn_t tegra_sflash_isr(int irq, void *context_data) 428 { 429 struct tegra_sflash_data *tsd = context_data; 430 431 tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS); 432 if (tsd->cur_direction & DATA_DIR_TX) 433 tsd->tx_status = tsd->status_reg & SPI_TX_OVF; 434 435 if (tsd->cur_direction & DATA_DIR_RX) 436 tsd->rx_status = tsd->status_reg & SPI_RX_UNF; 437 tegra_sflash_clear_status(tsd); 438 439 return handle_cpu_based_xfer(tsd); 440 } 441 442 static struct tegra_spi_platform_data *tegra_sflash_parse_dt( 443 struct platform_device *pdev) 444 { 445 struct tegra_spi_platform_data *pdata; 446 struct device_node *np = pdev->dev.of_node; 447 u32 max_freq; 448 449 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 450 if (!pdata) { 451 dev_err(&pdev->dev, "Memory alloc for pdata failed\n"); 452 return NULL; 453 } 454 455 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) 456 pdata->spi_max_frequency = max_freq; 457 458 return pdata; 459 } 460 461 static struct of_device_id tegra_sflash_of_match[] = { 462 { .compatible = "nvidia,tegra20-sflash", }, 463 {} 464 }; 465 MODULE_DEVICE_TABLE(of, tegra_sflash_of_match); 466 467 static int tegra_sflash_probe(struct platform_device *pdev) 468 { 469 struct spi_master *master; 470 struct tegra_sflash_data *tsd; 471 struct resource *r; 472 struct tegra_spi_platform_data *pdata = pdev->dev.platform_data; 473 int ret; 474 const struct of_device_id *match; 475 476 match = of_match_device(of_match_ptr(tegra_sflash_of_match), 477 &pdev->dev); 478 if (!match) { 479 dev_err(&pdev->dev, "Error: No device match found\n"); 480 return -ENODEV; 481 } 482 483 if (!pdata && pdev->dev.of_node) 484 pdata = tegra_sflash_parse_dt(pdev); 485 486 if (!pdata) { 487 dev_err(&pdev->dev, "No platform data, exiting\n"); 488 return -ENODEV; 489 } 490 491 if (!pdata->spi_max_frequency) 492 pdata->spi_max_frequency = 25000000; /* 25MHz */ 493 494 master = spi_alloc_master(&pdev->dev, sizeof(*tsd)); 495 if (!master) { 496 dev_err(&pdev->dev, "master allocation failed\n"); 497 return -ENOMEM; 498 } 499 500 /* the spi->mode bits understood by this driver: */ 501 master->mode_bits = SPI_CPOL | SPI_CPHA; 502 master->setup = tegra_sflash_setup; 503 master->transfer_one_message = tegra_sflash_transfer_one_message; 504 master->num_chipselect = MAX_CHIP_SELECT; 505 master->bus_num = -1; 506 507 dev_set_drvdata(&pdev->dev, master); 508 tsd = spi_master_get_devdata(master); 509 tsd->master = master; 510 tsd->dev = &pdev->dev; 511 spin_lock_init(&tsd->lock); 512 513 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 514 if (!r) { 515 dev_err(&pdev->dev, "No IO memory resource\n"); 516 ret = -ENODEV; 517 goto exit_free_master; 518 } 519 tsd->base = devm_ioremap_resource(&pdev->dev, r); 520 if (IS_ERR(tsd->base)) { 521 ret = PTR_ERR(tsd->base); 522 goto exit_free_master; 523 } 524 525 tsd->irq = platform_get_irq(pdev, 0); 526 ret = request_irq(tsd->irq, tegra_sflash_isr, 0, 527 dev_name(&pdev->dev), tsd); 528 if (ret < 0) { 529 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 530 tsd->irq); 531 goto exit_free_master; 532 } 533 534 tsd->clk = devm_clk_get(&pdev->dev, NULL); 535 if (IS_ERR(tsd->clk)) { 536 dev_err(&pdev->dev, "can not get clock\n"); 537 ret = PTR_ERR(tsd->clk); 538 goto exit_free_irq; 539 } 540 541 tsd->spi_max_frequency = pdata->spi_max_frequency; 542 init_completion(&tsd->xfer_completion); 543 pm_runtime_enable(&pdev->dev); 544 if (!pm_runtime_enabled(&pdev->dev)) { 545 ret = tegra_sflash_runtime_resume(&pdev->dev); 546 if (ret) 547 goto exit_pm_disable; 548 } 549 550 ret = pm_runtime_get_sync(&pdev->dev); 551 if (ret < 0) { 552 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 553 goto exit_pm_disable; 554 } 555 556 /* Reset controller */ 557 tegra_periph_reset_assert(tsd->clk); 558 udelay(2); 559 tegra_periph_reset_deassert(tsd->clk); 560 561 tsd->def_command_reg = SPI_M_S | SPI_CS_SW; 562 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 563 pm_runtime_put(&pdev->dev); 564 565 master->dev.of_node = pdev->dev.of_node; 566 ret = spi_register_master(master); 567 if (ret < 0) { 568 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 569 goto exit_pm_disable; 570 } 571 return ret; 572 573 exit_pm_disable: 574 pm_runtime_disable(&pdev->dev); 575 if (!pm_runtime_status_suspended(&pdev->dev)) 576 tegra_sflash_runtime_suspend(&pdev->dev); 577 exit_free_irq: 578 free_irq(tsd->irq, tsd); 579 exit_free_master: 580 spi_master_put(master); 581 return ret; 582 } 583 584 static int tegra_sflash_remove(struct platform_device *pdev) 585 { 586 struct spi_master *master = dev_get_drvdata(&pdev->dev); 587 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 588 589 free_irq(tsd->irq, tsd); 590 spi_unregister_master(master); 591 592 pm_runtime_disable(&pdev->dev); 593 if (!pm_runtime_status_suspended(&pdev->dev)) 594 tegra_sflash_runtime_suspend(&pdev->dev); 595 596 return 0; 597 } 598 599 #ifdef CONFIG_PM_SLEEP 600 static int tegra_sflash_suspend(struct device *dev) 601 { 602 struct spi_master *master = dev_get_drvdata(dev); 603 604 return spi_master_suspend(master); 605 } 606 607 static int tegra_sflash_resume(struct device *dev) 608 { 609 struct spi_master *master = dev_get_drvdata(dev); 610 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 611 int ret; 612 613 ret = pm_runtime_get_sync(dev); 614 if (ret < 0) { 615 dev_err(dev, "pm runtime failed, e = %d\n", ret); 616 return ret; 617 } 618 tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND); 619 pm_runtime_put(dev); 620 621 return spi_master_resume(master); 622 } 623 #endif 624 625 static int tegra_sflash_runtime_suspend(struct device *dev) 626 { 627 struct spi_master *master = dev_get_drvdata(dev); 628 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 629 630 /* Flush all write which are in PPSB queue by reading back */ 631 tegra_sflash_readl(tsd, SPI_COMMAND); 632 633 clk_disable_unprepare(tsd->clk); 634 return 0; 635 } 636 637 static int tegra_sflash_runtime_resume(struct device *dev) 638 { 639 struct spi_master *master = dev_get_drvdata(dev); 640 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 641 int ret; 642 643 ret = clk_prepare_enable(tsd->clk); 644 if (ret < 0) { 645 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret); 646 return ret; 647 } 648 return 0; 649 } 650 651 static const struct dev_pm_ops slink_pm_ops = { 652 SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend, 653 tegra_sflash_runtime_resume, NULL) 654 SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume) 655 }; 656 static struct platform_driver tegra_sflash_driver = { 657 .driver = { 658 .name = "spi-tegra-sflash", 659 .owner = THIS_MODULE, 660 .pm = &slink_pm_ops, 661 .of_match_table = of_match_ptr(tegra_sflash_of_match), 662 }, 663 .probe = tegra_sflash_probe, 664 .remove = tegra_sflash_remove, 665 }; 666 module_platform_driver(tegra_sflash_driver); 667 668 MODULE_ALIAS("platform:spi-tegra-sflash"); 669 MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver"); 670 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 671 MODULE_LICENSE("GPL v2"); 672