1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2012 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_FW_H 8 #define __QLA_FW_H 9 10 #define MBS_CHECKSUM_ERROR 0x4010 11 #define MBS_INVALID_PRODUCT_KEY 0x4020 12 13 /* 14 * Firmware Options. 15 */ 16 #define FO1_ENABLE_PUREX BIT_10 17 #define FO1_DISABLE_LED_CTRL BIT_6 18 #define FO1_ENABLE_8016 BIT_0 19 #define FO2_ENABLE_SEL_CLASS2 BIT_5 20 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14 21 #define FO3_HOLD_STS_IOCB BIT_12 22 23 /* 24 * Port Database structure definition for ISP 24xx. 25 */ 26 #define PDO_FORCE_ADISC BIT_1 27 #define PDO_FORCE_PLOGI BIT_0 28 29 30 #define PORT_DATABASE_24XX_SIZE 64 31 struct port_database_24xx { 32 uint16_t flags; 33 #define PDF_TASK_RETRY_ID BIT_14 34 #define PDF_FC_TAPE BIT_7 35 #define PDF_ACK0_CAPABLE BIT_6 36 #define PDF_FCP2_CONF BIT_5 37 #define PDF_CLASS_2 BIT_4 38 #define PDF_HARD_ADDR BIT_1 39 40 uint8_t current_login_state; 41 uint8_t last_login_state; 42 #define PDS_PLOGI_PENDING 0x03 43 #define PDS_PLOGI_COMPLETE 0x04 44 #define PDS_PRLI_PENDING 0x05 45 #define PDS_PRLI_COMPLETE 0x06 46 #define PDS_PORT_UNAVAILABLE 0x07 47 #define PDS_PRLO_PENDING 0x09 48 #define PDS_LOGO_PENDING 0x11 49 #define PDS_PRLI2_PENDING 0x12 50 51 uint8_t hard_address[3]; 52 uint8_t reserved_1; 53 54 uint8_t port_id[3]; 55 uint8_t sequence_id; 56 57 uint16_t port_timer; 58 59 uint16_t nport_handle; /* N_PORT handle. */ 60 61 uint16_t receive_data_size; 62 uint16_t reserved_2; 63 64 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 65 /* Bits 15-0 of word 0 */ 66 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 67 /* Bits 15-0 of word 3 */ 68 69 uint8_t port_name[WWN_SIZE]; 70 uint8_t node_name[WWN_SIZE]; 71 72 uint8_t reserved_3[24]; 73 }; 74 75 struct vp_database_24xx { 76 uint16_t vp_status; 77 uint8_t options; 78 uint8_t id; 79 uint8_t port_name[WWN_SIZE]; 80 uint8_t node_name[WWN_SIZE]; 81 uint16_t port_id_low; 82 uint16_t port_id_high; 83 }; 84 85 struct nvram_24xx { 86 /* NVRAM header. */ 87 uint8_t id[4]; 88 uint16_t nvram_version; 89 uint16_t reserved_0; 90 91 /* Firmware Initialization Control Block. */ 92 uint16_t version; 93 uint16_t reserved_1; 94 uint16_t frame_payload_size; 95 uint16_t execution_throttle; 96 uint16_t exchange_count; 97 uint16_t hard_address; 98 99 uint8_t port_name[WWN_SIZE]; 100 uint8_t node_name[WWN_SIZE]; 101 102 uint16_t login_retry_count; 103 uint16_t link_down_on_nos; 104 uint16_t interrupt_delay_timer; 105 uint16_t login_timeout; 106 107 uint32_t firmware_options_1; 108 uint32_t firmware_options_2; 109 uint32_t firmware_options_3; 110 111 /* Offset 56. */ 112 113 /* 114 * BIT 0 = Control Enable 115 * BIT 1-15 = 116 * 117 * BIT 0-7 = Reserved 118 * BIT 8-10 = Output Swing 1G 119 * BIT 11-13 = Output Emphasis 1G 120 * BIT 14-15 = Reserved 121 * 122 * BIT 0-7 = Reserved 123 * BIT 8-10 = Output Swing 2G 124 * BIT 11-13 = Output Emphasis 2G 125 * BIT 14-15 = Reserved 126 * 127 * BIT 0-7 = Reserved 128 * BIT 8-10 = Output Swing 4G 129 * BIT 11-13 = Output Emphasis 4G 130 * BIT 14-15 = Reserved 131 */ 132 uint16_t seriallink_options[4]; 133 134 uint16_t reserved_2[16]; 135 136 /* Offset 96. */ 137 uint16_t reserved_3[16]; 138 139 /* PCIe table entries. */ 140 uint16_t reserved_4[16]; 141 142 /* Offset 160. */ 143 uint16_t reserved_5[16]; 144 145 /* Offset 192. */ 146 uint16_t reserved_6[16]; 147 148 /* Offset 224. */ 149 uint16_t reserved_7[16]; 150 151 /* 152 * BIT 0 = Enable spinup delay 153 * BIT 1 = Disable BIOS 154 * BIT 2 = Enable Memory Map BIOS 155 * BIT 3 = Enable Selectable Boot 156 * BIT 4 = Disable RISC code load 157 * BIT 5 = Disable Serdes 158 * BIT 6 = 159 * BIT 7 = 160 * 161 * BIT 8 = 162 * BIT 9 = 163 * BIT 10 = Enable lip full login 164 * BIT 11 = Enable target reset 165 * BIT 12 = 166 * BIT 13 = 167 * BIT 14 = 168 * BIT 15 = Enable alternate WWN 169 * 170 * BIT 16-31 = 171 */ 172 uint32_t host_p; 173 174 uint8_t alternate_port_name[WWN_SIZE]; 175 uint8_t alternate_node_name[WWN_SIZE]; 176 177 uint8_t boot_port_name[WWN_SIZE]; 178 uint16_t boot_lun_number; 179 uint16_t reserved_8; 180 181 uint8_t alt1_boot_port_name[WWN_SIZE]; 182 uint16_t alt1_boot_lun_number; 183 uint16_t reserved_9; 184 185 uint8_t alt2_boot_port_name[WWN_SIZE]; 186 uint16_t alt2_boot_lun_number; 187 uint16_t reserved_10; 188 189 uint8_t alt3_boot_port_name[WWN_SIZE]; 190 uint16_t alt3_boot_lun_number; 191 uint16_t reserved_11; 192 193 /* 194 * BIT 0 = Selective Login 195 * BIT 1 = Alt-Boot Enable 196 * BIT 2 = Reserved 197 * BIT 3 = Boot Order List 198 * BIT 4 = Reserved 199 * BIT 5 = Selective LUN 200 * BIT 6 = Reserved 201 * BIT 7-31 = 202 */ 203 uint32_t efi_parameters; 204 205 uint8_t reset_delay; 206 uint8_t reserved_12; 207 uint16_t reserved_13; 208 209 uint16_t boot_id_number; 210 uint16_t reserved_14; 211 212 uint16_t max_luns_per_target; 213 uint16_t reserved_15; 214 215 uint16_t port_down_retry_count; 216 uint16_t link_down_timeout; 217 218 /* FCode parameters. */ 219 uint16_t fcode_parameter; 220 221 uint16_t reserved_16[3]; 222 223 /* Offset 352. */ 224 uint8_t prev_drv_ver_major; 225 uint8_t prev_drv_ver_submajob; 226 uint8_t prev_drv_ver_minor; 227 uint8_t prev_drv_ver_subminor; 228 229 uint16_t prev_bios_ver_major; 230 uint16_t prev_bios_ver_minor; 231 232 uint16_t prev_efi_ver_major; 233 uint16_t prev_efi_ver_minor; 234 235 uint16_t prev_fw_ver_major; 236 uint8_t prev_fw_ver_minor; 237 uint8_t prev_fw_ver_subminor; 238 239 uint16_t reserved_17[8]; 240 241 /* Offset 384. */ 242 uint16_t reserved_18[16]; 243 244 /* Offset 416. */ 245 uint16_t reserved_19[16]; 246 247 /* Offset 448. */ 248 uint16_t reserved_20[16]; 249 250 /* Offset 480. */ 251 uint8_t model_name[16]; 252 253 uint16_t reserved_21[2]; 254 255 /* Offset 500. */ 256 /* HW Parameter Block. */ 257 uint16_t pcie_table_sig; 258 uint16_t pcie_table_offset; 259 260 uint16_t subsystem_vendor_id; 261 uint16_t subsystem_device_id; 262 263 uint32_t checksum; 264 }; 265 266 /* 267 * ISP Initialization Control Block. 268 * Little endian except where noted. 269 */ 270 #define ICB_VERSION 1 271 struct init_cb_24xx { 272 uint16_t version; 273 uint16_t reserved_1; 274 275 uint16_t frame_payload_size; 276 uint16_t execution_throttle; 277 uint16_t exchange_count; 278 279 uint16_t hard_address; 280 281 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 282 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 283 284 uint16_t response_q_inpointer; 285 uint16_t request_q_outpointer; 286 287 uint16_t login_retry_count; 288 289 uint16_t prio_request_q_outpointer; 290 291 uint16_t response_q_length; 292 uint16_t request_q_length; 293 294 uint16_t link_down_on_nos; /* Milliseconds. */ 295 296 uint16_t prio_request_q_length; 297 298 uint32_t request_q_address[2]; 299 uint32_t response_q_address[2]; 300 uint32_t prio_request_q_address[2]; 301 302 uint16_t msix; 303 uint8_t reserved_2[6]; 304 305 uint16_t atio_q_inpointer; 306 uint16_t atio_q_length; 307 uint32_t atio_q_address[2]; 308 309 uint16_t interrupt_delay_timer; /* 100us increments. */ 310 uint16_t login_timeout; 311 312 /* 313 * BIT 0 = Enable Hard Loop Id 314 * BIT 1 = Enable Fairness 315 * BIT 2 = Enable Full-Duplex 316 * BIT 3 = Reserved 317 * BIT 4 = Enable Target Mode 318 * BIT 5 = Disable Initiator Mode 319 * BIT 6 = Reserved 320 * BIT 7 = Reserved 321 * 322 * BIT 8 = Reserved 323 * BIT 9 = Non Participating LIP 324 * BIT 10 = Descending Loop ID Search 325 * BIT 11 = Acquire Loop ID in LIPA 326 * BIT 12 = Reserved 327 * BIT 13 = Full Login after LIP 328 * BIT 14 = Node Name Option 329 * BIT 15-31 = Reserved 330 */ 331 uint32_t firmware_options_1; 332 333 /* 334 * BIT 0 = Operation Mode bit 0 335 * BIT 1 = Operation Mode bit 1 336 * BIT 2 = Operation Mode bit 2 337 * BIT 3 = Operation Mode bit 3 338 * BIT 4 = Connection Options bit 0 339 * BIT 5 = Connection Options bit 1 340 * BIT 6 = Connection Options bit 2 341 * BIT 7 = Enable Non part on LIHA failure 342 * 343 * BIT 8 = Enable Class 2 344 * BIT 9 = Enable ACK0 345 * BIT 10 = Reserved 346 * BIT 11 = Enable FC-SP Security 347 * BIT 12 = FC Tape Enable 348 * BIT 13 = Reserved 349 * BIT 14 = Enable Target PRLI Control 350 * BIT 15-31 = Reserved 351 */ 352 uint32_t firmware_options_2; 353 354 /* 355 * BIT 0 = Reserved 356 * BIT 1 = Soft ID only 357 * BIT 2 = Reserved 358 * BIT 3 = Reserved 359 * BIT 4 = FCP RSP Payload bit 0 360 * BIT 5 = FCP RSP Payload bit 1 361 * BIT 6 = Enable Receive Out-of-Order data frame handling 362 * BIT 7 = Disable Automatic PLOGI on Local Loop 363 * 364 * BIT 8 = Reserved 365 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 366 * BIT 10 = Reserved 367 * BIT 11 = Reserved 368 * BIT 12 = Reserved 369 * BIT 13 = Data Rate bit 0 370 * BIT 14 = Data Rate bit 1 371 * BIT 15 = Data Rate bit 2 372 * BIT 16 = Enable 75 ohm Termination Select 373 * BIT 17-31 = Reserved 374 */ 375 uint32_t firmware_options_3; 376 uint16_t qos; 377 uint16_t rid; 378 uint8_t reserved_3[20]; 379 }; 380 381 /* 382 * ISP queue - command entry structure definition. 383 */ 384 #define COMMAND_BIDIRECTIONAL 0x75 385 struct cmd_bidir { 386 uint8_t entry_type; /* Entry type. */ 387 uint8_t entry_count; /* Entry count. */ 388 uint8_t sys_define; /* System defined */ 389 uint8_t entry_status; /* Entry status. */ 390 391 uint32_t handle; /* System handle. */ 392 393 uint16_t nport_handle; /* N_PORT hanlde. */ 394 395 uint16_t timeout; /* Commnad timeout. */ 396 397 uint16_t wr_dseg_count; /* Write Data segment count. */ 398 uint16_t rd_dseg_count; /* Read Data segment count. */ 399 400 struct scsi_lun lun; /* FCP LUN (BE). */ 401 402 uint16_t control_flags; /* Control flags. */ 403 #define BD_WRAP_BACK BIT_3 404 #define BD_READ_DATA BIT_1 405 #define BD_WRITE_DATA BIT_0 406 407 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 408 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 409 410 uint16_t reserved[2]; /* Reserved */ 411 412 uint32_t rd_byte_count; /* Total Byte count Read. */ 413 uint32_t wr_byte_count; /* Total Byte count write. */ 414 415 uint8_t port_id[3]; /* PortID of destination port.*/ 416 uint8_t vp_index; 417 418 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 419 uint16_t fcp_data_dseg_len; /* Data segment length. */ 420 }; 421 422 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */ 423 struct cmd_type_6 { 424 uint8_t entry_type; /* Entry type. */ 425 uint8_t entry_count; /* Entry count. */ 426 uint8_t sys_define; /* System defined. */ 427 uint8_t entry_status; /* Entry Status. */ 428 429 uint32_t handle; /* System handle. */ 430 431 uint16_t nport_handle; /* N_PORT handle. */ 432 uint16_t timeout; /* Command timeout. */ 433 434 uint16_t dseg_count; /* Data segment count. */ 435 436 uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */ 437 438 struct scsi_lun lun; /* FCP LUN (BE). */ 439 440 uint16_t control_flags; /* Control flags. */ 441 #define CF_DIF_SEG_DESCR_ENABLE BIT_3 442 #define CF_DATA_SEG_DESCR_ENABLE BIT_2 443 #define CF_READ_DATA BIT_1 444 #define CF_WRITE_DATA BIT_0 445 446 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 447 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 448 449 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 450 451 uint32_t byte_count; /* Total byte count. */ 452 453 uint8_t port_id[3]; /* PortID of destination port. */ 454 uint8_t vp_index; 455 456 uint32_t fcp_data_dseg_address[2]; /* Data segment address. */ 457 uint32_t fcp_data_dseg_len; /* Data segment length. */ 458 }; 459 460 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */ 461 struct cmd_type_7 { 462 uint8_t entry_type; /* Entry type. */ 463 uint8_t entry_count; /* Entry count. */ 464 uint8_t sys_define; /* System defined. */ 465 uint8_t entry_status; /* Entry Status. */ 466 467 uint32_t handle; /* System handle. */ 468 469 uint16_t nport_handle; /* N_PORT handle. */ 470 uint16_t timeout; /* Command timeout. */ 471 #define FW_MAX_TIMEOUT 0x1999 472 473 uint16_t dseg_count; /* Data segment count. */ 474 uint16_t reserved_1; 475 476 struct scsi_lun lun; /* FCP LUN (BE). */ 477 478 uint16_t task_mgmt_flags; /* Task management flags. */ 479 #define TMF_CLEAR_ACA BIT_14 480 #define TMF_TARGET_RESET BIT_13 481 #define TMF_LUN_RESET BIT_12 482 #define TMF_CLEAR_TASK_SET BIT_10 483 #define TMF_ABORT_TASK_SET BIT_9 484 #define TMF_DSD_LIST_ENABLE BIT_2 485 #define TMF_READ_DATA BIT_1 486 #define TMF_WRITE_DATA BIT_0 487 488 uint8_t task; 489 #define TSK_SIMPLE 0 490 #define TSK_HEAD_OF_QUEUE 1 491 #define TSK_ORDERED 2 492 #define TSK_ACA 4 493 #define TSK_UNTAGGED 5 494 495 uint8_t crn; 496 497 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 498 uint32_t byte_count; /* Total byte count. */ 499 500 uint8_t port_id[3]; /* PortID of destination port. */ 501 uint8_t vp_index; 502 503 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 504 uint32_t dseg_0_len; /* Data segment 0 length. */ 505 }; 506 507 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6) 508 * (T10-DIF) */ 509 struct cmd_type_crc_2 { 510 uint8_t entry_type; /* Entry type. */ 511 uint8_t entry_count; /* Entry count. */ 512 uint8_t sys_define; /* System defined. */ 513 uint8_t entry_status; /* Entry Status. */ 514 515 uint32_t handle; /* System handle. */ 516 517 uint16_t nport_handle; /* N_PORT handle. */ 518 uint16_t timeout; /* Command timeout. */ 519 520 uint16_t dseg_count; /* Data segment count. */ 521 522 uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */ 523 524 struct scsi_lun lun; /* FCP LUN (BE). */ 525 526 uint16_t control_flags; /* Control flags. */ 527 528 uint16_t fcp_cmnd_dseg_len; /* Data segment length. */ 529 uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */ 530 531 uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */ 532 533 uint32_t byte_count; /* Total byte count. */ 534 535 uint8_t port_id[3]; /* PortID of destination port. */ 536 uint8_t vp_index; 537 538 uint32_t crc_context_address[2]; /* Data segment address. */ 539 uint16_t crc_context_len; /* Data segment length. */ 540 uint16_t reserved_1; /* MUST be set to 0. */ 541 }; 542 543 544 /* 545 * ISP queue - status entry structure definition. 546 */ 547 #define STATUS_TYPE 0x03 /* Status entry. */ 548 struct sts_entry_24xx { 549 uint8_t entry_type; /* Entry type. */ 550 uint8_t entry_count; /* Entry count. */ 551 uint8_t sys_define; /* System defined. */ 552 uint8_t entry_status; /* Entry Status. */ 553 554 uint32_t handle; /* System handle. */ 555 556 uint16_t comp_status; /* Completion status. */ 557 uint16_t ox_id; /* OX_ID used by the firmware. */ 558 559 uint32_t residual_len; /* FW calc residual transfer length. */ 560 561 uint16_t reserved_1; 562 uint16_t state_flags; /* State flags. */ 563 #define SF_TRANSFERRED_DATA BIT_11 564 #define SF_FCP_RSP_DMA BIT_0 565 566 uint16_t reserved_2; 567 uint16_t scsi_status; /* SCSI status. */ 568 #define SS_CONFIRMATION_REQ BIT_12 569 570 uint32_t rsp_residual_count; /* FCP RSP residual count. */ 571 572 uint32_t sense_len; /* FCP SENSE length. */ 573 uint32_t rsp_data_len; /* FCP response data length. */ 574 uint8_t data[28]; /* FCP response/sense information. */ 575 /* 576 * If DIF Error is set in comp_status, these additional fields are 577 * defined: 578 * 579 * !!! NOTE: Firmware sends expected/actual DIF data in big endian 580 * format; but all of the "data" field gets swab32-d in the beginning 581 * of qla2x00_status_entry(). 582 * 583 * &data[10] : uint8_t report_runt_bg[2]; - computed guard 584 * &data[12] : uint8_t actual_dif[8]; - DIF Data received 585 * &data[20] : uint8_t expected_dif[8]; - DIF Data computed 586 */ 587 }; 588 589 590 /* 591 * Status entry completion status 592 */ 593 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */ 594 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */ 595 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */ 596 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */ 597 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */ 598 599 /* 600 * ISP queue - marker entry structure definition. 601 */ 602 #define MARKER_TYPE 0x04 /* Marker entry. */ 603 struct mrk_entry_24xx { 604 uint8_t entry_type; /* Entry type. */ 605 uint8_t entry_count; /* Entry count. */ 606 uint8_t handle_count; /* Handle count. */ 607 uint8_t entry_status; /* Entry Status. */ 608 609 uint32_t handle; /* System handle. */ 610 611 uint16_t nport_handle; /* N_PORT handle. */ 612 613 uint8_t modifier; /* Modifier (7-0). */ 614 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 615 #define MK_SYNC_ID 1 /* Synchronize ID */ 616 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 617 uint8_t reserved_1; 618 619 uint8_t reserved_2; 620 uint8_t vp_index; 621 622 uint16_t reserved_3; 623 624 uint8_t lun[8]; /* FCP LUN (BE). */ 625 uint8_t reserved_4[40]; 626 }; 627 628 /* 629 * ISP queue - CT Pass-Through entry structure definition. 630 */ 631 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */ 632 struct ct_entry_24xx { 633 uint8_t entry_type; /* Entry type. */ 634 uint8_t entry_count; /* Entry count. */ 635 uint8_t sys_define; /* System Defined. */ 636 uint8_t entry_status; /* Entry Status. */ 637 638 uint32_t handle; /* System handle. */ 639 640 uint16_t comp_status; /* Completion status. */ 641 642 uint16_t nport_handle; /* N_PORT handle. */ 643 644 uint16_t cmd_dsd_count; 645 646 uint8_t vp_index; 647 uint8_t reserved_1; 648 649 uint16_t timeout; /* Command timeout. */ 650 uint16_t reserved_2; 651 652 uint16_t rsp_dsd_count; 653 654 uint8_t reserved_3[10]; 655 656 uint32_t rsp_byte_count; 657 uint32_t cmd_byte_count; 658 659 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 660 uint32_t dseg_0_len; /* Data segment 0 length. */ 661 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 662 uint32_t dseg_1_len; /* Data segment 1 length. */ 663 }; 664 665 /* 666 * ISP queue - ELS Pass-Through entry structure definition. 667 */ 668 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */ 669 struct els_entry_24xx { 670 uint8_t entry_type; /* Entry type. */ 671 uint8_t entry_count; /* Entry count. */ 672 uint8_t sys_define; /* System Defined. */ 673 uint8_t entry_status; /* Entry Status. */ 674 675 uint32_t handle; /* System handle. */ 676 677 uint16_t reserved_1; 678 679 uint16_t nport_handle; /* N_PORT handle. */ 680 681 uint16_t tx_dsd_count; 682 683 uint8_t vp_index; 684 uint8_t sof_type; 685 #define EST_SOFI3 (1 << 4) 686 #define EST_SOFI2 (3 << 4) 687 688 uint32_t rx_xchg_address; /* Receive exchange address. */ 689 uint16_t rx_dsd_count; 690 691 uint8_t opcode; 692 uint8_t reserved_2; 693 694 uint8_t port_id[3]; 695 uint8_t reserved_3; 696 697 uint16_t reserved_4; 698 699 uint16_t control_flags; /* Control flags. */ 700 #define ECF_PAYLOAD_DESCR_MASK (BIT_15|BIT_14|BIT_13) 701 #define EPD_ELS_COMMAND (0 << 13) 702 #define EPD_ELS_ACC (1 << 13) 703 #define EPD_ELS_RJT (2 << 13) 704 #define EPD_RX_XCHG (3 << 13) 705 #define ECF_CLR_PASSTHRU_PEND BIT_12 706 #define ECF_INCL_FRAME_HDR BIT_11 707 708 uint32_t rx_byte_count; 709 uint32_t tx_byte_count; 710 711 uint32_t tx_address[2]; /* Data segment 0 address. */ 712 uint32_t tx_len; /* Data segment 0 length. */ 713 uint32_t rx_address[2]; /* Data segment 1 address. */ 714 uint32_t rx_len; /* Data segment 1 length. */ 715 }; 716 717 struct els_sts_entry_24xx { 718 uint8_t entry_type; /* Entry type. */ 719 uint8_t entry_count; /* Entry count. */ 720 uint8_t sys_define; /* System Defined. */ 721 uint8_t entry_status; /* Entry Status. */ 722 723 uint32_t handle; /* System handle. */ 724 725 uint16_t comp_status; 726 727 uint16_t nport_handle; /* N_PORT handle. */ 728 729 uint16_t reserved_1; 730 731 uint8_t vp_index; 732 uint8_t sof_type; 733 734 uint32_t rx_xchg_address; /* Receive exchange address. */ 735 uint16_t reserved_2; 736 737 uint8_t opcode; 738 uint8_t reserved_3; 739 740 uint8_t port_id[3]; 741 uint8_t reserved_4; 742 743 uint16_t reserved_5; 744 745 uint16_t control_flags; /* Control flags. */ 746 uint32_t total_byte_count; 747 uint32_t error_subcode_1; 748 uint32_t error_subcode_2; 749 }; 750 /* 751 * ISP queue - Mailbox Command entry structure definition. 752 */ 753 #define MBX_IOCB_TYPE 0x39 754 struct mbx_entry_24xx { 755 uint8_t entry_type; /* Entry type. */ 756 uint8_t entry_count; /* Entry count. */ 757 uint8_t handle_count; /* Handle count. */ 758 uint8_t entry_status; /* Entry Status. */ 759 760 uint32_t handle; /* System handle. */ 761 762 uint16_t mbx[28]; 763 }; 764 765 766 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */ 767 struct logio_entry_24xx { 768 uint8_t entry_type; /* Entry type. */ 769 uint8_t entry_count; /* Entry count. */ 770 uint8_t sys_define; /* System defined. */ 771 uint8_t entry_status; /* Entry Status. */ 772 773 uint32_t handle; /* System handle. */ 774 775 uint16_t comp_status; /* Completion status. */ 776 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */ 777 778 uint16_t nport_handle; /* N_PORT handle. */ 779 780 uint16_t control_flags; /* Control flags. */ 781 /* Modifiers. */ 782 #define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */ 783 #define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */ 784 #define LCF_CLASS_2 BIT_8 /* Enable class 2 during PLOGI. */ 785 #define LCF_FREE_NPORT BIT_7 /* Release NPORT handle after LOGO. */ 786 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */ 787 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */ 788 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */ 789 #define LCF_COND_PLOGI BIT_4 /* PLOGI only if not logged-in. */ 790 #define LCF_IMPL_LOGO BIT_4 /* Perform an implicit LOGO. */ 791 #define LCF_IMPL_PRLO BIT_4 /* Perform an implicit PRLO. */ 792 /* Commands. */ 793 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */ 794 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */ 795 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */ 796 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */ 797 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */ 798 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */ 799 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */ 800 801 uint8_t vp_index; 802 uint8_t reserved_1; 803 804 uint8_t port_id[3]; /* PortID of destination port. */ 805 806 uint8_t rsp_size; /* Response size in 32bit words. */ 807 808 uint32_t io_parameter[11]; /* General I/O parameters. */ 809 #define LSC_SCODE_NOLINK 0x01 810 #define LSC_SCODE_NOIOCB 0x02 811 #define LSC_SCODE_NOXCB 0x03 812 #define LSC_SCODE_CMD_FAILED 0x04 813 #define LSC_SCODE_NOFABRIC 0x05 814 #define LSC_SCODE_FW_NOT_READY 0x07 815 #define LSC_SCODE_NOT_LOGGED_IN 0x09 816 #define LSC_SCODE_NOPCB 0x0A 817 818 #define LSC_SCODE_ELS_REJECT 0x18 819 #define LSC_SCODE_CMD_PARAM_ERR 0x19 820 #define LSC_SCODE_PORTID_USED 0x1A 821 #define LSC_SCODE_NPORT_USED 0x1B 822 #define LSC_SCODE_NONPORT 0x1C 823 #define LSC_SCODE_LOGGED_IN 0x1D 824 #define LSC_SCODE_NOFLOGI_ACC 0x1F 825 }; 826 827 #define TSK_MGMT_IOCB_TYPE 0x14 828 struct tsk_mgmt_entry { 829 uint8_t entry_type; /* Entry type. */ 830 uint8_t entry_count; /* Entry count. */ 831 uint8_t handle_count; /* Handle count. */ 832 uint8_t entry_status; /* Entry Status. */ 833 834 uint32_t handle; /* System handle. */ 835 836 uint16_t nport_handle; /* N_PORT handle. */ 837 838 uint16_t reserved_1; 839 840 uint16_t delay; /* Activity delay in seconds. */ 841 842 uint16_t timeout; /* Command timeout. */ 843 844 struct scsi_lun lun; /* FCP LUN (BE). */ 845 846 uint32_t control_flags; /* Control Flags. */ 847 #define TCF_NOTMCMD_TO_TARGET BIT_31 848 #define TCF_LUN_RESET BIT_4 849 #define TCF_ABORT_TASK_SET BIT_3 850 #define TCF_CLEAR_TASK_SET BIT_2 851 #define TCF_TARGET_RESET BIT_1 852 #define TCF_CLEAR_ACA BIT_0 853 854 uint8_t reserved_2[20]; 855 856 uint8_t port_id[3]; /* PortID of destination port. */ 857 uint8_t vp_index; 858 859 uint8_t reserved_3[12]; 860 }; 861 862 #define ABORT_IOCB_TYPE 0x33 863 struct abort_entry_24xx { 864 uint8_t entry_type; /* Entry type. */ 865 uint8_t entry_count; /* Entry count. */ 866 uint8_t handle_count; /* Handle count. */ 867 uint8_t entry_status; /* Entry Status. */ 868 869 uint32_t handle; /* System handle. */ 870 871 uint16_t nport_handle; /* N_PORT handle. */ 872 /* or Completion status. */ 873 874 uint16_t options; /* Options. */ 875 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 876 877 uint32_t handle_to_abort; /* System handle to abort. */ 878 879 uint16_t req_que_no; 880 uint8_t reserved_1[30]; 881 882 uint8_t port_id[3]; /* PortID of destination port. */ 883 uint8_t vp_index; 884 885 uint8_t reserved_2[12]; 886 }; 887 888 /* 889 * ISP I/O Register Set structure definitions. 890 */ 891 struct device_reg_24xx { 892 uint32_t flash_addr; /* Flash/NVRAM BIOS address. */ 893 #define FARX_DATA_FLAG BIT_31 894 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 895 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 896 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000 897 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000 898 899 #define FA_NVRAM_FUNC0_ADDR 0x80 900 #define FA_NVRAM_FUNC1_ADDR 0x180 901 902 #define FA_NVRAM_VPD_SIZE 0x200 903 #define FA_NVRAM_VPD0_ADDR 0x00 904 #define FA_NVRAM_VPD1_ADDR 0x100 905 906 #define FA_BOOT_CODE_ADDR 0x00000 907 /* 908 * RISC code begins at offset 512KB 909 * within flash. Consisting of two 910 * contiguous RISC code segments. 911 */ 912 #define FA_RISC_CODE_ADDR 0x20000 913 #define FA_RISC_CODE_SEGMENTS 2 914 915 #define FA_FLASH_DESCR_ADDR_24 0x11000 916 #define FA_FLASH_LAYOUT_ADDR_24 0x11400 917 #define FA_NPIV_CONF0_ADDR_24 0x16000 918 #define FA_NPIV_CONF1_ADDR_24 0x17000 919 920 #define FA_FW_AREA_ADDR 0x40000 921 #define FA_VPD_NVRAM_ADDR 0x48000 922 #define FA_FEATURE_ADDR 0x4C000 923 #define FA_FLASH_DESCR_ADDR 0x50000 924 #define FA_FLASH_LAYOUT_ADDR 0x50400 925 #define FA_HW_EVENT0_ADDR 0x54000 926 #define FA_HW_EVENT1_ADDR 0x54400 927 #define FA_HW_EVENT_SIZE 0x200 928 #define FA_HW_EVENT_ENTRY_SIZE 4 929 #define FA_NPIV_CONF0_ADDR 0x5C000 930 #define FA_NPIV_CONF1_ADDR 0x5D000 931 #define FA_FCP_PRIO0_ADDR 0x10000 932 #define FA_FCP_PRIO1_ADDR 0x12000 933 934 /* 935 * Flash Error Log Event Codes. 936 */ 937 #define HW_EVENT_RESET_ERR 0xF00B 938 #define HW_EVENT_ISP_ERR 0xF020 939 #define HW_EVENT_PARITY_ERR 0xF022 940 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023 941 #define HW_EVENT_FLASH_FW_ERR 0xF024 942 943 uint32_t flash_data; /* Flash/NVRAM BIOS data. */ 944 945 uint32_t ctrl_status; /* Control/Status. */ 946 #define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */ 947 #define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */ 948 #define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */ 949 #define CSRX_FUNCTION BIT_15 /* Function number. */ 950 /* PCI-X Bus Mode. */ 951 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8) 952 #define PBM_PCI_33MHZ (0 << 8) 953 #define PBM_PCIX_M1_66MHZ (1 << 8) 954 #define PBM_PCIX_M1_100MHZ (2 << 8) 955 #define PBM_PCIX_M1_133MHZ (3 << 8) 956 #define PBM_PCIX_M2_66MHZ (5 << 8) 957 #define PBM_PCIX_M2_100MHZ (6 << 8) 958 #define PBM_PCIX_M2_133MHZ (7 << 8) 959 #define PBM_PCI_66MHZ (8 << 8) 960 /* Max Write Burst byte count. */ 961 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4) 962 #define MWB_512_BYTES (0 << 4) 963 #define MWB_1024_BYTES (1 << 4) 964 #define MWB_2048_BYTES (2 << 4) 965 #define MWB_4096_BYTES (3 << 4) 966 967 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */ 968 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */ 969 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 970 971 uint32_t ictrl; /* Interrupt control. */ 972 #define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */ 973 974 uint32_t istatus; /* Interrupt status. */ 975 #define ISRX_RISC_INT BIT_3 /* RISC interrupt. */ 976 977 uint32_t unused_1[2]; /* Gap. */ 978 979 /* Request Queue. */ 980 uint32_t req_q_in; /* In-Pointer. */ 981 uint32_t req_q_out; /* Out-Pointer. */ 982 /* Response Queue. */ 983 uint32_t rsp_q_in; /* In-Pointer. */ 984 uint32_t rsp_q_out; /* Out-Pointer. */ 985 /* Priority Request Queue. */ 986 uint32_t preq_q_in; /* In-Pointer. */ 987 uint32_t preq_q_out; /* Out-Pointer. */ 988 989 uint32_t unused_2[2]; /* Gap. */ 990 991 /* ATIO Queue. */ 992 uint32_t atio_q_in; /* In-Pointer. */ 993 uint32_t atio_q_out; /* Out-Pointer. */ 994 995 uint32_t host_status; 996 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ 997 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ 998 999 uint32_t hccr; /* Host command & control register. */ 1000 /* HCCR statuses. */ 1001 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */ 1002 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */ 1003 /* HCCR commands. */ 1004 /* NOOP. */ 1005 #define HCCRX_NOOP 0x00000000 1006 /* Set RISC Reset. */ 1007 #define HCCRX_SET_RISC_RESET 0x10000000 1008 /* Clear RISC Reset. */ 1009 #define HCCRX_CLR_RISC_RESET 0x20000000 1010 /* Set RISC Pause. */ 1011 #define HCCRX_SET_RISC_PAUSE 0x30000000 1012 /* Releases RISC Pause. */ 1013 #define HCCRX_REL_RISC_PAUSE 0x40000000 1014 /* Set HOST to RISC interrupt. */ 1015 #define HCCRX_SET_HOST_INT 0x50000000 1016 /* Clear HOST to RISC interrupt. */ 1017 #define HCCRX_CLR_HOST_INT 0x60000000 1018 /* Clear RISC to PCI interrupt. */ 1019 #define HCCRX_CLR_RISC_INT 0xA0000000 1020 1021 uint32_t gpiod; /* GPIO Data register. */ 1022 1023 /* LED update mask. */ 1024 #define GPDX_LED_UPDATE_MASK (BIT_20|BIT_19|BIT_18) 1025 /* Data update mask. */ 1026 #define GPDX_DATA_UPDATE_MASK (BIT_17|BIT_16) 1027 /* Data update mask. */ 1028 #define GPDX_DATA_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1029 /* LED control mask. */ 1030 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2) 1031 /* LED bit values. Color names as 1032 * referenced in fw spec. 1033 */ 1034 #define GPDX_LED_YELLOW_ON BIT_2 1035 #define GPDX_LED_GREEN_ON BIT_3 1036 #define GPDX_LED_AMBER_ON BIT_4 1037 /* Data in/out. */ 1038 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1039 1040 uint32_t gpioe; /* GPIO Enable register. */ 1041 /* Enable update mask. */ 1042 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16) 1043 /* Enable update mask. */ 1044 #define GPEX_ENABLE_UPDATE_2_MASK (BIT_28|BIT_27|BIT_26|BIT_17|BIT_16) 1045 /* Enable. */ 1046 #define GPEX_ENABLE (BIT_1|BIT_0) 1047 1048 uint32_t iobase_addr; /* I/O Bus Base Address register. */ 1049 1050 uint32_t unused_3[10]; /* Gap. */ 1051 1052 uint16_t mailbox0; 1053 uint16_t mailbox1; 1054 uint16_t mailbox2; 1055 uint16_t mailbox3; 1056 uint16_t mailbox4; 1057 uint16_t mailbox5; 1058 uint16_t mailbox6; 1059 uint16_t mailbox7; 1060 uint16_t mailbox8; 1061 uint16_t mailbox9; 1062 uint16_t mailbox10; 1063 uint16_t mailbox11; 1064 uint16_t mailbox12; 1065 uint16_t mailbox13; 1066 uint16_t mailbox14; 1067 uint16_t mailbox15; 1068 uint16_t mailbox16; 1069 uint16_t mailbox17; 1070 uint16_t mailbox18; 1071 uint16_t mailbox19; 1072 uint16_t mailbox20; 1073 uint16_t mailbox21; 1074 uint16_t mailbox22; 1075 uint16_t mailbox23; 1076 uint16_t mailbox24; 1077 uint16_t mailbox25; 1078 uint16_t mailbox26; 1079 uint16_t mailbox27; 1080 uint16_t mailbox28; 1081 uint16_t mailbox29; 1082 uint16_t mailbox30; 1083 uint16_t mailbox31; 1084 1085 uint32_t iobase_window; 1086 uint32_t iobase_c4; 1087 uint32_t iobase_c8; 1088 uint32_t unused_4_1[6]; /* Gap. */ 1089 uint32_t iobase_q; 1090 uint32_t unused_5[2]; /* Gap. */ 1091 uint32_t iobase_select; 1092 uint32_t unused_6[2]; /* Gap. */ 1093 uint32_t iobase_sdata; 1094 }; 1095 1096 /* Trace Control *************************************************************/ 1097 1098 #define TC_AEN_DISABLE 0 1099 1100 #define TC_EFT_ENABLE 4 1101 #define TC_EFT_DISABLE 5 1102 1103 #define TC_FCE_ENABLE 8 1104 #define TC_FCE_OPTIONS 0 1105 #define TC_FCE_DEFAULT_RX_SIZE 2112 1106 #define TC_FCE_DEFAULT_TX_SIZE 2112 1107 #define TC_FCE_DISABLE 9 1108 #define TC_FCE_DISABLE_TRACE BIT_0 1109 1110 /* MID Support ***************************************************************/ 1111 1112 #define MIN_MULTI_ID_FABRIC 64 /* Must be power-of-2. */ 1113 #define MAX_MULTI_ID_FABRIC 256 /* ... */ 1114 1115 #define for_each_mapped_vp_idx(_ha, _idx) \ 1116 for (_idx = find_next_bit((_ha)->vp_idx_map, \ 1117 (_ha)->max_npiv_vports + 1, 1); \ 1118 _idx <= (_ha)->max_npiv_vports; \ 1119 _idx = find_next_bit((_ha)->vp_idx_map, \ 1120 (_ha)->max_npiv_vports + 1, _idx + 1)) \ 1121 1122 struct mid_conf_entry_24xx { 1123 uint16_t reserved_1; 1124 1125 /* 1126 * BIT 0 = Enable Hard Loop Id 1127 * BIT 1 = Acquire Loop ID in LIPA 1128 * BIT 2 = ID not Acquired 1129 * BIT 3 = Enable VP 1130 * BIT 4 = Enable Initiator Mode 1131 * BIT 5 = Disable Target Mode 1132 * BIT 6-7 = Reserved 1133 */ 1134 uint8_t options; 1135 1136 uint8_t hard_address; 1137 1138 uint8_t port_name[WWN_SIZE]; 1139 uint8_t node_name[WWN_SIZE]; 1140 }; 1141 1142 struct mid_init_cb_24xx { 1143 struct init_cb_24xx init_cb; 1144 1145 uint16_t count; 1146 uint16_t options; 1147 1148 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1149 }; 1150 1151 1152 struct mid_db_entry_24xx { 1153 uint16_t status; 1154 #define MDBS_NON_PARTIC BIT_3 1155 #define MDBS_ID_ACQUIRED BIT_1 1156 #define MDBS_ENABLED BIT_0 1157 1158 uint8_t options; 1159 uint8_t hard_address; 1160 1161 uint8_t port_name[WWN_SIZE]; 1162 uint8_t node_name[WWN_SIZE]; 1163 1164 uint8_t port_id[3]; 1165 uint8_t reserved_1; 1166 }; 1167 1168 /* 1169 * Virtual Port Control IOCB 1170 */ 1171 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */ 1172 struct vp_ctrl_entry_24xx { 1173 uint8_t entry_type; /* Entry type. */ 1174 uint8_t entry_count; /* Entry count. */ 1175 uint8_t sys_define; /* System defined. */ 1176 uint8_t entry_status; /* Entry Status. */ 1177 1178 uint32_t handle; /* System handle. */ 1179 1180 uint16_t vp_idx_failed; 1181 1182 uint16_t comp_status; /* Completion status. */ 1183 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */ 1184 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */ 1185 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1186 1187 uint16_t command; 1188 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */ 1189 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */ 1190 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */ 1191 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */ 1192 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */ 1193 1194 uint16_t vp_count; 1195 1196 uint8_t vp_idx_map[16]; 1197 uint16_t flags; 1198 uint16_t id; 1199 uint16_t reserved_4; 1200 uint16_t hopct; 1201 uint8_t reserved_5[24]; 1202 }; 1203 1204 /* 1205 * Modify Virtual Port Configuration IOCB 1206 */ 1207 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */ 1208 struct vp_config_entry_24xx { 1209 uint8_t entry_type; /* Entry type. */ 1210 uint8_t entry_count; /* Entry count. */ 1211 uint8_t handle_count; 1212 uint8_t entry_status; /* Entry Status. */ 1213 1214 uint32_t handle; /* System handle. */ 1215 1216 uint16_t flags; 1217 #define CS_VF_BIND_VPORTS_TO_VF BIT_0 1218 #define CS_VF_SET_QOS_OF_VPORTS BIT_1 1219 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2 1220 1221 uint16_t comp_status; /* Completion status. */ 1222 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */ 1223 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */ 1224 #define CS_VCT_ERROR 0x03 /* Unknown error. */ 1225 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */ 1226 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */ 1227 1228 uint8_t command; 1229 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */ 1230 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */ 1231 1232 uint8_t vp_count; 1233 1234 uint8_t vp_index1; 1235 uint8_t vp_index2; 1236 1237 uint8_t options_idx1; 1238 uint8_t hard_address_idx1; 1239 uint16_t reserved_vp1; 1240 uint8_t port_name_idx1[WWN_SIZE]; 1241 uint8_t node_name_idx1[WWN_SIZE]; 1242 1243 uint8_t options_idx2; 1244 uint8_t hard_address_idx2; 1245 uint16_t reserved_vp2; 1246 uint8_t port_name_idx2[WWN_SIZE]; 1247 uint8_t node_name_idx2[WWN_SIZE]; 1248 uint16_t id; 1249 uint16_t reserved_4; 1250 uint16_t hopct; 1251 uint8_t reserved_5[2]; 1252 }; 1253 1254 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */ 1255 struct vp_rpt_id_entry_24xx { 1256 uint8_t entry_type; /* Entry type. */ 1257 uint8_t entry_count; /* Entry count. */ 1258 uint8_t sys_define; /* System defined. */ 1259 uint8_t entry_status; /* Entry Status. */ 1260 1261 uint32_t handle; /* System handle. */ 1262 1263 uint16_t vp_count; /* Format 0 -- | VP setup | VP acq |. */ 1264 /* Format 1 -- | VP count |. */ 1265 uint16_t vp_idx; /* Format 0 -- Reserved. */ 1266 /* Format 1 -- VP status and index. */ 1267 1268 uint8_t port_id[3]; 1269 uint8_t format; 1270 1271 uint8_t vp_idx_map[16]; 1272 1273 uint8_t reserved_4[32]; 1274 }; 1275 1276 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */ 1277 struct vf_evfp_entry_24xx { 1278 uint8_t entry_type; /* Entry type. */ 1279 uint8_t entry_count; /* Entry count. */ 1280 uint8_t sys_define; /* System defined. */ 1281 uint8_t entry_status; /* Entry Status. */ 1282 1283 uint32_t handle; /* System handle. */ 1284 uint16_t comp_status; /* Completion status. */ 1285 uint16_t timeout; /* timeout */ 1286 uint16_t adim_tagging_mode; 1287 1288 uint16_t vfport_id; 1289 uint32_t exch_addr; 1290 1291 uint16_t nport_handle; /* N_PORT handle. */ 1292 uint16_t control_flags; 1293 uint32_t io_parameter_0; 1294 uint32_t io_parameter_1; 1295 uint32_t tx_address[2]; /* Data segment 0 address. */ 1296 uint32_t tx_len; /* Data segment 0 length. */ 1297 uint32_t rx_address[2]; /* Data segment 1 address. */ 1298 uint32_t rx_len; /* Data segment 1 length. */ 1299 }; 1300 1301 /* END MID Support ***********************************************************/ 1302 1303 /* Flash Description Table ***************************************************/ 1304 1305 struct qla_fdt_layout { 1306 uint8_t sig[4]; 1307 uint16_t version; 1308 uint16_t len; 1309 uint16_t checksum; 1310 uint8_t unused1[2]; 1311 uint8_t model[16]; 1312 uint16_t man_id; 1313 uint16_t id; 1314 uint8_t flags; 1315 uint8_t erase_cmd; 1316 uint8_t alt_erase_cmd; 1317 uint8_t wrt_enable_cmd; 1318 uint8_t wrt_enable_bits; 1319 uint8_t wrt_sts_reg_cmd; 1320 uint8_t unprotect_sec_cmd; 1321 uint8_t read_man_id_cmd; 1322 uint32_t block_size; 1323 uint32_t alt_block_size; 1324 uint32_t flash_size; 1325 uint32_t wrt_enable_data; 1326 uint8_t read_id_addr_len; 1327 uint8_t wrt_disable_bits; 1328 uint8_t read_dev_id_len; 1329 uint8_t chip_erase_cmd; 1330 uint16_t read_timeout; 1331 uint8_t protect_sec_cmd; 1332 uint8_t unused2[65]; 1333 }; 1334 1335 /* Flash Layout Table ********************************************************/ 1336 1337 struct qla_flt_location { 1338 uint8_t sig[4]; 1339 uint16_t start_lo; 1340 uint16_t start_hi; 1341 uint8_t version; 1342 uint8_t unused[5]; 1343 uint16_t checksum; 1344 }; 1345 1346 struct qla_flt_header { 1347 uint16_t version; 1348 uint16_t length; 1349 uint16_t checksum; 1350 uint16_t unused; 1351 }; 1352 1353 #define FLT_REG_FW 0x01 1354 #define FLT_REG_BOOT_CODE 0x07 1355 #define FLT_REG_VPD_0 0x14 1356 #define FLT_REG_NVRAM_0 0x15 1357 #define FLT_REG_VPD_1 0x16 1358 #define FLT_REG_NVRAM_1 0x17 1359 #define FLT_REG_FDT 0x1a 1360 #define FLT_REG_FLT 0x1c 1361 #define FLT_REG_HW_EVENT_0 0x1d 1362 #define FLT_REG_HW_EVENT_1 0x1f 1363 #define FLT_REG_NPIV_CONF_0 0x29 1364 #define FLT_REG_NPIV_CONF_1 0x2a 1365 #define FLT_REG_GOLD_FW 0x2f 1366 #define FLT_REG_FCP_PRIO_0 0x87 1367 #define FLT_REG_FCP_PRIO_1 0x88 1368 #define FLT_REG_FCOE_FW 0xA4 1369 #define FLT_REG_FCOE_VPD_0 0xA9 1370 #define FLT_REG_FCOE_NVRAM_0 0xAA 1371 #define FLT_REG_FCOE_VPD_1 0xAB 1372 #define FLT_REG_FCOE_NVRAM_1 0xAC 1373 1374 struct qla_flt_region { 1375 uint32_t code; 1376 uint32_t size; 1377 uint32_t start; 1378 uint32_t end; 1379 }; 1380 1381 /* Flash NPIV Configuration Table ********************************************/ 1382 1383 struct qla_npiv_header { 1384 uint8_t sig[2]; 1385 uint16_t version; 1386 uint16_t entries; 1387 uint16_t unused[4]; 1388 uint16_t checksum; 1389 }; 1390 1391 struct qla_npiv_entry { 1392 uint16_t flags; 1393 uint16_t vf_id; 1394 uint8_t q_qos; 1395 uint8_t f_qos; 1396 uint16_t unused1; 1397 uint8_t port_name[WWN_SIZE]; 1398 uint8_t node_name[WWN_SIZE]; 1399 }; 1400 1401 /* 84XX Support **************************************************************/ 1402 1403 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */ 1404 #define A84_PANIC_RECOVERY 0x1 1405 #define A84_OP_LOGIN_COMPLETE 0x2 1406 #define A84_DIAG_LOGIN_COMPLETE 0x3 1407 #define A84_GOLD_LOGIN_COMPLETE 0x4 1408 1409 #define MBC_ISP84XX_RESET 0x3a /* Reset. */ 1410 1411 #define FSTATE_REMOTE_FC_DOWN BIT_0 1412 #define FSTATE_NSL_LINK_DOWN BIT_1 1413 #define FSTATE_IS_DIAG_FW BIT_2 1414 #define FSTATE_LOGGED_IN BIT_3 1415 #define FSTATE_WAITING_FOR_VERIFY BIT_4 1416 1417 #define VERIFY_CHIP_IOCB_TYPE 0x1B 1418 struct verify_chip_entry_84xx { 1419 uint8_t entry_type; 1420 uint8_t entry_count; 1421 uint8_t sys_defined; 1422 uint8_t entry_status; 1423 1424 uint32_t handle; 1425 1426 uint16_t options; 1427 #define VCO_DONT_UPDATE_FW BIT_0 1428 #define VCO_FORCE_UPDATE BIT_1 1429 #define VCO_DONT_RESET_UPDATE BIT_2 1430 #define VCO_DIAG_FW BIT_3 1431 #define VCO_END_OF_DATA BIT_14 1432 #define VCO_ENABLE_DSD BIT_15 1433 1434 uint16_t reserved_1; 1435 1436 uint16_t data_seg_cnt; 1437 uint16_t reserved_2[3]; 1438 1439 uint32_t fw_ver; 1440 uint32_t exchange_address; 1441 1442 uint32_t reserved_3[3]; 1443 uint32_t fw_size; 1444 uint32_t fw_seq_size; 1445 uint32_t relative_offset; 1446 1447 uint32_t dseg_address[2]; 1448 uint32_t dseg_length; 1449 }; 1450 1451 struct verify_chip_rsp_84xx { 1452 uint8_t entry_type; 1453 uint8_t entry_count; 1454 uint8_t sys_defined; 1455 uint8_t entry_status; 1456 1457 uint32_t handle; 1458 1459 uint16_t comp_status; 1460 #define CS_VCS_CHIP_FAILURE 0x3 1461 #define CS_VCS_BAD_EXCHANGE 0x8 1462 #define CS_VCS_SEQ_COMPLETEi 0x40 1463 1464 uint16_t failure_code; 1465 #define VFC_CHECKSUM_ERROR 0x1 1466 #define VFC_INVALID_LEN 0x2 1467 #define VFC_ALREADY_IN_PROGRESS 0x8 1468 1469 uint16_t reserved_1[4]; 1470 1471 uint32_t fw_ver; 1472 uint32_t exchange_address; 1473 1474 uint32_t reserved_2[6]; 1475 }; 1476 1477 #define ACCESS_CHIP_IOCB_TYPE 0x2B 1478 struct access_chip_84xx { 1479 uint8_t entry_type; 1480 uint8_t entry_count; 1481 uint8_t sys_defined; 1482 uint8_t entry_status; 1483 1484 uint32_t handle; 1485 1486 uint16_t options; 1487 #define ACO_DUMP_MEMORY 0x0 1488 #define ACO_LOAD_MEMORY 0x1 1489 #define ACO_CHANGE_CONFIG_PARAM 0x2 1490 #define ACO_REQUEST_INFO 0x3 1491 1492 uint16_t reserved1; 1493 1494 uint16_t dseg_count; 1495 uint16_t reserved2[3]; 1496 1497 uint32_t parameter1; 1498 uint32_t parameter2; 1499 uint32_t parameter3; 1500 1501 uint32_t reserved3[3]; 1502 uint32_t total_byte_cnt; 1503 uint32_t reserved4; 1504 1505 uint32_t dseg_address[2]; 1506 uint32_t dseg_length; 1507 }; 1508 1509 struct access_chip_rsp_84xx { 1510 uint8_t entry_type; 1511 uint8_t entry_count; 1512 uint8_t sys_defined; 1513 uint8_t entry_status; 1514 1515 uint32_t handle; 1516 1517 uint16_t comp_status; 1518 uint16_t failure_code; 1519 uint32_t residual_count; 1520 1521 uint32_t reserved[12]; 1522 }; 1523 1524 /* 81XX Support **************************************************************/ 1525 1526 #define MBA_DCBX_START 0x8016 1527 #define MBA_DCBX_COMPLETE 0x8030 1528 #define MBA_FCF_CONF_ERR 0x8031 1529 #define MBA_DCBX_PARAM_UPDATE 0x8032 1530 #define MBA_IDC_COMPLETE 0x8100 1531 #define MBA_IDC_NOTIFY 0x8101 1532 #define MBA_IDC_TIME_EXT 0x8102 1533 1534 #define MBC_IDC_ACK 0x101 1535 #define MBC_RESTART_MPI_FW 0x3d 1536 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */ 1537 #define MBC_GET_XGMAC_STATS 0x7a 1538 #define MBC_GET_DCBX_PARAMS 0x51 1539 1540 /* 1541 * ISP83xx mailbox commands 1542 */ 1543 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */ 1544 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */ 1545 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */ 1546 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */ 1547 1548 /* Flash access control option field bit definitions */ 1549 #define FAC_OPT_FORCE_SEMAPHORE BIT_15 1550 #define FAC_OPT_REQUESTOR_ID BIT_14 1551 #define FAC_OPT_CMD_SUBCODE 0xff 1552 1553 /* Flash access control command subcodes */ 1554 #define FAC_OPT_CMD_WRITE_PROTECT 0x00 1555 #define FAC_OPT_CMD_WRITE_ENABLE 0x01 1556 #define FAC_OPT_CMD_ERASE_SECTOR 0x02 1557 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03 1558 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04 1559 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05 1560 1561 struct nvram_81xx { 1562 /* NVRAM header. */ 1563 uint8_t id[4]; 1564 uint16_t nvram_version; 1565 uint16_t reserved_0; 1566 1567 /* Firmware Initialization Control Block. */ 1568 uint16_t version; 1569 uint16_t reserved_1; 1570 uint16_t frame_payload_size; 1571 uint16_t execution_throttle; 1572 uint16_t exchange_count; 1573 uint16_t reserved_2; 1574 1575 uint8_t port_name[WWN_SIZE]; 1576 uint8_t node_name[WWN_SIZE]; 1577 1578 uint16_t login_retry_count; 1579 uint16_t reserved_3; 1580 uint16_t interrupt_delay_timer; 1581 uint16_t login_timeout; 1582 1583 uint32_t firmware_options_1; 1584 uint32_t firmware_options_2; 1585 uint32_t firmware_options_3; 1586 1587 uint16_t reserved_4[4]; 1588 1589 /* Offset 64. */ 1590 uint8_t enode_mac[6]; 1591 uint16_t reserved_5[5]; 1592 1593 /* Offset 80. */ 1594 uint16_t reserved_6[24]; 1595 1596 /* Offset 128. */ 1597 uint16_t ex_version; 1598 uint8_t prio_fcf_matching_flags; 1599 uint8_t reserved_6_1[3]; 1600 uint16_t pri_fcf_vlan_id; 1601 uint8_t pri_fcf_fabric_name[8]; 1602 uint16_t reserved_6_2[7]; 1603 uint8_t spma_mac_addr[6]; 1604 uint16_t reserved_6_3[14]; 1605 1606 /* Offset 192. */ 1607 uint16_t reserved_7[32]; 1608 1609 /* 1610 * BIT 0 = Enable spinup delay 1611 * BIT 1 = Disable BIOS 1612 * BIT 2 = Enable Memory Map BIOS 1613 * BIT 3 = Enable Selectable Boot 1614 * BIT 4 = Disable RISC code load 1615 * BIT 5 = Disable Serdes 1616 * BIT 6 = Opt boot mode 1617 * BIT 7 = Interrupt enable 1618 * 1619 * BIT 8 = EV Control enable 1620 * BIT 9 = Enable lip reset 1621 * BIT 10 = Enable lip full login 1622 * BIT 11 = Enable target reset 1623 * BIT 12 = Stop firmware 1624 * BIT 13 = Enable nodename option 1625 * BIT 14 = Default WWPN valid 1626 * BIT 15 = Enable alternate WWN 1627 * 1628 * BIT 16 = CLP LUN string 1629 * BIT 17 = CLP Target string 1630 * BIT 18 = CLP BIOS enable string 1631 * BIT 19 = CLP Serdes string 1632 * BIT 20 = CLP WWPN string 1633 * BIT 21 = CLP WWNN string 1634 * BIT 22 = 1635 * BIT 23 = 1636 * BIT 24 = Keep WWPN 1637 * BIT 25 = Temp WWPN 1638 * BIT 26-31 = 1639 */ 1640 uint32_t host_p; 1641 1642 uint8_t alternate_port_name[WWN_SIZE]; 1643 uint8_t alternate_node_name[WWN_SIZE]; 1644 1645 uint8_t boot_port_name[WWN_SIZE]; 1646 uint16_t boot_lun_number; 1647 uint16_t reserved_8; 1648 1649 uint8_t alt1_boot_port_name[WWN_SIZE]; 1650 uint16_t alt1_boot_lun_number; 1651 uint16_t reserved_9; 1652 1653 uint8_t alt2_boot_port_name[WWN_SIZE]; 1654 uint16_t alt2_boot_lun_number; 1655 uint16_t reserved_10; 1656 1657 uint8_t alt3_boot_port_name[WWN_SIZE]; 1658 uint16_t alt3_boot_lun_number; 1659 uint16_t reserved_11; 1660 1661 /* 1662 * BIT 0 = Selective Login 1663 * BIT 1 = Alt-Boot Enable 1664 * BIT 2 = Reserved 1665 * BIT 3 = Boot Order List 1666 * BIT 4 = Reserved 1667 * BIT 5 = Selective LUN 1668 * BIT 6 = Reserved 1669 * BIT 7-31 = 1670 */ 1671 uint32_t efi_parameters; 1672 1673 uint8_t reset_delay; 1674 uint8_t reserved_12; 1675 uint16_t reserved_13; 1676 1677 uint16_t boot_id_number; 1678 uint16_t reserved_14; 1679 1680 uint16_t max_luns_per_target; 1681 uint16_t reserved_15; 1682 1683 uint16_t port_down_retry_count; 1684 uint16_t link_down_timeout; 1685 1686 /* FCode parameters. */ 1687 uint16_t fcode_parameter; 1688 1689 uint16_t reserved_16[3]; 1690 1691 /* Offset 352. */ 1692 uint8_t reserved_17[4]; 1693 uint16_t reserved_18[5]; 1694 uint8_t reserved_19[2]; 1695 uint16_t reserved_20[8]; 1696 1697 /* Offset 384. */ 1698 uint8_t reserved_21[16]; 1699 uint16_t reserved_22[3]; 1700 1701 /* 1702 * BIT 0 = Extended BB credits for LR 1703 * BIT 1 = Virtual Fabric Enable 1704 * BIT 2 = Enhanced Features Unused 1705 * BIT 3-7 = Enhanced Features Reserved 1706 */ 1707 /* Enhanced Features */ 1708 uint8_t enhanced_features; 1709 1710 uint8_t reserved_23; 1711 uint16_t reserved_24[4]; 1712 1713 /* Offset 416. */ 1714 uint16_t reserved_25[32]; 1715 1716 /* Offset 480. */ 1717 uint8_t model_name[16]; 1718 1719 /* Offset 496. */ 1720 uint16_t feature_mask_l; 1721 uint16_t feature_mask_h; 1722 uint16_t reserved_26[2]; 1723 1724 uint16_t subsystem_vendor_id; 1725 uint16_t subsystem_device_id; 1726 1727 uint32_t checksum; 1728 }; 1729 1730 /* 1731 * ISP Initialization Control Block. 1732 * Little endian except where noted. 1733 */ 1734 #define ICB_VERSION 1 1735 struct init_cb_81xx { 1736 uint16_t version; 1737 uint16_t reserved_1; 1738 1739 uint16_t frame_payload_size; 1740 uint16_t execution_throttle; 1741 uint16_t exchange_count; 1742 1743 uint16_t reserved_2; 1744 1745 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1746 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1747 1748 uint16_t response_q_inpointer; 1749 uint16_t request_q_outpointer; 1750 1751 uint16_t login_retry_count; 1752 1753 uint16_t prio_request_q_outpointer; 1754 1755 uint16_t response_q_length; 1756 uint16_t request_q_length; 1757 1758 uint16_t reserved_3; 1759 1760 uint16_t prio_request_q_length; 1761 1762 uint32_t request_q_address[2]; 1763 uint32_t response_q_address[2]; 1764 uint32_t prio_request_q_address[2]; 1765 1766 uint8_t reserved_4[8]; 1767 1768 uint16_t atio_q_inpointer; 1769 uint16_t atio_q_length; 1770 uint32_t atio_q_address[2]; 1771 1772 uint16_t interrupt_delay_timer; /* 100us increments. */ 1773 uint16_t login_timeout; 1774 1775 /* 1776 * BIT 0-3 = Reserved 1777 * BIT 4 = Enable Target Mode 1778 * BIT 5 = Disable Initiator Mode 1779 * BIT 6 = Reserved 1780 * BIT 7 = Reserved 1781 * 1782 * BIT 8-13 = Reserved 1783 * BIT 14 = Node Name Option 1784 * BIT 15-31 = Reserved 1785 */ 1786 uint32_t firmware_options_1; 1787 1788 /* 1789 * BIT 0 = Operation Mode bit 0 1790 * BIT 1 = Operation Mode bit 1 1791 * BIT 2 = Operation Mode bit 2 1792 * BIT 3 = Operation Mode bit 3 1793 * BIT 4-7 = Reserved 1794 * 1795 * BIT 8 = Enable Class 2 1796 * BIT 9 = Enable ACK0 1797 * BIT 10 = Reserved 1798 * BIT 11 = Enable FC-SP Security 1799 * BIT 12 = FC Tape Enable 1800 * BIT 13 = Reserved 1801 * BIT 14 = Enable Target PRLI Control 1802 * BIT 15-31 = Reserved 1803 */ 1804 uint32_t firmware_options_2; 1805 1806 /* 1807 * BIT 0-3 = Reserved 1808 * BIT 4 = FCP RSP Payload bit 0 1809 * BIT 5 = FCP RSP Payload bit 1 1810 * BIT 6 = Enable Receive Out-of-Order data frame handling 1811 * BIT 7 = Reserved 1812 * 1813 * BIT 8 = Reserved 1814 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative offset handling 1815 * BIT 10-16 = Reserved 1816 * BIT 17 = Enable multiple FCFs 1817 * BIT 18-20 = MAC addressing mode 1818 * BIT 21-25 = Ethernet data rate 1819 * BIT 26 = Enable ethernet header rx IOCB for ATIO q 1820 * BIT 27 = Enable ethernet header rx IOCB for response q 1821 * BIT 28 = SPMA selection bit 0 1822 * BIT 28 = SPMA selection bit 1 1823 * BIT 30-31 = Reserved 1824 */ 1825 uint32_t firmware_options_3; 1826 1827 uint8_t reserved_5[8]; 1828 1829 uint8_t enode_mac[6]; 1830 1831 uint8_t reserved_6[10]; 1832 }; 1833 1834 struct mid_init_cb_81xx { 1835 struct init_cb_81xx init_cb; 1836 1837 uint16_t count; 1838 uint16_t options; 1839 1840 struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC]; 1841 }; 1842 1843 struct ex_init_cb_81xx { 1844 uint16_t ex_version; 1845 uint8_t prio_fcf_matching_flags; 1846 uint8_t reserved_1[3]; 1847 uint16_t pri_fcf_vlan_id; 1848 uint8_t pri_fcf_fabric_name[8]; 1849 uint16_t reserved_2[7]; 1850 uint8_t spma_mac_addr[6]; 1851 uint16_t reserved_3[14]; 1852 }; 1853 1854 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000 1855 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000 1856 1857 /* FCP priority config defines *************************************/ 1858 /* operations */ 1859 #define QLFC_FCP_PRIO_DISABLE 0x0 1860 #define QLFC_FCP_PRIO_ENABLE 0x1 1861 #define QLFC_FCP_PRIO_GET_CONFIG 0x2 1862 #define QLFC_FCP_PRIO_SET_CONFIG 0x3 1863 1864 struct qla_fcp_prio_entry { 1865 uint16_t flags; /* Describes parameter(s) in FCP */ 1866 /* priority entry that are valid */ 1867 #define FCP_PRIO_ENTRY_VALID 0x1 1868 #define FCP_PRIO_ENTRY_TAG_VALID 0x2 1869 #define FCP_PRIO_ENTRY_SPID_VALID 0x4 1870 #define FCP_PRIO_ENTRY_DPID_VALID 0x8 1871 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10 1872 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20 1873 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40 1874 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80 1875 uint8_t tag; /* Priority value */ 1876 uint8_t reserved; /* Reserved for future use */ 1877 uint32_t src_pid; /* Src port id. high order byte */ 1878 /* unused; -1 (wild card) */ 1879 uint32_t dst_pid; /* Src port id. high order byte */ 1880 /* unused; -1 (wild card) */ 1881 uint16_t lun_beg; /* 1st lun num of lun range. */ 1882 /* -1 (wild card) */ 1883 uint16_t lun_end; /* 2nd lun num of lun range. */ 1884 /* -1 (wild card) */ 1885 uint8_t src_wwpn[8]; /* Source WWPN: -1 (wild card) */ 1886 uint8_t dst_wwpn[8]; /* Destination WWPN: -1 (wild card) */ 1887 }; 1888 1889 struct qla_fcp_prio_cfg { 1890 uint8_t signature[4]; /* "HQOS" signature of config data */ 1891 uint16_t version; /* 1: Initial version */ 1892 uint16_t length; /* config data size in num bytes */ 1893 uint16_t checksum; /* config data bytes checksum */ 1894 uint16_t num_entries; /* Number of entries */ 1895 uint16_t size_of_entry; /* Size of each entry in num bytes */ 1896 uint8_t attributes; /* enable/disable, persistence */ 1897 #define FCP_PRIO_ATTR_DISABLE 0x0 1898 #define FCP_PRIO_ATTR_ENABLE 0x1 1899 #define FCP_PRIO_ATTR_PERSIST 0x2 1900 uint8_t reserved; /* Reserved for future use */ 1901 #define FCP_PRIO_CFG_HDR_SIZE 0x10 1902 struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */ 1903 #define FCP_PRIO_CFG_ENTRY_SIZE 0x20 1904 }; 1905 1906 #define FCP_PRIO_CFG_SIZE (32*1024) /* fcp prio data per port*/ 1907 1908 /* 25XX Support ****************************************************/ 1909 #define FA_FCP_PRIO0_ADDR_25 0x3C000 1910 #define FA_FCP_PRIO1_ADDR_25 0x3E000 1911 1912 /* 81XX Flash locations -- occupies second 2MB region. */ 1913 #define FA_BOOT_CODE_ADDR_81 0x80000 1914 #define FA_RISC_CODE_ADDR_81 0xA0000 1915 #define FA_FW_AREA_ADDR_81 0xC0000 1916 #define FA_VPD_NVRAM_ADDR_81 0xD0000 1917 #define FA_VPD0_ADDR_81 0xD0000 1918 #define FA_VPD1_ADDR_81 0xD0400 1919 #define FA_NVRAM0_ADDR_81 0xD0080 1920 #define FA_NVRAM1_ADDR_81 0xD0180 1921 #define FA_FEATURE_ADDR_81 0xD4000 1922 #define FA_FLASH_DESCR_ADDR_81 0xD8000 1923 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400 1924 #define FA_HW_EVENT0_ADDR_81 0xDC000 1925 #define FA_HW_EVENT1_ADDR_81 0xDC400 1926 #define FA_NPIV_CONF0_ADDR_81 0xD1000 1927 #define FA_NPIV_CONF1_ADDR_81 0xD2000 1928 1929 /* 83XX Flash locations -- occupies second 8MB region. */ 1930 #define FA_FLASH_LAYOUT_ADDR_83 0xFC400 1931 1932 #endif 1933