1 /* 2 * This is the Fusion MPT base driver providing common API layer interface 3 * for access to MPT (Message Passing Technology) firmware. 4 * 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 2 13 * of the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, 43 * USA. 44 */ 45 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/errno.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/types.h> 52 #include <linux/pci.h> 53 #include <linux/kdev_t.h> 54 #include <linux/blkdev.h> 55 #include <linux/delay.h> 56 #include <linux/interrupt.h> 57 #include <linux/dma-mapping.h> 58 #include <linux/io.h> 59 #include <linux/time.h> 60 #include <linux/ktime.h> 61 #include <linux/kthread.h> 62 #include <asm/page.h> /* To get host page size per arch */ 63 #include <linux/aer.h> 64 65 66 #include "mpt3sas_base.h" 67 68 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS]; 69 70 71 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */ 72 73 /* maximum controller queue depth */ 74 #define MAX_HBA_QUEUE_DEPTH 30000 75 #define MAX_CHAIN_DEPTH 100000 76 static int max_queue_depth = -1; 77 module_param(max_queue_depth, int, 0); 78 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth "); 79 80 static int max_sgl_entries = -1; 81 module_param(max_sgl_entries, int, 0); 82 MODULE_PARM_DESC(max_sgl_entries, " max sg entries "); 83 84 static int msix_disable = -1; 85 module_param(msix_disable, int, 0); 86 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)"); 87 88 static int smp_affinity_enable = 1; 89 module_param(smp_affinity_enable, int, S_IRUGO); 90 MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)"); 91 92 static int max_msix_vectors = -1; 93 module_param(max_msix_vectors, int, 0); 94 MODULE_PARM_DESC(max_msix_vectors, 95 " max msix vectors"); 96 97 static int mpt3sas_fwfault_debug; 98 MODULE_PARM_DESC(mpt3sas_fwfault_debug, 99 " enable detection of firmware fault and halt firmware - (default=0)"); 100 101 static int 102 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc); 103 104 /** 105 * mpt3sas_base_check_cmd_timeout - Function 106 * to check timeout and command termination due 107 * to Host reset. 108 * 109 * @ioc: per adapter object. 110 * @status: Status of issued command. 111 * @mpi_request:mf request pointer. 112 * @sz: size of buffer. 113 * 114 * @Returns - 1/0 Reset to be done or Not 115 */ 116 u8 117 mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc, 118 u8 status, void *mpi_request, int sz) 119 { 120 u8 issue_reset = 0; 121 122 if (!(status & MPT3_CMD_RESET)) 123 issue_reset = 1; 124 125 pr_err(MPT3SAS_FMT "Command %s\n", ioc->name, 126 ((issue_reset == 0) ? "terminated due to Host Reset" : "Timeout")); 127 _debug_dump_mf(mpi_request, sz); 128 129 return issue_reset; 130 } 131 132 /** 133 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug. 134 * @val: ? 135 * @kp: ? 136 * 137 * Return: ? 138 */ 139 static int 140 _scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp) 141 { 142 int ret = param_set_int(val, kp); 143 struct MPT3SAS_ADAPTER *ioc; 144 145 if (ret) 146 return ret; 147 148 /* global ioc spinlock to protect controller list on list operations */ 149 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug); 150 spin_lock(&gioc_lock); 151 list_for_each_entry(ioc, &mpt3sas_ioc_list, list) 152 ioc->fwfault_debug = mpt3sas_fwfault_debug; 153 spin_unlock(&gioc_lock); 154 return 0; 155 } 156 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug, 157 param_get_int, &mpt3sas_fwfault_debug, 0644); 158 159 /** 160 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem 161 * in BAR0 space. 162 * 163 * @ioc: per adapter object 164 * @reply: reply message frame(lower 32bit addr) 165 * @index: System request message index. 166 */ 167 static void 168 _base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply, 169 u32 index) 170 { 171 /* 172 * 256 is offset within sys register. 173 * 256 offset MPI frame starts. Max MPI frame supported is 32. 174 * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts 175 */ 176 u16 cmd_credit = ioc->facts.RequestCredit + 1; 177 void __iomem *reply_free_iomem = (void __iomem *)ioc->chip + 178 MPI_FRAME_START_OFFSET + 179 (cmd_credit * ioc->request_sz) + (index * sizeof(u32)); 180 181 writel(reply, reply_free_iomem); 182 } 183 184 /** 185 * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames 186 * to system/BAR0 region. 187 * 188 * @dst_iomem: Pointer to the destination location in BAR0 space. 189 * @src: Pointer to the Source data. 190 * @size: Size of data to be copied. 191 */ 192 static void 193 _base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size) 194 { 195 int i; 196 u32 *src_virt_mem = (u32 *)src; 197 198 for (i = 0; i < size/4; i++) 199 writel((u32)src_virt_mem[i], 200 (void __iomem *)dst_iomem + (i * 4)); 201 } 202 203 /** 204 * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region 205 * 206 * @dst_iomem: Pointer to the destination location in BAR0 space. 207 * @src: Pointer to the Source data. 208 * @size: Size of data to be copied. 209 */ 210 static void 211 _base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size) 212 { 213 int i; 214 u32 *src_virt_mem = (u32 *)(src); 215 216 for (i = 0; i < size/4; i++) 217 writel((u32)src_virt_mem[i], 218 (void __iomem *)dst_iomem + (i * 4)); 219 } 220 221 /** 222 * _base_get_chain - Calculates and Returns virtual chain address 223 * for the provided smid in BAR0 space. 224 * 225 * @ioc: per adapter object 226 * @smid: system request message index 227 * @sge_chain_count: Scatter gather chain count. 228 * 229 * Return: the chain address. 230 */ 231 static inline void __iomem* 232 _base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid, 233 u8 sge_chain_count) 234 { 235 void __iomem *base_chain, *chain_virt; 236 u16 cmd_credit = ioc->facts.RequestCredit + 1; 237 238 base_chain = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET + 239 (cmd_credit * ioc->request_sz) + 240 REPLY_FREE_POOL_SIZE; 241 chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth * 242 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 243 return chain_virt; 244 } 245 246 /** 247 * _base_get_chain_phys - Calculates and Returns physical address 248 * in BAR0 for scatter gather chains, for 249 * the provided smid. 250 * 251 * @ioc: per adapter object 252 * @smid: system request message index 253 * @sge_chain_count: Scatter gather chain count. 254 * 255 * Return: Physical chain address. 256 */ 257 static inline phys_addr_t 258 _base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid, 259 u8 sge_chain_count) 260 { 261 phys_addr_t base_chain_phys, chain_phys; 262 u16 cmd_credit = ioc->facts.RequestCredit + 1; 263 264 base_chain_phys = ioc->chip_phys + MPI_FRAME_START_OFFSET + 265 (cmd_credit * ioc->request_sz) + 266 REPLY_FREE_POOL_SIZE; 267 chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth * 268 ioc->request_sz) + (sge_chain_count * ioc->request_sz); 269 return chain_phys; 270 } 271 272 /** 273 * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host 274 * buffer address for the provided smid. 275 * (Each smid can have 64K starts from 17024) 276 * 277 * @ioc: per adapter object 278 * @smid: system request message index 279 * 280 * Return: Pointer to buffer location in BAR0. 281 */ 282 283 static void __iomem * 284 _base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 285 { 286 u16 cmd_credit = ioc->facts.RequestCredit + 1; 287 // Added extra 1 to reach end of chain. 288 void __iomem *chain_end = _base_get_chain(ioc, 289 cmd_credit + 1, 290 ioc->facts.MaxChainDepth); 291 return chain_end + (smid * 64 * 1024); 292 } 293 294 /** 295 * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped 296 * Host buffer Physical address for the provided smid. 297 * (Each smid can have 64K starts from 17024) 298 * 299 * @ioc: per adapter object 300 * @smid: system request message index 301 * 302 * Return: Pointer to buffer location in BAR0. 303 */ 304 static phys_addr_t 305 _base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid) 306 { 307 u16 cmd_credit = ioc->facts.RequestCredit + 1; 308 phys_addr_t chain_end_phys = _base_get_chain_phys(ioc, 309 cmd_credit + 1, 310 ioc->facts.MaxChainDepth); 311 return chain_end_phys + (smid * 64 * 1024); 312 } 313 314 /** 315 * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain 316 * lookup list and Provides chain_buffer 317 * address for the matching dma address. 318 * (Each smid can have 64K starts from 17024) 319 * 320 * @ioc: per adapter object 321 * @chain_buffer_dma: Chain buffer dma address. 322 * 323 * Return: Pointer to chain buffer. Or Null on Failure. 324 */ 325 static void * 326 _base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc, 327 dma_addr_t chain_buffer_dma) 328 { 329 u16 index, j; 330 struct chain_tracker *ct; 331 332 for (index = 0; index < ioc->scsiio_depth; index++) { 333 for (j = 0; j < ioc->chains_needed_per_io; j++) { 334 ct = &ioc->chain_lookup[index].chains_per_smid[j]; 335 if (ct && ct->chain_buffer_dma == chain_buffer_dma) 336 return ct->chain_buffer; 337 } 338 } 339 pr_info(MPT3SAS_FMT 340 "Provided chain_buffer_dma address is not in the lookup list\n", 341 ioc->name); 342 return NULL; 343 } 344 345 /** 346 * _clone_sg_entries - MPI EP's scsiio and config requests 347 * are handled here. Base function for 348 * double buffering, before submitting 349 * the requests. 350 * 351 * @ioc: per adapter object. 352 * @mpi_request: mf request pointer. 353 * @smid: system request message index. 354 */ 355 static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc, 356 void *mpi_request, u16 smid) 357 { 358 Mpi2SGESimple32_t *sgel, *sgel_next; 359 u32 sgl_flags, sge_chain_count = 0; 360 bool is_write = 0; 361 u16 i = 0; 362 void __iomem *buffer_iomem; 363 phys_addr_t buffer_iomem_phys; 364 void __iomem *buff_ptr; 365 phys_addr_t buff_ptr_phys; 366 void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 367 void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO]; 368 phys_addr_t dst_addr_phys; 369 MPI2RequestHeader_t *request_hdr; 370 struct scsi_cmnd *scmd; 371 struct scatterlist *sg_scmd = NULL; 372 int is_scsiio_req = 0; 373 374 request_hdr = (MPI2RequestHeader_t *) mpi_request; 375 376 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 377 Mpi25SCSIIORequest_t *scsiio_request = 378 (Mpi25SCSIIORequest_t *)mpi_request; 379 sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL; 380 is_scsiio_req = 1; 381 } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) { 382 Mpi2ConfigRequest_t *config_req = 383 (Mpi2ConfigRequest_t *)mpi_request; 384 sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE; 385 } else 386 return; 387 388 /* From smid we can get scsi_cmd, once we have sg_scmd, 389 * we just need to get sg_virt and sg_next to get virual 390 * address associated with sgel->Address. 391 */ 392 393 if (is_scsiio_req) { 394 /* Get scsi_cmd using smid */ 395 scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 396 if (scmd == NULL) { 397 pr_err(MPT3SAS_FMT "scmd is NULL\n", ioc->name); 398 return; 399 } 400 401 /* Get sg_scmd from scmd provided */ 402 sg_scmd = scsi_sglist(scmd); 403 } 404 405 /* 406 * 0 - 255 System register 407 * 256 - 4352 MPI Frame. (This is based on maxCredit 32) 408 * 4352 - 4864 Reply_free pool (512 byte is reserved 409 * considering maxCredit 32. Reply need extra 410 * room, for mCPU case kept four times of 411 * maxCredit). 412 * 4864 - 17152 SGE chain element. (32cmd * 3 chain of 413 * 128 byte size = 12288) 414 * 17152 - x Host buffer mapped with smid. 415 * (Each smid can have 64K Max IO.) 416 * BAR0+Last 1K MSIX Addr and Data 417 * Total size in use 2113664 bytes of 4MB BAR0 418 */ 419 420 buffer_iomem = _base_get_buffer_bar0(ioc, smid); 421 buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid); 422 423 buff_ptr = buffer_iomem; 424 buff_ptr_phys = buffer_iomem_phys; 425 WARN_ON(buff_ptr_phys > U32_MAX); 426 427 if (le32_to_cpu(sgel->FlagsLength) & 428 (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT)) 429 is_write = 1; 430 431 for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) { 432 433 sgl_flags = 434 (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT); 435 436 switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) { 437 case MPI2_SGE_FLAGS_CHAIN_ELEMENT: 438 /* 439 * Helper function which on passing 440 * chain_buffer_dma returns chain_buffer. Get 441 * the virtual address for sgel->Address 442 */ 443 sgel_next = 444 _base_get_chain_buffer_dma_to_chain_buffer(ioc, 445 le32_to_cpu(sgel->Address)); 446 if (sgel_next == NULL) 447 return; 448 /* 449 * This is coping 128 byte chain 450 * frame (not a host buffer) 451 */ 452 dst_chain_addr[sge_chain_count] = 453 _base_get_chain(ioc, 454 smid, sge_chain_count); 455 src_chain_addr[sge_chain_count] = 456 (void *) sgel_next; 457 dst_addr_phys = _base_get_chain_phys(ioc, 458 smid, sge_chain_count); 459 WARN_ON(dst_addr_phys > U32_MAX); 460 sgel->Address = 461 cpu_to_le32(lower_32_bits(dst_addr_phys)); 462 sgel = sgel_next; 463 sge_chain_count++; 464 break; 465 case MPI2_SGE_FLAGS_SIMPLE_ELEMENT: 466 if (is_write) { 467 if (is_scsiio_req) { 468 _base_clone_to_sys_mem(buff_ptr, 469 sg_virt(sg_scmd), 470 (le32_to_cpu(sgel->FlagsLength) & 471 0x00ffffff)); 472 /* 473 * FIXME: this relies on a a zero 474 * PCI mem_offset. 475 */ 476 sgel->Address = 477 cpu_to_le32((u32)buff_ptr_phys); 478 } else { 479 _base_clone_to_sys_mem(buff_ptr, 480 ioc->config_vaddr, 481 (le32_to_cpu(sgel->FlagsLength) & 482 0x00ffffff)); 483 sgel->Address = 484 cpu_to_le32((u32)buff_ptr_phys); 485 } 486 } 487 buff_ptr += (le32_to_cpu(sgel->FlagsLength) & 488 0x00ffffff); 489 buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) & 490 0x00ffffff); 491 if ((le32_to_cpu(sgel->FlagsLength) & 492 (MPI2_SGE_FLAGS_END_OF_BUFFER 493 << MPI2_SGE_FLAGS_SHIFT))) 494 goto eob_clone_chain; 495 else { 496 /* 497 * Every single element in MPT will have 498 * associated sg_next. Better to sanity that 499 * sg_next is not NULL, but it will be a bug 500 * if it is null. 501 */ 502 if (is_scsiio_req) { 503 sg_scmd = sg_next(sg_scmd); 504 if (sg_scmd) 505 sgel++; 506 else 507 goto eob_clone_chain; 508 } 509 } 510 break; 511 } 512 } 513 514 eob_clone_chain: 515 for (i = 0; i < sge_chain_count; i++) { 516 if (is_scsiio_req) 517 _base_clone_to_sys_mem(dst_chain_addr[i], 518 src_chain_addr[i], ioc->request_sz); 519 } 520 } 521 522 /** 523 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc 524 * @arg: input argument, used to derive ioc 525 * 526 * Return: 527 * 0 if controller is removed from pci subsystem. 528 * -1 for other case. 529 */ 530 static int mpt3sas_remove_dead_ioc_func(void *arg) 531 { 532 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg; 533 struct pci_dev *pdev; 534 535 if ((ioc == NULL)) 536 return -1; 537 538 pdev = ioc->pdev; 539 if ((pdev == NULL)) 540 return -1; 541 pci_stop_and_remove_bus_device_locked(pdev); 542 return 0; 543 } 544 545 /** 546 * _base_fault_reset_work - workq handling ioc fault conditions 547 * @work: input argument, used to derive ioc 548 * 549 * Context: sleep. 550 */ 551 static void 552 _base_fault_reset_work(struct work_struct *work) 553 { 554 struct MPT3SAS_ADAPTER *ioc = 555 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work); 556 unsigned long flags; 557 u32 doorbell; 558 int rc; 559 struct task_struct *p; 560 561 562 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 563 if (ioc->shost_recovery || ioc->pci_error_recovery) 564 goto rearm_timer; 565 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 566 567 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 568 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) { 569 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n", 570 ioc->name); 571 572 /* It may be possible that EEH recovery can resolve some of 573 * pci bus failure issues rather removing the dead ioc function 574 * by considering controller is in a non-operational state. So 575 * here priority is given to the EEH recovery. If it doesn't 576 * not resolve this issue, mpt3sas driver will consider this 577 * controller to non-operational state and remove the dead ioc 578 * function. 579 */ 580 if (ioc->non_operational_loop++ < 5) { 581 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, 582 flags); 583 goto rearm_timer; 584 } 585 586 /* 587 * Call _scsih_flush_pending_cmds callback so that we flush all 588 * pending commands back to OS. This call is required to aovid 589 * deadlock at block layer. Dead IOC will fail to do diag reset, 590 * and this call is safe since dead ioc will never return any 591 * command back from HW. 592 */ 593 ioc->schedule_dead_ioc_flush_running_cmds(ioc); 594 /* 595 * Set remove_host flag early since kernel thread will 596 * take some time to execute. 597 */ 598 ioc->remove_host = 1; 599 /*Remove the Dead Host */ 600 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc, 601 "%s_dead_ioc_%d", ioc->driver_name, ioc->id); 602 if (IS_ERR(p)) 603 pr_err(MPT3SAS_FMT 604 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n", 605 ioc->name, __func__); 606 else 607 pr_err(MPT3SAS_FMT 608 "%s: Running mpt3sas_dead_ioc thread success !!!!\n", 609 ioc->name, __func__); 610 return; /* don't rearm timer */ 611 } 612 613 ioc->non_operational_loop = 0; 614 615 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) { 616 rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 617 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name, 618 __func__, (rc == 0) ? "success" : "failed"); 619 doorbell = mpt3sas_base_get_iocstate(ioc, 0); 620 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 621 mpt3sas_base_fault_info(ioc, doorbell & 622 MPI2_DOORBELL_DATA_MASK); 623 if (rc && (doorbell & MPI2_IOC_STATE_MASK) != 624 MPI2_IOC_STATE_OPERATIONAL) 625 return; /* don't rearm timer */ 626 } 627 628 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 629 rearm_timer: 630 if (ioc->fault_reset_work_q) 631 queue_delayed_work(ioc->fault_reset_work_q, 632 &ioc->fault_reset_work, 633 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 634 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 635 } 636 637 /** 638 * mpt3sas_base_start_watchdog - start the fault_reset_work_q 639 * @ioc: per adapter object 640 * 641 * Context: sleep. 642 */ 643 void 644 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc) 645 { 646 unsigned long flags; 647 648 if (ioc->fault_reset_work_q) 649 return; 650 651 /* initialize fault polling */ 652 653 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work); 654 snprintf(ioc->fault_reset_work_q_name, 655 sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status", 656 ioc->driver_name, ioc->id); 657 ioc->fault_reset_work_q = 658 create_singlethread_workqueue(ioc->fault_reset_work_q_name); 659 if (!ioc->fault_reset_work_q) { 660 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n", 661 ioc->name, __func__, __LINE__); 662 return; 663 } 664 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 665 if (ioc->fault_reset_work_q) 666 queue_delayed_work(ioc->fault_reset_work_q, 667 &ioc->fault_reset_work, 668 msecs_to_jiffies(FAULT_POLLING_INTERVAL)); 669 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 670 } 671 672 /** 673 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q 674 * @ioc: per adapter object 675 * 676 * Context: sleep. 677 */ 678 void 679 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc) 680 { 681 unsigned long flags; 682 struct workqueue_struct *wq; 683 684 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 685 wq = ioc->fault_reset_work_q; 686 ioc->fault_reset_work_q = NULL; 687 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 688 if (wq) { 689 if (!cancel_delayed_work_sync(&ioc->fault_reset_work)) 690 flush_workqueue(wq); 691 destroy_workqueue(wq); 692 } 693 } 694 695 /** 696 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code 697 * @ioc: per adapter object 698 * @fault_code: fault code 699 */ 700 void 701 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code) 702 { 703 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n", 704 ioc->name, fault_code); 705 } 706 707 /** 708 * mpt3sas_halt_firmware - halt's mpt controller firmware 709 * @ioc: per adapter object 710 * 711 * For debugging timeout related issues. Writing 0xCOFFEE00 712 * to the doorbell register will halt controller firmware. With 713 * the purpose to stop both driver and firmware, the enduser can 714 * obtain a ring buffer from controller UART. 715 */ 716 void 717 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc) 718 { 719 u32 doorbell; 720 721 if (!ioc->fwfault_debug) 722 return; 723 724 dump_stack(); 725 726 doorbell = readl(&ioc->chip->Doorbell); 727 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 728 mpt3sas_base_fault_info(ioc , doorbell); 729 else { 730 writel(0xC0FFEE00, &ioc->chip->Doorbell); 731 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n", 732 ioc->name); 733 } 734 735 if (ioc->fwfault_debug == 2) 736 for (;;) 737 ; 738 else 739 panic("panic in %s\n", __func__); 740 } 741 742 /** 743 * _base_sas_ioc_info - verbose translation of the ioc status 744 * @ioc: per adapter object 745 * @mpi_reply: reply mf payload returned from firmware 746 * @request_hdr: request mf 747 */ 748 static void 749 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply, 750 MPI2RequestHeader_t *request_hdr) 751 { 752 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & 753 MPI2_IOCSTATUS_MASK; 754 char *desc = NULL; 755 u16 frame_sz; 756 char *func_str = NULL; 757 758 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */ 759 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST || 760 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH || 761 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION) 762 return; 763 764 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE) 765 return; 766 767 switch (ioc_status) { 768 769 /**************************************************************************** 770 * Common IOCStatus values for all replies 771 ****************************************************************************/ 772 773 case MPI2_IOCSTATUS_INVALID_FUNCTION: 774 desc = "invalid function"; 775 break; 776 case MPI2_IOCSTATUS_BUSY: 777 desc = "busy"; 778 break; 779 case MPI2_IOCSTATUS_INVALID_SGL: 780 desc = "invalid sgl"; 781 break; 782 case MPI2_IOCSTATUS_INTERNAL_ERROR: 783 desc = "internal error"; 784 break; 785 case MPI2_IOCSTATUS_INVALID_VPID: 786 desc = "invalid vpid"; 787 break; 788 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 789 desc = "insufficient resources"; 790 break; 791 case MPI2_IOCSTATUS_INSUFFICIENT_POWER: 792 desc = "insufficient power"; 793 break; 794 case MPI2_IOCSTATUS_INVALID_FIELD: 795 desc = "invalid field"; 796 break; 797 case MPI2_IOCSTATUS_INVALID_STATE: 798 desc = "invalid state"; 799 break; 800 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 801 desc = "op state not supported"; 802 break; 803 804 /**************************************************************************** 805 * Config IOCStatus values 806 ****************************************************************************/ 807 808 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 809 desc = "config invalid action"; 810 break; 811 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 812 desc = "config invalid type"; 813 break; 814 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 815 desc = "config invalid page"; 816 break; 817 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 818 desc = "config invalid data"; 819 break; 820 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 821 desc = "config no defaults"; 822 break; 823 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 824 desc = "config cant commit"; 825 break; 826 827 /**************************************************************************** 828 * SCSI IO Reply 829 ****************************************************************************/ 830 831 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR: 832 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE: 833 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 834 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 835 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 836 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 837 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 838 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 839 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 840 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 841 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 842 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 843 break; 844 845 /**************************************************************************** 846 * For use by SCSI Initiator and SCSI Target end-to-end data protection 847 ****************************************************************************/ 848 849 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR: 850 desc = "eedp guard error"; 851 break; 852 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR: 853 desc = "eedp ref tag error"; 854 break; 855 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR: 856 desc = "eedp app tag error"; 857 break; 858 859 /**************************************************************************** 860 * SCSI Target values 861 ****************************************************************************/ 862 863 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX: 864 desc = "target invalid io index"; 865 break; 866 case MPI2_IOCSTATUS_TARGET_ABORTED: 867 desc = "target aborted"; 868 break; 869 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: 870 desc = "target no conn retryable"; 871 break; 872 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION: 873 desc = "target no connection"; 874 break; 875 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: 876 desc = "target xfer count mismatch"; 877 break; 878 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: 879 desc = "target data offset error"; 880 break; 881 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: 882 desc = "target too much write data"; 883 break; 884 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT: 885 desc = "target iu too short"; 886 break; 887 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: 888 desc = "target ack nak timeout"; 889 break; 890 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED: 891 desc = "target nak received"; 892 break; 893 894 /**************************************************************************** 895 * Serial Attached SCSI values 896 ****************************************************************************/ 897 898 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 899 desc = "smp request failed"; 900 break; 901 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 902 desc = "smp data overrun"; 903 break; 904 905 /**************************************************************************** 906 * Diagnostic Buffer Post / Diagnostic Release values 907 ****************************************************************************/ 908 909 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED: 910 desc = "diagnostic released"; 911 break; 912 default: 913 break; 914 } 915 916 if (!desc) 917 return; 918 919 switch (request_hdr->Function) { 920 case MPI2_FUNCTION_CONFIG: 921 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size; 922 func_str = "config_page"; 923 break; 924 case MPI2_FUNCTION_SCSI_TASK_MGMT: 925 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t); 926 func_str = "task_mgmt"; 927 break; 928 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL: 929 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t); 930 func_str = "sas_iounit_ctl"; 931 break; 932 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR: 933 frame_sz = sizeof(Mpi2SepRequest_t); 934 func_str = "enclosure"; 935 break; 936 case MPI2_FUNCTION_IOC_INIT: 937 frame_sz = sizeof(Mpi2IOCInitRequest_t); 938 func_str = "ioc_init"; 939 break; 940 case MPI2_FUNCTION_PORT_ENABLE: 941 frame_sz = sizeof(Mpi2PortEnableRequest_t); 942 func_str = "port_enable"; 943 break; 944 case MPI2_FUNCTION_SMP_PASSTHROUGH: 945 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size; 946 func_str = "smp_passthru"; 947 break; 948 case MPI2_FUNCTION_NVME_ENCAPSULATED: 949 frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) + 950 ioc->sge_size; 951 func_str = "nvme_encapsulated"; 952 break; 953 default: 954 frame_sz = 32; 955 func_str = "unknown"; 956 break; 957 } 958 959 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n", 960 ioc->name, desc, ioc_status, request_hdr, func_str); 961 962 _debug_dump_mf(request_hdr, frame_sz/4); 963 } 964 965 /** 966 * _base_display_event_data - verbose translation of firmware asyn events 967 * @ioc: per adapter object 968 * @mpi_reply: reply mf payload returned from firmware 969 */ 970 static void 971 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc, 972 Mpi2EventNotificationReply_t *mpi_reply) 973 { 974 char *desc = NULL; 975 u16 event; 976 977 if (!(ioc->logging_level & MPT_DEBUG_EVENTS)) 978 return; 979 980 event = le16_to_cpu(mpi_reply->Event); 981 982 switch (event) { 983 case MPI2_EVENT_LOG_DATA: 984 desc = "Log Data"; 985 break; 986 case MPI2_EVENT_STATE_CHANGE: 987 desc = "Status Change"; 988 break; 989 case MPI2_EVENT_HARD_RESET_RECEIVED: 990 desc = "Hard Reset Received"; 991 break; 992 case MPI2_EVENT_EVENT_CHANGE: 993 desc = "Event Change"; 994 break; 995 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 996 desc = "Device Status Change"; 997 break; 998 case MPI2_EVENT_IR_OPERATION_STATUS: 999 if (!ioc->hide_ir_msg) 1000 desc = "IR Operation Status"; 1001 break; 1002 case MPI2_EVENT_SAS_DISCOVERY: 1003 { 1004 Mpi2EventDataSasDiscovery_t *event_data = 1005 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData; 1006 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name, 1007 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ? 1008 "start" : "stop"); 1009 if (event_data->DiscoveryStatus) 1010 pr_cont(" discovery_status(0x%08x)", 1011 le32_to_cpu(event_data->DiscoveryStatus)); 1012 pr_cont("\n"); 1013 return; 1014 } 1015 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 1016 desc = "SAS Broadcast Primitive"; 1017 break; 1018 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 1019 desc = "SAS Init Device Status Change"; 1020 break; 1021 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW: 1022 desc = "SAS Init Table Overflow"; 1023 break; 1024 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 1025 desc = "SAS Topology Change List"; 1026 break; 1027 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 1028 desc = "SAS Enclosure Device Status Change"; 1029 break; 1030 case MPI2_EVENT_IR_VOLUME: 1031 if (!ioc->hide_ir_msg) 1032 desc = "IR Volume"; 1033 break; 1034 case MPI2_EVENT_IR_PHYSICAL_DISK: 1035 if (!ioc->hide_ir_msg) 1036 desc = "IR Physical Disk"; 1037 break; 1038 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 1039 if (!ioc->hide_ir_msg) 1040 desc = "IR Configuration Change List"; 1041 break; 1042 case MPI2_EVENT_LOG_ENTRY_ADDED: 1043 if (!ioc->hide_ir_msg) 1044 desc = "Log Entry Added"; 1045 break; 1046 case MPI2_EVENT_TEMP_THRESHOLD: 1047 desc = "Temperature Threshold"; 1048 break; 1049 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 1050 desc = "Cable Event"; 1051 break; 1052 case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 1053 desc = "SAS Device Discovery Error"; 1054 break; 1055 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 1056 desc = "PCIE Device Status Change"; 1057 break; 1058 case MPI2_EVENT_PCIE_ENUMERATION: 1059 { 1060 Mpi26EventDataPCIeEnumeration_t *event_data = 1061 (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData; 1062 pr_info(MPT3SAS_FMT "PCIE Enumeration: (%s)", ioc->name, 1063 (event_data->ReasonCode == 1064 MPI26_EVENT_PCIE_ENUM_RC_STARTED) ? 1065 "start" : "stop"); 1066 if (event_data->EnumerationStatus) 1067 pr_info("enumeration_status(0x%08x)", 1068 le32_to_cpu(event_data->EnumerationStatus)); 1069 pr_info("\n"); 1070 return; 1071 } 1072 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 1073 desc = "PCIE Topology Change List"; 1074 break; 1075 } 1076 1077 if (!desc) 1078 return; 1079 1080 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc); 1081 } 1082 1083 /** 1084 * _base_sas_log_info - verbose translation of firmware log info 1085 * @ioc: per adapter object 1086 * @log_info: log info 1087 */ 1088 static void 1089 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info) 1090 { 1091 union loginfo_type { 1092 u32 loginfo; 1093 struct { 1094 u32 subcode:16; 1095 u32 code:8; 1096 u32 originator:4; 1097 u32 bus_type:4; 1098 } dw; 1099 }; 1100 union loginfo_type sas_loginfo; 1101 char *originator_str = NULL; 1102 1103 sas_loginfo.loginfo = log_info; 1104 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 1105 return; 1106 1107 /* each nexus loss loginfo */ 1108 if (log_info == 0x31170000) 1109 return; 1110 1111 /* eat the loginfos associated with task aborts */ 1112 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info == 1113 0x31140000 || log_info == 0x31130000)) 1114 return; 1115 1116 switch (sas_loginfo.dw.originator) { 1117 case 0: 1118 originator_str = "IOP"; 1119 break; 1120 case 1: 1121 originator_str = "PL"; 1122 break; 1123 case 2: 1124 if (!ioc->hide_ir_msg) 1125 originator_str = "IR"; 1126 else 1127 originator_str = "WarpDrive"; 1128 break; 1129 } 1130 1131 pr_warn(MPT3SAS_FMT 1132 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n", 1133 ioc->name, log_info, 1134 originator_str, sas_loginfo.dw.code, 1135 sas_loginfo.dw.subcode); 1136 } 1137 1138 /** 1139 * _base_display_reply_info - 1140 * @ioc: per adapter object 1141 * @smid: system request message index 1142 * @msix_index: MSIX table index supplied by the OS 1143 * @reply: reply message frame(lower 32bit addr) 1144 */ 1145 static void 1146 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1147 u32 reply) 1148 { 1149 MPI2DefaultReply_t *mpi_reply; 1150 u16 ioc_status; 1151 u32 loginfo = 0; 1152 1153 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1154 if (unlikely(!mpi_reply)) { 1155 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n", 1156 ioc->name, __FILE__, __LINE__, __func__); 1157 return; 1158 } 1159 ioc_status = le16_to_cpu(mpi_reply->IOCStatus); 1160 1161 if ((ioc_status & MPI2_IOCSTATUS_MASK) && 1162 (ioc->logging_level & MPT_DEBUG_REPLY)) { 1163 _base_sas_ioc_info(ioc , mpi_reply, 1164 mpt3sas_base_get_msg_frame(ioc, smid)); 1165 } 1166 1167 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 1168 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo); 1169 _base_sas_log_info(ioc, loginfo); 1170 } 1171 1172 if (ioc_status || loginfo) { 1173 ioc_status &= MPI2_IOCSTATUS_MASK; 1174 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo); 1175 } 1176 } 1177 1178 /** 1179 * mpt3sas_base_done - base internal command completion routine 1180 * @ioc: per adapter object 1181 * @smid: system request message index 1182 * @msix_index: MSIX table index supplied by the OS 1183 * @reply: reply message frame(lower 32bit addr) 1184 * 1185 * Return: 1186 * 1 meaning mf should be freed from _base_interrupt 1187 * 0 means the mf is freed from this function. 1188 */ 1189 u8 1190 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 1191 u32 reply) 1192 { 1193 MPI2DefaultReply_t *mpi_reply; 1194 1195 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1196 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK) 1197 return mpt3sas_check_for_pending_internal_cmds(ioc, smid); 1198 1199 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED) 1200 return 1; 1201 1202 ioc->base_cmds.status |= MPT3_CMD_COMPLETE; 1203 if (mpi_reply) { 1204 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID; 1205 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 1206 } 1207 ioc->base_cmds.status &= ~MPT3_CMD_PENDING; 1208 1209 complete(&ioc->base_cmds.done); 1210 return 1; 1211 } 1212 1213 /** 1214 * _base_async_event - main callback handler for firmware asyn events 1215 * @ioc: per adapter object 1216 * @msix_index: MSIX table index supplied by the OS 1217 * @reply: reply message frame(lower 32bit addr) 1218 * 1219 * Return: 1220 * 1 meaning mf should be freed from _base_interrupt 1221 * 0 means the mf is freed from this function. 1222 */ 1223 static u8 1224 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply) 1225 { 1226 Mpi2EventNotificationReply_t *mpi_reply; 1227 Mpi2EventAckRequest_t *ack_request; 1228 u16 smid; 1229 struct _event_ack_list *delayed_event_ack; 1230 1231 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 1232 if (!mpi_reply) 1233 return 1; 1234 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION) 1235 return 1; 1236 1237 _base_display_event_data(ioc, mpi_reply); 1238 1239 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED)) 1240 goto out; 1241 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 1242 if (!smid) { 1243 delayed_event_ack = kzalloc(sizeof(*delayed_event_ack), 1244 GFP_ATOMIC); 1245 if (!delayed_event_ack) 1246 goto out; 1247 INIT_LIST_HEAD(&delayed_event_ack->list); 1248 delayed_event_ack->Event = mpi_reply->Event; 1249 delayed_event_ack->EventContext = mpi_reply->EventContext; 1250 list_add_tail(&delayed_event_ack->list, 1251 &ioc->delayed_event_ack_list); 1252 dewtprintk(ioc, pr_info(MPT3SAS_FMT 1253 "DELAYED: EVENT ACK: event (0x%04x)\n", 1254 ioc->name, le16_to_cpu(mpi_reply->Event))); 1255 goto out; 1256 } 1257 1258 ack_request = mpt3sas_base_get_msg_frame(ioc, smid); 1259 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t)); 1260 ack_request->Function = MPI2_FUNCTION_EVENT_ACK; 1261 ack_request->Event = mpi_reply->Event; 1262 ack_request->EventContext = mpi_reply->EventContext; 1263 ack_request->VF_ID = 0; /* TODO */ 1264 ack_request->VP_ID = 0; 1265 mpt3sas_base_put_smid_default(ioc, smid); 1266 1267 out: 1268 1269 /* scsih callback handler */ 1270 mpt3sas_scsih_event_callback(ioc, msix_index, reply); 1271 1272 /* ctl callback handler */ 1273 mpt3sas_ctl_event_callback(ioc, msix_index, reply); 1274 1275 return 1; 1276 } 1277 1278 static struct scsiio_tracker * 1279 _get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1280 { 1281 struct scsi_cmnd *cmd; 1282 1283 if (WARN_ON(!smid) || 1284 WARN_ON(smid >= ioc->hi_priority_smid)) 1285 return NULL; 1286 1287 cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid); 1288 if (cmd) 1289 return scsi_cmd_priv(cmd); 1290 1291 return NULL; 1292 } 1293 1294 /** 1295 * _base_get_cb_idx - obtain the callback index 1296 * @ioc: per adapter object 1297 * @smid: system request message index 1298 * 1299 * Return: callback index. 1300 */ 1301 static u8 1302 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid) 1303 { 1304 int i; 1305 u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1; 1306 u8 cb_idx = 0xFF; 1307 1308 if (smid < ioc->hi_priority_smid) { 1309 struct scsiio_tracker *st; 1310 1311 if (smid < ctl_smid) { 1312 st = _get_st_from_smid(ioc, smid); 1313 if (st) 1314 cb_idx = st->cb_idx; 1315 } else if (smid == ctl_smid) 1316 cb_idx = ioc->ctl_cb_idx; 1317 } else if (smid < ioc->internal_smid) { 1318 i = smid - ioc->hi_priority_smid; 1319 cb_idx = ioc->hpr_lookup[i].cb_idx; 1320 } else if (smid <= ioc->hba_queue_depth) { 1321 i = smid - ioc->internal_smid; 1322 cb_idx = ioc->internal_lookup[i].cb_idx; 1323 } 1324 return cb_idx; 1325 } 1326 1327 /** 1328 * _base_mask_interrupts - disable interrupts 1329 * @ioc: per adapter object 1330 * 1331 * Disabling ResetIRQ, Reply and Doorbell Interrupts 1332 */ 1333 static void 1334 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1335 { 1336 u32 him_register; 1337 1338 ioc->mask_interrupts = 1; 1339 him_register = readl(&ioc->chip->HostInterruptMask); 1340 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK; 1341 writel(him_register, &ioc->chip->HostInterruptMask); 1342 readl(&ioc->chip->HostInterruptMask); 1343 } 1344 1345 /** 1346 * _base_unmask_interrupts - enable interrupts 1347 * @ioc: per adapter object 1348 * 1349 * Enabling only Reply Interrupts 1350 */ 1351 static void 1352 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc) 1353 { 1354 u32 him_register; 1355 1356 him_register = readl(&ioc->chip->HostInterruptMask); 1357 him_register &= ~MPI2_HIM_RIM; 1358 writel(him_register, &ioc->chip->HostInterruptMask); 1359 ioc->mask_interrupts = 0; 1360 } 1361 1362 union reply_descriptor { 1363 u64 word; 1364 struct { 1365 u32 low; 1366 u32 high; 1367 } u; 1368 }; 1369 1370 /** 1371 * _base_interrupt - MPT adapter (IOC) specific interrupt handler. 1372 * @irq: irq number (not used) 1373 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 1374 * 1375 * Return: IRQ_HANDLED if processed, else IRQ_NONE. 1376 */ 1377 static irqreturn_t 1378 _base_interrupt(int irq, void *bus_id) 1379 { 1380 struct adapter_reply_queue *reply_q = bus_id; 1381 union reply_descriptor rd; 1382 u32 completed_cmds; 1383 u8 request_desript_type; 1384 u16 smid; 1385 u8 cb_idx; 1386 u32 reply; 1387 u8 msix_index = reply_q->msix_index; 1388 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc; 1389 Mpi2ReplyDescriptorsUnion_t *rpf; 1390 u8 rc; 1391 1392 if (ioc->mask_interrupts) 1393 return IRQ_NONE; 1394 1395 if (!atomic_add_unless(&reply_q->busy, 1, 1)) 1396 return IRQ_NONE; 1397 1398 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index]; 1399 request_desript_type = rpf->Default.ReplyFlags 1400 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1401 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) { 1402 atomic_dec(&reply_q->busy); 1403 return IRQ_NONE; 1404 } 1405 1406 completed_cmds = 0; 1407 cb_idx = 0xFF; 1408 do { 1409 rd.word = le64_to_cpu(rpf->Words); 1410 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX) 1411 goto out; 1412 reply = 0; 1413 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1); 1414 if (request_desript_type == 1415 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS || 1416 request_desript_type == 1417 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 1418 request_desript_type == 1419 MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) { 1420 cb_idx = _base_get_cb_idx(ioc, smid); 1421 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1422 (likely(mpt_callbacks[cb_idx] != NULL))) { 1423 rc = mpt_callbacks[cb_idx](ioc, smid, 1424 msix_index, 0); 1425 if (rc) 1426 mpt3sas_base_free_smid(ioc, smid); 1427 } 1428 } else if (request_desript_type == 1429 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 1430 reply = le32_to_cpu( 1431 rpf->AddressReply.ReplyFrameAddress); 1432 if (reply > ioc->reply_dma_max_address || 1433 reply < ioc->reply_dma_min_address) 1434 reply = 0; 1435 if (smid) { 1436 cb_idx = _base_get_cb_idx(ioc, smid); 1437 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) && 1438 (likely(mpt_callbacks[cb_idx] != NULL))) { 1439 rc = mpt_callbacks[cb_idx](ioc, smid, 1440 msix_index, reply); 1441 if (reply) 1442 _base_display_reply_info(ioc, 1443 smid, msix_index, reply); 1444 if (rc) 1445 mpt3sas_base_free_smid(ioc, 1446 smid); 1447 } 1448 } else { 1449 _base_async_event(ioc, msix_index, reply); 1450 } 1451 1452 /* reply free queue handling */ 1453 if (reply) { 1454 ioc->reply_free_host_index = 1455 (ioc->reply_free_host_index == 1456 (ioc->reply_free_queue_depth - 1)) ? 1457 0 : ioc->reply_free_host_index + 1; 1458 ioc->reply_free[ioc->reply_free_host_index] = 1459 cpu_to_le32(reply); 1460 if (ioc->is_mcpu_endpoint) 1461 _base_clone_reply_to_sys_mem(ioc, 1462 reply, 1463 ioc->reply_free_host_index); 1464 writel(ioc->reply_free_host_index, 1465 &ioc->chip->ReplyFreeHostIndex); 1466 } 1467 } 1468 1469 rpf->Words = cpu_to_le64(ULLONG_MAX); 1470 reply_q->reply_post_host_index = 1471 (reply_q->reply_post_host_index == 1472 (ioc->reply_post_queue_depth - 1)) ? 0 : 1473 reply_q->reply_post_host_index + 1; 1474 request_desript_type = 1475 reply_q->reply_post_free[reply_q->reply_post_host_index]. 1476 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1477 completed_cmds++; 1478 /* Update the reply post host index after continuously 1479 * processing the threshold number of Reply Descriptors. 1480 * So that FW can find enough entries to post the Reply 1481 * Descriptors in the reply descriptor post queue. 1482 */ 1483 if (completed_cmds > ioc->hba_queue_depth/3) { 1484 if (ioc->combined_reply_queue) { 1485 writel(reply_q->reply_post_host_index | 1486 ((msix_index & 7) << 1487 MPI2_RPHI_MSIX_INDEX_SHIFT), 1488 ioc->replyPostRegisterIndex[msix_index/8]); 1489 } else { 1490 writel(reply_q->reply_post_host_index | 1491 (msix_index << 1492 MPI2_RPHI_MSIX_INDEX_SHIFT), 1493 &ioc->chip->ReplyPostHostIndex); 1494 } 1495 completed_cmds = 1; 1496 } 1497 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1498 goto out; 1499 if (!reply_q->reply_post_host_index) 1500 rpf = reply_q->reply_post_free; 1501 else 1502 rpf++; 1503 } while (1); 1504 1505 out: 1506 1507 if (!completed_cmds) { 1508 atomic_dec(&reply_q->busy); 1509 return IRQ_NONE; 1510 } 1511 1512 if (ioc->is_warpdrive) { 1513 writel(reply_q->reply_post_host_index, 1514 ioc->reply_post_host_index[msix_index]); 1515 atomic_dec(&reply_q->busy); 1516 return IRQ_HANDLED; 1517 } 1518 1519 /* Update Reply Post Host Index. 1520 * For those HBA's which support combined reply queue feature 1521 * 1. Get the correct Supplemental Reply Post Host Index Register. 1522 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host 1523 * Index Register address bank i.e replyPostRegisterIndex[], 1524 * 2. Then update this register with new reply host index value 1525 * in ReplyPostIndex field and the MSIxIndex field with 1526 * msix_index value reduced to a value between 0 and 7, 1527 * using a modulo 8 operation. Since each Supplemental Reply Post 1528 * Host Index Register supports 8 MSI-X vectors. 1529 * 1530 * For other HBA's just update the Reply Post Host Index register with 1531 * new reply host index value in ReplyPostIndex Field and msix_index 1532 * value in MSIxIndex field. 1533 */ 1534 if (ioc->combined_reply_queue) 1535 writel(reply_q->reply_post_host_index | ((msix_index & 7) << 1536 MPI2_RPHI_MSIX_INDEX_SHIFT), 1537 ioc->replyPostRegisterIndex[msix_index/8]); 1538 else 1539 writel(reply_q->reply_post_host_index | (msix_index << 1540 MPI2_RPHI_MSIX_INDEX_SHIFT), 1541 &ioc->chip->ReplyPostHostIndex); 1542 atomic_dec(&reply_q->busy); 1543 return IRQ_HANDLED; 1544 } 1545 1546 /** 1547 * _base_is_controller_msix_enabled - is controller support muli-reply queues 1548 * @ioc: per adapter object 1549 * 1550 * Return: Whether or not MSI/X is enabled. 1551 */ 1552 static inline int 1553 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc) 1554 { 1555 return (ioc->facts.IOCCapabilities & 1556 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable; 1557 } 1558 1559 /** 1560 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts 1561 * @ioc: per adapter object 1562 * Context: non ISR conext 1563 * 1564 * Called when a Task Management request has completed. 1565 */ 1566 void 1567 mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc) 1568 { 1569 struct adapter_reply_queue *reply_q; 1570 1571 /* If MSIX capability is turned off 1572 * then multi-queues are not enabled 1573 */ 1574 if (!_base_is_controller_msix_enabled(ioc)) 1575 return; 1576 1577 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 1578 if (ioc->shost_recovery || ioc->remove_host || 1579 ioc->pci_error_recovery) 1580 return; 1581 /* TMs are on msix_index == 0 */ 1582 if (reply_q->msix_index == 0) 1583 continue; 1584 synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index)); 1585 } 1586 } 1587 1588 /** 1589 * mpt3sas_base_release_callback_handler - clear interrupt callback handler 1590 * @cb_idx: callback index 1591 */ 1592 void 1593 mpt3sas_base_release_callback_handler(u8 cb_idx) 1594 { 1595 mpt_callbacks[cb_idx] = NULL; 1596 } 1597 1598 /** 1599 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler 1600 * @cb_func: callback function 1601 * 1602 * Return: Index of @cb_func. 1603 */ 1604 u8 1605 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func) 1606 { 1607 u8 cb_idx; 1608 1609 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--) 1610 if (mpt_callbacks[cb_idx] == NULL) 1611 break; 1612 1613 mpt_callbacks[cb_idx] = cb_func; 1614 return cb_idx; 1615 } 1616 1617 /** 1618 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler 1619 */ 1620 void 1621 mpt3sas_base_initialize_callback_handler(void) 1622 { 1623 u8 cb_idx; 1624 1625 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++) 1626 mpt3sas_base_release_callback_handler(cb_idx); 1627 } 1628 1629 1630 /** 1631 * _base_build_zero_len_sge - build zero length sg entry 1632 * @ioc: per adapter object 1633 * @paddr: virtual address for SGE 1634 * 1635 * Create a zero length scatter gather entry to insure the IOCs hardware has 1636 * something to use if the target device goes brain dead and tries 1637 * to send data even when none is asked for. 1638 */ 1639 static void 1640 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr) 1641 { 1642 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT | 1643 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST | 1644 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) << 1645 MPI2_SGE_FLAGS_SHIFT); 1646 ioc->base_add_sg_single(paddr, flags_length, -1); 1647 } 1648 1649 /** 1650 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr. 1651 * @paddr: virtual address for SGE 1652 * @flags_length: SGE flags and data transfer length 1653 * @dma_addr: Physical address 1654 */ 1655 static void 1656 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1657 { 1658 Mpi2SGESimple32_t *sgel = paddr; 1659 1660 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING | 1661 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1662 sgel->FlagsLength = cpu_to_le32(flags_length); 1663 sgel->Address = cpu_to_le32(dma_addr); 1664 } 1665 1666 1667 /** 1668 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr. 1669 * @paddr: virtual address for SGE 1670 * @flags_length: SGE flags and data transfer length 1671 * @dma_addr: Physical address 1672 */ 1673 static void 1674 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr) 1675 { 1676 Mpi2SGESimple64_t *sgel = paddr; 1677 1678 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING | 1679 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT; 1680 sgel->FlagsLength = cpu_to_le32(flags_length); 1681 sgel->Address = cpu_to_le64(dma_addr); 1682 } 1683 1684 /** 1685 * _base_get_chain_buffer_tracker - obtain chain tracker 1686 * @ioc: per adapter object 1687 * @scmd: SCSI commands of the IO request 1688 * 1689 * Return: chain tracker from chain_lookup table using key as 1690 * smid and smid's chain_offset. 1691 */ 1692 static struct chain_tracker * 1693 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, 1694 struct scsi_cmnd *scmd) 1695 { 1696 struct chain_tracker *chain_req; 1697 struct scsiio_tracker *st = scsi_cmd_priv(scmd); 1698 u16 smid = st->smid; 1699 u8 chain_offset = 1700 atomic_read(&ioc->chain_lookup[smid - 1].chain_offset); 1701 1702 if (chain_offset == ioc->chains_needed_per_io) 1703 return NULL; 1704 1705 chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset]; 1706 atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset); 1707 return chain_req; 1708 } 1709 1710 1711 /** 1712 * _base_build_sg - build generic sg 1713 * @ioc: per adapter object 1714 * @psge: virtual address for SGE 1715 * @data_out_dma: physical address for WRITES 1716 * @data_out_sz: data xfer size for WRITES 1717 * @data_in_dma: physical address for READS 1718 * @data_in_sz: data xfer size for READS 1719 */ 1720 static void 1721 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge, 1722 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1723 size_t data_in_sz) 1724 { 1725 u32 sgl_flags; 1726 1727 if (!data_out_sz && !data_in_sz) { 1728 _base_build_zero_len_sge(ioc, psge); 1729 return; 1730 } 1731 1732 if (data_out_sz && data_in_sz) { 1733 /* WRITE sgel first */ 1734 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1735 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC); 1736 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1737 ioc->base_add_sg_single(psge, sgl_flags | 1738 data_out_sz, data_out_dma); 1739 1740 /* incr sgel */ 1741 psge += ioc->sge_size; 1742 1743 /* READ sgel last */ 1744 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1745 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1746 MPI2_SGE_FLAGS_END_OF_LIST); 1747 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1748 ioc->base_add_sg_single(psge, sgl_flags | 1749 data_in_sz, data_in_dma); 1750 } else if (data_out_sz) /* WRITE */ { 1751 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1752 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1753 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC); 1754 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1755 ioc->base_add_sg_single(psge, sgl_flags | 1756 data_out_sz, data_out_dma); 1757 } else if (data_in_sz) /* READ */ { 1758 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 1759 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER | 1760 MPI2_SGE_FLAGS_END_OF_LIST); 1761 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 1762 ioc->base_add_sg_single(psge, sgl_flags | 1763 data_in_sz, data_in_dma); 1764 } 1765 } 1766 1767 /* IEEE format sgls */ 1768 1769 /** 1770 * _base_build_nvme_prp - This function is called for NVMe end devices to build 1771 * a native SGL (NVMe PRP). The native SGL is built starting in the first PRP 1772 * entry of the NVMe message (PRP1). If the data buffer is small enough to be 1773 * described entirely using PRP1, then PRP2 is not used. If needed, PRP2 is 1774 * used to describe a larger data buffer. If the data buffer is too large to 1775 * describe using the two PRP entriess inside the NVMe message, then PRP1 1776 * describes the first data memory segment, and PRP2 contains a pointer to a PRP 1777 * list located elsewhere in memory to describe the remaining data memory 1778 * segments. The PRP list will be contiguous. 1779 * 1780 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 1781 * consists of a list of PRP entries to describe a number of noncontigous 1782 * physical memory segments as a single memory buffer, just as a SGL does. Note 1783 * however, that this function is only used by the IOCTL call, so the memory 1784 * given will be guaranteed to be contiguous. There is no need to translate 1785 * non-contiguous SGL into a PRP in this case. All PRPs will describe 1786 * contiguous space that is one page size each. 1787 * 1788 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 1789 * a PRP list pointer or a PRP element, depending upon the command. PRP2 1790 * contains the second PRP element if the memory being described fits within 2 1791 * PRP entries, or a PRP list pointer if the PRP spans more than two entries. 1792 * 1793 * A PRP list pointer contains the address of a PRP list, structured as a linear 1794 * array of PRP entries. Each PRP entry in this list describes a segment of 1795 * physical memory. 1796 * 1797 * Each 64-bit PRP entry comprises an address and an offset field. The address 1798 * always points at the beginning of a 4KB physical memory page, and the offset 1799 * describes where within that 4KB page the memory segment begins. Only the 1800 * first element in a PRP list may contain a non-zero offest, implying that all 1801 * memory segments following the first begin at the start of a 4KB page. 1802 * 1803 * Each PRP element normally describes 4KB of physical memory, with exceptions 1804 * for the first and last elements in the list. If the memory being described 1805 * by the list begins at a non-zero offset within the first 4KB page, then the 1806 * first PRP element will contain a non-zero offset indicating where the region 1807 * begins within the 4KB page. The last memory segment may end before the end 1808 * of the 4KB segment, depending upon the overall size of the memory being 1809 * described by the PRP list. 1810 * 1811 * Since PRP entries lack any indication of size, the overall data buffer length 1812 * is used to determine where the end of the data memory buffer is located, and 1813 * how many PRP entries are required to describe it. 1814 * 1815 * @ioc: per adapter object 1816 * @smid: system request message index for getting asscociated SGL 1817 * @nvme_encap_request: the NVMe request msg frame pointer 1818 * @data_out_dma: physical address for WRITES 1819 * @data_out_sz: data xfer size for WRITES 1820 * @data_in_dma: physical address for READS 1821 * @data_in_sz: data xfer size for READS 1822 */ 1823 static void 1824 _base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid, 1825 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, 1826 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 1827 size_t data_in_sz) 1828 { 1829 int prp_size = NVME_PRP_SIZE; 1830 __le64 *prp_entry, *prp1_entry, *prp2_entry; 1831 __le64 *prp_page; 1832 dma_addr_t prp_entry_dma, prp_page_dma, dma_addr; 1833 u32 offset, entry_len; 1834 u32 page_mask_result, page_mask; 1835 size_t length; 1836 struct mpt3sas_nvme_cmd *nvme_cmd = 1837 (void *)nvme_encap_request->NVMe_Command; 1838 1839 /* 1840 * Not all commands require a data transfer. If no data, just return 1841 * without constructing any PRP. 1842 */ 1843 if (!data_in_sz && !data_out_sz) 1844 return; 1845 prp1_entry = &nvme_cmd->prp1; 1846 prp2_entry = &nvme_cmd->prp2; 1847 prp_entry = prp1_entry; 1848 /* 1849 * For the PRP entries, use the specially allocated buffer of 1850 * contiguous memory. 1851 */ 1852 prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid); 1853 prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 1854 1855 /* 1856 * Check if we are within 1 entry of a page boundary we don't 1857 * want our first entry to be a PRP List entry. 1858 */ 1859 page_mask = ioc->page_size - 1; 1860 page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask; 1861 if (!page_mask_result) { 1862 /* Bump up to next page boundary. */ 1863 prp_page = (__le64 *)((u8 *)prp_page + prp_size); 1864 prp_page_dma = prp_page_dma + prp_size; 1865 } 1866 1867 /* 1868 * Set PRP physical pointer, which initially points to the current PRP 1869 * DMA memory page. 1870 */ 1871 prp_entry_dma = prp_page_dma; 1872 1873 /* Get physical address and length of the data buffer. */ 1874 if (data_in_sz) { 1875 dma_addr = data_in_dma; 1876 length = data_in_sz; 1877 } else { 1878 dma_addr = data_out_dma; 1879 length = data_out_sz; 1880 } 1881 1882 /* Loop while the length is not zero. */ 1883 while (length) { 1884 /* 1885 * Check if we need to put a list pointer here if we are at 1886 * page boundary - prp_size (8 bytes). 1887 */ 1888 page_mask_result = (prp_entry_dma + prp_size) & page_mask; 1889 if (!page_mask_result) { 1890 /* 1891 * This is the last entry in a PRP List, so we need to 1892 * put a PRP list pointer here. What this does is: 1893 * - bump the current memory pointer to the next 1894 * address, which will be the next full page. 1895 * - set the PRP Entry to point to that page. This 1896 * is now the PRP List pointer. 1897 * - bump the PRP Entry pointer the start of the 1898 * next page. Since all of this PRP memory is 1899 * contiguous, no need to get a new page - it's 1900 * just the next address. 1901 */ 1902 prp_entry_dma++; 1903 *prp_entry = cpu_to_le64(prp_entry_dma); 1904 prp_entry++; 1905 } 1906 1907 /* Need to handle if entry will be part of a page. */ 1908 offset = dma_addr & page_mask; 1909 entry_len = ioc->page_size - offset; 1910 1911 if (prp_entry == prp1_entry) { 1912 /* 1913 * Must fill in the first PRP pointer (PRP1) before 1914 * moving on. 1915 */ 1916 *prp1_entry = cpu_to_le64(dma_addr); 1917 1918 /* 1919 * Now point to the second PRP entry within the 1920 * command (PRP2). 1921 */ 1922 prp_entry = prp2_entry; 1923 } else if (prp_entry == prp2_entry) { 1924 /* 1925 * Should the PRP2 entry be a PRP List pointer or just 1926 * a regular PRP pointer? If there is more than one 1927 * more page of data, must use a PRP List pointer. 1928 */ 1929 if (length > ioc->page_size) { 1930 /* 1931 * PRP2 will contain a PRP List pointer because 1932 * more PRP's are needed with this command. The 1933 * list will start at the beginning of the 1934 * contiguous buffer. 1935 */ 1936 *prp2_entry = cpu_to_le64(prp_entry_dma); 1937 1938 /* 1939 * The next PRP Entry will be the start of the 1940 * first PRP List. 1941 */ 1942 prp_entry = prp_page; 1943 } else { 1944 /* 1945 * After this, the PRP Entries are complete. 1946 * This command uses 2 PRP's and no PRP list. 1947 */ 1948 *prp2_entry = cpu_to_le64(dma_addr); 1949 } 1950 } else { 1951 /* 1952 * Put entry in list and bump the addresses. 1953 * 1954 * After PRP1 and PRP2 are filled in, this will fill in 1955 * all remaining PRP entries in a PRP List, one per 1956 * each time through the loop. 1957 */ 1958 *prp_entry = cpu_to_le64(dma_addr); 1959 prp_entry++; 1960 prp_entry_dma++; 1961 } 1962 1963 /* 1964 * Bump the phys address of the command's data buffer by the 1965 * entry_len. 1966 */ 1967 dma_addr += entry_len; 1968 1969 /* Decrement length accounting for last partial page. */ 1970 if (entry_len > length) 1971 length = 0; 1972 else 1973 length -= entry_len; 1974 } 1975 } 1976 1977 /** 1978 * base_make_prp_nvme - 1979 * Prepare PRPs(Physical Region Page)- SGLs specific to NVMe drives only 1980 * 1981 * @ioc: per adapter object 1982 * @scmd: SCSI command from the mid-layer 1983 * @mpi_request: mpi request 1984 * @smid: msg Index 1985 * @sge_count: scatter gather element count. 1986 * 1987 * Return: true: PRPs are built 1988 * false: IEEE SGLs needs to be built 1989 */ 1990 static void 1991 base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc, 1992 struct scsi_cmnd *scmd, 1993 Mpi25SCSIIORequest_t *mpi_request, 1994 u16 smid, int sge_count) 1995 { 1996 int sge_len, num_prp_in_chain = 0; 1997 Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl; 1998 __le64 *curr_buff; 1999 dma_addr_t msg_dma, sge_addr, offset; 2000 u32 page_mask, page_mask_result; 2001 struct scatterlist *sg_scmd; 2002 u32 first_prp_len; 2003 int data_len = scsi_bufflen(scmd); 2004 u32 nvme_pg_size; 2005 2006 nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE); 2007 /* 2008 * Nvme has a very convoluted prp format. One prp is required 2009 * for each page or partial page. Driver need to split up OS sg_list 2010 * entries if it is longer than one page or cross a page 2011 * boundary. Driver also have to insert a PRP list pointer entry as 2012 * the last entry in each physical page of the PRP list. 2013 * 2014 * NOTE: The first PRP "entry" is actually placed in the first 2015 * SGL entry in the main message as IEEE 64 format. The 2nd 2016 * entry in the main message is the chain element, and the rest 2017 * of the PRP entries are built in the contiguous pcie buffer. 2018 */ 2019 page_mask = nvme_pg_size - 1; 2020 2021 /* 2022 * Native SGL is needed. 2023 * Put a chain element in main message frame that points to the first 2024 * chain buffer. 2025 * 2026 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 2027 * a native SGL. 2028 */ 2029 2030 /* Set main message chain element pointer */ 2031 main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2032 /* 2033 * For NVMe the chain element needs to be the 2nd SG entry in the main 2034 * message. 2035 */ 2036 main_chain_element = (Mpi25IeeeSgeChain64_t *) 2037 ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 2038 2039 /* 2040 * For the PRP entries, use the specially allocated buffer of 2041 * contiguous memory. Normal chain buffers can't be used 2042 * because each chain buffer would need to be the size of an OS 2043 * page (4k). 2044 */ 2045 curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid); 2046 msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid); 2047 2048 main_chain_element->Address = cpu_to_le64(msg_dma); 2049 main_chain_element->NextChainOffset = 0; 2050 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2051 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2052 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 2053 2054 /* Build first prp, sge need not to be page aligned*/ 2055 ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL; 2056 sg_scmd = scsi_sglist(scmd); 2057 sge_addr = sg_dma_address(sg_scmd); 2058 sge_len = sg_dma_len(sg_scmd); 2059 2060 offset = sge_addr & page_mask; 2061 first_prp_len = nvme_pg_size - offset; 2062 2063 ptr_first_sgl->Address = cpu_to_le64(sge_addr); 2064 ptr_first_sgl->Length = cpu_to_le32(first_prp_len); 2065 2066 data_len -= first_prp_len; 2067 2068 if (sge_len > first_prp_len) { 2069 sge_addr += first_prp_len; 2070 sge_len -= first_prp_len; 2071 } else if (data_len && (sge_len == first_prp_len)) { 2072 sg_scmd = sg_next(sg_scmd); 2073 sge_addr = sg_dma_address(sg_scmd); 2074 sge_len = sg_dma_len(sg_scmd); 2075 } 2076 2077 for (;;) { 2078 offset = sge_addr & page_mask; 2079 2080 /* Put PRP pointer due to page boundary*/ 2081 page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask; 2082 if (unlikely(!page_mask_result)) { 2083 scmd_printk(KERN_NOTICE, 2084 scmd, "page boundary curr_buff: 0x%p\n", 2085 curr_buff); 2086 msg_dma += 8; 2087 *curr_buff = cpu_to_le64(msg_dma); 2088 curr_buff++; 2089 num_prp_in_chain++; 2090 } 2091 2092 *curr_buff = cpu_to_le64(sge_addr); 2093 curr_buff++; 2094 msg_dma += 8; 2095 num_prp_in_chain++; 2096 2097 sge_addr += nvme_pg_size; 2098 sge_len -= nvme_pg_size; 2099 data_len -= nvme_pg_size; 2100 2101 if (data_len <= 0) 2102 break; 2103 2104 if (sge_len > 0) 2105 continue; 2106 2107 sg_scmd = sg_next(sg_scmd); 2108 sge_addr = sg_dma_address(sg_scmd); 2109 sge_len = sg_dma_len(sg_scmd); 2110 } 2111 2112 main_chain_element->Length = 2113 cpu_to_le32(num_prp_in_chain * sizeof(u64)); 2114 return; 2115 } 2116 2117 static bool 2118 base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc, 2119 struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count) 2120 { 2121 u32 data_length = 0; 2122 bool build_prp = true; 2123 2124 data_length = scsi_bufflen(scmd); 2125 2126 /* If Datalenth is <= 16K and number of SGE’s entries are <= 2 2127 * we built IEEE SGL 2128 */ 2129 if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2)) 2130 build_prp = false; 2131 2132 return build_prp; 2133 } 2134 2135 /** 2136 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to 2137 * determine if the driver needs to build a native SGL. If so, that native 2138 * SGL is built in the special contiguous buffers allocated especially for 2139 * PCIe SGL creation. If the driver will not build a native SGL, return 2140 * TRUE and a normal IEEE SGL will be built. Currently this routine 2141 * supports NVMe. 2142 * @ioc: per adapter object 2143 * @mpi_request: mf request pointer 2144 * @smid: system request message index 2145 * @scmd: scsi command 2146 * @pcie_device: points to the PCIe device's info 2147 * 2148 * Return: 0 if native SGL was built, 1 if no SGL was built 2149 */ 2150 static int 2151 _base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc, 2152 Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd, 2153 struct _pcie_device *pcie_device) 2154 { 2155 int sges_left; 2156 2157 /* Get the SG list pointer and info. */ 2158 sges_left = scsi_dma_map(scmd); 2159 if (sges_left < 0) { 2160 sdev_printk(KERN_ERR, scmd->device, 2161 "scsi_dma_map failed: request for %d bytes!\n", 2162 scsi_bufflen(scmd)); 2163 return 1; 2164 } 2165 2166 /* Check if we need to build a native SG list. */ 2167 if (base_is_prp_possible(ioc, pcie_device, 2168 scmd, sges_left) == 0) { 2169 /* We built a native SG list, just return. */ 2170 goto out; 2171 } 2172 2173 /* 2174 * Build native NVMe PRP. 2175 */ 2176 base_make_prp_nvme(ioc, scmd, mpi_request, 2177 smid, sges_left); 2178 2179 return 0; 2180 out: 2181 scsi_dma_unmap(scmd); 2182 return 1; 2183 } 2184 2185 /** 2186 * _base_add_sg_single_ieee - add sg element for IEEE format 2187 * @paddr: virtual address for SGE 2188 * @flags: SGE flags 2189 * @chain_offset: number of 128 byte elements from start of segment 2190 * @length: data transfer length 2191 * @dma_addr: Physical address 2192 */ 2193 static void 2194 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length, 2195 dma_addr_t dma_addr) 2196 { 2197 Mpi25IeeeSgeChain64_t *sgel = paddr; 2198 2199 sgel->Flags = flags; 2200 sgel->NextChainOffset = chain_offset; 2201 sgel->Length = cpu_to_le32(length); 2202 sgel->Address = cpu_to_le64(dma_addr); 2203 } 2204 2205 /** 2206 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format 2207 * @ioc: per adapter object 2208 * @paddr: virtual address for SGE 2209 * 2210 * Create a zero length scatter gather entry to insure the IOCs hardware has 2211 * something to use if the target device goes brain dead and tries 2212 * to send data even when none is asked for. 2213 */ 2214 static void 2215 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr) 2216 { 2217 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2218 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 2219 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 2220 2221 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1); 2222 } 2223 2224 /** 2225 * _base_build_sg_scmd - main sg creation routine 2226 * pcie_device is unused here! 2227 * @ioc: per adapter object 2228 * @scmd: scsi command 2229 * @smid: system request message index 2230 * @unused: unused pcie_device pointer 2231 * Context: none. 2232 * 2233 * The main routine that builds scatter gather table from a given 2234 * scsi request sent via the .queuecommand main handler. 2235 * 2236 * Return: 0 success, anything else error 2237 */ 2238 static int 2239 _base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc, 2240 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused) 2241 { 2242 Mpi2SCSIIORequest_t *mpi_request; 2243 dma_addr_t chain_dma; 2244 struct scatterlist *sg_scmd; 2245 void *sg_local, *chain; 2246 u32 chain_offset; 2247 u32 chain_length; 2248 u32 chain_flags; 2249 int sges_left; 2250 u32 sges_in_segment; 2251 u32 sgl_flags; 2252 u32 sgl_flags_last_element; 2253 u32 sgl_flags_end_buffer; 2254 struct chain_tracker *chain_req; 2255 2256 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2257 2258 /* init scatter gather flags */ 2259 sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT; 2260 if (scmd->sc_data_direction == DMA_TO_DEVICE) 2261 sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 2262 sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT) 2263 << MPI2_SGE_FLAGS_SHIFT; 2264 sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT | 2265 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST) 2266 << MPI2_SGE_FLAGS_SHIFT; 2267 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT; 2268 2269 sg_scmd = scsi_sglist(scmd); 2270 sges_left = scsi_dma_map(scmd); 2271 if (sges_left < 0) { 2272 sdev_printk(KERN_ERR, scmd->device, 2273 "pci_map_sg failed: request for %d bytes!\n", 2274 scsi_bufflen(scmd)); 2275 return -ENOMEM; 2276 } 2277 2278 sg_local = &mpi_request->SGL; 2279 sges_in_segment = ioc->max_sges_in_main_message; 2280 if (sges_left <= sges_in_segment) 2281 goto fill_in_last_segment; 2282 2283 mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) + 2284 (sges_in_segment * ioc->sge_size))/4; 2285 2286 /* fill in main message segment when there is a chain following */ 2287 while (sges_in_segment) { 2288 if (sges_in_segment == 1) 2289 ioc->base_add_sg_single(sg_local, 2290 sgl_flags_last_element | sg_dma_len(sg_scmd), 2291 sg_dma_address(sg_scmd)); 2292 else 2293 ioc->base_add_sg_single(sg_local, sgl_flags | 2294 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2295 sg_scmd = sg_next(sg_scmd); 2296 sg_local += ioc->sge_size; 2297 sges_left--; 2298 sges_in_segment--; 2299 } 2300 2301 /* initializing the chain flags and pointers */ 2302 chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT; 2303 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2304 if (!chain_req) 2305 return -1; 2306 chain = chain_req->chain_buffer; 2307 chain_dma = chain_req->chain_buffer_dma; 2308 do { 2309 sges_in_segment = (sges_left <= 2310 ioc->max_sges_in_chain_message) ? sges_left : 2311 ioc->max_sges_in_chain_message; 2312 chain_offset = (sges_left == sges_in_segment) ? 2313 0 : (sges_in_segment * ioc->sge_size)/4; 2314 chain_length = sges_in_segment * ioc->sge_size; 2315 if (chain_offset) { 2316 chain_offset = chain_offset << 2317 MPI2_SGE_CHAIN_OFFSET_SHIFT; 2318 chain_length += ioc->sge_size; 2319 } 2320 ioc->base_add_sg_single(sg_local, chain_flags | chain_offset | 2321 chain_length, chain_dma); 2322 sg_local = chain; 2323 if (!chain_offset) 2324 goto fill_in_last_segment; 2325 2326 /* fill in chain segments */ 2327 while (sges_in_segment) { 2328 if (sges_in_segment == 1) 2329 ioc->base_add_sg_single(sg_local, 2330 sgl_flags_last_element | 2331 sg_dma_len(sg_scmd), 2332 sg_dma_address(sg_scmd)); 2333 else 2334 ioc->base_add_sg_single(sg_local, sgl_flags | 2335 sg_dma_len(sg_scmd), 2336 sg_dma_address(sg_scmd)); 2337 sg_scmd = sg_next(sg_scmd); 2338 sg_local += ioc->sge_size; 2339 sges_left--; 2340 sges_in_segment--; 2341 } 2342 2343 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2344 if (!chain_req) 2345 return -1; 2346 chain = chain_req->chain_buffer; 2347 chain_dma = chain_req->chain_buffer_dma; 2348 } while (1); 2349 2350 2351 fill_in_last_segment: 2352 2353 /* fill the last segment */ 2354 while (sges_left) { 2355 if (sges_left == 1) 2356 ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer | 2357 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2358 else 2359 ioc->base_add_sg_single(sg_local, sgl_flags | 2360 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2361 sg_scmd = sg_next(sg_scmd); 2362 sg_local += ioc->sge_size; 2363 sges_left--; 2364 } 2365 2366 return 0; 2367 } 2368 2369 /** 2370 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format 2371 * @ioc: per adapter object 2372 * @scmd: scsi command 2373 * @smid: system request message index 2374 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be 2375 * constructed on need. 2376 * Context: none. 2377 * 2378 * The main routine that builds scatter gather table from a given 2379 * scsi request sent via the .queuecommand main handler. 2380 * 2381 * Return: 0 success, anything else error 2382 */ 2383 static int 2384 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc, 2385 struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device) 2386 { 2387 Mpi25SCSIIORequest_t *mpi_request; 2388 dma_addr_t chain_dma; 2389 struct scatterlist *sg_scmd; 2390 void *sg_local, *chain; 2391 u32 chain_offset; 2392 u32 chain_length; 2393 int sges_left; 2394 u32 sges_in_segment; 2395 u8 simple_sgl_flags; 2396 u8 simple_sgl_flags_last; 2397 u8 chain_sgl_flags; 2398 struct chain_tracker *chain_req; 2399 2400 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 2401 2402 /* init scatter gather flags */ 2403 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2404 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2405 simple_sgl_flags_last = simple_sgl_flags | 2406 MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2407 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 2408 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2409 2410 /* Check if we need to build a native SG list. */ 2411 if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request, 2412 smid, scmd, pcie_device) == 0)) { 2413 /* We built a native SG list, just return. */ 2414 return 0; 2415 } 2416 2417 sg_scmd = scsi_sglist(scmd); 2418 sges_left = scsi_dma_map(scmd); 2419 if (sges_left < 0) { 2420 sdev_printk(KERN_ERR, scmd->device, 2421 "pci_map_sg failed: request for %d bytes!\n", 2422 scsi_bufflen(scmd)); 2423 return -ENOMEM; 2424 } 2425 2426 sg_local = &mpi_request->SGL; 2427 sges_in_segment = (ioc->request_sz - 2428 offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee; 2429 if (sges_left <= sges_in_segment) 2430 goto fill_in_last_segment; 2431 2432 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) + 2433 (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee); 2434 2435 /* fill in main message segment when there is a chain following */ 2436 while (sges_in_segment > 1) { 2437 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2438 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2439 sg_scmd = sg_next(sg_scmd); 2440 sg_local += ioc->sge_size_ieee; 2441 sges_left--; 2442 sges_in_segment--; 2443 } 2444 2445 /* initializing the pointers */ 2446 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2447 if (!chain_req) 2448 return -1; 2449 chain = chain_req->chain_buffer; 2450 chain_dma = chain_req->chain_buffer_dma; 2451 do { 2452 sges_in_segment = (sges_left <= 2453 ioc->max_sges_in_chain_message) ? sges_left : 2454 ioc->max_sges_in_chain_message; 2455 chain_offset = (sges_left == sges_in_segment) ? 2456 0 : sges_in_segment; 2457 chain_length = sges_in_segment * ioc->sge_size_ieee; 2458 if (chain_offset) 2459 chain_length += ioc->sge_size_ieee; 2460 _base_add_sg_single_ieee(sg_local, chain_sgl_flags, 2461 chain_offset, chain_length, chain_dma); 2462 2463 sg_local = chain; 2464 if (!chain_offset) 2465 goto fill_in_last_segment; 2466 2467 /* fill in chain segments */ 2468 while (sges_in_segment) { 2469 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2470 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2471 sg_scmd = sg_next(sg_scmd); 2472 sg_local += ioc->sge_size_ieee; 2473 sges_left--; 2474 sges_in_segment--; 2475 } 2476 2477 chain_req = _base_get_chain_buffer_tracker(ioc, scmd); 2478 if (!chain_req) 2479 return -1; 2480 chain = chain_req->chain_buffer; 2481 chain_dma = chain_req->chain_buffer_dma; 2482 } while (1); 2483 2484 2485 fill_in_last_segment: 2486 2487 /* fill the last segment */ 2488 while (sges_left > 0) { 2489 if (sges_left == 1) 2490 _base_add_sg_single_ieee(sg_local, 2491 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd), 2492 sg_dma_address(sg_scmd)); 2493 else 2494 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0, 2495 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd)); 2496 sg_scmd = sg_next(sg_scmd); 2497 sg_local += ioc->sge_size_ieee; 2498 sges_left--; 2499 } 2500 2501 return 0; 2502 } 2503 2504 /** 2505 * _base_build_sg_ieee - build generic sg for IEEE format 2506 * @ioc: per adapter object 2507 * @psge: virtual address for SGE 2508 * @data_out_dma: physical address for WRITES 2509 * @data_out_sz: data xfer size for WRITES 2510 * @data_in_dma: physical address for READS 2511 * @data_in_sz: data xfer size for READS 2512 */ 2513 static void 2514 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, 2515 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma, 2516 size_t data_in_sz) 2517 { 2518 u8 sgl_flags; 2519 2520 if (!data_out_sz && !data_in_sz) { 2521 _base_build_zero_len_sge_ieee(ioc, psge); 2522 return; 2523 } 2524 2525 if (data_out_sz && data_in_sz) { 2526 /* WRITE sgel first */ 2527 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2528 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2529 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2530 data_out_dma); 2531 2532 /* incr sgel */ 2533 psge += ioc->sge_size_ieee; 2534 2535 /* READ sgel last */ 2536 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 2537 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2538 data_in_dma); 2539 } else if (data_out_sz) /* WRITE */ { 2540 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2541 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2542 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2543 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz, 2544 data_out_dma); 2545 } else if (data_in_sz) /* READ */ { 2546 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 2547 MPI25_IEEE_SGE_FLAGS_END_OF_LIST | 2548 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 2549 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz, 2550 data_in_dma); 2551 } 2552 } 2553 2554 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) 2555 2556 /** 2557 * _base_config_dma_addressing - set dma addressing 2558 * @ioc: per adapter object 2559 * @pdev: PCI device struct 2560 * 2561 * Return: 0 for success, non-zero for failure. 2562 */ 2563 static int 2564 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) 2565 { 2566 struct sysinfo s; 2567 u64 consistent_dma_mask; 2568 2569 if (ioc->is_mcpu_endpoint) 2570 goto try_32bit; 2571 2572 if (ioc->dma_mask) 2573 consistent_dma_mask = DMA_BIT_MASK(64); 2574 else 2575 consistent_dma_mask = DMA_BIT_MASK(32); 2576 2577 if (sizeof(dma_addr_t) > 4) { 2578 const uint64_t required_mask = 2579 dma_get_required_mask(&pdev->dev); 2580 if ((required_mask > DMA_BIT_MASK(32)) && 2581 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && 2582 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) { 2583 ioc->base_add_sg_single = &_base_add_sg_single_64; 2584 ioc->sge_size = sizeof(Mpi2SGESimple64_t); 2585 ioc->dma_mask = 64; 2586 goto out; 2587 } 2588 } 2589 2590 try_32bit: 2591 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 2592 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { 2593 ioc->base_add_sg_single = &_base_add_sg_single_32; 2594 ioc->sge_size = sizeof(Mpi2SGESimple32_t); 2595 ioc->dma_mask = 32; 2596 } else 2597 return -ENODEV; 2598 2599 out: 2600 si_meminfo(&s); 2601 pr_info(MPT3SAS_FMT 2602 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", 2603 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram)); 2604 2605 return 0; 2606 } 2607 2608 static int 2609 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, 2610 struct pci_dev *pdev) 2611 { 2612 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { 2613 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 2614 return -ENODEV; 2615 } 2616 return 0; 2617 } 2618 2619 /** 2620 * _base_check_enable_msix - checks MSIX capabable. 2621 * @ioc: per adapter object 2622 * 2623 * Check to see if card is capable of MSIX, and set number 2624 * of available msix vectors 2625 */ 2626 static int 2627 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc) 2628 { 2629 int base; 2630 u16 message_control; 2631 2632 /* Check whether controller SAS2008 B0 controller, 2633 * if it is SAS2008 B0 controller use IO-APIC instead of MSIX 2634 */ 2635 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 && 2636 ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) { 2637 return -EINVAL; 2638 } 2639 2640 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX); 2641 if (!base) { 2642 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n", 2643 ioc->name)); 2644 return -EINVAL; 2645 } 2646 2647 /* get msix vector count */ 2648 /* NUMA_IO not supported for older controllers */ 2649 if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 || 2650 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 || 2651 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 || 2652 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 || 2653 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 || 2654 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 || 2655 ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2) 2656 ioc->msix_vector_count = 1; 2657 else { 2658 pci_read_config_word(ioc->pdev, base + 2, &message_control); 2659 ioc->msix_vector_count = (message_control & 0x3FF) + 1; 2660 } 2661 dinitprintk(ioc, pr_info(MPT3SAS_FMT 2662 "msix is supported, vector_count(%d)\n", 2663 ioc->name, ioc->msix_vector_count)); 2664 return 0; 2665 } 2666 2667 /** 2668 * _base_free_irq - free irq 2669 * @ioc: per adapter object 2670 * 2671 * Freeing respective reply_queue from the list. 2672 */ 2673 static void 2674 _base_free_irq(struct MPT3SAS_ADAPTER *ioc) 2675 { 2676 struct adapter_reply_queue *reply_q, *next; 2677 2678 if (list_empty(&ioc->reply_queue_list)) 2679 return; 2680 2681 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) { 2682 list_del(&reply_q->list); 2683 free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index), 2684 reply_q); 2685 kfree(reply_q); 2686 } 2687 } 2688 2689 /** 2690 * _base_request_irq - request irq 2691 * @ioc: per adapter object 2692 * @index: msix index into vector table 2693 * 2694 * Inserting respective reply_queue into the list. 2695 */ 2696 static int 2697 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index) 2698 { 2699 struct pci_dev *pdev = ioc->pdev; 2700 struct adapter_reply_queue *reply_q; 2701 int r; 2702 2703 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL); 2704 if (!reply_q) { 2705 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n", 2706 ioc->name, (int)sizeof(struct adapter_reply_queue)); 2707 return -ENOMEM; 2708 } 2709 reply_q->ioc = ioc; 2710 reply_q->msix_index = index; 2711 2712 atomic_set(&reply_q->busy, 0); 2713 if (ioc->msix_enable) 2714 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d", 2715 ioc->driver_name, ioc->id, index); 2716 else 2717 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d", 2718 ioc->driver_name, ioc->id); 2719 r = request_irq(pci_irq_vector(pdev, index), _base_interrupt, 2720 IRQF_SHARED, reply_q->name, reply_q); 2721 if (r) { 2722 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n", 2723 reply_q->name, pci_irq_vector(pdev, index)); 2724 kfree(reply_q); 2725 return -EBUSY; 2726 } 2727 2728 INIT_LIST_HEAD(&reply_q->list); 2729 list_add_tail(&reply_q->list, &ioc->reply_queue_list); 2730 return 0; 2731 } 2732 2733 /** 2734 * _base_assign_reply_queues - assigning msix index for each cpu 2735 * @ioc: per adapter object 2736 * 2737 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity 2738 * 2739 * It would nice if we could call irq_set_affinity, however it is not 2740 * an exported symbol 2741 */ 2742 static void 2743 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc) 2744 { 2745 unsigned int cpu, nr_cpus, nr_msix, index = 0; 2746 struct adapter_reply_queue *reply_q; 2747 2748 if (!_base_is_controller_msix_enabled(ioc)) 2749 return; 2750 2751 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz); 2752 2753 nr_cpus = num_online_cpus(); 2754 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count, 2755 ioc->facts.MaxMSIxVectors); 2756 if (!nr_msix) 2757 return; 2758 2759 if (smp_affinity_enable) { 2760 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 2761 const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev, 2762 reply_q->msix_index); 2763 if (!mask) { 2764 pr_warn(MPT3SAS_FMT "no affinity for msi %x\n", 2765 ioc->name, reply_q->msix_index); 2766 continue; 2767 } 2768 2769 for_each_cpu_and(cpu, mask, cpu_online_mask) { 2770 if (cpu >= ioc->cpu_msix_table_sz) 2771 break; 2772 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 2773 } 2774 } 2775 return; 2776 } 2777 cpu = cpumask_first(cpu_online_mask); 2778 2779 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 2780 2781 unsigned int i, group = nr_cpus / nr_msix; 2782 2783 if (cpu >= nr_cpus) 2784 break; 2785 2786 if (index < nr_cpus % nr_msix) 2787 group++; 2788 2789 for (i = 0 ; i < group ; i++) { 2790 ioc->cpu_msix_table[cpu] = reply_q->msix_index; 2791 cpu = cpumask_next(cpu, cpu_online_mask); 2792 } 2793 index++; 2794 } 2795 } 2796 2797 /** 2798 * _base_disable_msix - disables msix 2799 * @ioc: per adapter object 2800 * 2801 */ 2802 static void 2803 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc) 2804 { 2805 if (!ioc->msix_enable) 2806 return; 2807 pci_disable_msix(ioc->pdev); 2808 ioc->msix_enable = 0; 2809 } 2810 2811 /** 2812 * _base_enable_msix - enables msix, failback to io_apic 2813 * @ioc: per adapter object 2814 * 2815 */ 2816 static int 2817 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc) 2818 { 2819 int r; 2820 int i, local_max_msix_vectors; 2821 u8 try_msix = 0; 2822 unsigned int irq_flags = PCI_IRQ_MSIX; 2823 2824 if (msix_disable == -1 || msix_disable == 0) 2825 try_msix = 1; 2826 2827 if (!try_msix) 2828 goto try_ioapic; 2829 2830 if (_base_check_enable_msix(ioc) != 0) 2831 goto try_ioapic; 2832 2833 ioc->reply_queue_count = min_t(int, ioc->cpu_count, 2834 ioc->msix_vector_count); 2835 2836 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores" 2837 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count, 2838 ioc->cpu_count, max_msix_vectors); 2839 2840 if (!ioc->rdpq_array_enable && max_msix_vectors == -1) 2841 local_max_msix_vectors = (reset_devices) ? 1 : 8; 2842 else 2843 local_max_msix_vectors = max_msix_vectors; 2844 2845 if (local_max_msix_vectors > 0) 2846 ioc->reply_queue_count = min_t(int, local_max_msix_vectors, 2847 ioc->reply_queue_count); 2848 else if (local_max_msix_vectors == 0) 2849 goto try_ioapic; 2850 2851 if (ioc->msix_vector_count < ioc->cpu_count) 2852 smp_affinity_enable = 0; 2853 2854 if (smp_affinity_enable) 2855 irq_flags |= PCI_IRQ_AFFINITY; 2856 2857 r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count, 2858 irq_flags); 2859 if (r < 0) { 2860 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2861 "pci_alloc_irq_vectors failed (r=%d) !!!\n", 2862 ioc->name, r)); 2863 goto try_ioapic; 2864 } 2865 2866 ioc->msix_enable = 1; 2867 ioc->reply_queue_count = r; 2868 for (i = 0; i < ioc->reply_queue_count; i++) { 2869 r = _base_request_irq(ioc, i); 2870 if (r) { 2871 _base_free_irq(ioc); 2872 _base_disable_msix(ioc); 2873 goto try_ioapic; 2874 } 2875 } 2876 2877 return 0; 2878 2879 /* failback to io_apic interrupt routing */ 2880 try_ioapic: 2881 2882 ioc->reply_queue_count = 1; 2883 r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY); 2884 if (r < 0) { 2885 dfailprintk(ioc, pr_info(MPT3SAS_FMT 2886 "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n", 2887 ioc->name, r)); 2888 } else 2889 r = _base_request_irq(ioc, 0); 2890 2891 return r; 2892 } 2893 2894 /** 2895 * mpt3sas_base_unmap_resources - free controller resources 2896 * @ioc: per adapter object 2897 */ 2898 static void 2899 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) 2900 { 2901 struct pci_dev *pdev = ioc->pdev; 2902 2903 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n", 2904 ioc->name, __func__)); 2905 2906 _base_free_irq(ioc); 2907 _base_disable_msix(ioc); 2908 2909 kfree(ioc->replyPostRegisterIndex); 2910 ioc->replyPostRegisterIndex = NULL; 2911 2912 2913 if (ioc->chip_phys) { 2914 iounmap(ioc->chip); 2915 ioc->chip_phys = 0; 2916 } 2917 2918 if (pci_is_enabled(pdev)) { 2919 pci_release_selected_regions(ioc->pdev, ioc->bars); 2920 pci_disable_pcie_error_reporting(pdev); 2921 pci_disable_device(pdev); 2922 } 2923 } 2924 2925 /** 2926 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap) 2927 * @ioc: per adapter object 2928 * 2929 * Return: 0 for success, non-zero for failure. 2930 */ 2931 int 2932 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) 2933 { 2934 struct pci_dev *pdev = ioc->pdev; 2935 u32 memap_sz; 2936 u32 pio_sz; 2937 int i, r = 0; 2938 u64 pio_chip = 0; 2939 phys_addr_t chip_phys = 0; 2940 struct adapter_reply_queue *reply_q; 2941 2942 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", 2943 ioc->name, __func__)); 2944 2945 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 2946 if (pci_enable_device_mem(pdev)) { 2947 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n", 2948 ioc->name); 2949 ioc->bars = 0; 2950 return -ENODEV; 2951 } 2952 2953 2954 if (pci_request_selected_regions(pdev, ioc->bars, 2955 ioc->driver_name)) { 2956 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n", 2957 ioc->name); 2958 ioc->bars = 0; 2959 r = -ENODEV; 2960 goto out_fail; 2961 } 2962 2963 /* AER (Advanced Error Reporting) hooks */ 2964 pci_enable_pcie_error_reporting(pdev); 2965 2966 pci_set_master(pdev); 2967 2968 2969 if (_base_config_dma_addressing(ioc, pdev) != 0) { 2970 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n", 2971 ioc->name, pci_name(pdev)); 2972 r = -ENODEV; 2973 goto out_fail; 2974 } 2975 2976 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) && 2977 (!memap_sz || !pio_sz); i++) { 2978 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) { 2979 if (pio_sz) 2980 continue; 2981 pio_chip = (u64)pci_resource_start(pdev, i); 2982 pio_sz = pci_resource_len(pdev, i); 2983 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 2984 if (memap_sz) 2985 continue; 2986 ioc->chip_phys = pci_resource_start(pdev, i); 2987 chip_phys = ioc->chip_phys; 2988 memap_sz = pci_resource_len(pdev, i); 2989 ioc->chip = ioremap(ioc->chip_phys, memap_sz); 2990 } 2991 } 2992 2993 if (ioc->chip == NULL) { 2994 pr_err(MPT3SAS_FMT "unable to map adapter memory! " 2995 " or resource not found\n", ioc->name); 2996 r = -EINVAL; 2997 goto out_fail; 2998 } 2999 3000 _base_mask_interrupts(ioc); 3001 3002 r = _base_get_ioc_facts(ioc); 3003 if (r) 3004 goto out_fail; 3005 3006 if (!ioc->rdpq_array_enable_assigned) { 3007 ioc->rdpq_array_enable = ioc->rdpq_array_capable; 3008 ioc->rdpq_array_enable_assigned = 1; 3009 } 3010 3011 r = _base_enable_msix(ioc); 3012 if (r) 3013 goto out_fail; 3014 3015 /* Use the Combined reply queue feature only for SAS3 C0 & higher 3016 * revision HBAs and also only when reply queue count is greater than 8 3017 */ 3018 if (ioc->combined_reply_queue) { 3019 /* Determine the Supplemental Reply Post Host Index Registers 3020 * Addresse. Supplemental Reply Post Host Index Registers 3021 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and 3022 * each register is at offset bytes of 3023 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one. 3024 */ 3025 ioc->replyPostRegisterIndex = kcalloc( 3026 ioc->combined_reply_index_count, 3027 sizeof(resource_size_t *), GFP_KERNEL); 3028 if (!ioc->replyPostRegisterIndex) { 3029 dfailprintk(ioc, printk(MPT3SAS_FMT 3030 "allocation for reply Post Register Index failed!!!\n", 3031 ioc->name)); 3032 r = -ENOMEM; 3033 goto out_fail; 3034 } 3035 3036 for (i = 0; i < ioc->combined_reply_index_count; i++) { 3037 ioc->replyPostRegisterIndex[i] = (resource_size_t *) 3038 ((u8 __force *)&ioc->chip->Doorbell + 3039 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + 3040 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); 3041 } 3042 } 3043 3044 if (ioc->is_warpdrive) { 3045 ioc->reply_post_host_index[0] = (resource_size_t __iomem *) 3046 &ioc->chip->ReplyPostHostIndex; 3047 3048 for (i = 1; i < ioc->cpu_msix_table_sz; i++) 3049 ioc->reply_post_host_index[i] = 3050 (resource_size_t __iomem *) 3051 ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1) 3052 * 4))); 3053 } 3054 3055 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) 3056 pr_info(MPT3SAS_FMT "%s: IRQ %d\n", 3057 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" : 3058 "IO-APIC enabled"), 3059 pci_irq_vector(ioc->pdev, reply_q->msix_index)); 3060 3061 pr_info(MPT3SAS_FMT "iomem(%pap), mapped(0x%p), size(%d)\n", 3062 ioc->name, &chip_phys, ioc->chip, memap_sz); 3063 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n", 3064 ioc->name, (unsigned long long)pio_chip, pio_sz); 3065 3066 /* Save PCI configuration state for recovery from PCI AER/EEH errors */ 3067 pci_save_state(pdev); 3068 return 0; 3069 3070 out_fail: 3071 mpt3sas_base_unmap_resources(ioc); 3072 return r; 3073 } 3074 3075 /** 3076 * mpt3sas_base_get_msg_frame - obtain request mf pointer 3077 * @ioc: per adapter object 3078 * @smid: system request message index(smid zero is invalid) 3079 * 3080 * Return: virt pointer to message frame. 3081 */ 3082 void * 3083 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3084 { 3085 return (void *)(ioc->request + (smid * ioc->request_sz)); 3086 } 3087 3088 /** 3089 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr 3090 * @ioc: per adapter object 3091 * @smid: system request message index 3092 * 3093 * Return: virt pointer to sense buffer. 3094 */ 3095 void * 3096 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3097 { 3098 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE)); 3099 } 3100 3101 /** 3102 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr 3103 * @ioc: per adapter object 3104 * @smid: system request message index 3105 * 3106 * Return: phys pointer to the low 32bit address of the sense buffer. 3107 */ 3108 __le32 3109 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3110 { 3111 return cpu_to_le32(ioc->sense_dma + ((smid - 1) * 3112 SCSI_SENSE_BUFFERSIZE)); 3113 } 3114 3115 /** 3116 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr 3117 * @ioc: per adapter object 3118 * @smid: system request message index 3119 * 3120 * Return: virt pointer to a PCIe SGL. 3121 */ 3122 void * 3123 mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3124 { 3125 return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl); 3126 } 3127 3128 /** 3129 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr 3130 * @ioc: per adapter object 3131 * @smid: system request message index 3132 * 3133 * Return: phys pointer to the address of the PCIe buffer. 3134 */ 3135 dma_addr_t 3136 mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3137 { 3138 return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma; 3139 } 3140 3141 /** 3142 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address 3143 * @ioc: per adapter object 3144 * @phys_addr: lower 32 physical addr of the reply 3145 * 3146 * Converts 32bit lower physical addr into a virt address. 3147 */ 3148 void * 3149 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr) 3150 { 3151 if (!phys_addr) 3152 return NULL; 3153 return ioc->reply + (phys_addr - (u32)ioc->reply_dma); 3154 } 3155 3156 static inline u8 3157 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc) 3158 { 3159 return ioc->cpu_msix_table[raw_smp_processor_id()]; 3160 } 3161 3162 /** 3163 * mpt3sas_base_get_smid - obtain a free smid from internal queue 3164 * @ioc: per adapter object 3165 * @cb_idx: callback index 3166 * 3167 * Return: smid (zero is invalid) 3168 */ 3169 u16 3170 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3171 { 3172 unsigned long flags; 3173 struct request_tracker *request; 3174 u16 smid; 3175 3176 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3177 if (list_empty(&ioc->internal_free_list)) { 3178 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3179 pr_err(MPT3SAS_FMT "%s: smid not available\n", 3180 ioc->name, __func__); 3181 return 0; 3182 } 3183 3184 request = list_entry(ioc->internal_free_list.next, 3185 struct request_tracker, tracker_list); 3186 request->cb_idx = cb_idx; 3187 smid = request->smid; 3188 list_del(&request->tracker_list); 3189 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3190 return smid; 3191 } 3192 3193 /** 3194 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue 3195 * @ioc: per adapter object 3196 * @cb_idx: callback index 3197 * @scmd: pointer to scsi command object 3198 * 3199 * Return: smid (zero is invalid) 3200 */ 3201 u16 3202 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx, 3203 struct scsi_cmnd *scmd) 3204 { 3205 struct scsiio_tracker *request = scsi_cmd_priv(scmd); 3206 unsigned int tag = scmd->request->tag; 3207 u16 smid; 3208 3209 smid = tag + 1; 3210 request->cb_idx = cb_idx; 3211 request->msix_io = _base_get_msix_index(ioc); 3212 request->smid = smid; 3213 INIT_LIST_HEAD(&request->chain_list); 3214 return smid; 3215 } 3216 3217 /** 3218 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue 3219 * @ioc: per adapter object 3220 * @cb_idx: callback index 3221 * 3222 * Return: smid (zero is invalid) 3223 */ 3224 u16 3225 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx) 3226 { 3227 unsigned long flags; 3228 struct request_tracker *request; 3229 u16 smid; 3230 3231 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3232 if (list_empty(&ioc->hpr_free_list)) { 3233 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3234 return 0; 3235 } 3236 3237 request = list_entry(ioc->hpr_free_list.next, 3238 struct request_tracker, tracker_list); 3239 request->cb_idx = cb_idx; 3240 smid = request->smid; 3241 list_del(&request->tracker_list); 3242 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3243 return smid; 3244 } 3245 3246 static void 3247 _base_recovery_check(struct MPT3SAS_ADAPTER *ioc) 3248 { 3249 /* 3250 * See _wait_for_commands_to_complete() call with regards to this code. 3251 */ 3252 if (ioc->shost_recovery && ioc->pending_io_count) { 3253 ioc->pending_io_count = scsi_host_busy(ioc->shost); 3254 if (ioc->pending_io_count == 0) 3255 wake_up(&ioc->reset_wq); 3256 } 3257 } 3258 3259 void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc, 3260 struct scsiio_tracker *st) 3261 { 3262 if (WARN_ON(st->smid == 0)) 3263 return; 3264 st->cb_idx = 0xFF; 3265 st->direct_io = 0; 3266 atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0); 3267 st->smid = 0; 3268 } 3269 3270 /** 3271 * mpt3sas_base_free_smid - put smid back on free_list 3272 * @ioc: per adapter object 3273 * @smid: system request message index 3274 */ 3275 void 3276 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3277 { 3278 unsigned long flags; 3279 int i; 3280 3281 if (smid < ioc->hi_priority_smid) { 3282 struct scsiio_tracker *st; 3283 3284 st = _get_st_from_smid(ioc, smid); 3285 if (!st) { 3286 _base_recovery_check(ioc); 3287 return; 3288 } 3289 mpt3sas_base_clear_st(ioc, st); 3290 _base_recovery_check(ioc); 3291 return; 3292 } 3293 3294 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 3295 if (smid < ioc->internal_smid) { 3296 /* hi-priority */ 3297 i = smid - ioc->hi_priority_smid; 3298 ioc->hpr_lookup[i].cb_idx = 0xFF; 3299 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list); 3300 } else if (smid <= ioc->hba_queue_depth) { 3301 /* internal queue */ 3302 i = smid - ioc->internal_smid; 3303 ioc->internal_lookup[i].cb_idx = 0xFF; 3304 list_add(&ioc->internal_lookup[i].tracker_list, 3305 &ioc->internal_free_list); 3306 } 3307 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 3308 } 3309 3310 /** 3311 * _base_mpi_ep_writeq - 32 bit write to MMIO 3312 * @b: data payload 3313 * @addr: address in MMIO space 3314 * @writeq_lock: spin lock 3315 * 3316 * This special handling for MPI EP to take care of 32 bit 3317 * environment where its not quarenteed to send the entire word 3318 * in one transfer. 3319 */ 3320 static inline void 3321 _base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr, 3322 spinlock_t *writeq_lock) 3323 { 3324 unsigned long flags; 3325 3326 spin_lock_irqsave(writeq_lock, flags); 3327 __raw_writel((u32)(b), addr); 3328 __raw_writel((u32)(b >> 32), (addr + 4)); 3329 mmiowb(); 3330 spin_unlock_irqrestore(writeq_lock, flags); 3331 } 3332 3333 /** 3334 * _base_writeq - 64 bit write to MMIO 3335 * @b: data payload 3336 * @addr: address in MMIO space 3337 * @writeq_lock: spin lock 3338 * 3339 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes 3340 * care of 32 bit environment where its not quarenteed to send the entire word 3341 * in one transfer. 3342 */ 3343 #if defined(writeq) && defined(CONFIG_64BIT) 3344 static inline void 3345 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 3346 { 3347 __raw_writeq(b, addr); 3348 mmiowb(); 3349 } 3350 #else 3351 static inline void 3352 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock) 3353 { 3354 _base_mpi_ep_writeq(b, addr, writeq_lock); 3355 } 3356 #endif 3357 3358 /** 3359 * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware 3360 * @ioc: per adapter object 3361 * @smid: system request message index 3362 * @handle: device handle 3363 */ 3364 static void 3365 _base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 3366 { 3367 Mpi2RequestDescriptorUnion_t descriptor; 3368 u64 *request = (u64 *)&descriptor; 3369 void *mpi_req_iomem; 3370 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 3371 3372 _clone_sg_entries(ioc, (void *) mfp, smid); 3373 mpi_req_iomem = (void __force *)ioc->chip + 3374 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 3375 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 3376 ioc->request_sz); 3377 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 3378 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 3379 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 3380 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 3381 descriptor.SCSIIO.LMID = 0; 3382 _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3383 &ioc->scsi_lookup_lock); 3384 } 3385 3386 /** 3387 * _base_put_smid_scsi_io - send SCSI_IO request to firmware 3388 * @ioc: per adapter object 3389 * @smid: system request message index 3390 * @handle: device handle 3391 */ 3392 static void 3393 _base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle) 3394 { 3395 Mpi2RequestDescriptorUnion_t descriptor; 3396 u64 *request = (u64 *)&descriptor; 3397 3398 3399 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 3400 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 3401 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 3402 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 3403 descriptor.SCSIIO.LMID = 0; 3404 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3405 &ioc->scsi_lookup_lock); 3406 } 3407 3408 /** 3409 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware 3410 * @ioc: per adapter object 3411 * @smid: system request message index 3412 * @handle: device handle 3413 */ 3414 void 3415 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid, 3416 u16 handle) 3417 { 3418 Mpi2RequestDescriptorUnion_t descriptor; 3419 u64 *request = (u64 *)&descriptor; 3420 3421 descriptor.SCSIIO.RequestFlags = 3422 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 3423 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc); 3424 descriptor.SCSIIO.SMID = cpu_to_le16(smid); 3425 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle); 3426 descriptor.SCSIIO.LMID = 0; 3427 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3428 &ioc->scsi_lookup_lock); 3429 } 3430 3431 /** 3432 * mpt3sas_base_put_smid_hi_priority - send Task Management request to firmware 3433 * @ioc: per adapter object 3434 * @smid: system request message index 3435 * @msix_task: msix_task will be same as msix of IO incase of task abort else 0. 3436 */ 3437 void 3438 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid, 3439 u16 msix_task) 3440 { 3441 Mpi2RequestDescriptorUnion_t descriptor; 3442 void *mpi_req_iomem; 3443 u64 *request; 3444 3445 if (ioc->is_mcpu_endpoint) { 3446 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 3447 3448 /* TBD 256 is offset within sys register. */ 3449 mpi_req_iomem = (void __force *)ioc->chip 3450 + MPI_FRAME_START_OFFSET 3451 + (smid * ioc->request_sz); 3452 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 3453 ioc->request_sz); 3454 } 3455 3456 request = (u64 *)&descriptor; 3457 3458 descriptor.HighPriority.RequestFlags = 3459 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 3460 descriptor.HighPriority.MSIxIndex = msix_task; 3461 descriptor.HighPriority.SMID = cpu_to_le16(smid); 3462 descriptor.HighPriority.LMID = 0; 3463 descriptor.HighPriority.Reserved1 = 0; 3464 if (ioc->is_mcpu_endpoint) 3465 _base_mpi_ep_writeq(*request, 3466 &ioc->chip->RequestDescriptorPostLow, 3467 &ioc->scsi_lookup_lock); 3468 else 3469 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3470 &ioc->scsi_lookup_lock); 3471 } 3472 3473 /** 3474 * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to 3475 * firmware 3476 * @ioc: per adapter object 3477 * @smid: system request message index 3478 */ 3479 void 3480 mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3481 { 3482 Mpi2RequestDescriptorUnion_t descriptor; 3483 u64 *request = (u64 *)&descriptor; 3484 3485 descriptor.Default.RequestFlags = 3486 MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED; 3487 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 3488 descriptor.Default.SMID = cpu_to_le16(smid); 3489 descriptor.Default.LMID = 0; 3490 descriptor.Default.DescriptorTypeDependent = 0; 3491 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3492 &ioc->scsi_lookup_lock); 3493 } 3494 3495 /** 3496 * mpt3sas_base_put_smid_default - Default, primarily used for config pages 3497 * @ioc: per adapter object 3498 * @smid: system request message index 3499 */ 3500 void 3501 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid) 3502 { 3503 Mpi2RequestDescriptorUnion_t descriptor; 3504 void *mpi_req_iomem; 3505 u64 *request; 3506 3507 if (ioc->is_mcpu_endpoint) { 3508 __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid); 3509 3510 _clone_sg_entries(ioc, (void *) mfp, smid); 3511 /* TBD 256 is offset within sys register */ 3512 mpi_req_iomem = (void __force *)ioc->chip + 3513 MPI_FRAME_START_OFFSET + (smid * ioc->request_sz); 3514 _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp, 3515 ioc->request_sz); 3516 } 3517 request = (u64 *)&descriptor; 3518 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 3519 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc); 3520 descriptor.Default.SMID = cpu_to_le16(smid); 3521 descriptor.Default.LMID = 0; 3522 descriptor.Default.DescriptorTypeDependent = 0; 3523 if (ioc->is_mcpu_endpoint) 3524 _base_mpi_ep_writeq(*request, 3525 &ioc->chip->RequestDescriptorPostLow, 3526 &ioc->scsi_lookup_lock); 3527 else 3528 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow, 3529 &ioc->scsi_lookup_lock); 3530 } 3531 3532 /** 3533 * _base_display_OEMs_branding - Display branding string 3534 * @ioc: per adapter object 3535 */ 3536 static void 3537 _base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc) 3538 { 3539 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL) 3540 return; 3541 3542 switch (ioc->pdev->subsystem_vendor) { 3543 case PCI_VENDOR_ID_INTEL: 3544 switch (ioc->pdev->device) { 3545 case MPI2_MFGPAGE_DEVID_SAS2008: 3546 switch (ioc->pdev->subsystem_device) { 3547 case MPT2SAS_INTEL_RMS2LL080_SSDID: 3548 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3549 MPT2SAS_INTEL_RMS2LL080_BRANDING); 3550 break; 3551 case MPT2SAS_INTEL_RMS2LL040_SSDID: 3552 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3553 MPT2SAS_INTEL_RMS2LL040_BRANDING); 3554 break; 3555 case MPT2SAS_INTEL_SSD910_SSDID: 3556 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3557 MPT2SAS_INTEL_SSD910_BRANDING); 3558 break; 3559 default: 3560 pr_info(MPT3SAS_FMT 3561 "Intel(R) Controller: Subsystem ID: 0x%X\n", 3562 ioc->name, ioc->pdev->subsystem_device); 3563 break; 3564 } 3565 case MPI2_MFGPAGE_DEVID_SAS2308_2: 3566 switch (ioc->pdev->subsystem_device) { 3567 case MPT2SAS_INTEL_RS25GB008_SSDID: 3568 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3569 MPT2SAS_INTEL_RS25GB008_BRANDING); 3570 break; 3571 case MPT2SAS_INTEL_RMS25JB080_SSDID: 3572 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3573 MPT2SAS_INTEL_RMS25JB080_BRANDING); 3574 break; 3575 case MPT2SAS_INTEL_RMS25JB040_SSDID: 3576 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3577 MPT2SAS_INTEL_RMS25JB040_BRANDING); 3578 break; 3579 case MPT2SAS_INTEL_RMS25KB080_SSDID: 3580 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3581 MPT2SAS_INTEL_RMS25KB080_BRANDING); 3582 break; 3583 case MPT2SAS_INTEL_RMS25KB040_SSDID: 3584 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3585 MPT2SAS_INTEL_RMS25KB040_BRANDING); 3586 break; 3587 case MPT2SAS_INTEL_RMS25LB040_SSDID: 3588 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3589 MPT2SAS_INTEL_RMS25LB040_BRANDING); 3590 break; 3591 case MPT2SAS_INTEL_RMS25LB080_SSDID: 3592 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3593 MPT2SAS_INTEL_RMS25LB080_BRANDING); 3594 break; 3595 default: 3596 pr_info(MPT3SAS_FMT 3597 "Intel(R) Controller: Subsystem ID: 0x%X\n", 3598 ioc->name, ioc->pdev->subsystem_device); 3599 break; 3600 } 3601 case MPI25_MFGPAGE_DEVID_SAS3008: 3602 switch (ioc->pdev->subsystem_device) { 3603 case MPT3SAS_INTEL_RMS3JC080_SSDID: 3604 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3605 MPT3SAS_INTEL_RMS3JC080_BRANDING); 3606 break; 3607 3608 case MPT3SAS_INTEL_RS3GC008_SSDID: 3609 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3610 MPT3SAS_INTEL_RS3GC008_BRANDING); 3611 break; 3612 case MPT3SAS_INTEL_RS3FC044_SSDID: 3613 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3614 MPT3SAS_INTEL_RS3FC044_BRANDING); 3615 break; 3616 case MPT3SAS_INTEL_RS3UC080_SSDID: 3617 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3618 MPT3SAS_INTEL_RS3UC080_BRANDING); 3619 break; 3620 default: 3621 pr_info(MPT3SAS_FMT 3622 "Intel(R) Controller: Subsystem ID: 0x%X\n", 3623 ioc->name, ioc->pdev->subsystem_device); 3624 break; 3625 } 3626 break; 3627 default: 3628 pr_info(MPT3SAS_FMT 3629 "Intel(R) Controller: Subsystem ID: 0x%X\n", 3630 ioc->name, ioc->pdev->subsystem_device); 3631 break; 3632 } 3633 break; 3634 case PCI_VENDOR_ID_DELL: 3635 switch (ioc->pdev->device) { 3636 case MPI2_MFGPAGE_DEVID_SAS2008: 3637 switch (ioc->pdev->subsystem_device) { 3638 case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID: 3639 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3640 MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING); 3641 break; 3642 case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID: 3643 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3644 MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING); 3645 break; 3646 case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID: 3647 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3648 MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING); 3649 break; 3650 case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID: 3651 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3652 MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING); 3653 break; 3654 case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID: 3655 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3656 MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING); 3657 break; 3658 case MPT2SAS_DELL_PERC_H200_SSDID: 3659 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3660 MPT2SAS_DELL_PERC_H200_BRANDING); 3661 break; 3662 case MPT2SAS_DELL_6GBPS_SAS_SSDID: 3663 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3664 MPT2SAS_DELL_6GBPS_SAS_BRANDING); 3665 break; 3666 default: 3667 pr_info(MPT3SAS_FMT 3668 "Dell 6Gbps HBA: Subsystem ID: 0x%X\n", 3669 ioc->name, ioc->pdev->subsystem_device); 3670 break; 3671 } 3672 break; 3673 case MPI25_MFGPAGE_DEVID_SAS3008: 3674 switch (ioc->pdev->subsystem_device) { 3675 case MPT3SAS_DELL_12G_HBA_SSDID: 3676 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3677 MPT3SAS_DELL_12G_HBA_BRANDING); 3678 break; 3679 default: 3680 pr_info(MPT3SAS_FMT 3681 "Dell 12Gbps HBA: Subsystem ID: 0x%X\n", 3682 ioc->name, ioc->pdev->subsystem_device); 3683 break; 3684 } 3685 break; 3686 default: 3687 pr_info(MPT3SAS_FMT 3688 "Dell HBA: Subsystem ID: 0x%X\n", ioc->name, 3689 ioc->pdev->subsystem_device); 3690 break; 3691 } 3692 break; 3693 case PCI_VENDOR_ID_CISCO: 3694 switch (ioc->pdev->device) { 3695 case MPI25_MFGPAGE_DEVID_SAS3008: 3696 switch (ioc->pdev->subsystem_device) { 3697 case MPT3SAS_CISCO_12G_8E_HBA_SSDID: 3698 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3699 MPT3SAS_CISCO_12G_8E_HBA_BRANDING); 3700 break; 3701 case MPT3SAS_CISCO_12G_8I_HBA_SSDID: 3702 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3703 MPT3SAS_CISCO_12G_8I_HBA_BRANDING); 3704 break; 3705 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 3706 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3707 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 3708 break; 3709 default: 3710 pr_info(MPT3SAS_FMT 3711 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 3712 ioc->name, ioc->pdev->subsystem_device); 3713 break; 3714 } 3715 break; 3716 case MPI25_MFGPAGE_DEVID_SAS3108_1: 3717 switch (ioc->pdev->subsystem_device) { 3718 case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID: 3719 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3720 MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING); 3721 break; 3722 case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID: 3723 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3724 MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING 3725 ); 3726 break; 3727 default: 3728 pr_info(MPT3SAS_FMT 3729 "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n", 3730 ioc->name, ioc->pdev->subsystem_device); 3731 break; 3732 } 3733 break; 3734 default: 3735 pr_info(MPT3SAS_FMT 3736 "Cisco SAS HBA: Subsystem ID: 0x%X\n", 3737 ioc->name, ioc->pdev->subsystem_device); 3738 break; 3739 } 3740 break; 3741 case MPT2SAS_HP_3PAR_SSVID: 3742 switch (ioc->pdev->device) { 3743 case MPI2_MFGPAGE_DEVID_SAS2004: 3744 switch (ioc->pdev->subsystem_device) { 3745 case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID: 3746 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3747 MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING); 3748 break; 3749 default: 3750 pr_info(MPT3SAS_FMT 3751 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 3752 ioc->name, ioc->pdev->subsystem_device); 3753 break; 3754 } 3755 case MPI2_MFGPAGE_DEVID_SAS2308_2: 3756 switch (ioc->pdev->subsystem_device) { 3757 case MPT2SAS_HP_2_4_INTERNAL_SSDID: 3758 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3759 MPT2SAS_HP_2_4_INTERNAL_BRANDING); 3760 break; 3761 case MPT2SAS_HP_2_4_EXTERNAL_SSDID: 3762 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3763 MPT2SAS_HP_2_4_EXTERNAL_BRANDING); 3764 break; 3765 case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID: 3766 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3767 MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING); 3768 break; 3769 case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID: 3770 pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3771 MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING); 3772 break; 3773 default: 3774 pr_info(MPT3SAS_FMT 3775 "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n", 3776 ioc->name, ioc->pdev->subsystem_device); 3777 break; 3778 } 3779 default: 3780 pr_info(MPT3SAS_FMT 3781 "HP SAS HBA: Subsystem ID: 0x%X\n", 3782 ioc->name, ioc->pdev->subsystem_device); 3783 break; 3784 } 3785 default: 3786 break; 3787 } 3788 } 3789 3790 /** 3791 * _base_display_fwpkg_version - sends FWUpload request to pull FWPkg 3792 * version from FW Image Header. 3793 * @ioc: per adapter object 3794 * 3795 * Return: 0 for success, non-zero for failure. 3796 */ 3797 static int 3798 _base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc) 3799 { 3800 Mpi2FWImageHeader_t *FWImgHdr; 3801 Mpi25FWUploadRequest_t *mpi_request; 3802 Mpi2FWUploadReply_t mpi_reply; 3803 int r = 0; 3804 void *fwpkg_data = NULL; 3805 dma_addr_t fwpkg_data_dma; 3806 u16 smid, ioc_status; 3807 size_t data_length; 3808 3809 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 3810 __func__)); 3811 3812 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 3813 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 3814 ioc->name, __func__); 3815 return -EAGAIN; 3816 } 3817 3818 data_length = sizeof(Mpi2FWImageHeader_t); 3819 fwpkg_data = pci_alloc_consistent(ioc->pdev, data_length, 3820 &fwpkg_data_dma); 3821 if (!fwpkg_data) { 3822 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 3823 ioc->name, __FILE__, __LINE__, __func__); 3824 return -ENOMEM; 3825 } 3826 3827 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 3828 if (!smid) { 3829 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 3830 ioc->name, __func__); 3831 r = -EAGAIN; 3832 goto out; 3833 } 3834 3835 ioc->base_cmds.status = MPT3_CMD_PENDING; 3836 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 3837 ioc->base_cmds.smid = smid; 3838 memset(mpi_request, 0, sizeof(Mpi25FWUploadRequest_t)); 3839 mpi_request->Function = MPI2_FUNCTION_FW_UPLOAD; 3840 mpi_request->ImageType = MPI2_FW_UPLOAD_ITYPE_FW_FLASH; 3841 mpi_request->ImageSize = cpu_to_le32(data_length); 3842 ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma, 3843 data_length); 3844 init_completion(&ioc->base_cmds.done); 3845 mpt3sas_base_put_smid_default(ioc, smid); 3846 /* Wait for 15 seconds */ 3847 wait_for_completion_timeout(&ioc->base_cmds.done, 3848 FW_IMG_HDR_READ_TIMEOUT*HZ); 3849 pr_info(MPT3SAS_FMT "%s: complete\n", 3850 ioc->name, __func__); 3851 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 3852 pr_err(MPT3SAS_FMT "%s: timeout\n", 3853 ioc->name, __func__); 3854 _debug_dump_mf(mpi_request, 3855 sizeof(Mpi25FWUploadRequest_t)/4); 3856 r = -ETIME; 3857 } else { 3858 memset(&mpi_reply, 0, sizeof(Mpi2FWUploadReply_t)); 3859 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) { 3860 memcpy(&mpi_reply, ioc->base_cmds.reply, 3861 sizeof(Mpi2FWUploadReply_t)); 3862 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 3863 MPI2_IOCSTATUS_MASK; 3864 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 3865 FWImgHdr = (Mpi2FWImageHeader_t *)fwpkg_data; 3866 if (FWImgHdr->PackageVersion.Word) { 3867 pr_info(MPT3SAS_FMT "FW Package Version" 3868 "(%02d.%02d.%02d.%02d)\n", 3869 ioc->name, 3870 FWImgHdr->PackageVersion.Struct.Major, 3871 FWImgHdr->PackageVersion.Struct.Minor, 3872 FWImgHdr->PackageVersion.Struct.Unit, 3873 FWImgHdr->PackageVersion.Struct.Dev); 3874 } 3875 } else { 3876 _debug_dump_mf(&mpi_reply, 3877 sizeof(Mpi2FWUploadReply_t)/4); 3878 } 3879 } 3880 } 3881 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 3882 out: 3883 if (fwpkg_data) 3884 pci_free_consistent(ioc->pdev, data_length, fwpkg_data, 3885 fwpkg_data_dma); 3886 return r; 3887 } 3888 3889 /** 3890 * _base_display_ioc_capabilities - Disply IOC's capabilities. 3891 * @ioc: per adapter object 3892 */ 3893 static void 3894 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc) 3895 { 3896 int i = 0; 3897 char desc[16]; 3898 u32 iounit_pg1_flags; 3899 u32 bios_version; 3900 3901 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion); 3902 strncpy(desc, ioc->manu_pg0.ChipName, 16); 3903 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\ 3904 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n", 3905 ioc->name, desc, 3906 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24, 3907 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16, 3908 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8, 3909 ioc->facts.FWVersion.Word & 0x000000FF, 3910 ioc->pdev->revision, 3911 (bios_version & 0xFF000000) >> 24, 3912 (bios_version & 0x00FF0000) >> 16, 3913 (bios_version & 0x0000FF00) >> 8, 3914 bios_version & 0x000000FF); 3915 3916 _base_display_OEMs_branding(ioc); 3917 3918 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 3919 pr_info("%sNVMe", i ? "," : ""); 3920 i++; 3921 } 3922 3923 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name); 3924 3925 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 3926 pr_info("Initiator"); 3927 i++; 3928 } 3929 3930 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) { 3931 pr_info("%sTarget", i ? "," : ""); 3932 i++; 3933 } 3934 3935 i = 0; 3936 pr_info("), "); 3937 pr_info("Capabilities=("); 3938 3939 if (!ioc->hide_ir_msg) { 3940 if (ioc->facts.IOCCapabilities & 3941 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) { 3942 pr_info("Raid"); 3943 i++; 3944 } 3945 } 3946 3947 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) { 3948 pr_info("%sTLR", i ? "," : ""); 3949 i++; 3950 } 3951 3952 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) { 3953 pr_info("%sMulticast", i ? "," : ""); 3954 i++; 3955 } 3956 3957 if (ioc->facts.IOCCapabilities & 3958 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) { 3959 pr_info("%sBIDI Target", i ? "," : ""); 3960 i++; 3961 } 3962 3963 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) { 3964 pr_info("%sEEDP", i ? "," : ""); 3965 i++; 3966 } 3967 3968 if (ioc->facts.IOCCapabilities & 3969 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) { 3970 pr_info("%sSnapshot Buffer", i ? "," : ""); 3971 i++; 3972 } 3973 3974 if (ioc->facts.IOCCapabilities & 3975 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) { 3976 pr_info("%sDiag Trace Buffer", i ? "," : ""); 3977 i++; 3978 } 3979 3980 if (ioc->facts.IOCCapabilities & 3981 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) { 3982 pr_info("%sDiag Extended Buffer", i ? "," : ""); 3983 i++; 3984 } 3985 3986 if (ioc->facts.IOCCapabilities & 3987 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) { 3988 pr_info("%sTask Set Full", i ? "," : ""); 3989 i++; 3990 } 3991 3992 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 3993 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) { 3994 pr_info("%sNCQ", i ? "," : ""); 3995 i++; 3996 } 3997 3998 pr_info(")\n"); 3999 } 4000 4001 /** 4002 * mpt3sas_base_update_missing_delay - change the missing delay timers 4003 * @ioc: per adapter object 4004 * @device_missing_delay: amount of time till device is reported missing 4005 * @io_missing_delay: interval IO is returned when there is a missing device 4006 * 4007 * Passed on the command line, this function will modify the device missing 4008 * delay, as well as the io missing delay. This should be called at driver 4009 * load time. 4010 */ 4011 void 4012 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc, 4013 u16 device_missing_delay, u8 io_missing_delay) 4014 { 4015 u16 dmd, dmd_new, dmd_orignal; 4016 u8 io_missing_delay_original; 4017 u16 sz; 4018 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL; 4019 Mpi2ConfigReply_t mpi_reply; 4020 u8 num_phys = 0; 4021 u16 ioc_status; 4022 4023 mpt3sas_config_get_number_hba_phys(ioc, &num_phys); 4024 if (!num_phys) 4025 return; 4026 4027 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys * 4028 sizeof(Mpi2SasIOUnit1PhyData_t)); 4029 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL); 4030 if (!sas_iounit_pg1) { 4031 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 4032 ioc->name, __FILE__, __LINE__, __func__); 4033 goto out; 4034 } 4035 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply, 4036 sas_iounit_pg1, sz))) { 4037 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 4038 ioc->name, __FILE__, __LINE__, __func__); 4039 goto out; 4040 } 4041 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & 4042 MPI2_IOCSTATUS_MASK; 4043 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 4044 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n", 4045 ioc->name, __FILE__, __LINE__, __func__); 4046 goto out; 4047 } 4048 4049 /* device missing delay */ 4050 dmd = sas_iounit_pg1->ReportDeviceMissingDelay; 4051 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4052 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4053 else 4054 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4055 dmd_orignal = dmd; 4056 if (device_missing_delay > 0x7F) { 4057 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 : 4058 device_missing_delay; 4059 dmd = dmd / 16; 4060 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16; 4061 } else 4062 dmd = device_missing_delay; 4063 sas_iounit_pg1->ReportDeviceMissingDelay = dmd; 4064 4065 /* io missing delay */ 4066 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay; 4067 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay; 4068 4069 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1, 4070 sz)) { 4071 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16) 4072 dmd_new = (dmd & 4073 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16; 4074 else 4075 dmd_new = 4076 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK; 4077 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n", 4078 ioc->name, dmd_orignal, dmd_new); 4079 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n", 4080 ioc->name, io_missing_delay_original, 4081 io_missing_delay); 4082 ioc->device_missing_delay = dmd_new; 4083 ioc->io_missing_delay = io_missing_delay; 4084 } 4085 4086 out: 4087 kfree(sas_iounit_pg1); 4088 } 4089 4090 /** 4091 * _base_static_config_pages - static start of day config pages 4092 * @ioc: per adapter object 4093 */ 4094 static void 4095 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc) 4096 { 4097 Mpi2ConfigReply_t mpi_reply; 4098 u32 iounit_pg1_flags; 4099 4100 ioc->nvme_abort_timeout = 30; 4101 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0); 4102 if (ioc->ir_firmware) 4103 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply, 4104 &ioc->manu_pg10); 4105 4106 /* 4107 * Ensure correct T10 PI operation if vendor left EEDPTagMode 4108 * flag unset in NVDATA. 4109 */ 4110 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11); 4111 if (ioc->manu_pg11.EEDPTagMode == 0) { 4112 pr_err("%s: overriding NVDATA EEDPTagMode setting\n", 4113 ioc->name); 4114 ioc->manu_pg11.EEDPTagMode &= ~0x3; 4115 ioc->manu_pg11.EEDPTagMode |= 0x1; 4116 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply, 4117 &ioc->manu_pg11); 4118 } 4119 if (ioc->manu_pg11.AddlFlags2 & NVME_TASK_MNGT_CUSTOM_MASK) 4120 ioc->tm_custom_handling = 1; 4121 else { 4122 ioc->tm_custom_handling = 0; 4123 if (ioc->manu_pg11.NVMeAbortTO < NVME_TASK_ABORT_MIN_TIMEOUT) 4124 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MIN_TIMEOUT; 4125 else if (ioc->manu_pg11.NVMeAbortTO > 4126 NVME_TASK_ABORT_MAX_TIMEOUT) 4127 ioc->nvme_abort_timeout = NVME_TASK_ABORT_MAX_TIMEOUT; 4128 else 4129 ioc->nvme_abort_timeout = ioc->manu_pg11.NVMeAbortTO; 4130 } 4131 4132 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2); 4133 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3); 4134 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8); 4135 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0); 4136 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 4137 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8); 4138 _base_display_ioc_capabilities(ioc); 4139 4140 /* 4141 * Enable task_set_full handling in iounit_pg1 when the 4142 * facts capabilities indicate that its supported. 4143 */ 4144 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags); 4145 if ((ioc->facts.IOCCapabilities & 4146 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING)) 4147 iounit_pg1_flags &= 4148 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 4149 else 4150 iounit_pg1_flags |= 4151 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING; 4152 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags); 4153 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1); 4154 4155 if (ioc->iounit_pg8.NumSensors) 4156 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors; 4157 } 4158 4159 /** 4160 * mpt3sas_free_enclosure_list - release memory 4161 * @ioc: per adapter object 4162 * 4163 * Free memory allocated during encloure add. 4164 */ 4165 void 4166 mpt3sas_free_enclosure_list(struct MPT3SAS_ADAPTER *ioc) 4167 { 4168 struct _enclosure_node *enclosure_dev, *enclosure_dev_next; 4169 4170 /* Free enclosure list */ 4171 list_for_each_entry_safe(enclosure_dev, 4172 enclosure_dev_next, &ioc->enclosure_list, list) { 4173 list_del(&enclosure_dev->list); 4174 kfree(enclosure_dev); 4175 } 4176 } 4177 4178 /** 4179 * _base_release_memory_pools - release memory 4180 * @ioc: per adapter object 4181 * 4182 * Free memory allocated from _base_allocate_memory_pools. 4183 */ 4184 static void 4185 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) 4186 { 4187 int i = 0; 4188 int j = 0; 4189 struct chain_tracker *ct; 4190 struct reply_post_struct *rps; 4191 4192 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4193 __func__)); 4194 4195 if (ioc->request) { 4196 pci_free_consistent(ioc->pdev, ioc->request_dma_sz, 4197 ioc->request, ioc->request_dma); 4198 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4199 "request_pool(0x%p): free\n", 4200 ioc->name, ioc->request)); 4201 ioc->request = NULL; 4202 } 4203 4204 if (ioc->sense) { 4205 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 4206 dma_pool_destroy(ioc->sense_dma_pool); 4207 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4208 "sense_pool(0x%p): free\n", 4209 ioc->name, ioc->sense)); 4210 ioc->sense = NULL; 4211 } 4212 4213 if (ioc->reply) { 4214 dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma); 4215 dma_pool_destroy(ioc->reply_dma_pool); 4216 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4217 "reply_pool(0x%p): free\n", 4218 ioc->name, ioc->reply)); 4219 ioc->reply = NULL; 4220 } 4221 4222 if (ioc->reply_free) { 4223 dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free, 4224 ioc->reply_free_dma); 4225 dma_pool_destroy(ioc->reply_free_dma_pool); 4226 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4227 "reply_free_pool(0x%p): free\n", 4228 ioc->name, ioc->reply_free)); 4229 ioc->reply_free = NULL; 4230 } 4231 4232 if (ioc->reply_post) { 4233 do { 4234 rps = &ioc->reply_post[i]; 4235 if (rps->reply_post_free) { 4236 dma_pool_free( 4237 ioc->reply_post_free_dma_pool, 4238 rps->reply_post_free, 4239 rps->reply_post_free_dma); 4240 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4241 "reply_post_free_pool(0x%p): free\n", 4242 ioc->name, rps->reply_post_free)); 4243 rps->reply_post_free = NULL; 4244 } 4245 } while (ioc->rdpq_array_enable && 4246 (++i < ioc->reply_queue_count)); 4247 if (ioc->reply_post_free_array && 4248 ioc->rdpq_array_enable) { 4249 dma_pool_free(ioc->reply_post_free_array_dma_pool, 4250 ioc->reply_post_free_array, 4251 ioc->reply_post_free_array_dma); 4252 ioc->reply_post_free_array = NULL; 4253 } 4254 dma_pool_destroy(ioc->reply_post_free_array_dma_pool); 4255 dma_pool_destroy(ioc->reply_post_free_dma_pool); 4256 kfree(ioc->reply_post); 4257 } 4258 4259 if (ioc->pcie_sgl_dma_pool) { 4260 for (i = 0; i < ioc->scsiio_depth; i++) { 4261 dma_pool_free(ioc->pcie_sgl_dma_pool, 4262 ioc->pcie_sg_lookup[i].pcie_sgl, 4263 ioc->pcie_sg_lookup[i].pcie_sgl_dma); 4264 } 4265 if (ioc->pcie_sgl_dma_pool) 4266 dma_pool_destroy(ioc->pcie_sgl_dma_pool); 4267 } 4268 4269 if (ioc->config_page) { 4270 dexitprintk(ioc, pr_info(MPT3SAS_FMT 4271 "config_page(0x%p): free\n", ioc->name, 4272 ioc->config_page)); 4273 pci_free_consistent(ioc->pdev, ioc->config_page_sz, 4274 ioc->config_page, ioc->config_page_dma); 4275 } 4276 4277 kfree(ioc->hpr_lookup); 4278 kfree(ioc->internal_lookup); 4279 if (ioc->chain_lookup) { 4280 for (i = 0; i < ioc->scsiio_depth; i++) { 4281 for (j = ioc->chains_per_prp_buffer; 4282 j < ioc->chains_needed_per_io; j++) { 4283 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 4284 if (ct && ct->chain_buffer) 4285 dma_pool_free(ioc->chain_dma_pool, 4286 ct->chain_buffer, 4287 ct->chain_buffer_dma); 4288 } 4289 kfree(ioc->chain_lookup[i].chains_per_smid); 4290 } 4291 dma_pool_destroy(ioc->chain_dma_pool); 4292 kfree(ioc->chain_lookup); 4293 ioc->chain_lookup = NULL; 4294 } 4295 } 4296 4297 /** 4298 * is_MSB_are_same - checks whether all reply queues in a set are 4299 * having same upper 32bits in their base memory address. 4300 * @reply_pool_start_address: Base address of a reply queue set 4301 * @pool_sz: Size of single Reply Descriptor Post Queues pool size 4302 * 4303 * Return: 1 if reply queues in a set have a same upper 32bits in their base 4304 * memory address, else 0. 4305 */ 4306 4307 static int 4308 is_MSB_are_same(long reply_pool_start_address, u32 pool_sz) 4309 { 4310 long reply_pool_end_address; 4311 4312 reply_pool_end_address = reply_pool_start_address + pool_sz; 4313 4314 if (upper_32_bits(reply_pool_start_address) == 4315 upper_32_bits(reply_pool_end_address)) 4316 return 1; 4317 else 4318 return 0; 4319 } 4320 4321 /** 4322 * _base_allocate_memory_pools - allocate start of day memory pools 4323 * @ioc: per adapter object 4324 * 4325 * Return: 0 success, anything else error. 4326 */ 4327 static int 4328 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) 4329 { 4330 struct mpt3sas_facts *facts; 4331 u16 max_sge_elements; 4332 u16 chains_needed_per_io; 4333 u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; 4334 u32 retry_sz; 4335 u16 max_request_credit, nvme_blocks_needed; 4336 unsigned short sg_tablesize; 4337 u16 sge_size; 4338 int i, j; 4339 struct chain_tracker *ct; 4340 4341 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 4342 __func__)); 4343 4344 4345 retry_sz = 0; 4346 facts = &ioc->facts; 4347 4348 /* command line tunables for max sgl entries */ 4349 if (max_sgl_entries != -1) 4350 sg_tablesize = max_sgl_entries; 4351 else { 4352 if (ioc->hba_mpi_version_belonged == MPI2_VERSION) 4353 sg_tablesize = MPT2SAS_SG_DEPTH; 4354 else 4355 sg_tablesize = MPT3SAS_SG_DEPTH; 4356 } 4357 4358 /* max sgl entries <= MPT_KDUMP_MIN_PHYS_SEGMENTS in KDUMP mode */ 4359 if (reset_devices) 4360 sg_tablesize = min_t(unsigned short, sg_tablesize, 4361 MPT_KDUMP_MIN_PHYS_SEGMENTS); 4362 4363 if (ioc->is_mcpu_endpoint) 4364 ioc->shost->sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 4365 else { 4366 if (sg_tablesize < MPT_MIN_PHYS_SEGMENTS) 4367 sg_tablesize = MPT_MIN_PHYS_SEGMENTS; 4368 else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) { 4369 sg_tablesize = min_t(unsigned short, sg_tablesize, 4370 SG_MAX_SEGMENTS); 4371 pr_warn(MPT3SAS_FMT 4372 "sg_tablesize(%u) is bigger than kernel " 4373 "defined SG_CHUNK_SIZE(%u)\n", ioc->name, 4374 sg_tablesize, MPT_MAX_PHYS_SEGMENTS); 4375 } 4376 ioc->shost->sg_tablesize = sg_tablesize; 4377 } 4378 4379 ioc->internal_depth = min_t(int, (facts->HighPriorityCredit + (5)), 4380 (facts->RequestCredit / 4)); 4381 if (ioc->internal_depth < INTERNAL_CMDS_COUNT) { 4382 if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT + 4383 INTERNAL_SCSIIO_CMDS_COUNT)) { 4384 pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \ 4385 Credits, it has just %d number of credits\n", 4386 ioc->name, facts->RequestCredit); 4387 return -ENOMEM; 4388 } 4389 ioc->internal_depth = 10; 4390 } 4391 4392 ioc->hi_priority_depth = ioc->internal_depth - (5); 4393 /* command line tunables for max controller queue depth */ 4394 if (max_queue_depth != -1 && max_queue_depth != 0) { 4395 max_request_credit = min_t(u16, max_queue_depth + 4396 ioc->internal_depth, facts->RequestCredit); 4397 if (max_request_credit > MAX_HBA_QUEUE_DEPTH) 4398 max_request_credit = MAX_HBA_QUEUE_DEPTH; 4399 } else if (reset_devices) 4400 max_request_credit = min_t(u16, facts->RequestCredit, 4401 (MPT3SAS_KDUMP_SCSI_IO_DEPTH + ioc->internal_depth)); 4402 else 4403 max_request_credit = min_t(u16, facts->RequestCredit, 4404 MAX_HBA_QUEUE_DEPTH); 4405 4406 /* Firmware maintains additional facts->HighPriorityCredit number of 4407 * credits for HiPriprity Request messages, so hba queue depth will be 4408 * sum of max_request_credit and high priority queue depth. 4409 */ 4410 ioc->hba_queue_depth = max_request_credit + ioc->hi_priority_depth; 4411 4412 /* request frame size */ 4413 ioc->request_sz = facts->IOCRequestFrameSize * 4; 4414 4415 /* reply frame size */ 4416 ioc->reply_sz = facts->ReplyFrameSize * 4; 4417 4418 /* chain segment size */ 4419 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 4420 if (facts->IOCMaxChainSegmentSize) 4421 ioc->chain_segment_sz = 4422 facts->IOCMaxChainSegmentSize * 4423 MAX_CHAIN_ELEMT_SZ; 4424 else 4425 /* set to 128 bytes size if IOCMaxChainSegmentSize is zero */ 4426 ioc->chain_segment_sz = DEFAULT_NUM_FWCHAIN_ELEMTS * 4427 MAX_CHAIN_ELEMT_SZ; 4428 } else 4429 ioc->chain_segment_sz = ioc->request_sz; 4430 4431 /* calculate the max scatter element size */ 4432 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee); 4433 4434 retry_allocation: 4435 total_sz = 0; 4436 /* calculate number of sg elements left over in the 1st frame */ 4437 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) - 4438 sizeof(Mpi2SGEIOUnion_t)) + sge_size); 4439 ioc->max_sges_in_main_message = max_sge_elements/sge_size; 4440 4441 /* now do the same for a chain buffer */ 4442 max_sge_elements = ioc->chain_segment_sz - sge_size; 4443 ioc->max_sges_in_chain_message = max_sge_elements/sge_size; 4444 4445 /* 4446 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE 4447 */ 4448 chains_needed_per_io = ((ioc->shost->sg_tablesize - 4449 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message) 4450 + 1; 4451 if (chains_needed_per_io > facts->MaxChainDepth) { 4452 chains_needed_per_io = facts->MaxChainDepth; 4453 ioc->shost->sg_tablesize = min_t(u16, 4454 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message 4455 * chains_needed_per_io), ioc->shost->sg_tablesize); 4456 } 4457 ioc->chains_needed_per_io = chains_needed_per_io; 4458 4459 /* reply free queue sizing - taking into account for 64 FW events */ 4460 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 4461 4462 /* mCPU manage single counters for simplicity */ 4463 if (ioc->is_mcpu_endpoint) 4464 ioc->reply_post_queue_depth = ioc->reply_free_queue_depth; 4465 else { 4466 /* calculate reply descriptor post queue depth */ 4467 ioc->reply_post_queue_depth = ioc->hba_queue_depth + 4468 ioc->reply_free_queue_depth + 1; 4469 /* align the reply post queue on the next 16 count boundary */ 4470 if (ioc->reply_post_queue_depth % 16) 4471 ioc->reply_post_queue_depth += 16 - 4472 (ioc->reply_post_queue_depth % 16); 4473 } 4474 4475 if (ioc->reply_post_queue_depth > 4476 facts->MaxReplyDescriptorPostQueueDepth) { 4477 ioc->reply_post_queue_depth = 4478 facts->MaxReplyDescriptorPostQueueDepth - 4479 (facts->MaxReplyDescriptorPostQueueDepth % 16); 4480 ioc->hba_queue_depth = 4481 ((ioc->reply_post_queue_depth - 64) / 2) - 1; 4482 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64; 4483 } 4484 4485 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \ 4486 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), " 4487 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message, 4488 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize, 4489 ioc->chains_needed_per_io)); 4490 4491 /* reply post queue, 16 byte align */ 4492 reply_post_free_sz = ioc->reply_post_queue_depth * 4493 sizeof(Mpi2DefaultReplyDescriptor_t); 4494 4495 sz = reply_post_free_sz; 4496 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) 4497 sz *= ioc->reply_queue_count; 4498 4499 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? 4500 (ioc->reply_queue_count):1, 4501 sizeof(struct reply_post_struct), GFP_KERNEL); 4502 4503 if (!ioc->reply_post) { 4504 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n", 4505 ioc->name); 4506 goto out; 4507 } 4508 ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", 4509 &ioc->pdev->dev, sz, 16, 0); 4510 if (!ioc->reply_post_free_dma_pool) { 4511 pr_err(MPT3SAS_FMT 4512 "reply_post_free pool: dma_pool_create failed\n", 4513 ioc->name); 4514 goto out; 4515 } 4516 i = 0; 4517 do { 4518 ioc->reply_post[i].reply_post_free = 4519 dma_pool_alloc(ioc->reply_post_free_dma_pool, 4520 GFP_KERNEL, 4521 &ioc->reply_post[i].reply_post_free_dma); 4522 if (!ioc->reply_post[i].reply_post_free) { 4523 pr_err(MPT3SAS_FMT 4524 "reply_post_free pool: dma_pool_alloc failed\n", 4525 ioc->name); 4526 goto out; 4527 } 4528 memset(ioc->reply_post[i].reply_post_free, 0, sz); 4529 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4530 "reply post free pool (0x%p): depth(%d)," 4531 "element_size(%d), pool_size(%d kB)\n", ioc->name, 4532 ioc->reply_post[i].reply_post_free, 4533 ioc->reply_post_queue_depth, 8, sz/1024)); 4534 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4535 "reply_post_free_dma = (0x%llx)\n", ioc->name, 4536 (unsigned long long) 4537 ioc->reply_post[i].reply_post_free_dma)); 4538 total_sz += sz; 4539 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); 4540 4541 if (ioc->dma_mask == 64) { 4542 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { 4543 pr_warn(MPT3SAS_FMT 4544 "no suitable consistent DMA mask for %s\n", 4545 ioc->name, pci_name(ioc->pdev)); 4546 goto out; 4547 } 4548 } 4549 4550 ioc->scsiio_depth = ioc->hba_queue_depth - 4551 ioc->hi_priority_depth - ioc->internal_depth; 4552 4553 /* set the scsi host can_queue depth 4554 * with some internal commands that could be outstanding 4555 */ 4556 ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT; 4557 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4558 "scsi host: can_queue depth (%d)\n", 4559 ioc->name, ioc->shost->can_queue)); 4560 4561 4562 /* contiguous pool for request and chains, 16 byte align, one extra " 4563 * "frame for smid=0 4564 */ 4565 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth; 4566 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz); 4567 4568 /* hi-priority queue */ 4569 sz += (ioc->hi_priority_depth * ioc->request_sz); 4570 4571 /* internal queue */ 4572 sz += (ioc->internal_depth * ioc->request_sz); 4573 4574 ioc->request_dma_sz = sz; 4575 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma); 4576 if (!ioc->request) { 4577 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 4578 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 4579 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth, 4580 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 4581 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH) 4582 goto out; 4583 retry_sz = 64; 4584 ioc->hba_queue_depth -= retry_sz; 4585 _base_release_memory_pools(ioc); 4586 goto retry_allocation; 4587 } 4588 4589 if (retry_sz) 4590 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \ 4591 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), " 4592 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth, 4593 ioc->chains_needed_per_io, ioc->request_sz, sz/1024); 4594 4595 /* hi-priority queue */ 4596 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) * 4597 ioc->request_sz); 4598 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) * 4599 ioc->request_sz); 4600 4601 /* internal queue */ 4602 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth * 4603 ioc->request_sz); 4604 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth * 4605 ioc->request_sz); 4606 4607 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4608 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 4609 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz, 4610 (ioc->hba_queue_depth * ioc->request_sz)/1024)); 4611 4612 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n", 4613 ioc->name, (unsigned long long) ioc->request_dma)); 4614 total_sz += sz; 4615 4616 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n", 4617 ioc->name, ioc->request, ioc->scsiio_depth)); 4618 4619 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH); 4620 sz = ioc->scsiio_depth * sizeof(struct chain_lookup); 4621 ioc->chain_lookup = kzalloc(sz, GFP_KERNEL); 4622 if (!ioc->chain_lookup) { 4623 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages " 4624 "failed\n", ioc->name); 4625 goto out; 4626 } 4627 4628 sz = ioc->chains_needed_per_io * sizeof(struct chain_tracker); 4629 for (i = 0; i < ioc->scsiio_depth; i++) { 4630 ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL); 4631 if (!ioc->chain_lookup[i].chains_per_smid) { 4632 pr_err(MPT3SAS_FMT "chain_lookup: " 4633 " kzalloc failed\n", ioc->name); 4634 goto out; 4635 } 4636 } 4637 4638 /* initialize hi-priority queue smid's */ 4639 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth, 4640 sizeof(struct request_tracker), GFP_KERNEL); 4641 if (!ioc->hpr_lookup) { 4642 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n", 4643 ioc->name); 4644 goto out; 4645 } 4646 ioc->hi_priority_smid = ioc->scsiio_depth + 1; 4647 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4648 "hi_priority(0x%p): depth(%d), start smid(%d)\n", 4649 ioc->name, ioc->hi_priority, 4650 ioc->hi_priority_depth, ioc->hi_priority_smid)); 4651 4652 /* initialize internal queue smid's */ 4653 ioc->internal_lookup = kcalloc(ioc->internal_depth, 4654 sizeof(struct request_tracker), GFP_KERNEL); 4655 if (!ioc->internal_lookup) { 4656 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n", 4657 ioc->name); 4658 goto out; 4659 } 4660 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth; 4661 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4662 "internal(0x%p): depth(%d), start smid(%d)\n", 4663 ioc->name, ioc->internal, 4664 ioc->internal_depth, ioc->internal_smid)); 4665 /* 4666 * The number of NVMe page sized blocks needed is: 4667 * (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1 4668 * ((sg_tablesize * 8) - 1) is the max PRP's minus the first PRP entry 4669 * that is placed in the main message frame. 8 is the size of each PRP 4670 * entry or PRP list pointer entry. 8 is subtracted from page_size 4671 * because of the PRP list pointer entry at the end of a page, so this 4672 * is not counted as a PRP entry. The 1 added page is a round up. 4673 * 4674 * To avoid allocation failures due to the amount of memory that could 4675 * be required for NVMe PRP's, only each set of NVMe blocks will be 4676 * contiguous, so a new set is allocated for each possible I/O. 4677 */ 4678 ioc->chains_per_prp_buffer = 0; 4679 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) { 4680 nvme_blocks_needed = 4681 (ioc->shost->sg_tablesize * NVME_PRP_SIZE) - 1; 4682 nvme_blocks_needed /= (ioc->page_size - NVME_PRP_SIZE); 4683 nvme_blocks_needed++; 4684 4685 sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth; 4686 ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL); 4687 if (!ioc->pcie_sg_lookup) { 4688 pr_info(MPT3SAS_FMT 4689 "PCIe SGL lookup: kzalloc failed\n", ioc->name); 4690 goto out; 4691 } 4692 sz = nvme_blocks_needed * ioc->page_size; 4693 ioc->pcie_sgl_dma_pool = 4694 dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0); 4695 if (!ioc->pcie_sgl_dma_pool) { 4696 pr_info(MPT3SAS_FMT 4697 "PCIe SGL pool: dma_pool_create failed\n", 4698 ioc->name); 4699 goto out; 4700 } 4701 4702 ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz; 4703 ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer, 4704 ioc->chains_needed_per_io); 4705 4706 for (i = 0; i < ioc->scsiio_depth; i++) { 4707 ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc( 4708 ioc->pcie_sgl_dma_pool, GFP_KERNEL, 4709 &ioc->pcie_sg_lookup[i].pcie_sgl_dma); 4710 if (!ioc->pcie_sg_lookup[i].pcie_sgl) { 4711 pr_info(MPT3SAS_FMT 4712 "PCIe SGL pool: dma_pool_alloc failed\n", 4713 ioc->name); 4714 goto out; 4715 } 4716 for (j = 0; j < ioc->chains_per_prp_buffer; j++) { 4717 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 4718 ct->chain_buffer = 4719 ioc->pcie_sg_lookup[i].pcie_sgl + 4720 (j * ioc->chain_segment_sz); 4721 ct->chain_buffer_dma = 4722 ioc->pcie_sg_lookup[i].pcie_sgl_dma + 4723 (j * ioc->chain_segment_sz); 4724 } 4725 } 4726 4727 dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), " 4728 "element_size(%d), pool_size(%d kB)\n", ioc->name, 4729 ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024)); 4730 dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can " 4731 "fit in a PRP page(%d)\n", ioc->name, 4732 ioc->chains_per_prp_buffer)); 4733 total_sz += sz * ioc->scsiio_depth; 4734 } 4735 4736 ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev, 4737 ioc->chain_segment_sz, 16, 0); 4738 if (!ioc->chain_dma_pool) { 4739 pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n", 4740 ioc->name); 4741 goto out; 4742 } 4743 for (i = 0; i < ioc->scsiio_depth; i++) { 4744 for (j = ioc->chains_per_prp_buffer; 4745 j < ioc->chains_needed_per_io; j++) { 4746 ct = &ioc->chain_lookup[i].chains_per_smid[j]; 4747 ct->chain_buffer = dma_pool_alloc( 4748 ioc->chain_dma_pool, GFP_KERNEL, 4749 &ct->chain_buffer_dma); 4750 if (!ct->chain_buffer) { 4751 pr_err(MPT3SAS_FMT "chain_lookup: " 4752 " pci_pool_alloc failed\n", ioc->name); 4753 _base_release_memory_pools(ioc); 4754 goto out; 4755 } 4756 } 4757 total_sz += ioc->chain_segment_sz; 4758 } 4759 4760 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4761 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n", 4762 ioc->name, ioc->chain_depth, ioc->chain_segment_sz, 4763 ((ioc->chain_depth * ioc->chain_segment_sz))/1024)); 4764 4765 /* sense buffers, 4 byte align */ 4766 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE; 4767 ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4768 4, 0); 4769 if (!ioc->sense_dma_pool) { 4770 pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n", 4771 ioc->name); 4772 goto out; 4773 } 4774 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, 4775 &ioc->sense_dma); 4776 if (!ioc->sense) { 4777 pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n", 4778 ioc->name); 4779 goto out; 4780 } 4781 /* sense buffer requires to be in same 4 gb region. 4782 * Below function will check the same. 4783 * In case of failure, new pci pool will be created with updated 4784 * alignment. Older allocation and pool will be destroyed. 4785 * Alignment will be used such a way that next allocation if 4786 * success, will always meet same 4gb region requirement. 4787 * Actual requirement is not alignment, but we need start and end of 4788 * DMA address must have same upper 32 bit address. 4789 */ 4790 if (!is_MSB_are_same((long)ioc->sense, sz)) { 4791 //Release Sense pool & Reallocate 4792 dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); 4793 dma_pool_destroy(ioc->sense_dma_pool); 4794 ioc->sense = NULL; 4795 4796 ioc->sense_dma_pool = 4797 dma_pool_create("sense pool", &ioc->pdev->dev, sz, 4798 roundup_pow_of_two(sz), 0); 4799 if (!ioc->sense_dma_pool) { 4800 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n", 4801 ioc->name); 4802 goto out; 4803 } 4804 ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL, 4805 &ioc->sense_dma); 4806 if (!ioc->sense) { 4807 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n", 4808 ioc->name); 4809 goto out; 4810 } 4811 } 4812 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4813 "sense pool(0x%p): depth(%d), element_size(%d), pool_size" 4814 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth, 4815 SCSI_SENSE_BUFFERSIZE, sz/1024)); 4816 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n", 4817 ioc->name, (unsigned long long)ioc->sense_dma)); 4818 total_sz += sz; 4819 4820 /* reply pool, 4 byte align */ 4821 sz = ioc->reply_free_queue_depth * ioc->reply_sz; 4822 ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz, 4823 4, 0); 4824 if (!ioc->reply_dma_pool) { 4825 pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n", 4826 ioc->name); 4827 goto out; 4828 } 4829 ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL, 4830 &ioc->reply_dma); 4831 if (!ioc->reply) { 4832 pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n", 4833 ioc->name); 4834 goto out; 4835 } 4836 ioc->reply_dma_min_address = (u32)(ioc->reply_dma); 4837 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz; 4838 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4839 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n", 4840 ioc->name, ioc->reply, 4841 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024)); 4842 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n", 4843 ioc->name, (unsigned long long)ioc->reply_dma)); 4844 total_sz += sz; 4845 4846 /* reply free queue, 16 byte align */ 4847 sz = ioc->reply_free_queue_depth * 4; 4848 ioc->reply_free_dma_pool = dma_pool_create("reply_free pool", 4849 &ioc->pdev->dev, sz, 16, 0); 4850 if (!ioc->reply_free_dma_pool) { 4851 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n", 4852 ioc->name); 4853 goto out; 4854 } 4855 ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL, 4856 &ioc->reply_free_dma); 4857 if (!ioc->reply_free) { 4858 pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n", 4859 ioc->name); 4860 goto out; 4861 } 4862 memset(ioc->reply_free, 0, sz); 4863 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \ 4864 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name, 4865 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024)); 4866 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4867 "reply_free_dma (0x%llx)\n", 4868 ioc->name, (unsigned long long)ioc->reply_free_dma)); 4869 total_sz += sz; 4870 4871 if (ioc->rdpq_array_enable) { 4872 reply_post_free_array_sz = ioc->reply_queue_count * 4873 sizeof(Mpi2IOCInitRDPQArrayEntry); 4874 ioc->reply_post_free_array_dma_pool = 4875 dma_pool_create("reply_post_free_array pool", 4876 &ioc->pdev->dev, reply_post_free_array_sz, 16, 0); 4877 if (!ioc->reply_post_free_array_dma_pool) { 4878 dinitprintk(ioc, 4879 pr_info(MPT3SAS_FMT "reply_post_free_array pool: " 4880 "dma_pool_create failed\n", ioc->name)); 4881 goto out; 4882 } 4883 ioc->reply_post_free_array = 4884 dma_pool_alloc(ioc->reply_post_free_array_dma_pool, 4885 GFP_KERNEL, &ioc->reply_post_free_array_dma); 4886 if (!ioc->reply_post_free_array) { 4887 dinitprintk(ioc, 4888 pr_info(MPT3SAS_FMT "reply_post_free_array pool: " 4889 "dma_pool_alloc failed\n", ioc->name)); 4890 goto out; 4891 } 4892 } 4893 ioc->config_page_sz = 512; 4894 ioc->config_page = pci_alloc_consistent(ioc->pdev, 4895 ioc->config_page_sz, &ioc->config_page_dma); 4896 if (!ioc->config_page) { 4897 pr_err(MPT3SAS_FMT 4898 "config page: dma_pool_alloc failed\n", 4899 ioc->name); 4900 goto out; 4901 } 4902 dinitprintk(ioc, pr_info(MPT3SAS_FMT 4903 "config page(0x%p): size(%d)\n", 4904 ioc->name, ioc->config_page, ioc->config_page_sz)); 4905 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n", 4906 ioc->name, (unsigned long long)ioc->config_page_dma)); 4907 total_sz += ioc->config_page_sz; 4908 4909 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n", 4910 ioc->name, total_sz/1024); 4911 pr_info(MPT3SAS_FMT 4912 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n", 4913 ioc->name, ioc->shost->can_queue, facts->RequestCredit); 4914 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n", 4915 ioc->name, ioc->shost->sg_tablesize); 4916 return 0; 4917 4918 out: 4919 return -ENOMEM; 4920 } 4921 4922 /** 4923 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter. 4924 * @ioc: Pointer to MPT_ADAPTER structure 4925 * @cooked: Request raw or cooked IOC state 4926 * 4927 * Return: all IOC Doorbell register bits if cooked==0, else just the 4928 * Doorbell bits in MPI_IOC_STATE_MASK. 4929 */ 4930 u32 4931 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked) 4932 { 4933 u32 s, sc; 4934 4935 s = readl(&ioc->chip->Doorbell); 4936 sc = s & MPI2_IOC_STATE_MASK; 4937 return cooked ? sc : s; 4938 } 4939 4940 /** 4941 * _base_wait_on_iocstate - waiting on a particular ioc state 4942 * @ioc: ? 4943 * @ioc_state: controller state { READY, OPERATIONAL, or RESET } 4944 * @timeout: timeout in second 4945 * 4946 * Return: 0 for success, non-zero for failure. 4947 */ 4948 static int 4949 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout) 4950 { 4951 u32 count, cntdn; 4952 u32 current_state; 4953 4954 count = 0; 4955 cntdn = 1000 * timeout; 4956 do { 4957 current_state = mpt3sas_base_get_iocstate(ioc, 1); 4958 if (current_state == ioc_state) 4959 return 0; 4960 if (count && current_state == MPI2_IOC_STATE_FAULT) 4961 break; 4962 4963 usleep_range(1000, 1500); 4964 count++; 4965 } while (--cntdn); 4966 4967 return current_state; 4968 } 4969 4970 /** 4971 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by 4972 * a write to the doorbell) 4973 * @ioc: per adapter object 4974 * 4975 * Return: 0 for success, non-zero for failure. 4976 * 4977 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell. 4978 */ 4979 static int 4980 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc); 4981 4982 static int 4983 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 4984 { 4985 u32 cntdn, count; 4986 u32 int_status; 4987 4988 count = 0; 4989 cntdn = 1000 * timeout; 4990 do { 4991 int_status = readl(&ioc->chip->HostInterruptStatus); 4992 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 4993 dhsprintk(ioc, pr_info(MPT3SAS_FMT 4994 "%s: successful count(%d), timeout(%d)\n", 4995 ioc->name, __func__, count, timeout)); 4996 return 0; 4997 } 4998 4999 usleep_range(1000, 1500); 5000 count++; 5001 } while (--cntdn); 5002 5003 pr_err(MPT3SAS_FMT 5004 "%s: failed due to timeout count(%d), int_status(%x)!\n", 5005 ioc->name, __func__, count, int_status); 5006 return -EFAULT; 5007 } 5008 5009 static int 5010 _base_spin_on_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout) 5011 { 5012 u32 cntdn, count; 5013 u32 int_status; 5014 5015 count = 0; 5016 cntdn = 2000 * timeout; 5017 do { 5018 int_status = readl(&ioc->chip->HostInterruptStatus); 5019 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 5020 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5021 "%s: successful count(%d), timeout(%d)\n", 5022 ioc->name, __func__, count, timeout)); 5023 return 0; 5024 } 5025 5026 udelay(500); 5027 count++; 5028 } while (--cntdn); 5029 5030 pr_err(MPT3SAS_FMT 5031 "%s: failed due to timeout count(%d), int_status(%x)!\n", 5032 ioc->name, __func__, count, int_status); 5033 return -EFAULT; 5034 5035 } 5036 5037 /** 5038 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell. 5039 * @ioc: per adapter object 5040 * @timeout: timeout in second 5041 * 5042 * Return: 0 for success, non-zero for failure. 5043 * 5044 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to 5045 * doorbell. 5046 */ 5047 static int 5048 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout) 5049 { 5050 u32 cntdn, count; 5051 u32 int_status; 5052 u32 doorbell; 5053 5054 count = 0; 5055 cntdn = 1000 * timeout; 5056 do { 5057 int_status = readl(&ioc->chip->HostInterruptStatus); 5058 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 5059 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5060 "%s: successful count(%d), timeout(%d)\n", 5061 ioc->name, __func__, count, timeout)); 5062 return 0; 5063 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 5064 doorbell = readl(&ioc->chip->Doorbell); 5065 if ((doorbell & MPI2_IOC_STATE_MASK) == 5066 MPI2_IOC_STATE_FAULT) { 5067 mpt3sas_base_fault_info(ioc , doorbell); 5068 return -EFAULT; 5069 } 5070 } else if (int_status == 0xFFFFFFFF) 5071 goto out; 5072 5073 usleep_range(1000, 1500); 5074 count++; 5075 } while (--cntdn); 5076 5077 out: 5078 pr_err(MPT3SAS_FMT 5079 "%s: failed due to timeout count(%d), int_status(%x)!\n", 5080 ioc->name, __func__, count, int_status); 5081 return -EFAULT; 5082 } 5083 5084 /** 5085 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use 5086 * @ioc: per adapter object 5087 * @timeout: timeout in second 5088 * 5089 * Return: 0 for success, non-zero for failure. 5090 */ 5091 static int 5092 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout) 5093 { 5094 u32 cntdn, count; 5095 u32 doorbell_reg; 5096 5097 count = 0; 5098 cntdn = 1000 * timeout; 5099 do { 5100 doorbell_reg = readl(&ioc->chip->Doorbell); 5101 if (!(doorbell_reg & MPI2_DOORBELL_USED)) { 5102 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5103 "%s: successful count(%d), timeout(%d)\n", 5104 ioc->name, __func__, count, timeout)); 5105 return 0; 5106 } 5107 5108 usleep_range(1000, 1500); 5109 count++; 5110 } while (--cntdn); 5111 5112 pr_err(MPT3SAS_FMT 5113 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n", 5114 ioc->name, __func__, count, doorbell_reg); 5115 return -EFAULT; 5116 } 5117 5118 /** 5119 * _base_send_ioc_reset - send doorbell reset 5120 * @ioc: per adapter object 5121 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET 5122 * @timeout: timeout in second 5123 * 5124 * Return: 0 for success, non-zero for failure. 5125 */ 5126 static int 5127 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout) 5128 { 5129 u32 ioc_state; 5130 int r = 0; 5131 5132 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) { 5133 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n", 5134 ioc->name, __func__); 5135 return -EFAULT; 5136 } 5137 5138 if (!(ioc->facts.IOCCapabilities & 5139 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY)) 5140 return -EFAULT; 5141 5142 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name); 5143 5144 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT, 5145 &ioc->chip->Doorbell); 5146 if ((_base_wait_for_doorbell_ack(ioc, 15))) { 5147 r = -EFAULT; 5148 goto out; 5149 } 5150 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 5151 if (ioc_state) { 5152 pr_err(MPT3SAS_FMT 5153 "%s: failed going to ready state (ioc_state=0x%x)\n", 5154 ioc->name, __func__, ioc_state); 5155 r = -EFAULT; 5156 goto out; 5157 } 5158 out: 5159 pr_info(MPT3SAS_FMT "message unit reset: %s\n", 5160 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED")); 5161 return r; 5162 } 5163 5164 /** 5165 * _base_handshake_req_reply_wait - send request thru doorbell interface 5166 * @ioc: per adapter object 5167 * @request_bytes: request length 5168 * @request: pointer having request payload 5169 * @reply_bytes: reply length 5170 * @reply: pointer to reply payload 5171 * @timeout: timeout in second 5172 * 5173 * Return: 0 for success, non-zero for failure. 5174 */ 5175 static int 5176 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes, 5177 u32 *request, int reply_bytes, u16 *reply, int timeout) 5178 { 5179 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply; 5180 int i; 5181 u8 failed; 5182 __le32 *mfp; 5183 5184 /* make sure doorbell is not in use */ 5185 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) { 5186 pr_err(MPT3SAS_FMT 5187 "doorbell is in use (line=%d)\n", 5188 ioc->name, __LINE__); 5189 return -EFAULT; 5190 } 5191 5192 /* clear pending doorbell interrupts from previous state changes */ 5193 if (readl(&ioc->chip->HostInterruptStatus) & 5194 MPI2_HIS_IOC2SYS_DB_STATUS) 5195 writel(0, &ioc->chip->HostInterruptStatus); 5196 5197 /* send message to ioc */ 5198 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) | 5199 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)), 5200 &ioc->chip->Doorbell); 5201 5202 if ((_base_spin_on_doorbell_int(ioc, 5))) { 5203 pr_err(MPT3SAS_FMT 5204 "doorbell handshake int failed (line=%d)\n", 5205 ioc->name, __LINE__); 5206 return -EFAULT; 5207 } 5208 writel(0, &ioc->chip->HostInterruptStatus); 5209 5210 if ((_base_wait_for_doorbell_ack(ioc, 5))) { 5211 pr_err(MPT3SAS_FMT 5212 "doorbell handshake ack failed (line=%d)\n", 5213 ioc->name, __LINE__); 5214 return -EFAULT; 5215 } 5216 5217 /* send message 32-bits at a time */ 5218 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) { 5219 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell); 5220 if ((_base_wait_for_doorbell_ack(ioc, 5))) 5221 failed = 1; 5222 } 5223 5224 if (failed) { 5225 pr_err(MPT3SAS_FMT 5226 "doorbell handshake sending request failed (line=%d)\n", 5227 ioc->name, __LINE__); 5228 return -EFAULT; 5229 } 5230 5231 /* now wait for the reply */ 5232 if ((_base_wait_for_doorbell_int(ioc, timeout))) { 5233 pr_err(MPT3SAS_FMT 5234 "doorbell handshake int failed (line=%d)\n", 5235 ioc->name, __LINE__); 5236 return -EFAULT; 5237 } 5238 5239 /* read the first two 16-bits, it gives the total length of the reply */ 5240 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell) 5241 & MPI2_DOORBELL_DATA_MASK); 5242 writel(0, &ioc->chip->HostInterruptStatus); 5243 if ((_base_wait_for_doorbell_int(ioc, 5))) { 5244 pr_err(MPT3SAS_FMT 5245 "doorbell handshake int failed (line=%d)\n", 5246 ioc->name, __LINE__); 5247 return -EFAULT; 5248 } 5249 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell) 5250 & MPI2_DOORBELL_DATA_MASK); 5251 writel(0, &ioc->chip->HostInterruptStatus); 5252 5253 for (i = 2; i < default_reply->MsgLength * 2; i++) { 5254 if ((_base_wait_for_doorbell_int(ioc, 5))) { 5255 pr_err(MPT3SAS_FMT 5256 "doorbell handshake int failed (line=%d)\n", 5257 ioc->name, __LINE__); 5258 return -EFAULT; 5259 } 5260 if (i >= reply_bytes/2) /* overflow case */ 5261 readl(&ioc->chip->Doorbell); 5262 else 5263 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell) 5264 & MPI2_DOORBELL_DATA_MASK); 5265 writel(0, &ioc->chip->HostInterruptStatus); 5266 } 5267 5268 _base_wait_for_doorbell_int(ioc, 5); 5269 if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) { 5270 dhsprintk(ioc, pr_info(MPT3SAS_FMT 5271 "doorbell is in use (line=%d)\n", ioc->name, __LINE__)); 5272 } 5273 writel(0, &ioc->chip->HostInterruptStatus); 5274 5275 if (ioc->logging_level & MPT_DEBUG_INIT) { 5276 mfp = (__le32 *)reply; 5277 pr_info("\toffset:data\n"); 5278 for (i = 0; i < reply_bytes/4; i++) 5279 pr_info("\t[0x%02x]:%08x\n", i*4, 5280 le32_to_cpu(mfp[i])); 5281 } 5282 return 0; 5283 } 5284 5285 /** 5286 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW 5287 * @ioc: per adapter object 5288 * @mpi_reply: the reply payload from FW 5289 * @mpi_request: the request payload sent to FW 5290 * 5291 * The SAS IO Unit Control Request message allows the host to perform low-level 5292 * operations, such as resets on the PHYs of the IO Unit, also allows the host 5293 * to obtain the IOC assigned device handles for a device if it has other 5294 * identifying information about the device, in addition allows the host to 5295 * remove IOC resources associated with the device. 5296 * 5297 * Return: 0 for success, non-zero for failure. 5298 */ 5299 int 5300 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc, 5301 Mpi2SasIoUnitControlReply_t *mpi_reply, 5302 Mpi2SasIoUnitControlRequest_t *mpi_request) 5303 { 5304 u16 smid; 5305 u32 ioc_state; 5306 u8 issue_reset = 0; 5307 int rc; 5308 void *request; 5309 u16 wait_state_count; 5310 5311 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5312 __func__)); 5313 5314 mutex_lock(&ioc->base_cmds.mutex); 5315 5316 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 5317 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 5318 ioc->name, __func__); 5319 rc = -EAGAIN; 5320 goto out; 5321 } 5322 5323 wait_state_count = 0; 5324 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 5325 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 5326 if (wait_state_count++ == 10) { 5327 pr_err(MPT3SAS_FMT 5328 "%s: failed due to ioc not operational\n", 5329 ioc->name, __func__); 5330 rc = -EFAULT; 5331 goto out; 5332 } 5333 ssleep(1); 5334 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 5335 pr_info(MPT3SAS_FMT 5336 "%s: waiting for operational state(count=%d)\n", 5337 ioc->name, __func__, wait_state_count); 5338 } 5339 5340 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 5341 if (!smid) { 5342 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 5343 ioc->name, __func__); 5344 rc = -EAGAIN; 5345 goto out; 5346 } 5347 5348 rc = 0; 5349 ioc->base_cmds.status = MPT3_CMD_PENDING; 5350 request = mpt3sas_base_get_msg_frame(ioc, smid); 5351 ioc->base_cmds.smid = smid; 5352 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)); 5353 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 5354 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) 5355 ioc->ioc_link_reset_in_progress = 1; 5356 init_completion(&ioc->base_cmds.done); 5357 mpt3sas_base_put_smid_default(ioc, smid); 5358 wait_for_completion_timeout(&ioc->base_cmds.done, 5359 msecs_to_jiffies(10000)); 5360 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET || 5361 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) && 5362 ioc->ioc_link_reset_in_progress) 5363 ioc->ioc_link_reset_in_progress = 0; 5364 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 5365 issue_reset = 5366 mpt3sas_base_check_cmd_timeout(ioc, 5367 ioc->base_cmds.status, mpi_request, 5368 sizeof(Mpi2SasIoUnitControlRequest_t)/4); 5369 goto issue_host_reset; 5370 } 5371 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 5372 memcpy(mpi_reply, ioc->base_cmds.reply, 5373 sizeof(Mpi2SasIoUnitControlReply_t)); 5374 else 5375 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t)); 5376 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5377 goto out; 5378 5379 issue_host_reset: 5380 if (issue_reset) 5381 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 5382 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5383 rc = -EFAULT; 5384 out: 5385 mutex_unlock(&ioc->base_cmds.mutex); 5386 return rc; 5387 } 5388 5389 /** 5390 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device 5391 * @ioc: per adapter object 5392 * @mpi_reply: the reply payload from FW 5393 * @mpi_request: the request payload sent to FW 5394 * 5395 * The SCSI Enclosure Processor request message causes the IOC to 5396 * communicate with SES devices to control LED status signals. 5397 * 5398 * Return: 0 for success, non-zero for failure. 5399 */ 5400 int 5401 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc, 5402 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request) 5403 { 5404 u16 smid; 5405 u32 ioc_state; 5406 u8 issue_reset = 0; 5407 int rc; 5408 void *request; 5409 u16 wait_state_count; 5410 5411 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5412 __func__)); 5413 5414 mutex_lock(&ioc->base_cmds.mutex); 5415 5416 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) { 5417 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n", 5418 ioc->name, __func__); 5419 rc = -EAGAIN; 5420 goto out; 5421 } 5422 5423 wait_state_count = 0; 5424 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 5425 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) { 5426 if (wait_state_count++ == 10) { 5427 pr_err(MPT3SAS_FMT 5428 "%s: failed due to ioc not operational\n", 5429 ioc->name, __func__); 5430 rc = -EFAULT; 5431 goto out; 5432 } 5433 ssleep(1); 5434 ioc_state = mpt3sas_base_get_iocstate(ioc, 1); 5435 pr_info(MPT3SAS_FMT 5436 "%s: waiting for operational state(count=%d)\n", 5437 ioc->name, 5438 __func__, wait_state_count); 5439 } 5440 5441 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 5442 if (!smid) { 5443 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 5444 ioc->name, __func__); 5445 rc = -EAGAIN; 5446 goto out; 5447 } 5448 5449 rc = 0; 5450 ioc->base_cmds.status = MPT3_CMD_PENDING; 5451 request = mpt3sas_base_get_msg_frame(ioc, smid); 5452 ioc->base_cmds.smid = smid; 5453 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t)); 5454 init_completion(&ioc->base_cmds.done); 5455 mpt3sas_base_put_smid_default(ioc, smid); 5456 wait_for_completion_timeout(&ioc->base_cmds.done, 5457 msecs_to_jiffies(10000)); 5458 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 5459 issue_reset = 5460 mpt3sas_base_check_cmd_timeout(ioc, 5461 ioc->base_cmds.status, mpi_request, 5462 sizeof(Mpi2SepRequest_t)/4); 5463 goto issue_host_reset; 5464 } 5465 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID) 5466 memcpy(mpi_reply, ioc->base_cmds.reply, 5467 sizeof(Mpi2SepReply_t)); 5468 else 5469 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t)); 5470 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5471 goto out; 5472 5473 issue_host_reset: 5474 if (issue_reset) 5475 mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER); 5476 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 5477 rc = -EFAULT; 5478 out: 5479 mutex_unlock(&ioc->base_cmds.mutex); 5480 return rc; 5481 } 5482 5483 /** 5484 * _base_get_port_facts - obtain port facts reply and save in ioc 5485 * @ioc: per adapter object 5486 * @port: ? 5487 * 5488 * Return: 0 for success, non-zero for failure. 5489 */ 5490 static int 5491 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port) 5492 { 5493 Mpi2PortFactsRequest_t mpi_request; 5494 Mpi2PortFactsReply_t mpi_reply; 5495 struct mpt3sas_port_facts *pfacts; 5496 int mpi_reply_sz, mpi_request_sz, r; 5497 5498 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5499 __func__)); 5500 5501 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t); 5502 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t); 5503 memset(&mpi_request, 0, mpi_request_sz); 5504 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS; 5505 mpi_request.PortNumber = port; 5506 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 5507 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 5508 5509 if (r != 0) { 5510 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 5511 ioc->name, __func__, r); 5512 return r; 5513 } 5514 5515 pfacts = &ioc->pfacts[port]; 5516 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts)); 5517 pfacts->PortNumber = mpi_reply.PortNumber; 5518 pfacts->VP_ID = mpi_reply.VP_ID; 5519 pfacts->VF_ID = mpi_reply.VF_ID; 5520 pfacts->MaxPostedCmdBuffers = 5521 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers); 5522 5523 return 0; 5524 } 5525 5526 /** 5527 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL 5528 * @ioc: per adapter object 5529 * @timeout: 5530 * 5531 * Return: 0 for success, non-zero for failure. 5532 */ 5533 static int 5534 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout) 5535 { 5536 u32 ioc_state; 5537 int rc; 5538 5539 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name, 5540 __func__)); 5541 5542 if (ioc->pci_error_recovery) { 5543 dfailprintk(ioc, printk(MPT3SAS_FMT 5544 "%s: host in pci error recovery\n", ioc->name, __func__)); 5545 return -EFAULT; 5546 } 5547 5548 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 5549 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 5550 ioc->name, __func__, ioc_state)); 5551 5552 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) || 5553 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 5554 return 0; 5555 5556 if (ioc_state & MPI2_DOORBELL_USED) { 5557 dhsprintk(ioc, printk(MPT3SAS_FMT 5558 "unexpected doorbell active!\n", ioc->name)); 5559 goto issue_diag_reset; 5560 } 5561 5562 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 5563 mpt3sas_base_fault_info(ioc, ioc_state & 5564 MPI2_DOORBELL_DATA_MASK); 5565 goto issue_diag_reset; 5566 } 5567 5568 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout); 5569 if (ioc_state) { 5570 dfailprintk(ioc, printk(MPT3SAS_FMT 5571 "%s: failed going to ready state (ioc_state=0x%x)\n", 5572 ioc->name, __func__, ioc_state)); 5573 return -EFAULT; 5574 } 5575 5576 issue_diag_reset: 5577 rc = _base_diag_reset(ioc); 5578 return rc; 5579 } 5580 5581 /** 5582 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc 5583 * @ioc: per adapter object 5584 * 5585 * Return: 0 for success, non-zero for failure. 5586 */ 5587 static int 5588 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) 5589 { 5590 Mpi2IOCFactsRequest_t mpi_request; 5591 Mpi2IOCFactsReply_t mpi_reply; 5592 struct mpt3sas_facts *facts; 5593 int mpi_reply_sz, mpi_request_sz, r; 5594 5595 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5596 __func__)); 5597 5598 r = _base_wait_for_iocstate(ioc, 10); 5599 if (r) { 5600 dfailprintk(ioc, printk(MPT3SAS_FMT 5601 "%s: failed getting to correct state\n", 5602 ioc->name, __func__)); 5603 return r; 5604 } 5605 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t); 5606 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t); 5607 memset(&mpi_request, 0, mpi_request_sz); 5608 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS; 5609 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz, 5610 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5); 5611 5612 if (r != 0) { 5613 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 5614 ioc->name, __func__, r); 5615 return r; 5616 } 5617 5618 facts = &ioc->facts; 5619 memset(facts, 0, sizeof(struct mpt3sas_facts)); 5620 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion); 5621 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion); 5622 facts->VP_ID = mpi_reply.VP_ID; 5623 facts->VF_ID = mpi_reply.VF_ID; 5624 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions); 5625 facts->MaxChainDepth = mpi_reply.MaxChainDepth; 5626 facts->WhoInit = mpi_reply.WhoInit; 5627 facts->NumberOfPorts = mpi_reply.NumberOfPorts; 5628 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; 5629 if (ioc->msix_enable && (facts->MaxMSIxVectors <= 5630 MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) 5631 ioc->combined_reply_queue = 0; 5632 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); 5633 facts->MaxReplyDescriptorPostQueueDepth = 5634 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); 5635 facts->ProductID = le16_to_cpu(mpi_reply.ProductID); 5636 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities); 5637 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)) 5638 ioc->ir_firmware = 1; 5639 if ((facts->IOCCapabilities & 5640 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices)) 5641 ioc->rdpq_array_capable = 1; 5642 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word); 5643 facts->IOCRequestFrameSize = 5644 le16_to_cpu(mpi_reply.IOCRequestFrameSize); 5645 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 5646 facts->IOCMaxChainSegmentSize = 5647 le16_to_cpu(mpi_reply.IOCMaxChainSegmentSize); 5648 } 5649 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators); 5650 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets); 5651 ioc->shost->max_id = -1; 5652 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders); 5653 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures); 5654 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags); 5655 facts->HighPriorityCredit = 5656 le16_to_cpu(mpi_reply.HighPriorityCredit); 5657 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize; 5658 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle); 5659 facts->CurrentHostPageSize = mpi_reply.CurrentHostPageSize; 5660 5661 /* 5662 * Get the Page Size from IOC Facts. If it's 0, default to 4k. 5663 */ 5664 ioc->page_size = 1 << facts->CurrentHostPageSize; 5665 if (ioc->page_size == 1) { 5666 pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting " 5667 "default host page size to 4k\n", ioc->name); 5668 ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K; 5669 } 5670 dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n", 5671 ioc->name, facts->CurrentHostPageSize)); 5672 5673 dinitprintk(ioc, pr_info(MPT3SAS_FMT 5674 "hba queue depth(%d), max chains per io(%d)\n", 5675 ioc->name, facts->RequestCredit, 5676 facts->MaxChainDepth)); 5677 dinitprintk(ioc, pr_info(MPT3SAS_FMT 5678 "request frame size(%d), reply frame size(%d)\n", ioc->name, 5679 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4)); 5680 return 0; 5681 } 5682 5683 /** 5684 * _base_send_ioc_init - send ioc_init to firmware 5685 * @ioc: per adapter object 5686 * 5687 * Return: 0 for success, non-zero for failure. 5688 */ 5689 static int 5690 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc) 5691 { 5692 Mpi2IOCInitRequest_t mpi_request; 5693 Mpi2IOCInitReply_t mpi_reply; 5694 int i, r = 0; 5695 ktime_t current_time; 5696 u16 ioc_status; 5697 u32 reply_post_free_array_sz = 0; 5698 5699 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 5700 __func__)); 5701 5702 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t)); 5703 mpi_request.Function = MPI2_FUNCTION_IOC_INIT; 5704 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 5705 mpi_request.VF_ID = 0; /* TODO */ 5706 mpi_request.VP_ID = 0; 5707 mpi_request.MsgVersion = cpu_to_le16(ioc->hba_mpi_version_belonged); 5708 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION); 5709 mpi_request.HostPageSize = MPT3SAS_HOST_PAGE_SIZE_4K; 5710 5711 if (_base_is_controller_msix_enabled(ioc)) 5712 mpi_request.HostMSIxVectors = ioc->reply_queue_count; 5713 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4); 5714 mpi_request.ReplyDescriptorPostQueueDepth = 5715 cpu_to_le16(ioc->reply_post_queue_depth); 5716 mpi_request.ReplyFreeQueueDepth = 5717 cpu_to_le16(ioc->reply_free_queue_depth); 5718 5719 mpi_request.SenseBufferAddressHigh = 5720 cpu_to_le32((u64)ioc->sense_dma >> 32); 5721 mpi_request.SystemReplyAddressHigh = 5722 cpu_to_le32((u64)ioc->reply_dma >> 32); 5723 mpi_request.SystemRequestFrameBaseAddress = 5724 cpu_to_le64((u64)ioc->request_dma); 5725 mpi_request.ReplyFreeQueueAddress = 5726 cpu_to_le64((u64)ioc->reply_free_dma); 5727 5728 if (ioc->rdpq_array_enable) { 5729 reply_post_free_array_sz = ioc->reply_queue_count * 5730 sizeof(Mpi2IOCInitRDPQArrayEntry); 5731 memset(ioc->reply_post_free_array, 0, reply_post_free_array_sz); 5732 for (i = 0; i < ioc->reply_queue_count; i++) 5733 ioc->reply_post_free_array[i].RDPQBaseAddress = 5734 cpu_to_le64( 5735 (u64)ioc->reply_post[i].reply_post_free_dma); 5736 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE; 5737 mpi_request.ReplyDescriptorPostQueueAddress = 5738 cpu_to_le64((u64)ioc->reply_post_free_array_dma); 5739 } else { 5740 mpi_request.ReplyDescriptorPostQueueAddress = 5741 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma); 5742 } 5743 5744 /* This time stamp specifies number of milliseconds 5745 * since epoch ~ midnight January 1, 1970. 5746 */ 5747 current_time = ktime_get_real(); 5748 mpi_request.TimeStamp = cpu_to_le64(ktime_to_ms(current_time)); 5749 5750 if (ioc->logging_level & MPT_DEBUG_INIT) { 5751 __le32 *mfp; 5752 int i; 5753 5754 mfp = (__le32 *)&mpi_request; 5755 pr_info("\toffset:data\n"); 5756 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++) 5757 pr_info("\t[0x%02x]:%08x\n", i*4, 5758 le32_to_cpu(mfp[i])); 5759 } 5760 5761 r = _base_handshake_req_reply_wait(ioc, 5762 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request, 5763 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10); 5764 5765 if (r != 0) { 5766 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n", 5767 ioc->name, __func__, r); 5768 return r; 5769 } 5770 5771 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK; 5772 if (ioc_status != MPI2_IOCSTATUS_SUCCESS || 5773 mpi_reply.IOCLogInfo) { 5774 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__); 5775 r = -EIO; 5776 } 5777 5778 return r; 5779 } 5780 5781 /** 5782 * mpt3sas_port_enable_done - command completion routine for port enable 5783 * @ioc: per adapter object 5784 * @smid: system request message index 5785 * @msix_index: MSIX table index supplied by the OS 5786 * @reply: reply message frame(lower 32bit addr) 5787 * 5788 * Return: 1 meaning mf should be freed from _base_interrupt 5789 * 0 means the mf is freed from this function. 5790 */ 5791 u8 5792 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index, 5793 u32 reply) 5794 { 5795 MPI2DefaultReply_t *mpi_reply; 5796 u16 ioc_status; 5797 5798 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED) 5799 return 1; 5800 5801 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply); 5802 if (!mpi_reply) 5803 return 1; 5804 5805 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE) 5806 return 1; 5807 5808 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING; 5809 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE; 5810 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID; 5811 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4); 5812 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 5813 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) 5814 ioc->port_enable_failed = 1; 5815 5816 if (ioc->is_driver_loading) { 5817 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) { 5818 mpt3sas_port_enable_complete(ioc); 5819 return 1; 5820 } else { 5821 ioc->start_scan_failed = ioc_status; 5822 ioc->start_scan = 0; 5823 return 1; 5824 } 5825 } 5826 complete(&ioc->port_enable_cmds.done); 5827 return 1; 5828 } 5829 5830 /** 5831 * _base_send_port_enable - send port_enable(discovery stuff) to firmware 5832 * @ioc: per adapter object 5833 * 5834 * Return: 0 for success, non-zero for failure. 5835 */ 5836 static int 5837 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc) 5838 { 5839 Mpi2PortEnableRequest_t *mpi_request; 5840 Mpi2PortEnableReply_t *mpi_reply; 5841 int r = 0; 5842 u16 smid; 5843 u16 ioc_status; 5844 5845 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 5846 5847 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 5848 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 5849 ioc->name, __func__); 5850 return -EAGAIN; 5851 } 5852 5853 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 5854 if (!smid) { 5855 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 5856 ioc->name, __func__); 5857 return -EAGAIN; 5858 } 5859 5860 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 5861 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 5862 ioc->port_enable_cmds.smid = smid; 5863 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 5864 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 5865 5866 init_completion(&ioc->port_enable_cmds.done); 5867 mpt3sas_base_put_smid_default(ioc, smid); 5868 wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ); 5869 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) { 5870 pr_err(MPT3SAS_FMT "%s: timeout\n", 5871 ioc->name, __func__); 5872 _debug_dump_mf(mpi_request, 5873 sizeof(Mpi2PortEnableRequest_t)/4); 5874 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET) 5875 r = -EFAULT; 5876 else 5877 r = -ETIME; 5878 goto out; 5879 } 5880 5881 mpi_reply = ioc->port_enable_cmds.reply; 5882 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK; 5883 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5884 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n", 5885 ioc->name, __func__, ioc_status); 5886 r = -EFAULT; 5887 goto out; 5888 } 5889 5890 out: 5891 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 5892 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ? 5893 "SUCCESS" : "FAILED")); 5894 return r; 5895 } 5896 5897 /** 5898 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply) 5899 * @ioc: per adapter object 5900 * 5901 * Return: 0 for success, non-zero for failure. 5902 */ 5903 int 5904 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc) 5905 { 5906 Mpi2PortEnableRequest_t *mpi_request; 5907 u16 smid; 5908 5909 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name); 5910 5911 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 5912 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 5913 ioc->name, __func__); 5914 return -EAGAIN; 5915 } 5916 5917 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx); 5918 if (!smid) { 5919 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 5920 ioc->name, __func__); 5921 return -EAGAIN; 5922 } 5923 5924 ioc->port_enable_cmds.status = MPT3_CMD_PENDING; 5925 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 5926 ioc->port_enable_cmds.smid = smid; 5927 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t)); 5928 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE; 5929 5930 mpt3sas_base_put_smid_default(ioc, smid); 5931 return 0; 5932 } 5933 5934 /** 5935 * _base_determine_wait_on_discovery - desposition 5936 * @ioc: per adapter object 5937 * 5938 * Decide whether to wait on discovery to complete. Used to either 5939 * locate boot device, or report volumes ahead of physical devices. 5940 * 5941 * Return: 1 for wait, 0 for don't wait. 5942 */ 5943 static int 5944 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc) 5945 { 5946 /* We wait for discovery to complete if IR firmware is loaded. 5947 * The sas topology events arrive before PD events, so we need time to 5948 * turn on the bit in ioc->pd_handles to indicate PD 5949 * Also, it maybe required to report Volumes ahead of physical 5950 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set. 5951 */ 5952 if (ioc->ir_firmware) 5953 return 1; 5954 5955 /* if no Bios, then we don't need to wait */ 5956 if (!ioc->bios_pg3.BiosVersion) 5957 return 0; 5958 5959 /* Bios is present, then we drop down here. 5960 * 5961 * If there any entries in the Bios Page 2, then we wait 5962 * for discovery to complete. 5963 */ 5964 5965 /* Current Boot Device */ 5966 if ((ioc->bios_pg2.CurrentBootDeviceForm & 5967 MPI2_BIOSPAGE2_FORM_MASK) == 5968 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 5969 /* Request Boot Device */ 5970 (ioc->bios_pg2.ReqBootDeviceForm & 5971 MPI2_BIOSPAGE2_FORM_MASK) == 5972 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED && 5973 /* Alternate Request Boot Device */ 5974 (ioc->bios_pg2.ReqAltBootDeviceForm & 5975 MPI2_BIOSPAGE2_FORM_MASK) == 5976 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED) 5977 return 0; 5978 5979 return 1; 5980 } 5981 5982 /** 5983 * _base_unmask_events - turn on notification for this event 5984 * @ioc: per adapter object 5985 * @event: firmware event 5986 * 5987 * The mask is stored in ioc->event_masks. 5988 */ 5989 static void 5990 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event) 5991 { 5992 u32 desired_event; 5993 5994 if (event >= 128) 5995 return; 5996 5997 desired_event = (1 << (event % 32)); 5998 5999 if (event < 32) 6000 ioc->event_masks[0] &= ~desired_event; 6001 else if (event < 64) 6002 ioc->event_masks[1] &= ~desired_event; 6003 else if (event < 96) 6004 ioc->event_masks[2] &= ~desired_event; 6005 else if (event < 128) 6006 ioc->event_masks[3] &= ~desired_event; 6007 } 6008 6009 /** 6010 * _base_event_notification - send event notification 6011 * @ioc: per adapter object 6012 * 6013 * Return: 0 for success, non-zero for failure. 6014 */ 6015 static int 6016 _base_event_notification(struct MPT3SAS_ADAPTER *ioc) 6017 { 6018 Mpi2EventNotificationRequest_t *mpi_request; 6019 u16 smid; 6020 int r = 0; 6021 int i; 6022 6023 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6024 __func__)); 6025 6026 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 6027 pr_err(MPT3SAS_FMT "%s: internal command already in use\n", 6028 ioc->name, __func__); 6029 return -EAGAIN; 6030 } 6031 6032 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx); 6033 if (!smid) { 6034 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n", 6035 ioc->name, __func__); 6036 return -EAGAIN; 6037 } 6038 ioc->base_cmds.status = MPT3_CMD_PENDING; 6039 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid); 6040 ioc->base_cmds.smid = smid; 6041 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t)); 6042 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 6043 mpi_request->VF_ID = 0; /* TODO */ 6044 mpi_request->VP_ID = 0; 6045 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 6046 mpi_request->EventMasks[i] = 6047 cpu_to_le32(ioc->event_masks[i]); 6048 init_completion(&ioc->base_cmds.done); 6049 mpt3sas_base_put_smid_default(ioc, smid); 6050 wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ); 6051 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) { 6052 pr_err(MPT3SAS_FMT "%s: timeout\n", 6053 ioc->name, __func__); 6054 _debug_dump_mf(mpi_request, 6055 sizeof(Mpi2EventNotificationRequest_t)/4); 6056 if (ioc->base_cmds.status & MPT3_CMD_RESET) 6057 r = -EFAULT; 6058 else 6059 r = -ETIME; 6060 } else 6061 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n", 6062 ioc->name, __func__)); 6063 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 6064 return r; 6065 } 6066 6067 /** 6068 * mpt3sas_base_validate_event_type - validating event types 6069 * @ioc: per adapter object 6070 * @event_type: firmware event 6071 * 6072 * This will turn on firmware event notification when application 6073 * ask for that event. We don't mask events that are already enabled. 6074 */ 6075 void 6076 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type) 6077 { 6078 int i, j; 6079 u32 event_mask, desired_event; 6080 u8 send_update_to_fw; 6081 6082 for (i = 0, send_update_to_fw = 0; i < 6083 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) { 6084 event_mask = ~event_type[i]; 6085 desired_event = 1; 6086 for (j = 0; j < 32; j++) { 6087 if (!(event_mask & desired_event) && 6088 (ioc->event_masks[i] & desired_event)) { 6089 ioc->event_masks[i] &= ~desired_event; 6090 send_update_to_fw = 1; 6091 } 6092 desired_event = (desired_event << 1); 6093 } 6094 } 6095 6096 if (!send_update_to_fw) 6097 return; 6098 6099 mutex_lock(&ioc->base_cmds.mutex); 6100 _base_event_notification(ioc); 6101 mutex_unlock(&ioc->base_cmds.mutex); 6102 } 6103 6104 /** 6105 * _base_diag_reset - the "big hammer" start of day reset 6106 * @ioc: per adapter object 6107 * 6108 * Return: 0 for success, non-zero for failure. 6109 */ 6110 static int 6111 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc) 6112 { 6113 u32 host_diagnostic; 6114 u32 ioc_state; 6115 u32 count; 6116 u32 hcb_size; 6117 6118 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name); 6119 6120 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n", 6121 ioc->name)); 6122 6123 count = 0; 6124 do { 6125 /* Write magic sequence to WriteSequence register 6126 * Loop until in diagnostic mode 6127 */ 6128 drsprintk(ioc, pr_info(MPT3SAS_FMT 6129 "write magic sequence\n", ioc->name)); 6130 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 6131 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence); 6132 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence); 6133 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence); 6134 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence); 6135 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence); 6136 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence); 6137 6138 /* wait 100 msec */ 6139 msleep(100); 6140 6141 if (count++ > 20) 6142 goto out; 6143 6144 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 6145 drsprintk(ioc, pr_info(MPT3SAS_FMT 6146 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n", 6147 ioc->name, count, host_diagnostic)); 6148 6149 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0); 6150 6151 hcb_size = readl(&ioc->chip->HCBSize); 6152 6153 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n", 6154 ioc->name)); 6155 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER, 6156 &ioc->chip->HostDiagnostic); 6157 6158 /*This delay allows the chip PCIe hardware time to finish reset tasks*/ 6159 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000); 6160 6161 /* Approximately 300 second max wait */ 6162 for (count = 0; count < (300000000 / 6163 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) { 6164 6165 host_diagnostic = readl(&ioc->chip->HostDiagnostic); 6166 6167 if (host_diagnostic == 0xFFFFFFFF) 6168 goto out; 6169 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER)) 6170 break; 6171 6172 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC / 1000); 6173 } 6174 6175 if (host_diagnostic & MPI2_DIAG_HCB_MODE) { 6176 6177 drsprintk(ioc, pr_info(MPT3SAS_FMT 6178 "restart the adapter assuming the HCB Address points to good F/W\n", 6179 ioc->name)); 6180 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK; 6181 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW; 6182 writel(host_diagnostic, &ioc->chip->HostDiagnostic); 6183 6184 drsprintk(ioc, pr_info(MPT3SAS_FMT 6185 "re-enable the HCDW\n", ioc->name)); 6186 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE, 6187 &ioc->chip->HCBSize); 6188 } 6189 6190 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n", 6191 ioc->name)); 6192 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET, 6193 &ioc->chip->HostDiagnostic); 6194 6195 drsprintk(ioc, pr_info(MPT3SAS_FMT 6196 "disable writes to the diagnostic register\n", ioc->name)); 6197 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence); 6198 6199 drsprintk(ioc, pr_info(MPT3SAS_FMT 6200 "Wait for FW to go to the READY state\n", ioc->name)); 6201 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20); 6202 if (ioc_state) { 6203 pr_err(MPT3SAS_FMT 6204 "%s: failed going to ready state (ioc_state=0x%x)\n", 6205 ioc->name, __func__, ioc_state); 6206 goto out; 6207 } 6208 6209 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name); 6210 return 0; 6211 6212 out: 6213 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name); 6214 return -EFAULT; 6215 } 6216 6217 /** 6218 * _base_make_ioc_ready - put controller in READY state 6219 * @ioc: per adapter object 6220 * @type: FORCE_BIG_HAMMER or SOFT_RESET 6221 * 6222 * Return: 0 for success, non-zero for failure. 6223 */ 6224 static int 6225 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, enum reset_type type) 6226 { 6227 u32 ioc_state; 6228 int rc; 6229 int count; 6230 6231 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6232 __func__)); 6233 6234 if (ioc->pci_error_recovery) 6235 return 0; 6236 6237 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6238 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n", 6239 ioc->name, __func__, ioc_state)); 6240 6241 /* if in RESET state, it should move to READY state shortly */ 6242 count = 0; 6243 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 6244 while ((ioc_state & MPI2_IOC_STATE_MASK) != 6245 MPI2_IOC_STATE_READY) { 6246 if (count++ == 10) { 6247 pr_err(MPT3SAS_FMT 6248 "%s: failed going to ready state (ioc_state=0x%x)\n", 6249 ioc->name, __func__, ioc_state); 6250 return -EFAULT; 6251 } 6252 ssleep(1); 6253 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6254 } 6255 } 6256 6257 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) 6258 return 0; 6259 6260 if (ioc_state & MPI2_DOORBELL_USED) { 6261 dhsprintk(ioc, pr_info(MPT3SAS_FMT 6262 "unexpected doorbell active!\n", 6263 ioc->name)); 6264 goto issue_diag_reset; 6265 } 6266 6267 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 6268 mpt3sas_base_fault_info(ioc, ioc_state & 6269 MPI2_DOORBELL_DATA_MASK); 6270 goto issue_diag_reset; 6271 } 6272 6273 if (type == FORCE_BIG_HAMMER) 6274 goto issue_diag_reset; 6275 6276 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL) 6277 if (!(_base_send_ioc_reset(ioc, 6278 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15))) { 6279 return 0; 6280 } 6281 6282 issue_diag_reset: 6283 rc = _base_diag_reset(ioc); 6284 return rc; 6285 } 6286 6287 /** 6288 * _base_make_ioc_operational - put controller in OPERATIONAL state 6289 * @ioc: per adapter object 6290 * 6291 * Return: 0 for success, non-zero for failure. 6292 */ 6293 static int 6294 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc) 6295 { 6296 int r, i, index; 6297 unsigned long flags; 6298 u32 reply_address; 6299 u16 smid; 6300 struct _tr_list *delayed_tr, *delayed_tr_next; 6301 struct _sc_list *delayed_sc, *delayed_sc_next; 6302 struct _event_ack_list *delayed_event_ack, *delayed_event_ack_next; 6303 u8 hide_flag; 6304 struct adapter_reply_queue *reply_q; 6305 Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig; 6306 6307 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6308 __func__)); 6309 6310 /* clean the delayed target reset list */ 6311 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 6312 &ioc->delayed_tr_list, list) { 6313 list_del(&delayed_tr->list); 6314 kfree(delayed_tr); 6315 } 6316 6317 6318 list_for_each_entry_safe(delayed_tr, delayed_tr_next, 6319 &ioc->delayed_tr_volume_list, list) { 6320 list_del(&delayed_tr->list); 6321 kfree(delayed_tr); 6322 } 6323 6324 list_for_each_entry_safe(delayed_sc, delayed_sc_next, 6325 &ioc->delayed_sc_list, list) { 6326 list_del(&delayed_sc->list); 6327 kfree(delayed_sc); 6328 } 6329 6330 list_for_each_entry_safe(delayed_event_ack, delayed_event_ack_next, 6331 &ioc->delayed_event_ack_list, list) { 6332 list_del(&delayed_event_ack->list); 6333 kfree(delayed_event_ack); 6334 } 6335 6336 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags); 6337 6338 /* hi-priority queue */ 6339 INIT_LIST_HEAD(&ioc->hpr_free_list); 6340 smid = ioc->hi_priority_smid; 6341 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) { 6342 ioc->hpr_lookup[i].cb_idx = 0xFF; 6343 ioc->hpr_lookup[i].smid = smid; 6344 list_add_tail(&ioc->hpr_lookup[i].tracker_list, 6345 &ioc->hpr_free_list); 6346 } 6347 6348 /* internal queue */ 6349 INIT_LIST_HEAD(&ioc->internal_free_list); 6350 smid = ioc->internal_smid; 6351 for (i = 0; i < ioc->internal_depth; i++, smid++) { 6352 ioc->internal_lookup[i].cb_idx = 0xFF; 6353 ioc->internal_lookup[i].smid = smid; 6354 list_add_tail(&ioc->internal_lookup[i].tracker_list, 6355 &ioc->internal_free_list); 6356 } 6357 6358 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags); 6359 6360 /* initialize Reply Free Queue */ 6361 for (i = 0, reply_address = (u32)ioc->reply_dma ; 6362 i < ioc->reply_free_queue_depth ; i++, reply_address += 6363 ioc->reply_sz) { 6364 ioc->reply_free[i] = cpu_to_le32(reply_address); 6365 if (ioc->is_mcpu_endpoint) 6366 _base_clone_reply_to_sys_mem(ioc, 6367 reply_address, i); 6368 } 6369 6370 /* initialize reply queues */ 6371 if (ioc->is_driver_loading) 6372 _base_assign_reply_queues(ioc); 6373 6374 /* initialize Reply Post Free Queue */ 6375 index = 0; 6376 reply_post_free_contig = ioc->reply_post[0].reply_post_free; 6377 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 6378 /* 6379 * If RDPQ is enabled, switch to the next allocation. 6380 * Otherwise advance within the contiguous region. 6381 */ 6382 if (ioc->rdpq_array_enable) { 6383 reply_q->reply_post_free = 6384 ioc->reply_post[index++].reply_post_free; 6385 } else { 6386 reply_q->reply_post_free = reply_post_free_contig; 6387 reply_post_free_contig += ioc->reply_post_queue_depth; 6388 } 6389 6390 reply_q->reply_post_host_index = 0; 6391 for (i = 0; i < ioc->reply_post_queue_depth; i++) 6392 reply_q->reply_post_free[i].Words = 6393 cpu_to_le64(ULLONG_MAX); 6394 if (!_base_is_controller_msix_enabled(ioc)) 6395 goto skip_init_reply_post_free_queue; 6396 } 6397 skip_init_reply_post_free_queue: 6398 6399 r = _base_send_ioc_init(ioc); 6400 if (r) 6401 return r; 6402 6403 /* initialize reply free host index */ 6404 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1; 6405 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex); 6406 6407 /* initialize reply post host index */ 6408 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) { 6409 if (ioc->combined_reply_queue) 6410 writel((reply_q->msix_index & 7)<< 6411 MPI2_RPHI_MSIX_INDEX_SHIFT, 6412 ioc->replyPostRegisterIndex[reply_q->msix_index/8]); 6413 else 6414 writel(reply_q->msix_index << 6415 MPI2_RPHI_MSIX_INDEX_SHIFT, 6416 &ioc->chip->ReplyPostHostIndex); 6417 6418 if (!_base_is_controller_msix_enabled(ioc)) 6419 goto skip_init_reply_post_host_index; 6420 } 6421 6422 skip_init_reply_post_host_index: 6423 6424 _base_unmask_interrupts(ioc); 6425 6426 if (ioc->hba_mpi_version_belonged != MPI2_VERSION) { 6427 r = _base_display_fwpkg_version(ioc); 6428 if (r) 6429 return r; 6430 } 6431 6432 _base_static_config_pages(ioc); 6433 r = _base_event_notification(ioc); 6434 if (r) 6435 return r; 6436 6437 if (ioc->is_driver_loading) { 6438 6439 if (ioc->is_warpdrive && ioc->manu_pg10.OEMIdentifier 6440 == 0x80) { 6441 hide_flag = (u8) ( 6442 le32_to_cpu(ioc->manu_pg10.OEMSpecificFlags0) & 6443 MFG_PAGE10_HIDE_SSDS_MASK); 6444 if (hide_flag != MFG_PAGE10_HIDE_SSDS_MASK) 6445 ioc->mfg_pg10_hide_flag = hide_flag; 6446 } 6447 6448 ioc->wait_for_discovery_to_complete = 6449 _base_determine_wait_on_discovery(ioc); 6450 6451 return r; /* scan_start and scan_finished support */ 6452 } 6453 6454 r = _base_send_port_enable(ioc); 6455 if (r) 6456 return r; 6457 6458 return r; 6459 } 6460 6461 /** 6462 * mpt3sas_base_free_resources - free resources controller resources 6463 * @ioc: per adapter object 6464 */ 6465 void 6466 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc) 6467 { 6468 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6469 __func__)); 6470 6471 /* synchronizing freeing resource with pci_access_mutex lock */ 6472 mutex_lock(&ioc->pci_access_mutex); 6473 if (ioc->chip_phys && ioc->chip) { 6474 _base_mask_interrupts(ioc); 6475 ioc->shost_recovery = 1; 6476 _base_make_ioc_ready(ioc, SOFT_RESET); 6477 ioc->shost_recovery = 0; 6478 } 6479 6480 mpt3sas_base_unmap_resources(ioc); 6481 mutex_unlock(&ioc->pci_access_mutex); 6482 return; 6483 } 6484 6485 /** 6486 * mpt3sas_base_attach - attach controller instance 6487 * @ioc: per adapter object 6488 * 6489 * Return: 0 for success, non-zero for failure. 6490 */ 6491 int 6492 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) 6493 { 6494 int r, i; 6495 int cpu_id, last_cpu_id = 0; 6496 6497 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6498 __func__)); 6499 6500 /* setup cpu_msix_table */ 6501 ioc->cpu_count = num_online_cpus(); 6502 for_each_online_cpu(cpu_id) 6503 last_cpu_id = cpu_id; 6504 ioc->cpu_msix_table_sz = last_cpu_id + 1; 6505 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL); 6506 ioc->reply_queue_count = 1; 6507 if (!ioc->cpu_msix_table) { 6508 dfailprintk(ioc, pr_info(MPT3SAS_FMT 6509 "allocation for cpu_msix_table failed!!!\n", 6510 ioc->name)); 6511 r = -ENOMEM; 6512 goto out_free_resources; 6513 } 6514 6515 if (ioc->is_warpdrive) { 6516 ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz, 6517 sizeof(resource_size_t *), GFP_KERNEL); 6518 if (!ioc->reply_post_host_index) { 6519 dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation " 6520 "for reply_post_host_index failed!!!\n", 6521 ioc->name)); 6522 r = -ENOMEM; 6523 goto out_free_resources; 6524 } 6525 } 6526 6527 ioc->rdpq_array_enable_assigned = 0; 6528 ioc->dma_mask = 0; 6529 r = mpt3sas_base_map_resources(ioc); 6530 if (r) 6531 goto out_free_resources; 6532 6533 pci_set_drvdata(ioc->pdev, ioc->shost); 6534 r = _base_get_ioc_facts(ioc); 6535 if (r) 6536 goto out_free_resources; 6537 6538 switch (ioc->hba_mpi_version_belonged) { 6539 case MPI2_VERSION: 6540 ioc->build_sg_scmd = &_base_build_sg_scmd; 6541 ioc->build_sg = &_base_build_sg; 6542 ioc->build_zero_len_sge = &_base_build_zero_len_sge; 6543 break; 6544 case MPI25_VERSION: 6545 case MPI26_VERSION: 6546 /* 6547 * In SAS3.0, 6548 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and 6549 * Target Status - all require the IEEE formated scatter gather 6550 * elements. 6551 */ 6552 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee; 6553 ioc->build_sg = &_base_build_sg_ieee; 6554 ioc->build_nvme_prp = &_base_build_nvme_prp; 6555 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee; 6556 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t); 6557 6558 break; 6559 } 6560 6561 if (ioc->is_mcpu_endpoint) 6562 ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io; 6563 else 6564 ioc->put_smid_scsi_io = &_base_put_smid_scsi_io; 6565 6566 /* 6567 * These function pointers for other requests that don't 6568 * the require IEEE scatter gather elements. 6569 * 6570 * For example Configuration Pages and SAS IOUNIT Control don't. 6571 */ 6572 ioc->build_sg_mpi = &_base_build_sg; 6573 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge; 6574 6575 r = _base_make_ioc_ready(ioc, SOFT_RESET); 6576 if (r) 6577 goto out_free_resources; 6578 6579 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts, 6580 sizeof(struct mpt3sas_port_facts), GFP_KERNEL); 6581 if (!ioc->pfacts) { 6582 r = -ENOMEM; 6583 goto out_free_resources; 6584 } 6585 6586 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) { 6587 r = _base_get_port_facts(ioc, i); 6588 if (r) 6589 goto out_free_resources; 6590 } 6591 6592 r = _base_allocate_memory_pools(ioc); 6593 if (r) 6594 goto out_free_resources; 6595 6596 init_waitqueue_head(&ioc->reset_wq); 6597 6598 /* allocate memory pd handle bitmask list */ 6599 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8); 6600 if (ioc->facts.MaxDevHandle % 8) 6601 ioc->pd_handles_sz++; 6602 ioc->pd_handles = kzalloc(ioc->pd_handles_sz, 6603 GFP_KERNEL); 6604 if (!ioc->pd_handles) { 6605 r = -ENOMEM; 6606 goto out_free_resources; 6607 } 6608 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz, 6609 GFP_KERNEL); 6610 if (!ioc->blocking_handles) { 6611 r = -ENOMEM; 6612 goto out_free_resources; 6613 } 6614 6615 /* allocate memory for pending OS device add list */ 6616 ioc->pend_os_device_add_sz = (ioc->facts.MaxDevHandle / 8); 6617 if (ioc->facts.MaxDevHandle % 8) 6618 ioc->pend_os_device_add_sz++; 6619 ioc->pend_os_device_add = kzalloc(ioc->pend_os_device_add_sz, 6620 GFP_KERNEL); 6621 if (!ioc->pend_os_device_add) 6622 goto out_free_resources; 6623 6624 ioc->device_remove_in_progress_sz = ioc->pend_os_device_add_sz; 6625 ioc->device_remove_in_progress = 6626 kzalloc(ioc->device_remove_in_progress_sz, GFP_KERNEL); 6627 if (!ioc->device_remove_in_progress) 6628 goto out_free_resources; 6629 6630 ioc->fwfault_debug = mpt3sas_fwfault_debug; 6631 6632 /* base internal command bits */ 6633 mutex_init(&ioc->base_cmds.mutex); 6634 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6635 ioc->base_cmds.status = MPT3_CMD_NOT_USED; 6636 6637 /* port_enable command bits */ 6638 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6639 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED; 6640 6641 /* transport internal command bits */ 6642 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6643 ioc->transport_cmds.status = MPT3_CMD_NOT_USED; 6644 mutex_init(&ioc->transport_cmds.mutex); 6645 6646 /* scsih internal command bits */ 6647 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6648 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED; 6649 mutex_init(&ioc->scsih_cmds.mutex); 6650 6651 /* task management internal command bits */ 6652 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6653 ioc->tm_cmds.status = MPT3_CMD_NOT_USED; 6654 mutex_init(&ioc->tm_cmds.mutex); 6655 6656 /* config page internal command bits */ 6657 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6658 ioc->config_cmds.status = MPT3_CMD_NOT_USED; 6659 mutex_init(&ioc->config_cmds.mutex); 6660 6661 /* ctl module internal command bits */ 6662 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL); 6663 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL); 6664 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED; 6665 mutex_init(&ioc->ctl_cmds.mutex); 6666 6667 if (!ioc->base_cmds.reply || !ioc->port_enable_cmds.reply || 6668 !ioc->transport_cmds.reply || !ioc->scsih_cmds.reply || 6669 !ioc->tm_cmds.reply || !ioc->config_cmds.reply || 6670 !ioc->ctl_cmds.reply || !ioc->ctl_cmds.sense) { 6671 r = -ENOMEM; 6672 goto out_free_resources; 6673 } 6674 6675 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 6676 ioc->event_masks[i] = -1; 6677 6678 /* here we enable the events we care about */ 6679 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY); 6680 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE); 6681 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 6682 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE); 6683 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE); 6684 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST); 6685 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME); 6686 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK); 6687 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS); 6688 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED); 6689 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD); 6690 _base_unmask_events(ioc, MPI2_EVENT_ACTIVE_CABLE_EXCEPTION); 6691 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 6692 if (ioc->hba_mpi_version_belonged == MPI26_VERSION) { 6693 if (ioc->is_gen35_ioc) { 6694 _base_unmask_events(ioc, 6695 MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE); 6696 _base_unmask_events(ioc, MPI2_EVENT_PCIE_ENUMERATION); 6697 _base_unmask_events(ioc, 6698 MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 6699 } 6700 } 6701 r = _base_make_ioc_operational(ioc); 6702 if (r) 6703 goto out_free_resources; 6704 6705 ioc->non_operational_loop = 0; 6706 ioc->got_task_abort_from_ioctl = 0; 6707 return 0; 6708 6709 out_free_resources: 6710 6711 ioc->remove_host = 1; 6712 6713 mpt3sas_base_free_resources(ioc); 6714 _base_release_memory_pools(ioc); 6715 pci_set_drvdata(ioc->pdev, NULL); 6716 kfree(ioc->cpu_msix_table); 6717 if (ioc->is_warpdrive) 6718 kfree(ioc->reply_post_host_index); 6719 kfree(ioc->pd_handles); 6720 kfree(ioc->blocking_handles); 6721 kfree(ioc->device_remove_in_progress); 6722 kfree(ioc->pend_os_device_add); 6723 kfree(ioc->tm_cmds.reply); 6724 kfree(ioc->transport_cmds.reply); 6725 kfree(ioc->scsih_cmds.reply); 6726 kfree(ioc->config_cmds.reply); 6727 kfree(ioc->base_cmds.reply); 6728 kfree(ioc->port_enable_cmds.reply); 6729 kfree(ioc->ctl_cmds.reply); 6730 kfree(ioc->ctl_cmds.sense); 6731 kfree(ioc->pfacts); 6732 ioc->ctl_cmds.reply = NULL; 6733 ioc->base_cmds.reply = NULL; 6734 ioc->tm_cmds.reply = NULL; 6735 ioc->scsih_cmds.reply = NULL; 6736 ioc->transport_cmds.reply = NULL; 6737 ioc->config_cmds.reply = NULL; 6738 ioc->pfacts = NULL; 6739 return r; 6740 } 6741 6742 6743 /** 6744 * mpt3sas_base_detach - remove controller instance 6745 * @ioc: per adapter object 6746 */ 6747 void 6748 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc) 6749 { 6750 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name, 6751 __func__)); 6752 6753 mpt3sas_base_stop_watchdog(ioc); 6754 mpt3sas_base_free_resources(ioc); 6755 _base_release_memory_pools(ioc); 6756 mpt3sas_free_enclosure_list(ioc); 6757 pci_set_drvdata(ioc->pdev, NULL); 6758 kfree(ioc->cpu_msix_table); 6759 if (ioc->is_warpdrive) 6760 kfree(ioc->reply_post_host_index); 6761 kfree(ioc->pd_handles); 6762 kfree(ioc->blocking_handles); 6763 kfree(ioc->device_remove_in_progress); 6764 kfree(ioc->pend_os_device_add); 6765 kfree(ioc->pfacts); 6766 kfree(ioc->ctl_cmds.reply); 6767 kfree(ioc->ctl_cmds.sense); 6768 kfree(ioc->base_cmds.reply); 6769 kfree(ioc->port_enable_cmds.reply); 6770 kfree(ioc->tm_cmds.reply); 6771 kfree(ioc->transport_cmds.reply); 6772 kfree(ioc->scsih_cmds.reply); 6773 kfree(ioc->config_cmds.reply); 6774 } 6775 6776 /** 6777 * _base_pre_reset_handler - pre reset handler 6778 * @ioc: per adapter object 6779 */ 6780 static void _base_pre_reset_handler(struct MPT3SAS_ADAPTER *ioc) 6781 { 6782 mpt3sas_scsih_pre_reset_handler(ioc); 6783 mpt3sas_ctl_pre_reset_handler(ioc); 6784 dtmprintk(ioc, pr_info(MPT3SAS_FMT 6785 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__)); 6786 } 6787 6788 /** 6789 * _base_after_reset_handler - after reset handler 6790 * @ioc: per adapter object 6791 */ 6792 static void _base_after_reset_handler(struct MPT3SAS_ADAPTER *ioc) 6793 { 6794 mpt3sas_scsih_after_reset_handler(ioc); 6795 mpt3sas_ctl_after_reset_handler(ioc); 6796 dtmprintk(ioc, pr_info(MPT3SAS_FMT 6797 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__)); 6798 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) { 6799 ioc->transport_cmds.status |= MPT3_CMD_RESET; 6800 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid); 6801 complete(&ioc->transport_cmds.done); 6802 } 6803 if (ioc->base_cmds.status & MPT3_CMD_PENDING) { 6804 ioc->base_cmds.status |= MPT3_CMD_RESET; 6805 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid); 6806 complete(&ioc->base_cmds.done); 6807 } 6808 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) { 6809 ioc->port_enable_failed = 1; 6810 ioc->port_enable_cmds.status |= MPT3_CMD_RESET; 6811 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid); 6812 if (ioc->is_driver_loading) { 6813 ioc->start_scan_failed = 6814 MPI2_IOCSTATUS_INTERNAL_ERROR; 6815 ioc->start_scan = 0; 6816 ioc->port_enable_cmds.status = 6817 MPT3_CMD_NOT_USED; 6818 } else { 6819 complete(&ioc->port_enable_cmds.done); 6820 } 6821 } 6822 if (ioc->config_cmds.status & MPT3_CMD_PENDING) { 6823 ioc->config_cmds.status |= MPT3_CMD_RESET; 6824 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid); 6825 ioc->config_cmds.smid = USHRT_MAX; 6826 complete(&ioc->config_cmds.done); 6827 } 6828 } 6829 6830 /** 6831 * _base_reset_done_handler - reset done handler 6832 * @ioc: per adapter object 6833 */ 6834 static void _base_reset_done_handler(struct MPT3SAS_ADAPTER *ioc) 6835 { 6836 mpt3sas_scsih_reset_done_handler(ioc); 6837 mpt3sas_ctl_reset_done_handler(ioc); 6838 dtmprintk(ioc, pr_info(MPT3SAS_FMT 6839 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__)); 6840 } 6841 6842 /** 6843 * mpt3sas_wait_for_commands_to_complete - reset controller 6844 * @ioc: Pointer to MPT_ADAPTER structure 6845 * 6846 * This function is waiting 10s for all pending commands to complete 6847 * prior to putting controller in reset. 6848 */ 6849 void 6850 mpt3sas_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc) 6851 { 6852 u32 ioc_state; 6853 6854 ioc->pending_io_count = 0; 6855 6856 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6857 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) 6858 return; 6859 6860 /* pending command count */ 6861 ioc->pending_io_count = scsi_host_busy(ioc->shost); 6862 6863 if (!ioc->pending_io_count) 6864 return; 6865 6866 /* wait for pending commands to complete */ 6867 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ); 6868 } 6869 6870 /** 6871 * mpt3sas_base_hard_reset_handler - reset controller 6872 * @ioc: Pointer to MPT_ADAPTER structure 6873 * @type: FORCE_BIG_HAMMER or SOFT_RESET 6874 * 6875 * Return: 0 for success, non-zero for failure. 6876 */ 6877 int 6878 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, 6879 enum reset_type type) 6880 { 6881 int r; 6882 unsigned long flags; 6883 u32 ioc_state; 6884 u8 is_fault = 0, is_trigger = 0; 6885 6886 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name, 6887 __func__)); 6888 6889 if (ioc->pci_error_recovery) { 6890 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n", 6891 ioc->name, __func__); 6892 r = 0; 6893 goto out_unlocked; 6894 } 6895 6896 if (mpt3sas_fwfault_debug) 6897 mpt3sas_halt_firmware(ioc); 6898 6899 /* wait for an active reset in progress to complete */ 6900 mutex_lock(&ioc->reset_in_progress_mutex); 6901 6902 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 6903 ioc->shost_recovery = 1; 6904 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 6905 6906 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 6907 MPT3_DIAG_BUFFER_IS_REGISTERED) && 6908 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] & 6909 MPT3_DIAG_BUFFER_IS_RELEASED))) { 6910 is_trigger = 1; 6911 ioc_state = mpt3sas_base_get_iocstate(ioc, 0); 6912 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) 6913 is_fault = 1; 6914 } 6915 _base_pre_reset_handler(ioc); 6916 mpt3sas_wait_for_commands_to_complete(ioc); 6917 _base_mask_interrupts(ioc); 6918 r = _base_make_ioc_ready(ioc, type); 6919 if (r) 6920 goto out; 6921 _base_after_reset_handler(ioc); 6922 6923 /* If this hard reset is called while port enable is active, then 6924 * there is no reason to call make_ioc_operational 6925 */ 6926 if (ioc->is_driver_loading && ioc->port_enable_failed) { 6927 ioc->remove_host = 1; 6928 r = -EFAULT; 6929 goto out; 6930 } 6931 r = _base_get_ioc_facts(ioc); 6932 if (r) 6933 goto out; 6934 6935 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable) 6936 panic("%s: Issue occurred with flashing controller firmware." 6937 "Please reboot the system and ensure that the correct" 6938 " firmware version is running\n", ioc->name); 6939 6940 r = _base_make_ioc_operational(ioc); 6941 if (!r) 6942 _base_reset_done_handler(ioc); 6943 6944 out: 6945 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n", 6946 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED"))); 6947 6948 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags); 6949 ioc->shost_recovery = 0; 6950 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags); 6951 ioc->ioc_reset_count++; 6952 mutex_unlock(&ioc->reset_in_progress_mutex); 6953 6954 out_unlocked: 6955 if ((r == 0) && is_trigger) { 6956 if (is_fault) 6957 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT); 6958 else 6959 mpt3sas_trigger_master(ioc, 6960 MASTER_TRIGGER_ADAPTER_RESET); 6961 } 6962 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name, 6963 __func__)); 6964 return r; 6965 } 6966