xref: /linux/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h (revision e2be04c7f9958dde770eeb8b30e829ca969b37bb)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2000-2015 Avago Technologies.  All rights reserved.
4  *
5  *
6  *          Name:  mpi2_cnfg.h
7  *         Title:  MPI Configuration messages and pages
8  * Creation Date:  November 10, 2006
9  *
10  *   mpi2_cnfg.h Version:  02.00.35
11  *
12  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13  *       prefix are for use only on MPI v2.5 products, and must not be used
14  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
15  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16  *
17  * Version History
18  * ---------------
19  *
20  * Date      Version   Description
21  * --------  --------  ------------------------------------------------------
22  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
23  * 06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
24  *                     Added Manufacturing Page 11.
25  *                     Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26  *                     define.
27  * 06-26-07  02.00.02  Adding generic structure for product-specific
28  *                     Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29  *                     Rework of BIOS Page 2 configuration page.
30  *                     Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31  *                     forms.
32  *                     Added configuration pages IOC Page 8 and Driver
33  *                     Persistent Mapping Page 0.
34  * 08-31-07  02.00.03  Modified configuration pages dealing with Integrated
35  *                     RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36  *                     RAID Physical Disk Pages 0 and 1, RAID Configuration
37  *                     Page 0).
38  *                     Added new value for AccessStatus field of SAS Device
39  *                     Page 0 (_SATA_NEEDS_INITIALIZATION).
40  * 10-31-07  02.00.04  Added missing SEPDevHandle field to
41  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42  * 12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
43  *                     NVDATA.
44  *                     Modified IOC Page 7 to use masks and added field for
45  *                     SASBroadcastPrimitiveMasks.
46  *                     Added MPI2_CONFIG_PAGE_BIOS_4.
47  *                     Added MPI2_CONFIG_PAGE_LOG_0.
48  * 02-29-08  02.00.06  Modified various names to make them 32-character unique.
49  *                     Added SAS Device IDs.
50  *                     Updated Integrated RAID configuration pages including
51  *                     Manufacturing Page 4, IOC Page 6, and RAID Configuration
52  *                     Page 0.
53  * 05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54  *                     Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55  *                     Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56  *                     Added missing MaxNumRoutedSasAddresses field to
57  *                     MPI2_CONFIG_PAGE_EXPANDER_0.
58  *                     Added SAS Port Page 0.
59  *                     Modified structure layout for
60  *                     MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61  * 06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62  *                     MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63  * 10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64  *                     to 0x000000FF.
65  *                     Added two new values for the Physical Disk Coercion Size
66  *                     bits in the Flags field of Manufacturing Page 4.
67  *                     Added product-specific Manufacturing pages 16 to 31.
68  *                     Modified Flags bits for controlling write cache on SATA
69  *                     drives in IO Unit Page 1.
70  *                     Added new bit to AdditionalControlFlags of SAS IO Unit
71  *                     Page 1 to control Invalid Topology Correction.
72  *                     Added additional defines for RAID Volume Page 0
73  *                     VolumeStatusFlags field.
74  *                     Modified meaning of RAID Volume Page 0 VolumeSettings
75  *                     define for auto-configure of hot-swap drives.
76  *                     Added SupportedPhysDisks field to RAID Volume Page 1 and
77  *                     added related defines.
78  *                     Added PhysDiskAttributes field (and related defines) to
79  *                     RAID Physical Disk Page 0.
80  *                     Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81  *                     Added three new DiscoveryStatus bits for SAS IO Unit
82  *                     Page 0 and SAS Expander Page 0.
83  *                     Removed multiplexing information from SAS IO Unit pages.
84  *                     Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85  *                     Removed Zone Address Resolved bit from PhyInfo and from
86  *                     Expander Page 0 Flags field.
87  *                     Added two new AccessStatus values to SAS Device Page 0
88  *                     for indicating routing problems. Added 3 reserved words
89  *                     to this page.
90  * 01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
91  *                     Inserted missing reserved field into structure for IOC
92  *                     Page 6.
93  *                     Added more pending task bits to RAID Volume Page 0
94  *                     VolumeStatusFlags defines.
95  *                     Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96  *                     Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97  *                     and SAS Expander Page 0 to flag a downstream initiator
98  *                     when in simplified routing mode.
99  *                     Removed SATA Init Failure defines for DiscoveryStatus
100  *                     fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101  *                     Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102  *                     Added PortGroups, DmaGroup, and ControlGroup fields to
103  *                     SAS Device Page 0.
104  * 05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
105  *                     Unit Page 6.
106  *                     Added expander reduced functionality data to SAS
107  *                     Expander Page 0.
108  *                     Added SAS PHY Page 2 and SAS PHY Page 3.
109  * 07-30-09  02.00.12  Added IO Unit Page 7.
110  *                     Added new device ids.
111  *                     Added SAS IO Unit Page 5.
112  *                     Added partial and slumber power management capable flags
113  *                     to SAS Device Page 0 Flags field.
114  *                     Added PhyInfo defines for power condition.
115  *                     Added Ethernet configuration pages.
116  * 10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117  *                     Added SAS PHY Page 4 structure and defines.
118  * 02-10-10  02.00.14  Modified the comments for the configuration page
119  *                     structures that contain an array of data. The host
120  *                     should use the "count" field in the page data (e.g. the
121  *                     NumPhys field) to determine the number of valid elements
122  *                     in the array.
123  *                     Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124  *                     Added PowerManagementCapabilities to IO Unit Page 7.
125  *                     Added PortWidthModGroup field to
126  *                     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130  * 05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131  *                     define.
132  *                     Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133  *                     Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134  * 08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
135  *                     defines.
136  * 11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
137  *                     MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138  *                     the Pinout field.
139  *                     Added BoardTemperature and BoardTemperatureUnits fields
140  *                     to MPI2_CONFIG_PAGE_IO_UNIT_7.
141  *                     Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142  *                     and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143  * 02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144  *                     Added IO Unit Page 8, IO Unit Page 9,
145  *                     and IO Unit Page 10.
146  *                     Added SASNotifyPrimitiveMasks field to
147  *                     MPI2_CONFIG_PAGE_IOC_7.
148  * 03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
149  * 05-25-11  02.00.20  Cleaned up a few comments.
150  * 08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
151  *                     for PCIe link as obsolete.
152  *                     Added SpinupFlags field containing a Disable Spin-up bit
153  *                     to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154  *                     Unit Page 4.
155  * 11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156  *                     Added UEFIVersion field to BIOS Page 1 and defined new
157  *                     BiosOptions bits.
158  *                     Incorporating additions for MPI v2.5.
159  * 11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160  *                     Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161  * 12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162  *                     obsolete for MPI v2.5 and later.
163  *                     Added some defines for 12G SAS speeds.
164  * 04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165  *                     Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166  *                     match the specification.
167  * 08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168  *			future use.
169  * 12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170  *		       MPI2_CONFIG_PAGE_MAN_7.
171  *		       Added EnclosureLevel and ConnectorName fields to
172  *		       MPI2_CONFIG_PAGE_SAS_DEV_0.
173  *		       Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174  *		       MPI2_CONFIG_PAGE_SAS_DEV_0.
175  *		       Added EnclosureLevel field to
176  *		       MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177  *		       Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178  *		       MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179  * 01-08-14  02.00.28  Added more defines for the BiosOptions field of
180  *		       MPI2_CONFIG_PAGE_BIOS_1.
181  * 06-13-14  02.00.29  Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182  *                     more defines for the BiosOptions field.
183  * 11-18-14  02.00.30  Updated copyright information.
184  *                     Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185  *                     Added AdapterOrderAux fields to BIOS Page 3.
186  * 03-16-15  02.00.31  Updated for MPI v2.6.
187  *                     Added Flags field to IO Unit Page 7.
188  *                     Added new SAS Phy Event codes
189  * 05-25-15  02.00.33  Added more defines for the BiosOptions field of
190  *                     MPI2_CONFIG_PAGE_BIOS_1.
191  * 08-25-15  02.00.34  Bumped Header Version.
192  * 12-18-15  02.00.35  Added SATADeviceWaitTime to SAS IO Unit Page 4.
193  * --------------------------------------------------------------------------
194  */
195 
196 #ifndef MPI2_CNFG_H
197 #define MPI2_CNFG_H
198 
199 /*****************************************************************************
200 *  Configuration Page Header and defines
201 *****************************************************************************/
202 
203 /*Config Page Header */
204 typedef struct _MPI2_CONFIG_PAGE_HEADER {
205 	U8                 PageVersion;                /*0x00 */
206 	U8                 PageLength;                 /*0x01 */
207 	U8                 PageNumber;                 /*0x02 */
208 	U8                 PageType;                   /*0x03 */
209 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
210 	Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
211 
212 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
213 	MPI2_CONFIG_PAGE_HEADER  Struct;
214 	U8                       Bytes[4];
215 	U16                      Word16[2];
216 	U32                      Word32;
217 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
218 	Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
219 
220 /*Extended Config Page Header */
221 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
222 	U8                  PageVersion;                /*0x00 */
223 	U8                  Reserved1;                  /*0x01 */
224 	U8                  PageNumber;                 /*0x02 */
225 	U8                  PageType;                   /*0x03 */
226 	U16                 ExtPageLength;              /*0x04 */
227 	U8                  ExtPageType;                /*0x06 */
228 	U8                  Reserved2;                  /*0x07 */
229 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
230 	*PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
231 	Mpi2ConfigExtendedPageHeader_t,
232 	*pMpi2ConfigExtendedPageHeader_t;
233 
234 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
235 	MPI2_CONFIG_PAGE_HEADER          Struct;
236 	MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
237 	U8                               Bytes[8];
238 	U16                              Word16[4];
239 	U32                              Word32[2];
240 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
241 	*PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
242 	Mpi2ConfigPageExtendedHeaderUnion,
243 	*pMpi2ConfigPageExtendedHeaderUnion;
244 
245 
246 /*PageType field values */
247 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
248 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
249 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
250 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
251 
252 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
253 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
254 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
255 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
256 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
257 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
258 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
259 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
260 
261 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
262 
263 
264 /*ExtPageType field values */
265 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
266 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
267 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
268 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
269 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
270 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
271 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
272 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
273 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
274 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
275 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
276 
277 
278 /*****************************************************************************
279 *  PageAddress defines
280 *****************************************************************************/
281 
282 /*RAID Volume PageAddress format */
283 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
284 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
285 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
286 
287 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
288 
289 
290 /*RAID Physical Disk PageAddress format */
291 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
292 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
293 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
294 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
295 
296 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
297 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
298 
299 
300 /*SAS Expander PageAddress format */
301 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
302 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
303 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
304 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
305 
306 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
307 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
308 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
309 
310 
311 /*SAS Device PageAddress format */
312 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
313 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
314 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
315 
316 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
317 
318 
319 /*SAS PHY PageAddress format */
320 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
321 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
322 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
323 
324 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
325 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
326 
327 
328 /*SAS Port PageAddress format */
329 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
330 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
331 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
332 
333 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
334 
335 
336 /*SAS Enclosure PageAddress format */
337 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
338 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
339 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
340 
341 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
342 
343 
344 /*RAID Configuration PageAddress format */
345 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
346 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
347 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
348 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
349 
350 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
351 
352 
353 /*Driver Persistent Mapping PageAddress format */
354 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
355 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
356 
357 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
358 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
359 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
360 
361 
362 /*Ethernet PageAddress format */
363 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
364 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
365 
366 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
367 
368 
369 /****************************************************************************
370 *  Configuration messages
371 ****************************************************************************/
372 
373 /*Configuration Request Message */
374 typedef struct _MPI2_CONFIG_REQUEST {
375 	U8                      Action;                     /*0x00 */
376 	U8                      SGLFlags;                   /*0x01 */
377 	U8                      ChainOffset;                /*0x02 */
378 	U8                      Function;                   /*0x03 */
379 	U16                     ExtPageLength;              /*0x04 */
380 	U8                      ExtPageType;                /*0x06 */
381 	U8                      MsgFlags;                   /*0x07 */
382 	U8                      VP_ID;                      /*0x08 */
383 	U8                      VF_ID;                      /*0x09 */
384 	U16                     Reserved1;                  /*0x0A */
385 	U8                      Reserved2;                  /*0x0C */
386 	U8                      ProxyVF_ID;                 /*0x0D */
387 	U16                     Reserved4;                  /*0x0E */
388 	U32                     Reserved3;                  /*0x10 */
389 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
390 	U32                     PageAddress;                /*0x18 */
391 	MPI2_SGE_IO_UNION       PageBufferSGE;              /*0x1C */
392 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
393 	Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
394 
395 /*values for the Action field */
396 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
397 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
398 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
399 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
400 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
401 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
402 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
403 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
404 
405 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
406 
407 
408 /*Config Reply Message */
409 typedef struct _MPI2_CONFIG_REPLY {
410 	U8                      Action;                     /*0x00 */
411 	U8                      SGLFlags;                   /*0x01 */
412 	U8                      MsgLength;                  /*0x02 */
413 	U8                      Function;                   /*0x03 */
414 	U16                     ExtPageLength;              /*0x04 */
415 	U8                      ExtPageType;                /*0x06 */
416 	U8                      MsgFlags;                   /*0x07 */
417 	U8                      VP_ID;                      /*0x08 */
418 	U8                      VF_ID;                      /*0x09 */
419 	U16                     Reserved1;                  /*0x0A */
420 	U16                     Reserved2;                  /*0x0C */
421 	U16                     IOCStatus;                  /*0x0E */
422 	U32                     IOCLogInfo;                 /*0x10 */
423 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
424 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
425 	Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
426 
427 
428 
429 /*****************************************************************************
430 *
431 *              C o n f i g u r a t i o n    P a g e s
432 *
433 *****************************************************************************/
434 
435 /****************************************************************************
436 *  Manufacturing Config pages
437 ****************************************************************************/
438 
439 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
440 
441 /*MPI v2.0 SAS products */
442 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
443 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
444 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
445 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
446 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
447 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
448 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
449 
450 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
451 
452 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
453 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
454 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
455 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
456 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
457 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
458 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
459 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
460 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
461 
462 /*MPI v2.5 SAS products */
463 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
464 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
465 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
466 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
467 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
468 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
469 
470 /* MPI v2.6 SAS Products */
471 #define MPI26_MFGPAGE_DEVID_SAS3216                 (0x00C9)
472 #define MPI26_MFGPAGE_DEVID_SAS3224                 (0x00C4)
473 #define MPI26_MFGPAGE_DEVID_SAS3316_1               (0x00C5)
474 #define MPI26_MFGPAGE_DEVID_SAS3316_2               (0x00C6)
475 #define MPI26_MFGPAGE_DEVID_SAS3316_3               (0x00C7)
476 #define MPI26_MFGPAGE_DEVID_SAS3316_4               (0x00C8)
477 #define MPI26_MFGPAGE_DEVID_SAS3324_1               (0x00C0)
478 #define MPI26_MFGPAGE_DEVID_SAS3324_2               (0x00C1)
479 #define MPI26_MFGPAGE_DEVID_SAS3324_3               (0x00C2)
480 #define MPI26_MFGPAGE_DEVID_SAS3324_4               (0x00C3)
481 
482 #define MPI26_MFGPAGE_DEVID_SAS3516                 (0x00AA)
483 #define MPI26_MFGPAGE_DEVID_SAS3516_1               (0x00AB)
484 #define MPI26_MFGPAGE_DEVID_SAS3416                 (0x00AC)
485 #define MPI26_MFGPAGE_DEVID_SAS3508                 (0x00AD)
486 #define MPI26_MFGPAGE_DEVID_SAS3508_1               (0x00AE)
487 #define MPI26_MFGPAGE_DEVID_SAS3408                 (0x00AF)
488 
489 /*Manufacturing Page 0 */
490 
491 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
492 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
493 	U8                      ChipName[16];               /*0x04 */
494 	U8                      ChipRevision[8];            /*0x14 */
495 	U8                      BoardName[16];              /*0x1C */
496 	U8                      BoardAssembly[16];          /*0x2C */
497 	U8                      BoardTracerNumber[16];      /*0x3C */
498 } MPI2_CONFIG_PAGE_MAN_0,
499 	*PTR_MPI2_CONFIG_PAGE_MAN_0,
500 	Mpi2ManufacturingPage0_t,
501 	*pMpi2ManufacturingPage0_t;
502 
503 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
504 
505 
506 /*Manufacturing Page 1 */
507 
508 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
509 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
510 	U8                      VPD[256];                   /*0x04 */
511 } MPI2_CONFIG_PAGE_MAN_1,
512 	*PTR_MPI2_CONFIG_PAGE_MAN_1,
513 	Mpi2ManufacturingPage1_t,
514 	*pMpi2ManufacturingPage1_t;
515 
516 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
517 
518 
519 typedef struct _MPI2_CHIP_REVISION_ID {
520 	U16 DeviceID;                                       /*0x00 */
521 	U8  PCIRevisionID;                                  /*0x02 */
522 	U8  Reserved;                                       /*0x03 */
523 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
524 	Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
525 
526 
527 /*Manufacturing Page 2 */
528 
529 /*
530  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
531  *one and check Header.PageLength at runtime.
532  */
533 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
534 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
535 #endif
536 
537 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
538 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
539 	MPI2_CHIP_REVISION_ID   ChipId;                     /*0x04 */
540 	U32
541 		HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
542 } MPI2_CONFIG_PAGE_MAN_2,
543 	*PTR_MPI2_CONFIG_PAGE_MAN_2,
544 	Mpi2ManufacturingPage2_t,
545 	*pMpi2ManufacturingPage2_t;
546 
547 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
548 
549 
550 /*Manufacturing Page 3 */
551 
552 /*
553  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
554  *one and check Header.PageLength at runtime.
555  */
556 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
557 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
558 #endif
559 
560 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
561 	MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
562 	MPI2_CHIP_REVISION_ID               ChipId;         /*0x04 */
563 	U32
564 		Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
565 } MPI2_CONFIG_PAGE_MAN_3,
566 	*PTR_MPI2_CONFIG_PAGE_MAN_3,
567 	Mpi2ManufacturingPage3_t,
568 	*pMpi2ManufacturingPage3_t;
569 
570 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
571 
572 
573 /*Manufacturing Page 4 */
574 
575 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
576 	U8                          PowerSaveFlags;                 /*0x00 */
577 	U8                          InternalOperationsSleepTime;    /*0x01 */
578 	U8                          InternalOperationsRunTime;      /*0x02 */
579 	U8                          HostIdleTime;                   /*0x03 */
580 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
581 	*PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
582 	Mpi2ManPage4PwrSaveSettings_t,
583 	*pMpi2ManPage4PwrSaveSettings_t;
584 
585 /*defines for the PowerSaveFlags field */
586 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
587 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
588 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
589 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
590 
591 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
592 	MPI2_CONFIG_PAGE_HEADER             Header;                 /*0x00 */
593 	U32                                 Reserved1;              /*0x04 */
594 	U32                                 Flags;                  /*0x08 */
595 	U8                                  InquirySize;            /*0x0C */
596 	U8                                  Reserved2;              /*0x0D */
597 	U16                                 Reserved3;              /*0x0E */
598 	U8                                  InquiryData[56];        /*0x10 */
599 	U32                                 RAID0VolumeSettings;    /*0x48 */
600 	U32                                 RAID1EVolumeSettings;   /*0x4C */
601 	U32                                 RAID1VolumeSettings;    /*0x50 */
602 	U32                                 RAID10VolumeSettings;   /*0x54 */
603 	U32                                 Reserved4;              /*0x58 */
604 	U32                                 Reserved5;              /*0x5C */
605 	MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /*0x60 */
606 	U8                                  MaxOCEDisks;            /*0x64 */
607 	U8                                  ResyncRate;             /*0x65 */
608 	U16                                 DataScrubDuration;      /*0x66 */
609 	U8                                  MaxHotSpares;           /*0x68 */
610 	U8                                  MaxPhysDisksPerVol;     /*0x69 */
611 	U8                                  MaxPhysDisks;           /*0x6A */
612 	U8                                  MaxVolumes;             /*0x6B */
613 } MPI2_CONFIG_PAGE_MAN_4,
614 	*PTR_MPI2_CONFIG_PAGE_MAN_4,
615 	Mpi2ManufacturingPage4_t,
616 	*pMpi2ManufacturingPage4_t;
617 
618 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
619 
620 /*Manufacturing Page 4 Flags field */
621 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
622 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
623 
624 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
625 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
626 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
627 
628 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
629 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
630 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
631 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
632 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
633 
634 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
635 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
636 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
637 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
638 
639 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
640 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
641 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
642 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
643 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
644 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
645 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
646 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
647 
648 
649 /*Manufacturing Page 5 */
650 
651 /*
652  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
653  *one and check the value returned for NumPhys at runtime.
654  */
655 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
656 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
657 #endif
658 
659 typedef struct _MPI2_MANUFACTURING5_ENTRY {
660 	U64                                 WWID;           /*0x00 */
661 	U64                                 DeviceName;     /*0x08 */
662 } MPI2_MANUFACTURING5_ENTRY,
663 	*PTR_MPI2_MANUFACTURING5_ENTRY,
664 	Mpi2Manufacturing5Entry_t,
665 	*pMpi2Manufacturing5Entry_t;
666 
667 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
668 	MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
669 	U8                                  NumPhys;        /*0x04 */
670 	U8                                  Reserved1;      /*0x05 */
671 	U16                                 Reserved2;      /*0x06 */
672 	U32                                 Reserved3;      /*0x08 */
673 	U32                                 Reserved4;      /*0x0C */
674 	MPI2_MANUFACTURING5_ENTRY
675 		Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
676 } MPI2_CONFIG_PAGE_MAN_5,
677 	*PTR_MPI2_CONFIG_PAGE_MAN_5,
678 	Mpi2ManufacturingPage5_t,
679 	*pMpi2ManufacturingPage5_t;
680 
681 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
682 
683 
684 /*Manufacturing Page 6 */
685 
686 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
687 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
688 	U32                             ProductSpecificInfo;/*0x04 */
689 } MPI2_CONFIG_PAGE_MAN_6,
690 	*PTR_MPI2_CONFIG_PAGE_MAN_6,
691 	Mpi2ManufacturingPage6_t,
692 	*pMpi2ManufacturingPage6_t;
693 
694 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
695 
696 
697 /*Manufacturing Page 7 */
698 
699 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
700 	U32                         Pinout;                 /*0x00 */
701 	U8                          Connector[16];          /*0x04 */
702 	U8                          Location;               /*0x14 */
703 	U8                          ReceptacleID;           /*0x15 */
704 	U16                         Slot;                   /*0x16 */
705 	U32                         Reserved2;              /*0x18 */
706 } MPI2_MANPAGE7_CONNECTOR_INFO,
707 	*PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
708 	Mpi2ManPage7ConnectorInfo_t,
709 	*pMpi2ManPage7ConnectorInfo_t;
710 
711 /*defines for the Pinout field */
712 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
713 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
714 
715 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
716 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
717 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
718 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
719 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
720 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
721 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
722 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
723 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
724 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
725 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
726 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
727 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
728 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
729 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
730 
731 /*defines for the Location field */
732 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
733 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
734 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
735 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
736 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
737 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
738 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
739 
740 /*
741  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
742  *one and check the value returned for NumPhys at runtime.
743  */
744 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
745 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
746 #endif
747 
748 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
749 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
750 	U32                             Reserved1;          /*0x04 */
751 	U32                             Reserved2;          /*0x08 */
752 	U32                             Flags;              /*0x0C */
753 	U8                              EnclosureName[16];  /*0x10 */
754 	U8                              NumPhys;            /*0x20 */
755 	U8                              Reserved3;          /*0x21 */
756 	U16                             Reserved4;          /*0x22 */
757 	MPI2_MANPAGE7_CONNECTOR_INFO
758 	ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
759 } MPI2_CONFIG_PAGE_MAN_7,
760 	*PTR_MPI2_CONFIG_PAGE_MAN_7,
761 	Mpi2ManufacturingPage7_t,
762 	*pMpi2ManufacturingPage7_t;
763 
764 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
765 
766 /*defines for the Flags field */
767 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
768 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
769 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
770 
771 
772 /*
773  *Generic structure to use for product-specific manufacturing pages
774  *(currently Manufacturing Page 8 through Manufacturing Page 31).
775  */
776 
777 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
778 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
779 	U32                             ProductSpecificInfo;/*0x04 */
780 } MPI2_CONFIG_PAGE_MAN_PS,
781 	*PTR_MPI2_CONFIG_PAGE_MAN_PS,
782 	Mpi2ManufacturingPagePS_t,
783 	*pMpi2ManufacturingPagePS_t;
784 
785 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
786 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
787 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
788 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
789 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
790 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
791 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
792 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
793 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
794 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
795 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
796 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
797 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
798 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
799 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
800 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
801 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
802 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
803 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
804 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
805 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
806 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
807 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
808 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
809 
810 
811 /****************************************************************************
812 *  IO Unit Config Pages
813 ****************************************************************************/
814 
815 /*IO Unit Page 0 */
816 
817 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
818 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
819 	U64                     UniqueValue;                /*0x04 */
820 	MPI2_VERSION_UNION      NvdataVersionDefault;       /*0x08 */
821 	MPI2_VERSION_UNION      NvdataVersionPersistent;    /*0x0A */
822 } MPI2_CONFIG_PAGE_IO_UNIT_0,
823 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
824 	Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
825 
826 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
827 
828 
829 /*IO Unit Page 1 */
830 
831 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
832 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
833 	U32                     Flags;                      /*0x04 */
834 } MPI2_CONFIG_PAGE_IO_UNIT_1,
835 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
836 	Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
837 
838 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
839 
840 /*IO Unit Page 1 Flags defines */
841 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
842 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
843 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
844 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
845 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
846 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
847 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
848 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
849 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
850 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
851 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
852 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
853 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
854 
855 
856 /*IO Unit Page 3 */
857 
858 /*
859  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
860  *one and check the value returned for GPIOCount at runtime.
861  */
862 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
863 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
864 #endif
865 
866 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
867 	MPI2_CONFIG_PAGE_HEADER Header;			 /*0x00 */
868 	U8                      GPIOCount;		 /*0x04 */
869 	U8                      Reserved1;		 /*0x05 */
870 	U16                     Reserved2;		 /*0x06 */
871 	U16
872 		GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
873 } MPI2_CONFIG_PAGE_IO_UNIT_3,
874 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
875 	Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
876 
877 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
878 
879 /*defines for IO Unit Page 3 GPIOVal field */
880 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
881 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
882 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
883 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
884 
885 
886 /*IO Unit Page 5 */
887 
888 /*
889  *Upper layer code (drivers, utilities, etc.) should leave this define set to
890  *one and check the value returned for NumDmaEngines at runtime.
891  */
892 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
893 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
894 #endif
895 
896 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
897 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
898 	U64
899 		RaidAcceleratorBufferBaseAddress;           /*0x04 */
900 	U64
901 		RaidAcceleratorBufferSize;                  /*0x0C */
902 	U64
903 		RaidAcceleratorControlBaseAddress;          /*0x14 */
904 	U8                      RAControlSize;              /*0x1C */
905 	U8                      NumDmaEngines;              /*0x1D */
906 	U8                      RAMinControlSize;           /*0x1E */
907 	U8                      RAMaxControlSize;           /*0x1F */
908 	U32                     Reserved1;                  /*0x20 */
909 	U32                     Reserved2;                  /*0x24 */
910 	U32                     Reserved3;                  /*0x28 */
911 	U32
912 	DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
913 } MPI2_CONFIG_PAGE_IO_UNIT_5,
914 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
915 	Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
916 
917 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
918 
919 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
920 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
921 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
922 
923 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
924 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
925 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
926 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
927 
928 
929 /*IO Unit Page 6 */
930 
931 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
932 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
933 	U16                     Flags;                  /*0x04 */
934 	U8                      RAHostControlSize;      /*0x06 */
935 	U8                      Reserved0;              /*0x07 */
936 	U64
937 		RaidAcceleratorHostControlBaseAddress;  /*0x08 */
938 	U32                     Reserved1;              /*0x10 */
939 	U32                     Reserved2;              /*0x14 */
940 	U32                     Reserved3;              /*0x18 */
941 } MPI2_CONFIG_PAGE_IO_UNIT_6,
942 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
943 	Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
944 
945 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
946 
947 /*defines for IO Unit Page 6 Flags field */
948 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
949 
950 
951 /*IO Unit Page 7 */
952 
953 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
954 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
955 	U8                      CurrentPowerMode;       /*0x04 */
956 	U8                      PreviousPowerMode;      /*0x05 */
957 	U8                      PCIeWidth;              /*0x06 */
958 	U8                      PCIeSpeed;              /*0x07 */
959 	U32                     ProcessorState;         /*0x08 */
960 	U32
961 		PowerManagementCapabilities;            /*0x0C */
962 	U16                     IOCTemperature;         /*0x10 */
963 	U8
964 		IOCTemperatureUnits;                    /*0x12 */
965 	U8                      IOCSpeed;               /*0x13 */
966 	U16                     BoardTemperature;       /*0x14 */
967 	U8
968 		BoardTemperatureUnits;                  /*0x16 */
969 	U8                      Reserved3;              /*0x17 */
970 	U32			BoardPowerRequirement;	/*0x18 */
971 	U32			PCISlotPowerAllocation;	/*0x1C */
972 /* reserved prior to MPI v2.6 */
973 	U8		Flags;			/* 0x20 */
974 	U8		Reserved6;			/* 0x21 */
975 	U16		Reserved7;			/* 0x22 */
976 	U32		Reserved8;			/* 0x24 */
977 } MPI2_CONFIG_PAGE_IO_UNIT_7,
978 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
979 	Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
980 
981 #define MPI2_IOUNITPAGE7_PAGEVERSION			(0x05)
982 
983 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
984 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
985 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
986 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
987 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
988 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
989 
990 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
991 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
992 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
993 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
994 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
995 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
996 
997 
998 /*defines for IO Unit Page 7 PCIeWidth field */
999 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
1000 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
1001 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
1002 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
1003 
1004 /*defines for IO Unit Page 7 PCIeSpeed field */
1005 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
1006 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
1007 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
1008 
1009 /*defines for IO Unit Page 7 ProcessorState field */
1010 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
1011 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
1012 
1013 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
1014 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1015 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1016 
1017 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
1018 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1019 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1020 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1021 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1022 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1023 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1024 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1025 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1026 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1027 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1028 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1029 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1030 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1031 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1032 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1033 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008)
1034 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004)
1035 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002)
1036 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001)
1037 
1038 /*obsolete names for the PowerManagementCapabilities bits (above) */
1039 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1040 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1041 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1042 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /*obsolete */
1043 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /*obsolete */
1044 
1045 
1046 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
1047 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1048 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1049 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1050 
1051 /*defines for IO Unit Page 7 IOCSpeed field */
1052 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1053 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1054 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1055 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1056 
1057 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1058 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1059 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1060 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1061 
1062 /* defines for IO Unit Page 7 Flags field */
1063 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC       (0x01)
1064 
1065 /*IO Unit Page 8 */
1066 
1067 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1068 
1069 typedef struct _MPI2_IOUNIT8_SENSOR {
1070 	U16                     Flags;                  /*0x00 */
1071 	U16                     Reserved1;              /*0x02 */
1072 	U16
1073 		Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1074 	U32                     Reserved2;              /*0x0C */
1075 	U32                     Reserved3;              /*0x10 */
1076 	U32                     Reserved4;              /*0x14 */
1077 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1078 	Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1079 
1080 /*defines for IO Unit Page 8 Sensor Flags field */
1081 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1082 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1083 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1084 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1085 
1086 /*
1087  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1088  *one and check the value returned for NumSensors at runtime.
1089  */
1090 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1091 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1092 #endif
1093 
1094 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1095 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1096 	U32                     Reserved1;              /*0x04 */
1097 	U32                     Reserved2;              /*0x08 */
1098 	U8                      NumSensors;             /*0x0C */
1099 	U8                      PollingInterval;        /*0x0D */
1100 	U16                     Reserved3;              /*0x0E */
1101 	MPI2_IOUNIT8_SENSOR
1102 		Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1103 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1104 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1105 	Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1106 
1107 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1108 
1109 
1110 /*IO Unit Page 9 */
1111 
1112 typedef struct _MPI2_IOUNIT9_SENSOR {
1113 	U16                     CurrentTemperature;     /*0x00 */
1114 	U16                     Reserved1;              /*0x02 */
1115 	U8                      Flags;                  /*0x04 */
1116 	U8                      Reserved2;              /*0x05 */
1117 	U16                     Reserved3;              /*0x06 */
1118 	U32                     Reserved4;              /*0x08 */
1119 	U32                     Reserved5;              /*0x0C */
1120 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1121 	Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1122 
1123 /*defines for IO Unit Page 9 Sensor Flags field */
1124 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1125 
1126 /*
1127  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1128  *one and check the value returned for NumSensors at runtime.
1129  */
1130 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1131 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1132 #endif
1133 
1134 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1135 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1136 	U32                     Reserved1;              /*0x04 */
1137 	U32                     Reserved2;              /*0x08 */
1138 	U8                      NumSensors;             /*0x0C */
1139 	U8                      Reserved4;              /*0x0D */
1140 	U16                     Reserved3;              /*0x0E */
1141 	MPI2_IOUNIT9_SENSOR
1142 		Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1143 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1144 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1145 	Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1146 
1147 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1148 
1149 
1150 /*IO Unit Page 10 */
1151 
1152 typedef struct _MPI2_IOUNIT10_FUNCTION {
1153 	U8                      CreditPercent;      /*0x00 */
1154 	U8                      Reserved1;          /*0x01 */
1155 	U16                     Reserved2;          /*0x02 */
1156 } MPI2_IOUNIT10_FUNCTION,
1157 	*PTR_MPI2_IOUNIT10_FUNCTION,
1158 	Mpi2IOUnit10Function_t,
1159 	*pMpi2IOUnit10Function_t;
1160 
1161 /*
1162  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1163  *one and check the value returned for NumFunctions at runtime.
1164  */
1165 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1166 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1167 #endif
1168 
1169 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1170 	MPI2_CONFIG_PAGE_HEADER Header;                      /*0x00 */
1171 	U8                      NumFunctions;                /*0x04 */
1172 	U8                      Reserved1;                   /*0x05 */
1173 	U16                     Reserved2;                   /*0x06 */
1174 	U32                     Reserved3;                   /*0x08 */
1175 	U32                     Reserved4;                   /*0x0C */
1176 	MPI2_IOUNIT10_FUNCTION
1177 		Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1178 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1179 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1180 	Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1181 
1182 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1183 
1184 
1185 /* IO Unit Page 11 (for MPI v2.6 and later) */
1186 
1187 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1188 	U8          MaxTargetSpinup;            /* 0x00 */
1189 	U8          SpinupDelay;                /* 0x01 */
1190 	U8          SpinupFlags;                /* 0x02 */
1191 	U8          Reserved1;                  /* 0x03 */
1192 } MPI26_IOUNIT11_SPINUP_GROUP,
1193 	*PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1194 	Mpi26IOUnit11SpinupGroup_t,
1195 	*pMpi26IOUnit11SpinupGroup_t;
1196 
1197 /* defines for IO Unit Page 11 SpinupFlags */
1198 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG          (0x01)
1199 
1200 
1201 /*
1202  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1203  * four and check the value returned for NumPhys at runtime.
1204  */
1205 #ifndef MPI26_IOUNITPAGE11_PHY_MAX
1206 #define MPI26_IOUNITPAGE11_PHY_MAX        (4)
1207 #endif
1208 
1209 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1210 	MPI2_CONFIG_PAGE_HEADER       Header;			       /*0x00 */
1211 	U32                           Reserved1;                      /*0x04 */
1212 	MPI26_IOUNIT11_SPINUP_GROUP   SpinupGroupParameters[4];       /*0x08 */
1213 	U32                           Reserved2;                      /*0x18 */
1214 	U32                           Reserved3;                      /*0x1C */
1215 	U32                           Reserved4;                      /*0x20 */
1216 	U8                            BootDeviceWaitTime;             /*0x24 */
1217 	U8                            Reserved5;                      /*0x25 */
1218 	U16                           Reserved6;                      /*0x26 */
1219 	U8                            NumPhys;                        /*0x28 */
1220 	U8                            PEInitialSpinupDelay;           /*0x29 */
1221 	U8                            PEReplyDelay;                   /*0x2A */
1222 	U8                            Flags;                          /*0x2B */
1223 	U8			      PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1224 } MPI26_CONFIG_PAGE_IO_UNIT_11,
1225 	*PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1226 	Mpi26IOUnitPage11_t,
1227 	*pMpi26IOUnitPage11_t;
1228 
1229 #define MPI26_IOUNITPAGE11_PAGEVERSION                  (0x00)
1230 
1231 /* defines for Flags field */
1232 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE        (0x01)
1233 
1234 /* defines for PHY field */
1235 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK        (0x03)
1236 
1237 
1238 
1239 
1240 
1241 
1242 /****************************************************************************
1243 *  IOC Config Pages
1244 ****************************************************************************/
1245 
1246 /*IOC Page 0 */
1247 
1248 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1249 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1250 	U32                     Reserved1;                  /*0x04 */
1251 	U32                     Reserved2;                  /*0x08 */
1252 	U16                     VendorID;                   /*0x0C */
1253 	U16                     DeviceID;                   /*0x0E */
1254 	U8                      RevisionID;                 /*0x10 */
1255 	U8                      Reserved3;                  /*0x11 */
1256 	U16                     Reserved4;                  /*0x12 */
1257 	U32                     ClassCode;                  /*0x14 */
1258 	U16                     SubsystemVendorID;          /*0x18 */
1259 	U16                     SubsystemID;                /*0x1A */
1260 } MPI2_CONFIG_PAGE_IOC_0,
1261 	*PTR_MPI2_CONFIG_PAGE_IOC_0,
1262 	Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1263 
1264 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1265 
1266 
1267 /*IOC Page 1 */
1268 
1269 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1270 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1271 	U32                     Flags;                      /*0x04 */
1272 	U32                     CoalescingTimeout;          /*0x08 */
1273 	U8                      CoalescingDepth;            /*0x0C */
1274 	U8                      PCISlotNum;                 /*0x0D */
1275 	U8                      PCIBusNum;                  /*0x0E */
1276 	U8                      PCIDomainSegment;           /*0x0F */
1277 	U32                     Reserved1;                  /*0x10 */
1278 	U32                     Reserved2;                  /*0x14 */
1279 } MPI2_CONFIG_PAGE_IOC_1,
1280 	*PTR_MPI2_CONFIG_PAGE_IOC_1,
1281 	Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1282 
1283 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1284 
1285 /*defines for IOC Page 1 Flags field */
1286 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1287 
1288 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1289 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1290 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1291 
1292 /*IOC Page 6 */
1293 
1294 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1295 	MPI2_CONFIG_PAGE_HEADER Header;         /*0x00 */
1296 	U32
1297 		CapabilitiesFlags;              /*0x04 */
1298 	U8                      MaxDrivesRAID0; /*0x08 */
1299 	U8                      MaxDrivesRAID1; /*0x09 */
1300 	U8
1301 		 MaxDrivesRAID1E;                /*0x0A */
1302 	U8
1303 		 MaxDrivesRAID10;		/*0x0B */
1304 	U8                      MinDrivesRAID0; /*0x0C */
1305 	U8                      MinDrivesRAID1; /*0x0D */
1306 	U8
1307 		 MinDrivesRAID1E;                /*0x0E */
1308 	U8
1309 		 MinDrivesRAID10;                /*0x0F */
1310 	U32                     Reserved1;      /*0x10 */
1311 	U8
1312 		 MaxGlobalHotSpares;             /*0x14 */
1313 	U8                      MaxPhysDisks;   /*0x15 */
1314 	U8                      MaxVolumes;     /*0x16 */
1315 	U8                      MaxConfigs;     /*0x17 */
1316 	U8                      MaxOCEDisks;    /*0x18 */
1317 	U8                      Reserved2;      /*0x19 */
1318 	U16                     Reserved3;      /*0x1A */
1319 	U32
1320 		SupportedStripeSizeMapRAID0;    /*0x1C */
1321 	U32
1322 		SupportedStripeSizeMapRAID1E;   /*0x20 */
1323 	U32
1324 		SupportedStripeSizeMapRAID10;   /*0x24 */
1325 	U32                     Reserved4;      /*0x28 */
1326 	U32                     Reserved5;      /*0x2C */
1327 	U16
1328 		DefaultMetadataSize;            /*0x30 */
1329 	U16                     Reserved6;      /*0x32 */
1330 	U16
1331 		MaxBadBlockTableEntries;        /*0x34 */
1332 	U16                     Reserved7;      /*0x36 */
1333 	U32
1334 		IRNvsramVersion;                /*0x38 */
1335 } MPI2_CONFIG_PAGE_IOC_6,
1336 	*PTR_MPI2_CONFIG_PAGE_IOC_6,
1337 	Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1338 
1339 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1340 
1341 /*defines for IOC Page 6 CapabilitiesFlags */
1342 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1343 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1344 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1345 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1346 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1347 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1348 
1349 
1350 /*IOC Page 7 */
1351 
1352 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1353 
1354 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1355 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1356 	U32                     Reserved1;                  /*0x04 */
1357 	U32
1358 		EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1359 	U16                     SASBroadcastPrimitiveMasks; /*0x18 */
1360 	U16                     SASNotifyPrimitiveMasks;    /*0x1A */
1361 	U32                     Reserved3;                  /*0x1C */
1362 } MPI2_CONFIG_PAGE_IOC_7,
1363 	*PTR_MPI2_CONFIG_PAGE_IOC_7,
1364 	Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1365 
1366 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1367 
1368 
1369 /*IOC Page 8 */
1370 
1371 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1372 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1373 	U8                      NumDevsPerEnclosure;        /*0x04 */
1374 	U8                      Reserved1;                  /*0x05 */
1375 	U16                     Reserved2;                  /*0x06 */
1376 	U16                     MaxPersistentEntries;       /*0x08 */
1377 	U16                     MaxNumPhysicalMappedIDs;    /*0x0A */
1378 	U16                     Flags;                      /*0x0C */
1379 	U16                     Reserved3;                  /*0x0E */
1380 	U16                     IRVolumeMappingFlags;       /*0x10 */
1381 	U16                     Reserved4;                  /*0x12 */
1382 	U32                     Reserved5;                  /*0x14 */
1383 } MPI2_CONFIG_PAGE_IOC_8,
1384 	*PTR_MPI2_CONFIG_PAGE_IOC_8,
1385 	Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1386 
1387 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1388 
1389 /*defines for IOC Page 8 Flags field */
1390 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1391 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1392 
1393 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1394 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1395 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1396 
1397 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1398 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1399 
1400 /*defines for IOC Page 8 IRVolumeMappingFlags */
1401 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1402 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1403 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1404 
1405 
1406 /****************************************************************************
1407 *  BIOS Config Pages
1408 ****************************************************************************/
1409 
1410 /*BIOS Page 1 */
1411 
1412 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1413 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1414 	U32                     BiosOptions;                /*0x04 */
1415 	U32                     IOCSettings;                /*0x08 */
1416 	U8                      SSUTimeout;                 /*0x0C */
1417 	U8                      Reserved1;                  /*0x0D */
1418 	U16                     Reserved2;                  /*0x0E */
1419 	U32                     DeviceSettings;             /*0x10 */
1420 	U16                     NumberOfDevices;            /*0x14 */
1421 	U16                     UEFIVersion;                /*0x16 */
1422 	U16                     IOTimeoutBlockDevicesNonRM; /*0x18 */
1423 	U16                     IOTimeoutSequential;        /*0x1A */
1424 	U16                     IOTimeoutOther;             /*0x1C */
1425 	U16                     IOTimeoutBlockDevicesRM;    /*0x1E */
1426 } MPI2_CONFIG_PAGE_BIOS_1,
1427 	*PTR_MPI2_CONFIG_PAGE_BIOS_1,
1428 	Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1429 
1430 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x07)
1431 
1432 /*values for BIOS Page 1 BiosOptions field */
1433 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
1434 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
1435 
1436 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1437 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1438 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
1439 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
1440 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID                        (0x00001000)
1441 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS                        (0x00001800)
1442 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY                        (0x00002000)
1443 
1444 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS		(0x00000400)
1445 
1446 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD	(0x00000300)
1447 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD	(0x00000000)
1448 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD	(0x00000100)
1449 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD	(0x00000200)
1450 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD	(0x00000300)
1451 
1452 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1453 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1454 
1455 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1456 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1457 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1458 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1459 
1460 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1461 
1462 /*values for BIOS Page 1 IOCSettings field */
1463 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1464 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1465 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1466 
1467 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1468 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1469 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1470 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1471 
1472 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1473 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1474 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1475 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1476 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1477 
1478 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1479 
1480 /*values for BIOS Page 1 DeviceSettings field */
1481 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1482 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1483 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1484 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1485 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1486 
1487 /*defines for BIOS Page 1 UEFIVersion field */
1488 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1489 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1490 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1491 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1492 
1493 
1494 
1495 /*BIOS Page 2 */
1496 
1497 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1498 	U32         Reserved1;                              /*0x00 */
1499 	U32         Reserved2;                              /*0x04 */
1500 	U32         Reserved3;                              /*0x08 */
1501 	U32         Reserved4;                              /*0x0C */
1502 	U32         Reserved5;                              /*0x10 */
1503 	U32         Reserved6;                              /*0x14 */
1504 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1505 	*PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1506 	Mpi2BootDeviceAdapterOrder_t,
1507 	*pMpi2BootDeviceAdapterOrder_t;
1508 
1509 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1510 	U64         SASAddress;                             /*0x00 */
1511 	U8          LUN[8];                                 /*0x08 */
1512 	U32         Reserved1;                              /*0x10 */
1513 	U32         Reserved2;                              /*0x14 */
1514 } MPI2_BOOT_DEVICE_SAS_WWID,
1515 	*PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1516 	Mpi2BootDeviceSasWwid_t,
1517 	*pMpi2BootDeviceSasWwid_t;
1518 
1519 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1520 	U64         EnclosureLogicalID;                     /*0x00 */
1521 	U32         Reserved1;                              /*0x08 */
1522 	U32         Reserved2;                              /*0x0C */
1523 	U16         SlotNumber;                             /*0x10 */
1524 	U16         Reserved3;                              /*0x12 */
1525 	U32         Reserved4;                              /*0x14 */
1526 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1527 	*PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1528 	Mpi2BootDeviceEnclosureSlot_t,
1529 	*pMpi2BootDeviceEnclosureSlot_t;
1530 
1531 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1532 	U64         DeviceName;                             /*0x00 */
1533 	U8          LUN[8];                                 /*0x08 */
1534 	U32         Reserved1;                              /*0x10 */
1535 	U32         Reserved2;                              /*0x14 */
1536 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1537 	*PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1538 	Mpi2BootDeviceDeviceName_t,
1539 	*pMpi2BootDeviceDeviceName_t;
1540 
1541 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1542 	MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1543 	MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1544 	MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1545 	MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1546 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1547 	*PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1548 	Mpi2BiosPage2BootDevice_t,
1549 	*pMpi2BiosPage2BootDevice_t;
1550 
1551 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1552 	MPI2_CONFIG_PAGE_HEADER     Header;                 /*0x00 */
1553 	U32                         Reserved1;              /*0x04 */
1554 	U32                         Reserved2;              /*0x08 */
1555 	U32                         Reserved3;              /*0x0C */
1556 	U32                         Reserved4;              /*0x10 */
1557 	U32                         Reserved5;              /*0x14 */
1558 	U32                         Reserved6;              /*0x18 */
1559 	U8                          ReqBootDeviceForm;      /*0x1C */
1560 	U8                          Reserved7;              /*0x1D */
1561 	U16                         Reserved8;              /*0x1E */
1562 	MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /*0x20 */
1563 	U8                          ReqAltBootDeviceForm;   /*0x38 */
1564 	U8                          Reserved9;              /*0x39 */
1565 	U16                         Reserved10;             /*0x3A */
1566 	MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /*0x3C */
1567 	U8                          CurrentBootDeviceForm;  /*0x58 */
1568 	U8                          Reserved11;             /*0x59 */
1569 	U16                         Reserved12;             /*0x5A */
1570 	MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /*0x58 */
1571 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1572 	Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1573 
1574 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1575 
1576 /*values for BIOS Page 2 BootDeviceForm fields */
1577 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1578 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1579 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1580 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1581 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1582 
1583 
1584 /*BIOS Page 3 */
1585 
1586 #define MPI2_BIOSPAGE3_NUM_ADAPTER      (4)
1587 
1588 typedef struct _MPI2_ADAPTER_INFO {
1589 	U8      PciBusNumber;                        /*0x00 */
1590 	U8      PciDeviceAndFunctionNumber;          /*0x01 */
1591 	U16     AdapterFlags;                        /*0x02 */
1592 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1593 	Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1594 
1595 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1596 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1597 
1598 typedef struct _MPI2_ADAPTER_ORDER_AUX {
1599 	U64     WWID;					/* 0x00 */
1600 	U32     Reserved1;				/* 0x08 */
1601 	U32     Reserved2;				/* 0x0C */
1602 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1603 	Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1604 
1605 
1606 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1607 	MPI2_CONFIG_PAGE_HEADER Header;              /*0x00 */
1608 	U32                     GlobalFlags;         /*0x04 */
1609 	U32                     BiosVersion;         /*0x08 */
1610 	MPI2_ADAPTER_INFO       AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1611 	U32                     Reserved1;           /*0x1C */
1612 	MPI2_ADAPTER_ORDER_AUX  AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1613 } MPI2_CONFIG_PAGE_BIOS_3,
1614 	*PTR_MPI2_CONFIG_PAGE_BIOS_3,
1615 	Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1616 
1617 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x01)
1618 
1619 /*values for BIOS Page 3 GlobalFlags */
1620 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1621 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1622 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1623 
1624 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1625 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1626 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1627 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1628 
1629 
1630 /*BIOS Page 4 */
1631 
1632 /*
1633  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1634  *one and check the value returned for NumPhys at runtime.
1635  */
1636 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1637 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1638 #endif
1639 
1640 typedef struct _MPI2_BIOS4_ENTRY {
1641 	U64                     ReassignmentWWID;       /*0x00 */
1642 	U64                     ReassignmentDeviceName; /*0x08 */
1643 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1644 	Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1645 
1646 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1647 	MPI2_CONFIG_PAGE_HEADER Header;             /*0x00 */
1648 	U8                      NumPhys;            /*0x04 */
1649 	U8                      Reserved1;          /*0x05 */
1650 	U16                     Reserved2;          /*0x06 */
1651 	MPI2_BIOS4_ENTRY
1652 		Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /*0x08 */
1653 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1654 	Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1655 
1656 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1657 
1658 
1659 /****************************************************************************
1660 *  RAID Volume Config Pages
1661 ****************************************************************************/
1662 
1663 /*RAID Volume Page 0 */
1664 
1665 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1666 	U8                      RAIDSetNum;        /*0x00 */
1667 	U8                      PhysDiskMap;       /*0x01 */
1668 	U8                      PhysDiskNum;       /*0x02 */
1669 	U8                      Reserved;          /*0x03 */
1670 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1671 	Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1672 
1673 /*defines for the PhysDiskMap field */
1674 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1675 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1676 
1677 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1678 	U16                     Settings;          /*0x00 */
1679 	U8                      HotSparePool;      /*0x01 */
1680 	U8                      Reserved;          /*0x02 */
1681 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1682 	Mpi2RaidVol0Settings_t,
1683 	*pMpi2RaidVol0Settings_t;
1684 
1685 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1686 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1687 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1688 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1689 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1690 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1691 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1692 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1693 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1694 
1695 /*RAID Volume Page 0 VolumeSettings defines */
1696 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1697 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1698 
1699 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1700 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1701 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1702 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1703 
1704 /*
1705  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1706  *one and check the value returned for NumPhysDisks at runtime.
1707  */
1708 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1709 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1710 #endif
1711 
1712 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1713 	MPI2_CONFIG_PAGE_HEADER Header;            /*0x00 */
1714 	U16                     DevHandle;         /*0x04 */
1715 	U8                      VolumeState;       /*0x06 */
1716 	U8                      VolumeType;        /*0x07 */
1717 	U32                     VolumeStatusFlags; /*0x08 */
1718 	MPI2_RAIDVOL0_SETTINGS  VolumeSettings;    /*0x0C */
1719 	U64                     MaxLBA;            /*0x10 */
1720 	U32                     StripeSize;        /*0x18 */
1721 	U16                     BlockSize;         /*0x1C */
1722 	U16                     Reserved1;         /*0x1E */
1723 	U8                      SupportedPhysDisks;/*0x20 */
1724 	U8                      ResyncRate;        /*0x21 */
1725 	U16                     DataScrubDuration; /*0x22 */
1726 	U8                      NumPhysDisks;      /*0x24 */
1727 	U8                      Reserved2;         /*0x25 */
1728 	U8                      Reserved3;         /*0x26 */
1729 	U8                      InactiveStatus;    /*0x27 */
1730 	MPI2_RAIDVOL0_PHYS_DISK
1731 	PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1732 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1733 	*PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1734 	Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1735 
1736 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1737 
1738 /*values for RAID VolumeState */
1739 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1740 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1741 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1742 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1743 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1744 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1745 
1746 /*values for RAID VolumeType */
1747 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1748 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1749 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1750 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1751 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1752 
1753 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1754 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1755 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1756 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1757 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1758 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1759 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1760 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1761 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1762 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1763 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1764 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1765 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1766 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1767 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1768 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1769 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1770 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1771 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1772 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1773 
1774 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1775 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1776 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1777 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1778 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1779 
1780 /*values for RAID Volume Page 0 InactiveStatus field */
1781 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1782 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1783 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1784 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1785 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1786 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1787 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1788 
1789 
1790 /*RAID Volume Page 1 */
1791 
1792 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1793 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1794 	U16                     DevHandle;                  /*0x04 */
1795 	U16                     Reserved0;                  /*0x06 */
1796 	U8                      GUID[24];                   /*0x08 */
1797 	U8                      Name[16];                   /*0x20 */
1798 	U64                     WWID;                       /*0x30 */
1799 	U32                     Reserved1;                  /*0x38 */
1800 	U32                     Reserved2;                  /*0x3C */
1801 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1802 	*PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1803 	Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1804 
1805 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1806 
1807 
1808 /****************************************************************************
1809 *  RAID Physical Disk Config Pages
1810 ****************************************************************************/
1811 
1812 /*RAID Physical Disk Page 0 */
1813 
1814 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1815 	U16                     Reserved1;                  /*0x00 */
1816 	U8                      HotSparePool;               /*0x02 */
1817 	U8                      Reserved2;                  /*0x03 */
1818 } MPI2_RAIDPHYSDISK0_SETTINGS,
1819 	*PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1820 	Mpi2RaidPhysDisk0Settings_t,
1821 	*pMpi2RaidPhysDisk0Settings_t;
1822 
1823 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1824 
1825 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1826 	U8                      VendorID[8];                /*0x00 */
1827 	U8                      ProductID[16];              /*0x08 */
1828 	U8                      ProductRevLevel[4];         /*0x18 */
1829 	U8                      SerialNum[32];              /*0x1C */
1830 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1831 	*PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1832 	Mpi2RaidPhysDisk0InquiryData_t,
1833 	*pMpi2RaidPhysDisk0InquiryData_t;
1834 
1835 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1836 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1837 	U16                             DevHandle;          /*0x04 */
1838 	U8                              Reserved1;          /*0x06 */
1839 	U8                              PhysDiskNum;        /*0x07 */
1840 	MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;   /*0x08 */
1841 	U32                             Reserved2;          /*0x0C */
1842 	MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;        /*0x10 */
1843 	U32                             Reserved3;          /*0x4C */
1844 	U8                              PhysDiskState;      /*0x50 */
1845 	U8                              OfflineReason;      /*0x51 */
1846 	U8                              IncompatibleReason; /*0x52 */
1847 	U8                              PhysDiskAttributes; /*0x53 */
1848 	U32                             PhysDiskStatusFlags;/*0x54 */
1849 	U64                             DeviceMaxLBA;       /*0x58 */
1850 	U64                             HostMaxLBA;         /*0x60 */
1851 	U64                             CoercedMaxLBA;      /*0x68 */
1852 	U16                             BlockSize;          /*0x70 */
1853 	U16                             Reserved5;          /*0x72 */
1854 	U32                             Reserved6;          /*0x74 */
1855 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1856 	*PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1857 	Mpi2RaidPhysDiskPage0_t,
1858 	*pMpi2RaidPhysDiskPage0_t;
1859 
1860 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1861 
1862 /*PhysDiskState defines */
1863 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1864 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1865 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1866 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1867 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1868 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1869 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1870 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1871 
1872 /*OfflineReason defines */
1873 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1874 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1875 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1876 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1877 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1878 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1879 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1880 
1881 /*IncompatibleReason defines */
1882 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1883 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1884 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1885 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1886 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1887 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1888 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1889 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1890 
1891 /*PhysDiskAttributes defines */
1892 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1893 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1894 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1895 
1896 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1897 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1898 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1899 
1900 /*PhysDiskStatusFlags defines */
1901 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1902 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1903 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1904 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1905 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1906 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1907 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1908 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1909 
1910 
1911 /*RAID Physical Disk Page 1 */
1912 
1913 /*
1914  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1915  *one and check the value returned for NumPhysDiskPaths at runtime.
1916  */
1917 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1918 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1919 #endif
1920 
1921 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
1922 	U16             DevHandle;          /*0x00 */
1923 	U16             Reserved1;          /*0x02 */
1924 	U64             WWID;               /*0x04 */
1925 	U64             OwnerWWID;          /*0x0C */
1926 	U8              OwnerIdentifier;    /*0x14 */
1927 	U8              Reserved2;          /*0x15 */
1928 	U16             Flags;              /*0x16 */
1929 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
1930 	Mpi2RaidPhysDisk1Path_t,
1931 	*pMpi2RaidPhysDisk1Path_t;
1932 
1933 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1934 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1935 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1936 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1937 
1938 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
1939 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1940 	U8                              NumPhysDiskPaths;   /*0x04 */
1941 	U8                              PhysDiskNum;        /*0x05 */
1942 	U16                             Reserved1;          /*0x06 */
1943 	U32                             Reserved2;          /*0x08 */
1944 	MPI2_RAIDPHYSDISK1_PATH
1945 		PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
1946 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1947 	*PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1948 	Mpi2RaidPhysDiskPage1_t,
1949 	*pMpi2RaidPhysDiskPage1_t;
1950 
1951 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1952 
1953 
1954 /****************************************************************************
1955 *  values for fields used by several types of SAS Config Pages
1956 ****************************************************************************/
1957 
1958 /*values for NegotiatedLinkRates fields */
1959 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1960 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1961 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1962 /*link rates used for Negotiated Physical and Logical Link Rate */
1963 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1964 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1965 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1966 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1967 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1968 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1969 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
1970 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1971 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1972 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1973 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
1974 
1975 
1976 /*values for AttachedPhyInfo fields */
1977 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1978 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1979 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1980 
1981 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1982 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1983 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1984 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1985 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1986 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1987 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1988 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1989 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1990 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1991 
1992 
1993 /*values for PhyInfo fields */
1994 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1995 
1996 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1997 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
1998 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1999 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
2000 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
2001 
2002 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
2003 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
2004 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
2005 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
2006 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
2007 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
2008 
2009 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
2010 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
2011 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
2012 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
2013 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
2014 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
2015 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
2016 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
2017 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
2018 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
2019 
2020 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
2021 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
2022 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
2023 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
2024 
2025 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
2026 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
2027 
2028 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
2029 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
2030 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
2031 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
2032 
2033 
2034 /*values for SAS ProgrammedLinkRate fields */
2035 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
2036 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
2037 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
2038 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
2039 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
2040 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
2041 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
2042 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
2043 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
2044 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
2045 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
2046 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
2047 
2048 
2049 /*values for SAS HwLinkRate fields */
2050 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
2051 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
2052 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
2053 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
2054 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
2055 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
2056 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
2057 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
2058 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
2059 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
2060 
2061 
2062 
2063 /****************************************************************************
2064 *  SAS IO Unit Config Pages
2065 ****************************************************************************/
2066 
2067 /*SAS IO Unit Page 0 */
2068 
2069 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2070 	U8          Port;                   /*0x00 */
2071 	U8          PortFlags;              /*0x01 */
2072 	U8          PhyFlags;               /*0x02 */
2073 	U8          NegotiatedLinkRate;     /*0x03 */
2074 	U32         ControllerPhyDeviceInfo;/*0x04 */
2075 	U16         AttachedDevHandle;      /*0x08 */
2076 	U16         ControllerDevHandle;    /*0x0A */
2077 	U32         DiscoveryStatus;        /*0x0C */
2078 	U32         Reserved;               /*0x10 */
2079 } MPI2_SAS_IO_UNIT0_PHY_DATA,
2080 	*PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2081 	Mpi2SasIOUnit0PhyData_t,
2082 	*pMpi2SasIOUnit0PhyData_t;
2083 
2084 /*
2085  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2086  *one and check the value returned for NumPhys at runtime.
2087  */
2088 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
2089 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
2090 #endif
2091 
2092 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2093 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2094 	U32                                 Reserved1;/*0x08 */
2095 	U8                                  NumPhys;  /*0x0C */
2096 	U8                                  Reserved2;/*0x0D */
2097 	U16                                 Reserved3;/*0x0E */
2098 	MPI2_SAS_IO_UNIT0_PHY_DATA
2099 		PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];    /*0x10 */
2100 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
2101 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2102 	Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2103 
2104 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
2105 
2106 /*values for SAS IO Unit Page 0 PortFlags */
2107 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
2108 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
2109 
2110 /*values for SAS IO Unit Page 0 PhyFlags */
2111 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
2112 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
2113 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
2114 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
2115 
2116 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2117 
2118 /*see mpi2_sas.h for values for
2119  *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2120 
2121 /*values for SAS IO Unit Page 0 DiscoveryStatus */
2122 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
2123 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
2124 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
2125 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
2126 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2127 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2128 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2129 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2130 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2131 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2132 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2133 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2134 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2135 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2136 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2137 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2138 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2139 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2140 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2141 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2142 
2143 
2144 /*SAS IO Unit Page 1 */
2145 
2146 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2147 	U8          Port;                       /*0x00 */
2148 	U8          PortFlags;                  /*0x01 */
2149 	U8          PhyFlags;                   /*0x02 */
2150 	U8          MaxMinLinkRate;             /*0x03 */
2151 	U32         ControllerPhyDeviceInfo;    /*0x04 */
2152 	U16         MaxTargetPortConnectTime;   /*0x08 */
2153 	U16         Reserved1;                  /*0x0A */
2154 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2155 	*PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2156 	Mpi2SasIOUnit1PhyData_t,
2157 	*pMpi2SasIOUnit1PhyData_t;
2158 
2159 /*
2160  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2161  *one and check the value returned for NumPhys at runtime.
2162  */
2163 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2164 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2165 #endif
2166 
2167 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2168 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
2169 	U16
2170 		ControlFlags;                       /*0x08 */
2171 	U16
2172 		SASNarrowMaxQueueDepth;             /*0x0A */
2173 	U16
2174 		AdditionalControlFlags;             /*0x0C */
2175 	U16
2176 		SASWideMaxQueueDepth;               /*0x0E */
2177 	U8
2178 		NumPhys;                            /*0x10 */
2179 	U8
2180 		SATAMaxQDepth;                      /*0x11 */
2181 	U8
2182 		ReportDeviceMissingDelay;           /*0x12 */
2183 	U8
2184 		IODeviceMissingDelay;               /*0x13 */
2185 	MPI2_SAS_IO_UNIT1_PHY_DATA
2186 		PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /*0x14 */
2187 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2188 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2189 	Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2190 
2191 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2192 
2193 /*values for SAS IO Unit Page 1 ControlFlags */
2194 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2195 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2196 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
2197 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2198 
2199 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2200 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2201 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2202 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2203 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2204 
2205 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2206 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2207 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2208 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2209 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2210 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2211 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2212 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
2213 
2214 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2215 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
2216 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2217 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2218 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2219 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2220 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2221 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2222 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2223 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2224 
2225 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2226 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2227 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2228 
2229 /*values for SAS IO Unit Page 1 PortFlags */
2230 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2231 
2232 /*values for SAS IO Unit Page 1 PhyFlags */
2233 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
2234 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
2235 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2236 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2237 
2238 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2239 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2240 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2241 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2242 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2243 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2244 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2245 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2246 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2247 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2248 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2249 
2250 /*see mpi2_sas.h for values for
2251  *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2252 
2253 
2254 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2255 
2256 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2257 	U8          MaxTargetSpinup;            /*0x00 */
2258 	U8          SpinupDelay;                /*0x01 */
2259 	U8          SpinupFlags;                /*0x02 */
2260 	U8          Reserved1;                  /*0x03 */
2261 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2262 	*PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2263 	Mpi2SasIOUnit4SpinupGroup_t,
2264 	*pMpi2SasIOUnit4SpinupGroup_t;
2265 /*defines for SAS IO Unit Page 4 SpinupFlags */
2266 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2267 
2268 
2269 /*
2270  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2271  *one and check the value returned for NumPhys at runtime.
2272  */
2273 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2274 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2275 #endif
2276 
2277 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2278 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;/*0x00 */
2279 	MPI2_SAS_IOUNIT4_SPINUP_GROUP
2280 		SpinupGroupParameters[4];       /*0x08 */
2281 	U32
2282 		Reserved1;                      /*0x18 */
2283 	U32
2284 		Reserved2;                      /*0x1C */
2285 	U32
2286 		Reserved3;                      /*0x20 */
2287 	U8
2288 		BootDeviceWaitTime;             /*0x24 */
2289 	U8
2290 		SATADeviceWaitTime;		/*0x25 */
2291 	U16
2292 		Reserved5;                      /*0x26 */
2293 	U8
2294 		NumPhys;                        /*0x28 */
2295 	U8
2296 		PEInitialSpinupDelay;           /*0x29 */
2297 	U8
2298 		PEReplyDelay;                   /*0x2A */
2299 	U8
2300 		Flags;                          /*0x2B */
2301 	U8
2302 		PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /*0x2C */
2303 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2304 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2305 	Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2306 
2307 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2308 
2309 /*defines for Flags field */
2310 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2311 
2312 /*defines for PHY field */
2313 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2314 
2315 
2316 /*SAS IO Unit Page 5 */
2317 
2318 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2319 	U8          ControlFlags;               /*0x00 */
2320 	U8          PortWidthModGroup;          /*0x01 */
2321 	U16         InactivityTimerExponent;    /*0x02 */
2322 	U8          SATAPartialTimeout;         /*0x04 */
2323 	U8          Reserved2;                  /*0x05 */
2324 	U8          SATASlumberTimeout;         /*0x06 */
2325 	U8          Reserved3;                  /*0x07 */
2326 	U8          SASPartialTimeout;          /*0x08 */
2327 	U8          Reserved4;                  /*0x09 */
2328 	U8          SASSlumberTimeout;          /*0x0A */
2329 	U8          Reserved5;                  /*0x0B */
2330 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2331 	*PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2332 	Mpi2SasIOUnit5PhyPmSettings_t,
2333 	*pMpi2SasIOUnit5PhyPmSettings_t;
2334 
2335 /*defines for ControlFlags field */
2336 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2337 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2338 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2339 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2340 
2341 /*defines for PortWidthModeGroup field */
2342 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2343 
2344 /*defines for InactivityTimerExponent field */
2345 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2346 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2347 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2348 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2349 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2350 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2351 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2352 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2353 
2354 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2355 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2356 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2357 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2358 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2359 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2360 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2361 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2362 
2363 /*
2364  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2365  *one and check the value returned for NumPhys at runtime.
2366  */
2367 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2368 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2369 #endif
2370 
2371 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2372 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2373 	U8                                  NumPhys;  /*0x08 */
2374 	U8                                  Reserved1;/*0x09 */
2375 	U16                                 Reserved2;/*0x0A */
2376 	U32                                 Reserved3;/*0x0C */
2377 	MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2378 	SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2379 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2380 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2381 	Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2382 
2383 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2384 
2385 
2386 /*SAS IO Unit Page 6 */
2387 
2388 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2389 	U8          CurrentStatus;              /*0x00 */
2390 	U8          CurrentModulation;          /*0x01 */
2391 	U8          CurrentUtilization;         /*0x02 */
2392 	U8          Reserved1;                  /*0x03 */
2393 	U32         Reserved2;                  /*0x04 */
2394 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2395 	*PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2396 	Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2397 	*pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2398 
2399 /*defines for CurrentStatus field */
2400 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2401 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2402 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2403 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2404 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2405 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2406 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2407 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2408 
2409 /*defines for CurrentModulation field */
2410 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2411 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2412 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2413 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2414 
2415 /*
2416  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2417  *one and check the value returned for NumGroups at runtime.
2418  */
2419 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2420 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2421 #endif
2422 
2423 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2424 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /*0x00 */
2425 	U32                                 Reserved1;              /*0x08 */
2426 	U32                                 Reserved2;              /*0x0C */
2427 	U8                                  NumGroups;              /*0x10 */
2428 	U8                                  Reserved3;              /*0x11 */
2429 	U16                                 Reserved4;              /*0x12 */
2430 	MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2431 	PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2432 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2433 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2434 	Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2435 
2436 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2437 
2438 
2439 /*SAS IO Unit Page 7 */
2440 
2441 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2442 	U8          Flags;                      /*0x00 */
2443 	U8          Reserved1;                  /*0x01 */
2444 	U16         Reserved2;                  /*0x02 */
2445 	U8          Threshold75Pct;             /*0x04 */
2446 	U8          Threshold50Pct;             /*0x05 */
2447 	U8          Threshold25Pct;             /*0x06 */
2448 	U8          Reserved3;                  /*0x07 */
2449 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2450 	*PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2451 	Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2452 	*pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2453 
2454 /*defines for Flags field */
2455 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2456 
2457 
2458 /*
2459  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2460  *one and check the value returned for NumGroups at runtime.
2461  */
2462 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2463 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2464 #endif
2465 
2466 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2467 	MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;             /*0x00 */
2468 	U8                               SamplingInterval;   /*0x08 */
2469 	U8                               WindowLength;       /*0x09 */
2470 	U16                              Reserved1;          /*0x0A */
2471 	U32                              Reserved2;          /*0x0C */
2472 	U32                              Reserved3;          /*0x10 */
2473 	U8                               NumGroups;          /*0x14 */
2474 	U8                               Reserved4;          /*0x15 */
2475 	U16                              Reserved5;          /*0x16 */
2476 	MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2477 	PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2478 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2479 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2480 	Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2481 
2482 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2483 
2484 
2485 /*SAS IO Unit Page 8 */
2486 
2487 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2488 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2489 		Header;                         /*0x00 */
2490 	U32
2491 		Reserved1;                      /*0x08 */
2492 	U32
2493 		PowerManagementCapabilities;    /*0x0C */
2494 	U8
2495 		TxRxSleepStatus;                /*0x10 */
2496 	U8
2497 		Reserved2;                      /*0x11 */
2498 	U16
2499 		Reserved3;                      /*0x12 */
2500 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2501 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2502 	Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2503 
2504 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2505 
2506 /*defines for PowerManagementCapabilities field */
2507 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2508 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2509 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2510 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2511 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2512 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2513 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2514 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2515 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2516 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2517 
2518 /*defines for TxRxSleepStatus field */
2519 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2520 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2521 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2522 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2523 
2524 
2525 
2526 /*SAS IO Unit Page 16 */
2527 
2528 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2529 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2530 		Header;                             /*0x00 */
2531 	U64
2532 		TimeStamp;                          /*0x08 */
2533 	U32
2534 		Reserved1;                          /*0x10 */
2535 	U32
2536 		Reserved2;                          /*0x14 */
2537 	U32
2538 		FastPathPendedRequests;             /*0x18 */
2539 	U32
2540 		FastPathUnPendedRequests;           /*0x1C */
2541 	U32
2542 		FastPathHostRequestStarts;          /*0x20 */
2543 	U32
2544 		FastPathFirmwareRequestStarts;      /*0x24 */
2545 	U32
2546 		FastPathHostCompletions;            /*0x28 */
2547 	U32
2548 		FastPathFirmwareCompletions;        /*0x2C */
2549 	U32
2550 		NonFastPathRequestStarts;           /*0x30 */
2551 	U32
2552 		NonFastPathHostCompletions;         /*0x30 */
2553 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2554 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2555 	Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2556 
2557 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2558 
2559 
2560 /****************************************************************************
2561 *  SAS Expander Config Pages
2562 ****************************************************************************/
2563 
2564 /*SAS Expander Page 0 */
2565 
2566 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2567 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2568 		Header;                     /*0x00 */
2569 	U8
2570 		PhysicalPort;               /*0x08 */
2571 	U8
2572 		ReportGenLength;            /*0x09 */
2573 	U16
2574 		EnclosureHandle;            /*0x0A */
2575 	U64
2576 		SASAddress;                 /*0x0C */
2577 	U32
2578 		DiscoveryStatus;            /*0x14 */
2579 	U16
2580 		DevHandle;                  /*0x18 */
2581 	U16
2582 		ParentDevHandle;            /*0x1A */
2583 	U16
2584 		ExpanderChangeCount;        /*0x1C */
2585 	U16
2586 		ExpanderRouteIndexes;       /*0x1E */
2587 	U8
2588 		NumPhys;                    /*0x20 */
2589 	U8
2590 		SASLevel;                   /*0x21 */
2591 	U16
2592 		Flags;                      /*0x22 */
2593 	U16
2594 		STPBusInactivityTimeLimit;  /*0x24 */
2595 	U16
2596 		STPMaxConnectTimeLimit;     /*0x26 */
2597 	U16
2598 		STP_SMP_NexusLossTime;      /*0x28 */
2599 	U16
2600 		MaxNumRoutedSasAddresses;   /*0x2A */
2601 	U64
2602 		ActiveZoneManagerSASAddress;/*0x2C */
2603 	U16
2604 		ZoneLockInactivityLimit;    /*0x34 */
2605 	U16
2606 		Reserved1;                  /*0x36 */
2607 	U8
2608 		TimeToReducedFunc;          /*0x38 */
2609 	U8
2610 		InitialTimeToReducedFunc;   /*0x39 */
2611 	U8
2612 		MaxReducedFuncTime;         /*0x3A */
2613 	U8
2614 		Reserved2;                  /*0x3B */
2615 } MPI2_CONFIG_PAGE_EXPANDER_0,
2616 	*PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2617 	Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2618 
2619 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2620 
2621 /*values for SAS Expander Page 0 DiscoveryStatus field */
2622 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2623 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2624 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2625 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2626 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2627 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2628 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2629 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2630 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2631 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2632 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2633 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2634 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2635 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2636 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2637 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2638 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2639 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2640 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2641 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2642 
2643 /*values for SAS Expander Page 0 Flags field */
2644 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2645 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2646 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2647 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2648 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2649 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2650 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2651 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2652 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2653 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2654 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2655 
2656 
2657 /*SAS Expander Page 1 */
2658 
2659 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2660 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2661 		Header;                     /*0x00 */
2662 	U8
2663 		PhysicalPort;               /*0x08 */
2664 	U8
2665 		Reserved1;                  /*0x09 */
2666 	U16
2667 		Reserved2;                  /*0x0A */
2668 	U8
2669 		NumPhys;                    /*0x0C */
2670 	U8
2671 		Phy;                        /*0x0D */
2672 	U16
2673 		NumTableEntriesProgrammed;  /*0x0E */
2674 	U8
2675 		ProgrammedLinkRate;         /*0x10 */
2676 	U8
2677 		HwLinkRate;                 /*0x11 */
2678 	U16
2679 		AttachedDevHandle;          /*0x12 */
2680 	U32
2681 		PhyInfo;                    /*0x14 */
2682 	U32
2683 		AttachedDeviceInfo;         /*0x18 */
2684 	U16
2685 		ExpanderDevHandle;          /*0x1C */
2686 	U8
2687 		ChangeCount;                /*0x1E */
2688 	U8
2689 		NegotiatedLinkRate;         /*0x1F */
2690 	U8
2691 		PhyIdentifier;              /*0x20 */
2692 	U8
2693 		AttachedPhyIdentifier;      /*0x21 */
2694 	U8
2695 		Reserved3;                  /*0x22 */
2696 	U8
2697 		DiscoveryInfo;              /*0x23 */
2698 	U32
2699 		AttachedPhyInfo;            /*0x24 */
2700 	U8
2701 		ZoneGroup;                  /*0x28 */
2702 	U8
2703 		SelfConfigStatus;           /*0x29 */
2704 	U16
2705 		Reserved4;                  /*0x2A */
2706 } MPI2_CONFIG_PAGE_EXPANDER_1,
2707 	*PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2708 	Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2709 
2710 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2711 
2712 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2713 
2714 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2715 
2716 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2717 
2718 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2719  *used for the AttachedDeviceInfo field */
2720 
2721 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2722 
2723 /*values for SAS Expander Page 1 DiscoveryInfo field */
2724 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2725 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2726 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2727 
2728 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2729 
2730 
2731 /****************************************************************************
2732 *  SAS Device Config Pages
2733 ****************************************************************************/
2734 
2735 /*SAS Device Page 0 */
2736 
2737 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2738 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2739 		Header;                 /*0x00 */
2740 	U16
2741 		Slot;                   /*0x08 */
2742 	U16
2743 		EnclosureHandle;        /*0x0A */
2744 	U64
2745 		SASAddress;             /*0x0C */
2746 	U16
2747 		ParentDevHandle;        /*0x14 */
2748 	U8
2749 		PhyNum;                 /*0x16 */
2750 	U8
2751 		AccessStatus;           /*0x17 */
2752 	U16
2753 		DevHandle;              /*0x18 */
2754 	U8
2755 		AttachedPhyIdentifier;  /*0x1A */
2756 	U8
2757 		ZoneGroup;              /*0x1B */
2758 	U32
2759 		DeviceInfo;             /*0x1C */
2760 	U16
2761 		Flags;                  /*0x20 */
2762 	U8
2763 		PhysicalPort;           /*0x22 */
2764 	U8
2765 		MaxPortConnections;     /*0x23 */
2766 	U64
2767 		DeviceName;             /*0x24 */
2768 	U8
2769 		PortGroups;             /*0x2C */
2770 	U8
2771 		DmaGroup;               /*0x2D */
2772 	U8
2773 		ControlGroup;           /*0x2E */
2774 	U8
2775 		EnclosureLevel;		/*0x2F */
2776 	U32
2777 		ConnectorName[4];	/*0x30 */
2778 	U32
2779 		Reserved3;              /*0x34 */
2780 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2781 	*PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2782 	Mpi2SasDevicePage0_t,
2783 	*pMpi2SasDevicePage0_t;
2784 
2785 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2786 
2787 /*values for SAS Device Page 0 AccessStatus field */
2788 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2789 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2790 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2791 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2792 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2793 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2794 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2795 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2796 /*specific values for SATA Init failures */
2797 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2798 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2799 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2800 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2801 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2802 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2803 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2804 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2805 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2806 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2807 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2808 
2809 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2810 
2811 /*values for SAS Device Page 0 Flags field */
2812 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2813 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2814 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2815 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2816 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2817 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2818 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2819 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2820 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2821 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2822 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2823 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2824 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2825 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE              (0x0004)
2826 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2827 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2828 
2829 
2830 /*SAS Device Page 1 */
2831 
2832 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2833 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2834 		Header;                 /*0x00 */
2835 	U32
2836 		Reserved1;              /*0x08 */
2837 	U64
2838 		SASAddress;             /*0x0C */
2839 	U32
2840 		Reserved2;              /*0x14 */
2841 	U16
2842 		DevHandle;              /*0x18 */
2843 	U16
2844 		Reserved3;              /*0x1A */
2845 	U8
2846 		InitialRegDeviceFIS[20];/*0x1C */
2847 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2848 	*PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2849 	Mpi2SasDevicePage1_t,
2850 	*pMpi2SasDevicePage1_t;
2851 
2852 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2853 
2854 
2855 /****************************************************************************
2856 *  SAS PHY Config Pages
2857 ****************************************************************************/
2858 
2859 /*SAS PHY Page 0 */
2860 
2861 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2862 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2863 		Header;                 /*0x00 */
2864 	U16
2865 		OwnerDevHandle;         /*0x08 */
2866 	U16
2867 		Reserved1;              /*0x0A */
2868 	U16
2869 		AttachedDevHandle;      /*0x0C */
2870 	U8
2871 		AttachedPhyIdentifier;  /*0x0E */
2872 	U8
2873 		Reserved2;              /*0x0F */
2874 	U32
2875 		AttachedPhyInfo;        /*0x10 */
2876 	U8
2877 		ProgrammedLinkRate;     /*0x14 */
2878 	U8
2879 		HwLinkRate;             /*0x15 */
2880 	U8
2881 		ChangeCount;            /*0x16 */
2882 	U8
2883 		Flags;                  /*0x17 */
2884 	U32
2885 		PhyInfo;                /*0x18 */
2886 	U8
2887 		NegotiatedLinkRate;     /*0x1C */
2888 	U8
2889 		Reserved3;              /*0x1D */
2890 	U16
2891 		Reserved4;              /*0x1E */
2892 } MPI2_CONFIG_PAGE_SAS_PHY_0,
2893 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2894 	Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2895 
2896 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2897 
2898 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2899 
2900 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2901 
2902 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2903 
2904 /*values for SAS PHY Page 0 Flags field */
2905 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2906 
2907 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2908 
2909 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2910 
2911 
2912 /*SAS PHY Page 1 */
2913 
2914 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2915 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2916 		Header;                     /*0x00 */
2917 	U32
2918 		Reserved1;                  /*0x08 */
2919 	U32
2920 		InvalidDwordCount;          /*0x0C */
2921 	U32
2922 		RunningDisparityErrorCount; /*0x10 */
2923 	U32
2924 		LossDwordSynchCount;        /*0x14 */
2925 	U32
2926 		PhyResetProblemCount;       /*0x18 */
2927 } MPI2_CONFIG_PAGE_SAS_PHY_1,
2928 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2929 	Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
2930 
2931 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2932 
2933 
2934 /*SAS PHY Page 2 */
2935 
2936 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2937 	U8          PhyEventCode;       /*0x00 */
2938 	U8          Reserved1;          /*0x01 */
2939 	U16         Reserved2;          /*0x02 */
2940 	U32         PhyEventInfo;       /*0x04 */
2941 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
2942 	Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
2943 
2944 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2945 
2946 
2947 /*
2948  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2949  *one and check the value returned for NumPhyEvents at runtime.
2950  */
2951 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2952 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2953 #endif
2954 
2955 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2956 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2957 		Header;                     /*0x00 */
2958 	U32
2959 		Reserved1;                  /*0x08 */
2960 	U8
2961 		NumPhyEvents;               /*0x0C */
2962 	U8
2963 		Reserved2;                  /*0x0D */
2964 	U16
2965 		Reserved3;                  /*0x0E */
2966 	MPI2_SASPHY2_PHY_EVENT
2967 		PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
2968 } MPI2_CONFIG_PAGE_SAS_PHY_2,
2969 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2970 	Mpi2SasPhyPage2_t,
2971 	*pMpi2SasPhyPage2_t;
2972 
2973 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2974 
2975 
2976 /*SAS PHY Page 3 */
2977 
2978 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2979 	U8          PhyEventCode;       /*0x00 */
2980 	U8          Reserved1;          /*0x01 */
2981 	U16         Reserved2;          /*0x02 */
2982 	U8          CounterType;        /*0x04 */
2983 	U8          ThresholdWindow;    /*0x05 */
2984 	U8          TimeUnits;          /*0x06 */
2985 	U8          Reserved3;          /*0x07 */
2986 	U32         EventThreshold;     /*0x08 */
2987 	U16         ThresholdFlags;     /*0x0C */
2988 	U16         Reserved4;          /*0x0E */
2989 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
2990 	*PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2991 	Mpi2SasPhy3PhyEventConfig_t,
2992 	*pMpi2SasPhy3PhyEventConfig_t;
2993 
2994 /*values for PhyEventCode field */
2995 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2996 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2997 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2998 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2999 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
3000 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
3001 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
3002 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
3003 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
3004 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
3005 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
3006 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
3007 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
3008 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
3009 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
3010 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
3011 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
3012 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
3013 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
3014 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
3015 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
3016 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
3017 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
3018 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
3019 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
3020 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
3021 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
3022 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
3023 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
3024 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
3025 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
3026 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
3027 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
3028 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
3029 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
3030 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
3031 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
3032 
3033 /*Following codes are product specific and in MPI v2.6 and later */
3034 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME		    (0xD3)
3035 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xD4)
3036 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME	            (0xD5)
3037 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT	    (0xD6)
3038 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START	            (0xD7)
3039 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT	    (0xD8)
3040 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN	    (0xD9)
3041 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE	    (0xDA)
3042 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE	    (0xDB)
3043 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE	    (0xDC)
3044 
3045 
3046 /*values for the CounterType field */
3047 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
3048 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
3049 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
3050 
3051 /*values for the TimeUnits field */
3052 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
3053 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
3054 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
3055 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
3056 
3057 /*values for the ThresholdFlags field */
3058 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
3059 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
3060 
3061 /*
3062  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3063  *one and check the value returned for NumPhyEvents at runtime.
3064  */
3065 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
3066 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
3067 #endif
3068 
3069 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3070 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3071 		Header;                     /*0x00 */
3072 	U32
3073 		Reserved1;                  /*0x08 */
3074 	U8
3075 		NumPhyEvents;               /*0x0C */
3076 	U8
3077 		Reserved2;                  /*0x0D */
3078 	U16
3079 		Reserved3;                  /*0x0E */
3080 	MPI2_SASPHY3_PHY_EVENT_CONFIG
3081 		PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
3082 } MPI2_CONFIG_PAGE_SAS_PHY_3,
3083 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3084 	Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3085 
3086 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
3087 
3088 
3089 /*SAS PHY Page 4 */
3090 
3091 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3092 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3093 		Header;                     /*0x00 */
3094 	U16
3095 		Reserved1;                  /*0x08 */
3096 	U8
3097 		Reserved2;                  /*0x0A */
3098 	U8
3099 		Flags;                      /*0x0B */
3100 	U8
3101 		InitialFrame[28];           /*0x0C */
3102 } MPI2_CONFIG_PAGE_SAS_PHY_4,
3103 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3104 	Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3105 
3106 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
3107 
3108 /*values for the Flags field */
3109 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
3110 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
3111 
3112 
3113 
3114 
3115 /****************************************************************************
3116 *  SAS Port Config Pages
3117 ****************************************************************************/
3118 
3119 /*SAS Port Page 0 */
3120 
3121 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3122 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3123 		Header;                     /*0x00 */
3124 	U8
3125 		PortNumber;                 /*0x08 */
3126 	U8
3127 		PhysicalPort;               /*0x09 */
3128 	U8
3129 		PortWidth;                  /*0x0A */
3130 	U8
3131 		PhysicalPortWidth;          /*0x0B */
3132 	U8
3133 		ZoneGroup;                  /*0x0C */
3134 	U8
3135 		Reserved1;                  /*0x0D */
3136 	U16
3137 		Reserved2;                  /*0x0E */
3138 	U64
3139 		SASAddress;                 /*0x10 */
3140 	U32
3141 		DeviceInfo;                 /*0x18 */
3142 	U32
3143 		Reserved3;                  /*0x1C */
3144 	U32
3145 		Reserved4;                  /*0x20 */
3146 } MPI2_CONFIG_PAGE_SAS_PORT_0,
3147 	*PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3148 	Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3149 
3150 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
3151 
3152 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3153 
3154 
3155 /****************************************************************************
3156 *  SAS Enclosure Config Pages
3157 ****************************************************************************/
3158 
3159 /*SAS Enclosure Page 0 */
3160 
3161 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3162 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3163 		Header;                     /*0x00 */
3164 	U32
3165 		Reserved1;                  /*0x08 */
3166 	U64
3167 		EnclosureLogicalID;         /*0x0C */
3168 	U16
3169 		Flags;                      /*0x14 */
3170 	U16
3171 		EnclosureHandle;            /*0x16 */
3172 	U16
3173 		NumSlots;                   /*0x18 */
3174 	U16
3175 		StartSlot;                  /*0x1A */
3176 	U8
3177 		Reserved2;                  /*0x1C */
3178 	U8
3179 		EnclosureLevel;		    /*0x1D */
3180 	U16
3181 		SEPDevHandle;               /*0x1E */
3182 	U32
3183 		Reserved3;                  /*0x20 */
3184 	U32
3185 		Reserved4;                  /*0x24 */
3186 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3187 	*PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3188 	Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t;
3189 
3190 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
3191 
3192 /*values for SAS Enclosure Page 0 Flags field */
3193 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
3194 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
3195 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
3196 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
3197 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
3198 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
3199 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
3200 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
3201 
3202 
3203 /****************************************************************************
3204 *  Log Config Page
3205 ****************************************************************************/
3206 
3207 /*Log Page 0 */
3208 
3209 /*
3210  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3211  *one and check the value returned for NumLogEntries at runtime.
3212  */
3213 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3214 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
3215 #endif
3216 
3217 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
3218 
3219 typedef struct _MPI2_LOG_0_ENTRY {
3220 	U64         TimeStamp;                      /*0x00 */
3221 	U32         Reserved1;                      /*0x08 */
3222 	U16         LogSequence;                    /*0x0C */
3223 	U16         LogEntryQualifier;              /*0x0E */
3224 	U8          VP_ID;                          /*0x10 */
3225 	U8          VF_ID;                          /*0x11 */
3226 	U16         Reserved2;                      /*0x12 */
3227 	U8
3228 		LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3229 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3230 	Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3231 
3232 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3233 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
3234 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
3235 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
3236 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
3237 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
3238 
3239 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3240 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;       /*0x00 */
3241 	U32                                 Reserved1;    /*0x08 */
3242 	U32                                 Reserved2;    /*0x0C */
3243 	U16                                 NumLogEntries;/*0x10 */
3244 	U16                                 Reserved3;    /*0x12 */
3245 	MPI2_LOG_0_ENTRY
3246 		LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3247 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3248 	Mpi2LogPage0_t, *pMpi2LogPage0_t;
3249 
3250 #define MPI2_LOG_0_PAGEVERSION              (0x02)
3251 
3252 
3253 /****************************************************************************
3254 *  RAID Config Page
3255 ****************************************************************************/
3256 
3257 /*RAID Page 0 */
3258 
3259 /*
3260  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3261  *one and check the value returned for NumElements at runtime.
3262  */
3263 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3264 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
3265 #endif
3266 
3267 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3268 	U16                     ElementFlags;             /*0x00 */
3269 	U16                     VolDevHandle;             /*0x02 */
3270 	U8                      HotSparePool;             /*0x04 */
3271 	U8                      PhysDiskNum;              /*0x05 */
3272 	U16                     PhysDiskDevHandle;        /*0x06 */
3273 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3274 	*PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3275 	Mpi2RaidConfig0ConfigElement_t,
3276 	*pMpi2RaidConfig0ConfigElement_t;
3277 
3278 /*values for the ElementFlags field */
3279 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
3280 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
3281 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
3282 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
3283 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
3284 
3285 
3286 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3287 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;         /*0x00 */
3288 	U8                                  NumHotSpares;   /*0x08 */
3289 	U8                                  NumPhysDisks;   /*0x09 */
3290 	U8                                  NumVolumes;     /*0x0A */
3291 	U8                                  ConfigNum;      /*0x0B */
3292 	U32                                 Flags;          /*0x0C */
3293 	U8                                  ConfigGUID[24]; /*0x10 */
3294 	U32                                 Reserved1;      /*0x28 */
3295 	U8                                  NumElements;    /*0x2C */
3296 	U8                                  Reserved2;      /*0x2D */
3297 	U16                                 Reserved3;      /*0x2E */
3298 	MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3299 		ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3300 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3301 	*PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3302 	Mpi2RaidConfigurationPage0_t,
3303 	*pMpi2RaidConfigurationPage0_t;
3304 
3305 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
3306 
3307 /*values for RAID Configuration Page 0 Flags field */
3308 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
3309 
3310 
3311 /****************************************************************************
3312 *  Driver Persistent Mapping Config Pages
3313 ****************************************************************************/
3314 
3315 /*Driver Persistent Mapping Page 0 */
3316 
3317 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3318 	U64	PhysicalIdentifier;         /*0x00 */
3319 	U16	MappingInformation;         /*0x08 */
3320 	U16	DeviceIndex;                /*0x0A */
3321 	U32	PhysicalBitsMapping;        /*0x0C */
3322 	U32	Reserved1;                  /*0x10 */
3323 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3324 	*PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3325 	Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3326 
3327 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3328 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
3329 	MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;  /*0x08 */
3330 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3331 	*PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3332 	Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3333 
3334 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3335 
3336 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3337 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3338 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3339 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3340 
3341 
3342 /****************************************************************************
3343 *  Ethernet Config Pages
3344 ****************************************************************************/
3345 
3346 /*Ethernet Page 0 */
3347 
3348 /*IP address (union of IPv4 and IPv6) */
3349 typedef union _MPI2_ETHERNET_IP_ADDR {
3350 	U32     IPv4Addr;
3351 	U32     IPv6Addr[4];
3352 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3353 	Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3354 
3355 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3356 
3357 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3358 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;          /*0x00 */
3359 	U8                                  NumInterfaces;   /*0x08 */
3360 	U8                                  Reserved0;       /*0x09 */
3361 	U16                                 Reserved1;       /*0x0A */
3362 	U32                                 Status;          /*0x0C */
3363 	U8                                  MediaState;      /*0x10 */
3364 	U8                                  Reserved2;       /*0x11 */
3365 	U16                                 Reserved3;       /*0x12 */
3366 	U8                                  MacAddress[6];   /*0x14 */
3367 	U8                                  Reserved4;       /*0x1A */
3368 	U8                                  Reserved5;       /*0x1B */
3369 	MPI2_ETHERNET_IP_ADDR               IpAddress;       /*0x1C */
3370 	MPI2_ETHERNET_IP_ADDR               SubnetMask;      /*0x2C */
3371 	MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;/*0x3C */
3372 	MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;   /*0x4C */
3373 	MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;   /*0x5C */
3374 	MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;   /*0x6C */
3375 	U8
3376 		HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3377 } MPI2_CONFIG_PAGE_ETHERNET_0,
3378 	*PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3379 	Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3380 
3381 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3382 
3383 /*values for Ethernet Page 0 Status field */
3384 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3385 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3386 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3387 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3388 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3389 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3390 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3391 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3392 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3393 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3394 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3395 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3396 
3397 /*values for Ethernet Page 0 MediaState field */
3398 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3399 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3400 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3401 
3402 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3403 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3404 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3405 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3406 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3407 
3408 
3409 /*Ethernet Page 1 */
3410 
3411 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3412 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3413 		Header;                 /*0x00 */
3414 	U32
3415 		Reserved0;              /*0x08 */
3416 	U32
3417 		Flags;                  /*0x0C */
3418 	U8
3419 		MediaState;             /*0x10 */
3420 	U8
3421 		Reserved1;              /*0x11 */
3422 	U16
3423 		Reserved2;              /*0x12 */
3424 	U8
3425 		MacAddress[6];          /*0x14 */
3426 	U8
3427 		Reserved3;              /*0x1A */
3428 	U8
3429 		Reserved4;              /*0x1B */
3430 	MPI2_ETHERNET_IP_ADDR
3431 		StaticIpAddress;        /*0x1C */
3432 	MPI2_ETHERNET_IP_ADDR
3433 		StaticSubnetMask;       /*0x2C */
3434 	MPI2_ETHERNET_IP_ADDR
3435 		StaticGatewayIpAddress; /*0x3C */
3436 	MPI2_ETHERNET_IP_ADDR
3437 		StaticDNS1IpAddress;    /*0x4C */
3438 	MPI2_ETHERNET_IP_ADDR
3439 		StaticDNS2IpAddress;    /*0x5C */
3440 	U32
3441 		Reserved5;              /*0x6C */
3442 	U32
3443 		Reserved6;              /*0x70 */
3444 	U32
3445 		Reserved7;              /*0x74 */
3446 	U32
3447 		Reserved8;              /*0x78 */
3448 	U8
3449 		HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3450 } MPI2_CONFIG_PAGE_ETHERNET_1,
3451 	*PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3452 	Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3453 
3454 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3455 
3456 /*values for Ethernet Page 1 Flags field */
3457 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3458 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3459 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3460 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3461 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3462 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3463 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3464 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3465 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3466 
3467 /*values for Ethernet Page 1 MediaState field */
3468 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3469 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3470 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3471 
3472 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3473 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3474 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3475 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3476 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3477 
3478 
3479 /****************************************************************************
3480 *  Extended Manufacturing Config Pages
3481 ****************************************************************************/
3482 
3483 /*
3484  *Generic structure to use for product-specific extended manufacturing pages
3485  *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3486  *Page 60).
3487  */
3488 
3489 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3490 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3491 		Header;                 /*0x00 */
3492 	U32
3493 		ProductSpecificInfo;    /*0x08 */
3494 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3495 	*PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3496 	Mpi2ExtManufacturingPagePS_t,
3497 	*pMpi2ExtManufacturingPagePS_t;
3498 
3499 /*PageVersion should be provided by product-specific code */
3500 
3501 #endif
3502