1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Linux MegaRAID driver for SAS based RAID controllers 4 * 5 * Copyright (c) 2009-2013 LSI Corporation 6 * Copyright (c) 2013-2016 Avago Technologies 7 * Copyright (c) 2016-2018 Broadcom Inc. 8 * 9 * FILE: megaraid_sas_fusion.h 10 * 11 * Authors: Broadcom Inc. 12 * Manoj Jose 13 * Sumant Patro 14 * Kashyap Desai <kashyap.desai@broadcom.com> 15 * Sumit Saxena <sumit.saxena@broadcom.com> 16 * 17 * Send feedback to: megaraidlinux.pdl@broadcom.com 18 */ 19 20 #ifndef _MEGARAID_SAS_FUSION_H_ 21 #define _MEGARAID_SAS_FUSION_H_ 22 23 /* Fusion defines */ 24 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 25 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 26 #define MEGASAS_MAX_CHAIN_SHIFT 5 27 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 28 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 29 #define MEGASAS_256K_IO 128 30 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 31 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 32 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 33 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 34 #define MEGASAS_LOAD_BALANCE_FLAG 0x1 35 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 36 #define HOST_DIAG_WRITE_ENABLE 0x80 37 #define HOST_DIAG_RESET_ADAPTER 0x4 38 #define MEGASAS_FUSION_MAX_RESET_TRIES 3 39 #define MAX_MSIX_QUEUES_FUSION 128 40 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16 41 #define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK) 42 43 /* Invader defines */ 44 #define MPI2_TYPE_CUDA 0x2 45 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 46 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 47 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 48 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 49 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 50 #define MR_RL_WRITE_THROUGH_MODE 0x00 51 #define MR_RL_WRITE_BACK_MODE 0x01 52 53 /* T10 PI defines */ 54 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 55 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 56 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 57 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 58 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 59 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 60 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 61 62 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 63 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 64 65 /* 66 * Raid context flags 67 */ 68 69 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 70 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 71 enum MR_RAID_FLAGS_IO_SUB_TYPE { 72 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 73 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 74 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 75 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 76 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 77 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 78 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 79 }; 80 81 /* 82 * Request descriptor types 83 */ 84 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 85 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 86 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 87 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 88 89 #define MEGASAS_FP_CMD_LEN 16 90 #define MEGASAS_FUSION_IN_RESET 0 91 #define THRESHOLD_REPLY_COUNT 50 92 #define RAID_1_PEER_CMDS 2 93 #define JBOD_MAPS_COUNT 2 94 #define MEGASAS_REDUCE_QD_COUNT 64 95 #define IOC_INIT_FRAME_SIZE 4096 96 97 /* 98 * Raid Context structure which describes MegaRAID specific IO Parameters 99 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 100 */ 101 102 struct RAID_CONTEXT { 103 #if defined(__BIG_ENDIAN_BITFIELD) 104 u8 nseg:4; 105 u8 type:4; 106 #else 107 u8 type:4; 108 u8 nseg:4; 109 #endif 110 u8 resvd0; 111 __le16 timeout_value; 112 u8 reg_lock_flags; 113 u8 resvd1; 114 __le16 virtual_disk_tgt_id; 115 __le64 reg_lock_row_lba; 116 __le32 reg_lock_length; 117 __le16 next_lmid; 118 u8 ex_status; 119 u8 status; 120 u8 raid_flags; 121 u8 num_sge; 122 __le16 config_seq_num; 123 u8 span_arm; 124 u8 priority; 125 u8 num_sge_ext; 126 u8 resvd2; 127 }; 128 129 /* 130 * Raid Context structure which describes ventura MegaRAID specific 131 * IO Paramenters ,This resides at offset 0x60 where the SGL normally 132 * starts in MPT IO Frames 133 */ 134 struct RAID_CONTEXT_G35 { 135 #define RAID_CONTEXT_NSEG_MASK 0x00F0 136 #define RAID_CONTEXT_NSEG_SHIFT 4 137 #define RAID_CONTEXT_TYPE_MASK 0x000F 138 #define RAID_CONTEXT_TYPE_SHIFT 0 139 u16 nseg_type; 140 u16 timeout_value; /* 0x02 -0x03 */ 141 u16 routing_flags; // 0x04 -0x05 routing flags 142 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */ 143 u64 reg_lock_row_lba; /* 0x08 - 0x0F */ 144 u32 reg_lock_length; /* 0x10 - 0x13 */ 145 union { 146 u16 next_lmid; /* 0x14 - 0x15 */ 147 u16 peer_smid; /* used for the raid 1/10 fp writes */ 148 } smid; 149 u8 ex_status; /* 0x16 : OUT */ 150 u8 status; /* 0x17 status */ 151 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4], 152 * resvd[3:1], preferredCpu[0] 153 */ 154 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */ 155 u16 config_seq_num; /* 0x1A -0x1B */ 156 union { 157 /* 158 * Bit format: 159 * --------------------------------- 160 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 161 * --------------------------------- 162 * Byte0 | numSGE[7]- numSGE[0] | 163 * --------------------------------- 164 * Byte1 |SD | resvd | numSGE 8-11 | 165 * -------------------------------- 166 */ 167 #define NUM_SGE_MASK_LOWER 0xFF 168 #define NUM_SGE_MASK_UPPER 0x0F 169 #define NUM_SGE_SHIFT_UPPER 8 170 #define STREAM_DETECT_SHIFT 7 171 #define STREAM_DETECT_MASK 0x80 172 struct { 173 #if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */ 174 u16 stream_detected:1; 175 u16 reserved:3; 176 u16 num_sge:12; 177 #else 178 u16 num_sge:12; 179 u16 reserved:3; 180 u16 stream_detected:1; 181 #endif 182 } bits; 183 u8 bytes[2]; 184 } u; 185 u8 resvd2[2]; /* 0x1E-0x1F */ 186 }; 187 188 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1 189 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2 190 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3 191 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4 192 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5 193 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6 194 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7 195 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8 196 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00 197 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12 198 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000 199 200 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35, 201 u16 sge_count) 202 { 203 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER); 204 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER) 205 & NUM_SGE_MASK_UPPER); 206 } 207 208 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35) 209 { 210 u16 sge_count; 211 212 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER) 213 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0])); 214 return sge_count; 215 } 216 217 #define SET_STREAM_DETECTED(rctx_g35) \ 218 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK) 219 220 #define CLEAR_STREAM_DETECTED(rctx_g35) \ 221 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK)) 222 223 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35) 224 { 225 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK)); 226 } 227 228 union RAID_CONTEXT_UNION { 229 struct RAID_CONTEXT raid_context; 230 struct RAID_CONTEXT_G35 raid_context_g35; 231 }; 232 233 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 234 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 235 236 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 237 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 238 239 /* number of bits per index in U32 TrackStream */ 240 #define BITS_PER_INDEX_STREAM 4 241 #define INVALID_STREAM_NUM 16 242 #define MR_STREAM_BITMAP 0x76543210 243 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 244 #define ZERO_LAST_STREAM 0x0fffffff 245 #define MAX_STREAMS_TRACKED 8 246 247 /* 248 * define region lock types 249 */ 250 enum REGION_TYPE { 251 REGION_TYPE_UNUSED = 0, 252 REGION_TYPE_SHARED_READ = 1, 253 REGION_TYPE_SHARED_WRITE = 2, 254 REGION_TYPE_EXCLUSIVE = 3, 255 }; 256 257 /* MPI2 defines */ 258 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 259 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 260 #define MPI2_VERSION_MAJOR (0x02) 261 #define MPI2_VERSION_MINOR (0x00) 262 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 263 #define MPI2_VERSION_MAJOR_SHIFT (8) 264 #define MPI2_VERSION_MINOR_MASK (0x00FF) 265 #define MPI2_VERSION_MINOR_SHIFT (0) 266 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 267 MPI2_VERSION_MINOR) 268 #define MPI2_HEADER_VERSION_UNIT (0x10) 269 #define MPI2_HEADER_VERSION_DEV (0x00) 270 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 271 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 272 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 273 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 274 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 275 MPI2_HEADER_VERSION_DEV) 276 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 277 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 278 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 279 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 280 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 281 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 282 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 283 /* EEDP escape mode */ 284 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040) 285 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 286 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 287 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 288 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 289 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 290 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 291 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 292 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 293 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 294 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 295 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 296 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 297 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 298 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 299 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 300 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 301 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 302 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 303 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 304 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 305 306 struct MPI25_IEEE_SGE_CHAIN64 { 307 __le64 Address; 308 __le32 Length; 309 __le16 Reserved1; 310 u8 NextChainOffset; 311 u8 Flags; 312 }; 313 314 struct MPI2_SGE_SIMPLE_UNION { 315 __le32 FlagsLength; 316 union { 317 __le32 Address32; 318 __le64 Address64; 319 } u; 320 }; 321 322 struct MPI2_SCSI_IO_CDB_EEDP32 { 323 u8 CDB[20]; /* 0x00 */ 324 __be32 PrimaryReferenceTag; /* 0x14 */ 325 __be16 PrimaryApplicationTag; /* 0x18 */ 326 __be16 PrimaryApplicationTagMask; /* 0x1A */ 327 __le32 TransferLength; /* 0x1C */ 328 }; 329 330 struct MPI2_SGE_CHAIN_UNION { 331 __le16 Length; 332 u8 NextChainOffset; 333 u8 Flags; 334 union { 335 __le32 Address32; 336 __le64 Address64; 337 } u; 338 }; 339 340 struct MPI2_IEEE_SGE_SIMPLE32 { 341 __le32 Address; 342 __le32 FlagsLength; 343 }; 344 345 struct MPI2_IEEE_SGE_CHAIN32 { 346 __le32 Address; 347 __le32 FlagsLength; 348 }; 349 350 struct MPI2_IEEE_SGE_SIMPLE64 { 351 __le64 Address; 352 __le32 Length; 353 __le16 Reserved1; 354 u8 Reserved2; 355 u8 Flags; 356 }; 357 358 struct MPI2_IEEE_SGE_CHAIN64 { 359 __le64 Address; 360 __le32 Length; 361 __le16 Reserved1; 362 u8 Reserved2; 363 u8 Flags; 364 }; 365 366 union MPI2_IEEE_SGE_SIMPLE_UNION { 367 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 368 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 369 }; 370 371 union MPI2_IEEE_SGE_CHAIN_UNION { 372 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 373 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 374 }; 375 376 union MPI2_SGE_IO_UNION { 377 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 378 struct MPI2_SGE_CHAIN_UNION MpiChain; 379 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 380 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 381 }; 382 383 union MPI2_SCSI_IO_CDB_UNION { 384 u8 CDB32[32]; 385 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 386 struct MPI2_SGE_SIMPLE_UNION SGE; 387 }; 388 389 /**************************************************************************** 390 * SCSI Task Management messages 391 ****************************************************************************/ 392 393 /*SCSI Task Management Request Message */ 394 struct MPI2_SCSI_TASK_MANAGE_REQUEST { 395 u16 DevHandle; /*0x00 */ 396 u8 ChainOffset; /*0x02 */ 397 u8 Function; /*0x03 */ 398 u8 Reserved1; /*0x04 */ 399 u8 TaskType; /*0x05 */ 400 u8 Reserved2; /*0x06 */ 401 u8 MsgFlags; /*0x07 */ 402 u8 VP_ID; /*0x08 */ 403 u8 VF_ID; /*0x09 */ 404 u16 Reserved3; /*0x0A */ 405 u8 LUN[8]; /*0x0C */ 406 u32 Reserved4[7]; /*0x14 */ 407 u16 TaskMID; /*0x30 */ 408 u16 Reserved5; /*0x32 */ 409 }; 410 411 412 /*SCSI Task Management Reply Message */ 413 struct MPI2_SCSI_TASK_MANAGE_REPLY { 414 u16 DevHandle; /*0x00 */ 415 u8 MsgLength; /*0x02 */ 416 u8 Function; /*0x03 */ 417 u8 ResponseCode; /*0x04 */ 418 u8 TaskType; /*0x05 */ 419 u8 Reserved1; /*0x06 */ 420 u8 MsgFlags; /*0x07 */ 421 u8 VP_ID; /*0x08 */ 422 u8 VF_ID; /*0x09 */ 423 u16 Reserved2; /*0x0A */ 424 u16 Reserved3; /*0x0C */ 425 u16 IOCStatus; /*0x0E */ 426 u32 IOCLogInfo; /*0x10 */ 427 u32 TerminationCount; /*0x14 */ 428 u32 ResponseInfo; /*0x18 */ 429 }; 430 431 struct MR_TM_REQUEST { 432 char request[128]; 433 }; 434 435 struct MR_TM_REPLY { 436 char reply[128]; 437 }; 438 439 /* SCSI Task Management Request Message */ 440 struct MR_TASK_MANAGE_REQUEST { 441 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 442 struct MR_TM_REQUEST TmRequest; 443 union { 444 struct { 445 #if defined(__BIG_ENDIAN_BITFIELD) 446 u32 reserved1:30; 447 u32 isTMForPD:1; 448 u32 isTMForLD:1; 449 #else 450 u32 isTMForLD:1; 451 u32 isTMForPD:1; 452 u32 reserved1:30; 453 #endif 454 u32 reserved2; 455 } tmReqFlags; 456 struct MR_TM_REPLY TMReply; 457 }; 458 }; 459 460 /* TaskType values */ 461 462 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 463 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 464 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 465 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 466 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 467 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 468 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 469 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 470 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 471 472 /* ResponseCode values */ 473 474 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 475 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 476 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 477 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 478 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 479 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 480 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 481 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 482 483 /* 484 * RAID SCSI IO Request Message 485 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 486 */ 487 struct MPI2_RAID_SCSI_IO_REQUEST { 488 __le16 DevHandle; /* 0x00 */ 489 u8 ChainOffset; /* 0x02 */ 490 u8 Function; /* 0x03 */ 491 __le16 Reserved1; /* 0x04 */ 492 u8 Reserved2; /* 0x06 */ 493 u8 MsgFlags; /* 0x07 */ 494 u8 VP_ID; /* 0x08 */ 495 u8 VF_ID; /* 0x09 */ 496 __le16 Reserved3; /* 0x0A */ 497 __le32 SenseBufferLowAddress; /* 0x0C */ 498 __le16 SGLFlags; /* 0x10 */ 499 u8 SenseBufferLength; /* 0x12 */ 500 u8 Reserved4; /* 0x13 */ 501 u8 SGLOffset0; /* 0x14 */ 502 u8 SGLOffset1; /* 0x15 */ 503 u8 SGLOffset2; /* 0x16 */ 504 u8 SGLOffset3; /* 0x17 */ 505 __le32 SkipCount; /* 0x18 */ 506 __le32 DataLength; /* 0x1C */ 507 __le32 BidirectionalDataLength; /* 0x20 */ 508 __le16 IoFlags; /* 0x24 */ 509 __le16 EEDPFlags; /* 0x26 */ 510 __le32 EEDPBlockSize; /* 0x28 */ 511 __le32 SecondaryReferenceTag; /* 0x2C */ 512 __le16 SecondaryApplicationTag; /* 0x30 */ 513 __le16 ApplicationTagTranslationMask; /* 0x32 */ 514 u8 LUN[8]; /* 0x34 */ 515 __le32 Control; /* 0x3C */ 516 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 517 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 518 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 519 }; 520 521 /* 522 * MPT RAID MFA IO Descriptor. 523 */ 524 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 525 u32 RequestFlags:8; 526 u32 MessageAddress1:24; 527 u32 MessageAddress2; 528 }; 529 530 /* Default Request Descriptor */ 531 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 532 u8 RequestFlags; /* 0x00 */ 533 u8 MSIxIndex; /* 0x01 */ 534 __le16 SMID; /* 0x02 */ 535 __le16 LMID; /* 0x04 */ 536 __le16 DescriptorTypeDependent; /* 0x06 */ 537 }; 538 539 /* High Priority Request Descriptor */ 540 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 541 u8 RequestFlags; /* 0x00 */ 542 u8 MSIxIndex; /* 0x01 */ 543 __le16 SMID; /* 0x02 */ 544 __le16 LMID; /* 0x04 */ 545 __le16 Reserved1; /* 0x06 */ 546 }; 547 548 /* SCSI IO Request Descriptor */ 549 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 550 u8 RequestFlags; /* 0x00 */ 551 u8 MSIxIndex; /* 0x01 */ 552 __le16 SMID; /* 0x02 */ 553 __le16 LMID; /* 0x04 */ 554 __le16 DevHandle; /* 0x06 */ 555 }; 556 557 /* SCSI Target Request Descriptor */ 558 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 559 u8 RequestFlags; /* 0x00 */ 560 u8 MSIxIndex; /* 0x01 */ 561 __le16 SMID; /* 0x02 */ 562 __le16 LMID; /* 0x04 */ 563 __le16 IoIndex; /* 0x06 */ 564 }; 565 566 /* RAID Accelerator Request Descriptor */ 567 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 568 u8 RequestFlags; /* 0x00 */ 569 u8 MSIxIndex; /* 0x01 */ 570 __le16 SMID; /* 0x02 */ 571 __le16 LMID; /* 0x04 */ 572 __le16 Reserved; /* 0x06 */ 573 }; 574 575 /* union of Request Descriptors */ 576 union MEGASAS_REQUEST_DESCRIPTOR_UNION { 577 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 578 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 579 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 580 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 581 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 582 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 583 union { 584 struct { 585 __le32 low; 586 __le32 high; 587 } u; 588 __le64 Words; 589 }; 590 }; 591 592 /* Default Reply Descriptor */ 593 struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 594 u8 ReplyFlags; /* 0x00 */ 595 u8 MSIxIndex; /* 0x01 */ 596 __le16 DescriptorTypeDependent1; /* 0x02 */ 597 __le32 DescriptorTypeDependent2; /* 0x04 */ 598 }; 599 600 /* Address Reply Descriptor */ 601 struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 602 u8 ReplyFlags; /* 0x00 */ 603 u8 MSIxIndex; /* 0x01 */ 604 __le16 SMID; /* 0x02 */ 605 __le32 ReplyFrameAddress; /* 0x04 */ 606 }; 607 608 /* SCSI IO Success Reply Descriptor */ 609 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 610 u8 ReplyFlags; /* 0x00 */ 611 u8 MSIxIndex; /* 0x01 */ 612 __le16 SMID; /* 0x02 */ 613 __le16 TaskTag; /* 0x04 */ 614 __le16 Reserved1; /* 0x06 */ 615 }; 616 617 /* TargetAssist Success Reply Descriptor */ 618 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 619 u8 ReplyFlags; /* 0x00 */ 620 u8 MSIxIndex; /* 0x01 */ 621 __le16 SMID; /* 0x02 */ 622 u8 SequenceNumber; /* 0x04 */ 623 u8 Reserved1; /* 0x05 */ 624 __le16 IoIndex; /* 0x06 */ 625 }; 626 627 /* Target Command Buffer Reply Descriptor */ 628 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 629 u8 ReplyFlags; /* 0x00 */ 630 u8 MSIxIndex; /* 0x01 */ 631 u8 VP_ID; /* 0x02 */ 632 u8 Flags; /* 0x03 */ 633 __le16 InitiatorDevHandle; /* 0x04 */ 634 __le16 IoIndex; /* 0x06 */ 635 }; 636 637 /* RAID Accelerator Success Reply Descriptor */ 638 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 639 u8 ReplyFlags; /* 0x00 */ 640 u8 MSIxIndex; /* 0x01 */ 641 __le16 SMID; /* 0x02 */ 642 __le32 Reserved; /* 0x04 */ 643 }; 644 645 /* union of Reply Descriptors */ 646 union MPI2_REPLY_DESCRIPTORS_UNION { 647 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 648 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 649 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 650 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 651 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 652 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 653 RAIDAcceleratorSuccess; 654 __le64 Words; 655 }; 656 657 /* IOCInit Request message */ 658 struct MPI2_IOC_INIT_REQUEST { 659 u8 WhoInit; /* 0x00 */ 660 u8 Reserved1; /* 0x01 */ 661 u8 ChainOffset; /* 0x02 */ 662 u8 Function; /* 0x03 */ 663 __le16 Reserved2; /* 0x04 */ 664 u8 Reserved3; /* 0x06 */ 665 u8 MsgFlags; /* 0x07 */ 666 u8 VP_ID; /* 0x08 */ 667 u8 VF_ID; /* 0x09 */ 668 __le16 Reserved4; /* 0x0A */ 669 __le16 MsgVersion; /* 0x0C */ 670 __le16 HeaderVersion; /* 0x0E */ 671 u32 Reserved5; /* 0x10 */ 672 __le16 Reserved6; /* 0x14 */ 673 u8 HostPageSize; /* 0x16 */ 674 u8 HostMSIxVectors; /* 0x17 */ 675 __le16 Reserved8; /* 0x18 */ 676 __le16 SystemRequestFrameSize; /* 0x1A */ 677 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 678 __le16 ReplyFreeQueueDepth; /* 0x1E */ 679 __le32 SenseBufferAddressHigh; /* 0x20 */ 680 __le32 SystemReplyAddressHigh; /* 0x24 */ 681 __le64 SystemRequestFrameBaseAddress; /* 0x28 */ 682 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 683 __le64 ReplyFreeQueueAddress; /* 0x38 */ 684 __le64 TimeStamp; /* 0x40 */ 685 }; 686 687 /* mrpriv defines */ 688 #define MR_PD_INVALID 0xFFFF 689 #define MR_DEVHANDLE_INVALID 0xFFFF 690 #define MAX_SPAN_DEPTH 8 691 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 692 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 693 #define MAX_ROW_SIZE 32 694 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 695 #define MAX_LOGICAL_DRIVES 64 696 #define MAX_LOGICAL_DRIVES_EXT 256 697 #define MAX_LOGICAL_DRIVES_DYN 512 698 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 699 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 700 #define MAX_ARRAYS 128 701 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 702 #define MAX_ARRAYS_EXT 256 703 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT) 704 #define MAX_API_ARRAYS_DYN 512 705 #define MAX_PHYSICAL_DEVICES 256 706 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 707 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 708 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 709 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 710 #define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103 711 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/ 712 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200 713 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200 714 #define MR_DCMD_CTRL_SNAPDUMP_GET_PROPERTIES 0x01200100 715 #define MR_DCMD_CTRL_DEVICE_LIST_GET 0x01190600 716 717 struct MR_DEV_HANDLE_INFO { 718 __le16 curDevHdl; 719 u8 validHandles; 720 u8 interfaceType; 721 __le16 devHandle[2]; 722 }; 723 724 struct MR_ARRAY_INFO { 725 __le16 pd[MAX_RAIDMAP_ROW_SIZE]; 726 }; 727 728 struct MR_QUAD_ELEMENT { 729 __le64 logStart; 730 __le64 logEnd; 731 __le64 offsetInSpan; 732 __le32 diff; 733 __le32 reserved1; 734 }; 735 736 struct MR_SPAN_INFO { 737 __le32 noElements; 738 __le32 reserved1; 739 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 740 }; 741 742 struct MR_LD_SPAN { 743 __le64 startBlk; 744 __le64 numBlks; 745 __le16 arrayRef; 746 u8 spanRowSize; 747 u8 spanRowDataSize; 748 u8 reserved[4]; 749 }; 750 751 struct MR_SPAN_BLOCK_INFO { 752 __le64 num_rows; 753 struct MR_LD_SPAN span; 754 struct MR_SPAN_INFO block_span_info; 755 }; 756 757 #define MR_RAID_CTX_CPUSEL_0 0 758 #define MR_RAID_CTX_CPUSEL_1 1 759 #define MR_RAID_CTX_CPUSEL_2 2 760 #define MR_RAID_CTX_CPUSEL_3 3 761 #define MR_RAID_CTX_CPUSEL_FCFS 0xF 762 763 struct MR_CPU_AFFINITY_MASK { 764 union { 765 struct { 766 #ifndef MFI_BIG_ENDIAN 767 u8 hw_path:1; 768 u8 cpu0:1; 769 u8 cpu1:1; 770 u8 cpu2:1; 771 u8 cpu3:1; 772 u8 reserved:3; 773 #else 774 u8 reserved:3; 775 u8 cpu3:1; 776 u8 cpu2:1; 777 u8 cpu1:1; 778 u8 cpu0:1; 779 u8 hw_path:1; 780 #endif 781 }; 782 u8 core_mask; 783 }; 784 }; 785 786 struct MR_IO_AFFINITY { 787 union { 788 struct { 789 struct MR_CPU_AFFINITY_MASK pdRead; 790 struct MR_CPU_AFFINITY_MASK pdWrite; 791 struct MR_CPU_AFFINITY_MASK ldRead; 792 struct MR_CPU_AFFINITY_MASK ldWrite; 793 }; 794 u32 word; 795 }; 796 u8 maxCores; /* Total cores + HW Path in ROC */ 797 u8 reserved[3]; 798 }; 799 800 struct MR_LD_RAID { 801 struct { 802 #if defined(__BIG_ENDIAN_BITFIELD) 803 u32 reserved4:2; 804 u32 fp_cache_bypass_capable:1; 805 u32 fp_rmw_capable:1; 806 u32 disable_coalescing:1; 807 u32 fpBypassRegionLock:1; 808 u32 tmCapable:1; 809 u32 fpNonRWCapable:1; 810 u32 fpReadAcrossStripe:1; 811 u32 fpWriteAcrossStripe:1; 812 u32 fpReadCapable:1; 813 u32 fpWriteCapable:1; 814 u32 encryptionType:8; 815 u32 pdPiMode:4; 816 u32 ldPiMode:4; 817 u32 reserved5:2; 818 u32 ra_capable:1; 819 u32 fpCapable:1; 820 #else 821 u32 fpCapable:1; 822 u32 ra_capable:1; 823 u32 reserved5:2; 824 u32 ldPiMode:4; 825 u32 pdPiMode:4; 826 u32 encryptionType:8; 827 u32 fpWriteCapable:1; 828 u32 fpReadCapable:1; 829 u32 fpWriteAcrossStripe:1; 830 u32 fpReadAcrossStripe:1; 831 u32 fpNonRWCapable:1; 832 u32 tmCapable:1; 833 u32 fpBypassRegionLock:1; 834 u32 disable_coalescing:1; 835 u32 fp_rmw_capable:1; 836 u32 fp_cache_bypass_capable:1; 837 u32 reserved4:2; 838 #endif 839 } capability; 840 __le32 reserved6; 841 __le64 size; 842 u8 spanDepth; 843 u8 level; 844 u8 stripeShift; 845 u8 rowSize; 846 u8 rowDataSize; 847 u8 writeMode; 848 u8 PRL; 849 u8 SRL; 850 __le16 targetId; 851 u8 ldState; 852 u8 regTypeReqOnWrite; 853 u8 modFactor; 854 u8 regTypeReqOnRead; 855 __le16 seqNum; 856 857 struct { 858 u32 ldSyncRequired:1; 859 u32 reserved:31; 860 } flags; 861 862 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */ 863 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/ 864 /* Ox2D This LD accept priority boost of this type */ 865 u8 ld_accept_priority_type; 866 u8 reserved2[2]; /* 0x2E - 0x2F */ 867 /* 0x30 - 0x33, Logical block size for the LD */ 868 u32 logical_block_length; 869 struct { 870 #ifndef MFI_BIG_ENDIAN 871 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */ 872 u32 ld_pi_exp:4; 873 /* 0x34, LOGICAL BLOCKS PER PHYSICAL 874 * BLOCK EXPONENT from READ CAPACITY 16 875 */ 876 u32 ld_logical_block_exp:4; 877 u32 reserved1:24; /* 0x34 */ 878 #else 879 u32 reserved1:24; /* 0x34 */ 880 /* 0x34, LOGICAL BLOCKS PER PHYSICAL 881 * BLOCK EXPONENT from READ CAPACITY 16 882 */ 883 u32 ld_logical_block_exp:4; 884 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */ 885 u32 ld_pi_exp:4; 886 #endif 887 }; /* 0x34 - 0x37 */ 888 /* 0x38 - 0x3f, This will determine which 889 * core will process LD IO and PD IO. 890 */ 891 struct MR_IO_AFFINITY cpuAffinity; 892 /* Bit definiations are specified by MR_IO_AFFINITY */ 893 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */ 894 }; 895 896 struct MR_LD_SPAN_MAP { 897 struct MR_LD_RAID ldRaid; 898 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 899 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 900 }; 901 902 struct MR_FW_RAID_MAP { 903 __le32 totalSize; 904 union { 905 struct { 906 __le32 maxLd; 907 __le32 maxSpanDepth; 908 __le32 maxRowSize; 909 __le32 maxPdCount; 910 __le32 maxArrays; 911 } validationInfo; 912 __le32 version[5]; 913 }; 914 915 __le32 ldCount; 916 __le32 Reserved1; 917 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 918 MAX_RAIDMAP_VIEWS]; 919 u8 fpPdIoTimeoutSec; 920 u8 reserved2[7]; 921 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 922 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 923 struct MR_LD_SPAN_MAP ldSpanMap[1]; 924 }; 925 926 struct IO_REQUEST_INFO { 927 u64 ldStartBlock; 928 u32 numBlocks; 929 u16 ldTgtId; 930 u8 isRead; 931 __le16 devHandle; 932 u8 pd_interface; 933 u64 pdBlock; 934 u8 fpOkForIo; 935 u8 IoforUnevenSpan; 936 u8 start_span; 937 u8 do_fp_rlbypass; 938 u64 start_row; 939 u8 span_arm; /* span[7:5], arm[4:0] */ 940 u8 pd_after_lb; 941 u16 r1_alt_dev_handle; /* raid 1/10 only */ 942 bool ra_capable; 943 }; 944 945 struct MR_LD_TARGET_SYNC { 946 u8 targetId; 947 u8 reserved; 948 __le16 seqNum; 949 }; 950 951 /* 952 * RAID Map descriptor Types. 953 * Each element should uniquely idetify one data structure in the RAID map 954 */ 955 enum MR_RAID_MAP_DESC_TYPE { 956 /* MR_DEV_HANDLE_INFO data */ 957 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0, 958 /* target to Ld num Index map */ 959 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1, 960 /* MR_ARRAY_INFO data */ 961 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2, 962 /* MR_LD_SPAN_MAP data */ 963 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3, 964 RAID_MAP_DESC_TYPE_COUNT, 965 }; 966 967 /* 968 * This table defines the offset, size and num elements of each descriptor 969 * type in the RAID Map buffer 970 */ 971 struct MR_RAID_MAP_DESC_TABLE { 972 /* Raid map descriptor type */ 973 u32 raid_map_desc_type; 974 /* Offset into the RAID map buffer where 975 * descriptor data is saved 976 */ 977 u32 raid_map_desc_offset; 978 /* total size of the 979 * descriptor buffer 980 */ 981 u32 raid_map_desc_buffer_size; 982 /* Number of elements contained in the 983 * descriptor buffer 984 */ 985 u32 raid_map_desc_elements; 986 }; 987 988 /* 989 * Dynamic Raid Map Structure. 990 */ 991 struct MR_FW_RAID_MAP_DYNAMIC { 992 u32 raid_map_size; /* total size of RAID Map structure */ 993 u32 desc_table_offset;/* Offset of desc table into RAID map*/ 994 u32 desc_table_size; /* Total Size of desc table */ 995 /* Total Number of elements in the desc table */ 996 u32 desc_table_num_elements; 997 u64 reserved1; 998 u32 reserved2[3]; /*future use */ 999 /* timeout value used by driver in FP IOs */ 1000 u8 fp_pd_io_timeout_sec; 1001 u8 reserved3[3]; 1002 /* when this seqNum increments, driver needs to 1003 * release RMW buffers asap 1004 */ 1005 u32 rmw_fp_seq_num; 1006 u16 ld_count; /* count of lds. */ 1007 u16 ar_count; /* count of arrays */ 1008 u16 span_count; /* count of spans */ 1009 u16 reserved4[3]; 1010 /* 1011 * The below structure of pointers is only to be used by the driver. 1012 * This is added in the ,API to reduce the amount of code changes 1013 * needed in the driver to support dynamic RAID map Firmware should 1014 * not update these pointers while preparing the raid map 1015 */ 1016 union { 1017 struct { 1018 struct MR_DEV_HANDLE_INFO *dev_hndl_info; 1019 u16 *ld_tgt_id_to_ld; 1020 struct MR_ARRAY_INFO *ar_map_info; 1021 struct MR_LD_SPAN_MAP *ld_span_map; 1022 }; 1023 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT]; 1024 }; 1025 /* 1026 * RAID Map descriptor table defines the layout of data in the RAID Map. 1027 * The size of the descriptor table itself could change. 1028 */ 1029 /* Variable Size descriptor Table. */ 1030 struct MR_RAID_MAP_DESC_TABLE 1031 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT]; 1032 /* Variable Size buffer containing all data */ 1033 u32 raid_map_desc_data[1]; 1034 }; /* Dynamicaly sized RAID MAp structure */ 1035 1036 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1037 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1038 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1039 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1040 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1041 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1042 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1043 1044 #define MPI2_SGE_FLAGS_SHIFT (0x02) 1045 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1046 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1047 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1048 1049 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1050 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1051 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1052 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1053 1054 #define MEGASAS_DEFAULT_SNAP_DUMP_WAIT_TIME 15 1055 #define MEGASAS_MAX_SNAP_DUMP_WAIT_TIME 60 1056 1057 struct megasas_register_set; 1058 struct megasas_instance; 1059 1060 union desc_word { 1061 u64 word; 1062 struct { 1063 u32 low; 1064 u32 high; 1065 } u; 1066 }; 1067 1068 struct megasas_cmd_fusion { 1069 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 1070 dma_addr_t io_request_phys_addr; 1071 1072 union MPI2_SGE_IO_UNION *sg_frame; 1073 dma_addr_t sg_frame_phys_addr; 1074 1075 u8 *sense; 1076 dma_addr_t sense_phys_addr; 1077 1078 struct list_head list; 1079 struct scsi_cmnd *scmd; 1080 struct megasas_instance *instance; 1081 1082 u8 retry_for_fw_reset; 1083 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1084 1085 /* 1086 * Context for a MFI frame. 1087 * Used to get the mfi cmd from list when a MFI cmd is completed 1088 */ 1089 u32 sync_cmd_idx; 1090 u32 index; 1091 u8 pd_r1_lb; 1092 struct completion done; 1093 u8 pd_interface; 1094 u16 r1_alt_dev_handle; /* raid 1/10 only*/ 1095 bool cmd_completed; /* raid 1/10 fp writes status holder */ 1096 1097 }; 1098 1099 struct LD_LOAD_BALANCE_INFO { 1100 u8 loadBalanceFlag; 1101 u8 reserved1; 1102 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 1103 u64 last_accessed_block[MAX_PHYSICAL_DEVICES]; 1104 }; 1105 1106 /* SPAN_SET is info caclulated from span info from Raid map per LD */ 1107 typedef struct _LD_SPAN_SET { 1108 u64 log_start_lba; 1109 u64 log_end_lba; 1110 u64 span_row_start; 1111 u64 span_row_end; 1112 u64 data_strip_start; 1113 u64 data_strip_end; 1114 u64 data_row_start; 1115 u64 data_row_end; 1116 u8 strip_offset[MAX_SPAN_DEPTH]; 1117 u32 span_row_data_width; 1118 u32 diff; 1119 u32 reserved[2]; 1120 } LD_SPAN_SET, *PLD_SPAN_SET; 1121 1122 typedef struct LOG_BLOCK_SPAN_INFO { 1123 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1124 } LD_SPAN_INFO, *PLD_SPAN_INFO; 1125 1126 struct MR_FW_RAID_MAP_ALL { 1127 struct MR_FW_RAID_MAP raidMap; 1128 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1129 } __attribute__ ((packed)); 1130 1131 struct MR_DRV_RAID_MAP { 1132 /* total size of this structure, including this field. 1133 * This feild will be manupulated by driver for ext raid map, 1134 * else pick the value from firmware raid map. 1135 */ 1136 __le32 totalSize; 1137 1138 union { 1139 struct { 1140 __le32 maxLd; 1141 __le32 maxSpanDepth; 1142 __le32 maxRowSize; 1143 __le32 maxPdCount; 1144 __le32 maxArrays; 1145 } validationInfo; 1146 __le32 version[5]; 1147 }; 1148 1149 /* timeout value used by driver in FP IOs*/ 1150 u8 fpPdIoTimeoutSec; 1151 u8 reserved2[7]; 1152 1153 __le16 ldCount; 1154 __le16 arCount; 1155 __le16 spanCount; 1156 __le16 reserve3; 1157 1158 struct MR_DEV_HANDLE_INFO 1159 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 1160 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 1161 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 1162 struct MR_LD_SPAN_MAP ldSpanMap[1]; 1163 1164 }; 1165 1166 /* Driver raid map size is same as raid map ext 1167 * MR_DRV_RAID_MAP_ALL is created to sync with old raid. 1168 * And it is mainly for code re-use purpose. 1169 */ 1170 struct MR_DRV_RAID_MAP_ALL { 1171 1172 struct MR_DRV_RAID_MAP raidMap; 1173 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 1174 } __packed; 1175 1176 1177 1178 struct MR_FW_RAID_MAP_EXT { 1179 /* Not usred in new map */ 1180 u32 reserved; 1181 1182 union { 1183 struct { 1184 u32 maxLd; 1185 u32 maxSpanDepth; 1186 u32 maxRowSize; 1187 u32 maxPdCount; 1188 u32 maxArrays; 1189 } validationInfo; 1190 u32 version[5]; 1191 }; 1192 1193 u8 fpPdIoTimeoutSec; 1194 u8 reserved2[7]; 1195 1196 __le16 ldCount; 1197 __le16 arCount; 1198 __le16 spanCount; 1199 __le16 reserve3; 1200 1201 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 1202 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 1203 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 1204 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 1205 }; 1206 1207 /* 1208 * * define MR_PD_CFG_SEQ structure for system PDs 1209 * */ 1210 struct MR_PD_CFG_SEQ { 1211 u16 seqNum; 1212 u16 devHandle; 1213 struct { 1214 #if defined(__BIG_ENDIAN_BITFIELD) 1215 u8 reserved:7; 1216 u8 tmCapable:1; 1217 #else 1218 u8 tmCapable:1; 1219 u8 reserved:7; 1220 #endif 1221 } capability; 1222 u8 reserved; 1223 u16 pd_target_id; 1224 } __packed; 1225 1226 struct MR_PD_CFG_SEQ_NUM_SYNC { 1227 __le32 size; 1228 __le32 count; 1229 struct MR_PD_CFG_SEQ seq[1]; 1230 } __packed; 1231 1232 /* stream detection */ 1233 struct STREAM_DETECT { 1234 u64 next_seq_lba; /* next LBA to match sequential access */ 1235 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */ 1236 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */ 1237 u32 count_cmds_in_stream; /* count of host commands in this stream */ 1238 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */ 1239 u8 is_read; /* SCSI OpCode for this stream */ 1240 u8 group_depth; /* total number of host commands in group */ 1241 /* TRUE if cannot add any more commands to this group */ 1242 bool group_flush; 1243 u8 reserved[7]; /* pad to 64-bit alignment */ 1244 }; 1245 1246 struct LD_STREAM_DETECT { 1247 bool write_back; /* TRUE if WB, FALSE if WT */ 1248 bool fp_write_enabled; 1249 bool members_ssds; 1250 bool fp_cache_bypass_capable; 1251 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */ 1252 /* this is the array of stream detect structures (one per stream) */ 1253 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED]; 1254 }; 1255 1256 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY { 1257 u64 RDPQBaseAddress; 1258 u32 Reserved1; 1259 u32 Reserved2; 1260 }; 1261 1262 struct rdpq_alloc_detail { 1263 struct dma_pool *dma_pool_ptr; 1264 dma_addr_t pool_entry_phys; 1265 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt; 1266 }; 1267 1268 struct fusion_context { 1269 struct megasas_cmd_fusion **cmd_list; 1270 dma_addr_t req_frames_desc_phys; 1271 u8 *req_frames_desc; 1272 1273 struct dma_pool *io_request_frames_pool; 1274 dma_addr_t io_request_frames_phys; 1275 u8 *io_request_frames; 1276 1277 struct dma_pool *sg_dma_pool; 1278 struct dma_pool *sense_dma_pool; 1279 1280 u8 *sense; 1281 dma_addr_t sense_phys_addr; 1282 1283 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION]; 1284 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION]; 1285 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT]; 1286 struct dma_pool *reply_frames_desc_pool; 1287 struct dma_pool *reply_frames_desc_pool_align; 1288 1289 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; 1290 1291 u32 reply_q_depth; 1292 u32 request_alloc_sz; 1293 u32 reply_alloc_sz; 1294 u32 io_frames_alloc_sz; 1295 1296 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt; 1297 dma_addr_t rdpq_phys; 1298 u16 max_sge_in_main_msg; 1299 u16 max_sge_in_chain; 1300 1301 u8 chain_offset_io_request; 1302 u8 chain_offset_mfi_pthru; 1303 1304 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2]; 1305 dma_addr_t ld_map_phys[2]; 1306 1307 /*Non dma-able memory. Driver local copy.*/ 1308 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 1309 1310 u32 max_map_sz; 1311 u32 current_map_sz; 1312 u32 old_map_sz; 1313 u32 new_map_sz; 1314 u32 drv_map_sz; 1315 u32 drv_map_pages; 1316 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT]; 1317 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT]; 1318 u8 fast_path_io; 1319 struct LD_LOAD_BALANCE_INFO *load_balance_info; 1320 u32 load_balance_info_pages; 1321 LD_SPAN_INFO *log_to_span; 1322 u32 log_to_span_pages; 1323 struct LD_STREAM_DETECT **stream_detect_by_ld; 1324 dma_addr_t ioc_init_request_phys; 1325 struct MPI2_IOC_INIT_REQUEST *ioc_init_request; 1326 struct megasas_cmd *ioc_init_cmd; 1327 1328 }; 1329 1330 union desc_value { 1331 __le64 word; 1332 struct { 1333 __le32 low; 1334 __le32 high; 1335 } u; 1336 }; 1337 1338 enum CMD_RET_VALUES { 1339 REFIRE_CMD = 1, 1340 COMPLETE_CMD = 2, 1341 RETURN_CMD = 3, 1342 }; 1343 1344 struct MR_SNAPDUMP_PROPERTIES { 1345 u8 offload_num; 1346 u8 max_num_supported; 1347 u8 cur_num_supported; 1348 u8 trigger_min_num_sec_before_ocr; 1349 u8 reserved[12]; 1350 }; 1351 1352 void megasas_free_cmds_fusion(struct megasas_instance *instance); 1353 int megasas_ioc_init_fusion(struct megasas_instance *instance); 1354 u8 megasas_get_map_info(struct megasas_instance *instance); 1355 int megasas_sync_map_info(struct megasas_instance *instance); 1356 void megasas_release_fusion(struct megasas_instance *instance); 1357 void megasas_reset_reply_desc(struct megasas_instance *instance); 1358 int megasas_check_mpio_paths(struct megasas_instance *instance, 1359 struct scsi_cmnd *scmd); 1360 void megasas_fusion_ocr_wq(struct work_struct *work); 1361 1362 #endif /* _MEGARAID_SAS_FUSION_H_ */ 1363