1 /* 2 * This file is part of the Chelsio FCoE driver for Linux. 3 * 4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CSIO_HW_H__ 36 #define __CSIO_HW_H__ 37 38 #include <linux/kernel.h> 39 #include <linux/pci.h> 40 #include <linux/device.h> 41 #include <linux/workqueue.h> 42 #include <linux/compiler.h> 43 #include <linux/cdev.h> 44 #include <linux/list.h> 45 #include <linux/mempool.h> 46 #include <linux/io.h> 47 #include <linux/spinlock_types.h> 48 #include <scsi/scsi_device.h> 49 #include <scsi/scsi_transport_fc.h> 50 51 #include "t4_hw.h" 52 #include "csio_hw_chip.h" 53 #include "csio_wr.h" 54 #include "csio_mb.h" 55 #include "csio_scsi.h" 56 #include "csio_defs.h" 57 #include "t4_regs.h" 58 #include "t4_msg.h" 59 60 /* 61 * An error value used by host. Should not clash with FW defined return values. 62 */ 63 #define FW_HOSTERROR 255 64 65 #define CSIO_HW_NAME "Chelsio FCoE Adapter" 66 #define CSIO_MAX_PFN 8 67 #define CSIO_MAX_PPORTS 4 68 69 #define CSIO_MAX_LUN 0xFFFF 70 #define CSIO_MAX_QUEUE 2048 71 #define CSIO_MAX_CMD_PER_LUN 32 72 #define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024) 73 #define CSIO_MAX_SECTOR_SIZE 128 74 75 /* Interrupts */ 76 #define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode 77 * (Forward intr iq + fw iq) */ 78 #define CSIO_EXTRA_VECS 2 /* non-data + FW evt */ 79 #define CSIO_MAX_SCSI_CPU 128 80 #define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS) 81 #define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS) 82 83 /* Queues */ 84 enum { 85 CSIO_INTR_WRSIZE = 128, 86 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE), 87 CSIO_FWEVT_WRSIZE = 128, 88 CSIO_FWEVT_IQLEN = 128, 89 CSIO_FWEVT_FLBUFS = 64, 90 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN), 91 CSIO_HW_NIQ = 1, 92 CSIO_HW_NFLQ = 1, 93 CSIO_HW_NEQ = 1, 94 CSIO_HW_NINTXQ = 1, 95 }; 96 97 struct csio_msix_entries { 98 void *dev_id; /* Priv object associated w/ this msix*/ 99 char desc[24]; /* Description of this vector */ 100 }; 101 102 struct csio_scsi_qset { 103 int iq_idx; /* Ingress index */ 104 int eq_idx; /* Egress index */ 105 uint32_t intr_idx; /* MSIX Vector index */ 106 }; 107 108 struct csio_scsi_cpu_info { 109 int16_t max_cpus; 110 }; 111 112 extern int csio_dbg_level; 113 extern unsigned int csio_port_mask; 114 extern int csio_msi; 115 116 #define CSIO_VENDOR_ID 0x1425 117 #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00 118 #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF 119 120 #define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \ 121 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \ 122 PM_TX_F | PM_RX_F | ULP_RX_F | \ 123 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F) 124 125 /* 126 * Hard parameters used to initialize the card in the absence of a 127 * configuration file. 128 */ 129 enum { 130 /* General */ 131 CSIO_SGE_DBFIFO_INT_THRESH = 10, 132 133 CSIO_SGE_RX_DMA_OFFSET = 2, 134 135 CSIO_SGE_FLBUF_SIZE1 = 65536, 136 CSIO_SGE_FLBUF_SIZE2 = 1536, 137 CSIO_SGE_FLBUF_SIZE3 = 9024, 138 CSIO_SGE_FLBUF_SIZE4 = 9216, 139 CSIO_SGE_FLBUF_SIZE5 = 2048, 140 CSIO_SGE_FLBUF_SIZE6 = 128, 141 CSIO_SGE_FLBUF_SIZE7 = 8192, 142 CSIO_SGE_FLBUF_SIZE8 = 16384, 143 144 CSIO_SGE_TIMER_VAL_0 = 5, 145 CSIO_SGE_TIMER_VAL_1 = 10, 146 CSIO_SGE_TIMER_VAL_2 = 20, 147 CSIO_SGE_TIMER_VAL_3 = 50, 148 CSIO_SGE_TIMER_VAL_4 = 100, 149 CSIO_SGE_TIMER_VAL_5 = 200, 150 151 CSIO_SGE_INT_CNT_VAL_0 = 1, 152 CSIO_SGE_INT_CNT_VAL_1 = 4, 153 CSIO_SGE_INT_CNT_VAL_2 = 8, 154 CSIO_SGE_INT_CNT_VAL_3 = 16, 155 }; 156 157 /* Slowpath events */ 158 enum csio_evt { 159 CSIO_EVT_FW = 0, /* FW event */ 160 CSIO_EVT_MBX, /* MBX event */ 161 CSIO_EVT_SCN, /* State change notification */ 162 CSIO_EVT_DEV_LOSS, /* Device loss event */ 163 CSIO_EVT_MAX, /* Max supported event */ 164 }; 165 166 #define CSIO_EVT_MSG_SIZE 512 167 #define CSIO_EVTQ_SIZE 512 168 169 /* Event msg */ 170 struct csio_evt_msg { 171 struct list_head list; /* evt queue*/ 172 enum csio_evt type; 173 uint8_t data[CSIO_EVT_MSG_SIZE]; 174 }; 175 176 enum { 177 SERNUM_LEN = 16, /* Serial # length */ 178 EC_LEN = 16, /* E/C length */ 179 ID_LEN = 16, /* ID length */ 180 }; 181 182 enum { 183 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */ 184 }; 185 186 /* serial flash and firmware constants */ 187 enum { 188 SF_ATTEMPTS = 10, /* max retries for SF operations */ 189 190 /* flash command opcodes */ 191 SF_PROG_PAGE = 2, /* program page */ 192 SF_WR_DISABLE = 4, /* disable writes */ 193 SF_RD_STATUS = 5, /* read status register */ 194 SF_WR_ENABLE = 6, /* enable writes */ 195 SF_RD_DATA_FAST = 0xb, /* read flash */ 196 SF_RD_ID = 0x9f, /* read ID */ 197 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 198 }; 199 200 /* Management module */ 201 enum { 202 CSIO_MGMT_EQ_WRSIZE = 512, 203 CSIO_MGMT_IQ_WRSIZE = 128, 204 CSIO_MGMT_EQLEN = 64, 205 CSIO_MGMT_IQLEN = 64, 206 }; 207 208 #define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE) 209 #define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE) 210 211 /* mgmt module stats */ 212 struct csio_mgmtm_stats { 213 uint32_t n_abort_req; /* Total abort request */ 214 uint32_t n_abort_rsp; /* Total abort response */ 215 uint32_t n_close_req; /* Total close request */ 216 uint32_t n_close_rsp; /* Total close response */ 217 uint32_t n_err; /* Total Errors */ 218 uint32_t n_drop; /* Total request dropped */ 219 uint32_t n_active; /* Count of active_q */ 220 uint32_t n_cbfn; /* Count of cbfn_q */ 221 }; 222 223 /* MGMT module */ 224 struct csio_mgmtm { 225 struct csio_hw *hw; /* Pointer to HW moduel */ 226 int eq_idx; /* Egress queue index */ 227 int iq_idx; /* Ingress queue index */ 228 int msi_vec; /* MSI vector */ 229 struct list_head active_q; /* Outstanding ELS/CT */ 230 struct list_head abort_q; /* Outstanding abort req */ 231 struct list_head cbfn_q; /* Completion queue */ 232 struct list_head mgmt_req_freelist; /* Free poll of reqs */ 233 /* ELSCT request freelist*/ 234 struct timer_list mgmt_timer; /* MGMT timer */ 235 struct csio_mgmtm_stats stats; /* ELS/CT stats */ 236 }; 237 238 struct csio_adap_desc { 239 char model_no[16]; 240 char description[32]; 241 }; 242 243 struct pci_params { 244 uint16_t vendor_id; 245 uint16_t device_id; 246 int vpd_cap_addr; 247 uint16_t speed; 248 uint8_t width; 249 }; 250 251 /* User configurable hw parameters */ 252 struct csio_hw_params { 253 uint32_t sf_size; /* serial flash 254 * size in bytes 255 */ 256 uint32_t sf_nsec; /* # of flash sectors */ 257 struct pci_params pci; 258 uint32_t log_level; /* Module-level for 259 * debug log. 260 */ 261 }; 262 263 struct csio_vpd { 264 uint32_t cclk; 265 uint8_t ec[EC_LEN + 1]; 266 uint8_t sn[SERNUM_LEN + 1]; 267 uint8_t id[ID_LEN + 1]; 268 }; 269 270 struct csio_pport { 271 uint16_t pcap; 272 uint8_t portid; 273 uint8_t link_status; 274 uint16_t link_speed; 275 uint8_t mac[6]; 276 uint8_t mod_type; 277 uint8_t rsvd1; 278 uint8_t rsvd2; 279 uint8_t rsvd3; 280 }; 281 282 /* fcoe resource information */ 283 struct csio_fcoe_res_info { 284 uint16_t e_d_tov; 285 uint16_t r_a_tov_seq; 286 uint16_t r_a_tov_els; 287 uint16_t r_r_tov; 288 uint32_t max_xchgs; 289 uint32_t max_ssns; 290 uint32_t used_xchgs; 291 uint32_t used_ssns; 292 uint32_t max_fcfs; 293 uint32_t max_vnps; 294 uint32_t used_fcfs; 295 uint32_t used_vnps; 296 }; 297 298 /* HW State machine Events */ 299 enum csio_hw_ev { 300 CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */ 301 CSIO_HWE_INIT, /* Config done, start Init */ 302 CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */ 303 CSIO_HWE_FATAL, /* Fatal error during initialization */ 304 CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */ 305 CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */ 306 CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */ 307 CSIO_HWE_QUIESCED, /* HBA quiesced */ 308 CSIO_HWE_HBA_RESET, /* HBA reset requested */ 309 CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */ 310 CSIO_HWE_FW_DLOAD, /* FW download requested */ 311 CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */ 312 CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */ 313 CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */ 314 CSIO_HWE_MAX, /* Max HW event */ 315 }; 316 317 /* hw stats */ 318 struct csio_hw_stats { 319 uint32_t n_evt_activeq; /* Number of event in active Q */ 320 uint32_t n_evt_freeq; /* Number of event in free Q */ 321 uint32_t n_evt_drop; /* Number of event droped */ 322 uint32_t n_evt_unexp; /* Number of unexpected events */ 323 uint32_t n_pcich_offline;/* Number of pci channel offline */ 324 uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */ 325 uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/ 326 uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/ 327 uint32_t n_cpl_unexp; /* Number of unexpected cpl */ 328 uint32_t n_mbint_unexp; /* Number of unexpected mbox */ 329 /* interrupt */ 330 uint32_t n_plint_unexp; /* Number of unexpected PL */ 331 /* interrupt */ 332 uint32_t n_plint_cnt; /* Number of PL interrupt */ 333 uint32_t n_int_stray; /* Number of stray interrupt */ 334 uint32_t n_err; /* Number of hw errors */ 335 uint32_t n_err_fatal; /* Number of fatal errors */ 336 uint32_t n_err_nomem; /* Number of memory alloc failure */ 337 uint32_t n_err_io; /* Number of IO failure */ 338 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */ 339 uint64_t n_reset_start; /* Start time after the reset */ 340 uint32_t rsvd1; 341 }; 342 343 /* Defines for hw->flags */ 344 #define CSIO_HWF_MASTER 0x00000001 /* This is the Master 345 * function for the 346 * card. 347 */ 348 #define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt 349 * enable bit set? 350 */ 351 #define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */ 352 #define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been 353 * allocated memory. 354 */ 355 #define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been 356 * allocated in FW. 357 */ 358 #define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */ 359 #define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device 360 * id cached */ 361 #define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing 362 * FW events 363 */ 364 #define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config 365 * params 366 */ 367 #define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts 368 * enabled? 369 */ 370 371 #define csio_is_hw_intr_enabled(__hw) \ 372 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED) 373 #define csio_is_host_intr_enabled(__hw) \ 374 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED) 375 #define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER) 376 #define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID) 377 #define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED) 378 #define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID) 379 #define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED) 380 381 /* Defines for intr_mode */ 382 enum csio_intr_mode { 383 CSIO_IM_NONE = 0, 384 CSIO_IM_INTX = 1, 385 CSIO_IM_MSI = 2, 386 CSIO_IM_MSIX = 3, 387 }; 388 389 /* Master HW structure: One per function */ 390 struct csio_hw { 391 struct csio_sm sm; /* State machine: should 392 * be the 1st member. 393 */ 394 spinlock_t lock; /* Lock for hw */ 395 396 struct csio_scsim scsim; /* SCSI module*/ 397 struct csio_wrm wrm; /* Work request module*/ 398 struct pci_dev *pdev; /* PCI device */ 399 400 void __iomem *regstart; /* Virtual address of 401 * register map 402 */ 403 /* SCSI queue sets */ 404 uint32_t num_sqsets; /* Number of SCSI 405 * queue sets */ 406 uint32_t num_scsi_msix_cpus; /* Number of CPUs that 407 * will be used 408 * for ingress 409 * processing. 410 */ 411 412 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU]; 413 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS]; 414 415 uint32_t evtflag; /* Event flag */ 416 uint32_t flags; /* HW flags */ 417 418 struct csio_mgmtm mgmtm; /* management module */ 419 struct csio_mbm mbm; /* Mailbox module */ 420 421 /* Lnodes */ 422 uint32_t num_lns; /* Number of lnodes */ 423 struct csio_lnode *rln; /* Root lnode */ 424 struct list_head sln_head; /* Sibling node list 425 * list 426 */ 427 int intr_iq_idx; /* Forward interrupt 428 * queue. 429 */ 430 int fwevt_iq_idx; /* FW evt queue */ 431 struct work_struct evtq_work; /* Worker thread for 432 * HW events. 433 */ 434 struct list_head evt_free_q; /* freelist of evt 435 * elements 436 */ 437 struct list_head evt_active_q; /* active evt queue*/ 438 439 /* board related info */ 440 char name[32]; 441 char hw_ver[16]; 442 char model_desc[32]; 443 char drv_version[32]; 444 char fwrev_str[32]; 445 uint32_t optrom_ver; 446 uint32_t fwrev; 447 uint32_t tp_vers; 448 char chip_ver; 449 uint16_t chip_id; /* Tells T4/T5 chip */ 450 enum csio_dev_state fw_state; 451 struct csio_vpd vpd; 452 453 uint8_t pfn; /* Physical Function 454 * number 455 */ 456 uint32_t port_vec; /* Port vector */ 457 uint8_t num_pports; /* Number of physical 458 * ports. 459 */ 460 uint8_t rst_retries; /* Reset retries */ 461 uint8_t cur_evt; /* current s/m evt */ 462 uint8_t prev_evt; /* Previous s/m evt */ 463 uint32_t dev_num; /* device number */ 464 struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */ 465 struct csio_hw_params params; /* Hw parameters */ 466 467 struct pci_pool *scsi_pci_pool; /* PCI pool for SCSI */ 468 mempool_t *mb_mempool; /* Mailbox memory pool*/ 469 mempool_t *rnode_mempool; /* rnode memory pool */ 470 471 /* Interrupt */ 472 enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */ 473 uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt 474 * index 475 */ 476 uint32_t nondata_intr_idx; /* nondata MSIX/intr 477 * idx 478 */ 479 480 uint8_t cfg_neq; /* FW configured no of 481 * egress queues 482 */ 483 uint8_t cfg_niq; /* FW configured no of 484 * iq queues. 485 */ 486 487 struct csio_fcoe_res_info fres_info; /* Fcoe resource info */ 488 struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific 489 * Operations 490 */ 491 492 /* MSIX vectors */ 493 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS]; 494 495 struct dentry *debugfs_root; /* Debug FS */ 496 struct csio_hw_stats stats; /* Hw statistics */ 497 }; 498 499 /* Register access macros */ 500 #define csio_reg(_b, _r) ((_b) + (_r)) 501 502 #define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r))) 503 #define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r))) 504 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r))) 505 #define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r))) 506 507 #define csio_wr_reg8(_h, _v, _r) writeb((_v), \ 508 csio_reg((_h)->regstart, (_r))) 509 #define csio_wr_reg16(_h, _v, _r) writew((_v), \ 510 csio_reg((_h)->regstart, (_r))) 511 #define csio_wr_reg32(_h, _v, _r) writel((_v), \ 512 csio_reg((_h)->regstart, (_r))) 513 #define csio_wr_reg64(_h, _v, _r) writeq((_v), \ 514 csio_reg((_h)->regstart, (_r))) 515 516 void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t); 517 518 /* Core clocks <==> uSecs */ 519 static inline uint32_t 520 csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks) 521 { 522 /* add Core Clock / 2 to round ticks to nearest uS */ 523 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk; 524 } 525 526 static inline uint32_t 527 csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us) 528 { 529 return (us * hw->vpd.cclk) / 1000; 530 } 531 532 /* Easy access macros */ 533 #define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm)) 534 #define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm)) 535 #define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim)) 536 #define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm)) 537 538 #define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number) 539 #define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn)) 540 #define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn)) 541 542 #define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i)) 543 #define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx) 544 #define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i)) 545 #define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx) 546 547 /* Printing/logging */ 548 #define CSIO_DEVID(__dev) ((__dev)->dev_num) 549 #define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF) 550 #define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF) 551 552 #define csio_info(__hw, __fmt, ...) \ 553 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) 554 555 #define csio_fatal(__hw, __fmt, ...) \ 556 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) 557 558 #define csio_err(__hw, __fmt, ...) \ 559 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) 560 561 #define csio_warn(__hw, __fmt, ...) \ 562 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__) 563 564 #ifdef __CSIO_DEBUG__ 565 #define csio_dbg(__hw, __fmt, ...) \ 566 csio_info((__hw), __fmt, ##__VA_ARGS__); 567 #else 568 #define csio_dbg(__hw, __fmt, ...) 569 #endif 570 571 int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int, 572 int, int, uint32_t *); 573 void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int, 574 unsigned int, unsigned int); 575 int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *); 576 void csio_hw_intr_disable(struct csio_hw *); 577 int csio_hw_slow_intr_handler(struct csio_hw *); 578 int csio_handle_intr_status(struct csio_hw *, unsigned int, 579 const struct intr_info *); 580 581 int csio_hw_start(struct csio_hw *); 582 int csio_hw_stop(struct csio_hw *); 583 int csio_hw_reset(struct csio_hw *); 584 int csio_is_hw_ready(struct csio_hw *); 585 int csio_is_hw_removing(struct csio_hw *); 586 587 int csio_fwevtq_handler(struct csio_hw *); 588 void csio_evtq_worker(struct work_struct *); 589 int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t); 590 void csio_evtq_flush(struct csio_hw *hw); 591 592 int csio_request_irqs(struct csio_hw *); 593 void csio_intr_enable(struct csio_hw *); 594 void csio_intr_disable(struct csio_hw *, bool); 595 void csio_hw_fatal_err(struct csio_hw *); 596 597 struct csio_lnode *csio_lnode_alloc(struct csio_hw *); 598 int csio_config_queues(struct csio_hw *); 599 600 int csio_hw_init(struct csio_hw *); 601 void csio_hw_exit(struct csio_hw *); 602 #endif /* ifndef __CSIO_HW_H__ */ 603