1 /* 2 * This file is part of the Chelsio FCoE driver for Linux. 3 * 4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/pci.h> 36 #include <linux/pci_regs.h> 37 #include <linux/firmware.h> 38 #include <linux/stddef.h> 39 #include <linux/delay.h> 40 #include <linux/string.h> 41 #include <linux/compiler.h> 42 #include <linux/jiffies.h> 43 #include <linux/kernel.h> 44 #include <linux/log2.h> 45 46 #include "csio_hw.h" 47 #include "csio_lnode.h" 48 #include "csio_rnode.h" 49 50 int csio_force_master; 51 int csio_dbg_level = 0xFEFF; 52 unsigned int csio_port_mask = 0xf; 53 54 /* Default FW event queue entries. */ 55 static uint32_t csio_evtq_sz = CSIO_EVTQ_SIZE; 56 57 /* Default MSI param level */ 58 int csio_msi = 2; 59 60 /* FCoE function instances */ 61 static int dev_num; 62 63 /* FCoE Adapter types & its description */ 64 static const struct csio_adap_desc csio_fcoe_adapters[] = { 65 {"T440-Dbg 10G", "Chelsio T440-Dbg 10G [FCoE]"}, 66 {"T420-CR 10G", "Chelsio T420-CR 10G [FCoE]"}, 67 {"T422-CR 10G/1G", "Chelsio T422-CR 10G/1G [FCoE]"}, 68 {"T440-CR 10G", "Chelsio T440-CR 10G [FCoE]"}, 69 {"T420-BCH 10G", "Chelsio T420-BCH 10G [FCoE]"}, 70 {"T440-BCH 10G", "Chelsio T440-BCH 10G [FCoE]"}, 71 {"T440-CH 10G", "Chelsio T440-CH 10G [FCoE]"}, 72 {"T420-SO 10G", "Chelsio T420-SO 10G [FCoE]"}, 73 {"T420-CX4 10G", "Chelsio T420-CX4 10G [FCoE]"}, 74 {"T420-BT 10G", "Chelsio T420-BT 10G [FCoE]"}, 75 {"T404-BT 1G", "Chelsio T404-BT 1G [FCoE]"}, 76 {"B420-SR 10G", "Chelsio B420-SR 10G [FCoE]"}, 77 {"B404-BT 1G", "Chelsio B404-BT 1G [FCoE]"}, 78 {"T480-CR 10G", "Chelsio T480-CR 10G [FCoE]"}, 79 {"T440-LP-CR 10G", "Chelsio T440-LP-CR 10G [FCoE]"}, 80 {"T4 FPGA", "Chelsio T4 FPGA [FCoE]"} 81 }; 82 83 static void csio_mgmtm_cleanup(struct csio_mgmtm *); 84 static void csio_hw_mbm_cleanup(struct csio_hw *); 85 86 /* State machine forward declarations */ 87 static void csio_hws_uninit(struct csio_hw *, enum csio_hw_ev); 88 static void csio_hws_configuring(struct csio_hw *, enum csio_hw_ev); 89 static void csio_hws_initializing(struct csio_hw *, enum csio_hw_ev); 90 static void csio_hws_ready(struct csio_hw *, enum csio_hw_ev); 91 static void csio_hws_quiescing(struct csio_hw *, enum csio_hw_ev); 92 static void csio_hws_quiesced(struct csio_hw *, enum csio_hw_ev); 93 static void csio_hws_resetting(struct csio_hw *, enum csio_hw_ev); 94 static void csio_hws_removing(struct csio_hw *, enum csio_hw_ev); 95 static void csio_hws_pcierr(struct csio_hw *, enum csio_hw_ev); 96 97 static void csio_hw_initialize(struct csio_hw *hw); 98 static void csio_evtq_stop(struct csio_hw *hw); 99 static void csio_evtq_start(struct csio_hw *hw); 100 101 int csio_is_hw_ready(struct csio_hw *hw) 102 { 103 return csio_match_state(hw, csio_hws_ready); 104 } 105 106 int csio_is_hw_removing(struct csio_hw *hw) 107 { 108 return csio_match_state(hw, csio_hws_removing); 109 } 110 111 112 /* 113 * csio_hw_wait_op_done_val - wait until an operation is completed 114 * @hw: the HW module 115 * @reg: the register to check for completion 116 * @mask: a single-bit field within @reg that indicates completion 117 * @polarity: the value of the field when the operation is completed 118 * @attempts: number of check iterations 119 * @delay: delay in usecs between iterations 120 * @valp: where to store the value of the register at completion time 121 * 122 * Wait until an operation is completed by checking a bit in a register 123 * up to @attempts times. If @valp is not NULL the value of the register 124 * at the time it indicated completion is stored there. Returns 0 if the 125 * operation completes and -EAGAIN otherwise. 126 */ 127 static int 128 csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, 129 int polarity, int attempts, int delay, uint32_t *valp) 130 { 131 uint32_t val; 132 while (1) { 133 val = csio_rd_reg32(hw, reg); 134 135 if (!!(val & mask) == polarity) { 136 if (valp) 137 *valp = val; 138 return 0; 139 } 140 141 if (--attempts == 0) 142 return -EAGAIN; 143 if (delay) 144 udelay(delay); 145 } 146 } 147 148 void 149 csio_set_reg_field(struct csio_hw *hw, uint32_t reg, uint32_t mask, 150 uint32_t value) 151 { 152 uint32_t val = csio_rd_reg32(hw, reg) & ~mask; 153 154 csio_wr_reg32(hw, val | value, reg); 155 /* Flush */ 156 csio_rd_reg32(hw, reg); 157 158 } 159 160 /* 161 * csio_hw_mc_read - read from MC through backdoor accesses 162 * @hw: the hw module 163 * @addr: address of first byte requested 164 * @data: 64 bytes of data containing the requested address 165 * @ecc: where to store the corresponding 64-bit ECC word 166 * 167 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 168 * that covers the requested address @addr. If @parity is not %NULL it 169 * is assigned the 64-bit ECC word for the read data. 170 */ 171 int 172 csio_hw_mc_read(struct csio_hw *hw, uint32_t addr, __be32 *data, 173 uint64_t *ecc) 174 { 175 int i; 176 177 if (csio_rd_reg32(hw, MC_BIST_CMD) & START_BIST) 178 return -EBUSY; 179 csio_wr_reg32(hw, addr & ~0x3fU, MC_BIST_CMD_ADDR); 180 csio_wr_reg32(hw, 64, MC_BIST_CMD_LEN); 181 csio_wr_reg32(hw, 0xc, MC_BIST_DATA_PATTERN); 182 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1), 183 MC_BIST_CMD); 184 i = csio_hw_wait_op_done_val(hw, MC_BIST_CMD, START_BIST, 185 0, 10, 1, NULL); 186 if (i) 187 return i; 188 189 #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) 190 191 for (i = 15; i >= 0; i--) 192 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); 193 if (ecc) 194 *ecc = csio_rd_reg64(hw, MC_DATA(16)); 195 #undef MC_DATA 196 return 0; 197 } 198 199 /* 200 * csio_hw_edc_read - read from EDC through backdoor accesses 201 * @hw: the hw module 202 * @idx: which EDC to access 203 * @addr: address of first byte requested 204 * @data: 64 bytes of data containing the requested address 205 * @ecc: where to store the corresponding 64-bit ECC word 206 * 207 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 208 * that covers the requested address @addr. If @parity is not %NULL it 209 * is assigned the 64-bit ECC word for the read data. 210 */ 211 int 212 csio_hw_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 213 uint64_t *ecc) 214 { 215 int i; 216 217 idx *= EDC_STRIDE; 218 if (csio_rd_reg32(hw, EDC_BIST_CMD + idx) & START_BIST) 219 return -EBUSY; 220 csio_wr_reg32(hw, addr & ~0x3fU, EDC_BIST_CMD_ADDR + idx); 221 csio_wr_reg32(hw, 64, EDC_BIST_CMD_LEN + idx); 222 csio_wr_reg32(hw, 0xc, EDC_BIST_DATA_PATTERN + idx); 223 csio_wr_reg32(hw, BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST, 224 EDC_BIST_CMD + idx); 225 i = csio_hw_wait_op_done_val(hw, EDC_BIST_CMD + idx, START_BIST, 226 0, 10, 1, NULL); 227 if (i) 228 return i; 229 230 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) 231 232 for (i = 15; i >= 0; i--) 233 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); 234 if (ecc) 235 *ecc = csio_rd_reg64(hw, EDC_DATA(16)); 236 #undef EDC_DATA 237 return 0; 238 } 239 240 /* 241 * csio_mem_win_rw - read/write memory through PCIE memory window 242 * @hw: the adapter 243 * @addr: address of first byte requested 244 * @data: MEMWIN0_APERTURE bytes of data containing the requested address 245 * @dir: direction of transfer 1 => read, 0 => write 246 * 247 * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a 248 * MEMWIN0_APERTURE-byte-aligned address that covers the requested 249 * address @addr. 250 */ 251 static int 252 csio_mem_win_rw(struct csio_hw *hw, u32 addr, u32 *data, int dir) 253 { 254 int i; 255 256 /* 257 * Setup offset into PCIE memory window. Address must be a 258 * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to 259 * ensure that changes propagate before we attempt to use the new 260 * values.) 261 */ 262 csio_wr_reg32(hw, addr & ~(MEMWIN0_APERTURE - 1), 263 PCIE_MEM_ACCESS_OFFSET); 264 csio_rd_reg32(hw, PCIE_MEM_ACCESS_OFFSET); 265 266 /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */ 267 for (i = 0; i < MEMWIN0_APERTURE; i = i + sizeof(__be32)) { 268 if (dir) 269 *data++ = csio_rd_reg32(hw, (MEMWIN0_BASE + i)); 270 else 271 csio_wr_reg32(hw, *data++, (MEMWIN0_BASE + i)); 272 } 273 274 return 0; 275 } 276 277 /* 278 * csio_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 279 * @hw: the csio_hw 280 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 281 * @addr: address within indicated memory type 282 * @len: amount of memory to transfer 283 * @buf: host memory buffer 284 * @dir: direction of transfer 1 => read, 0 => write 285 * 286 * Reads/writes an [almost] arbitrary memory region in the firmware: the 287 * firmware memory address, length and host buffer must be aligned on 288 * 32-bit boudaries. The memory is transferred as a raw byte sequence 289 * from/to the firmware's memory. If this memory contains data 290 * structures which contain multi-byte integers, it's the callers 291 * responsibility to perform appropriate byte order conversions. 292 */ 293 static int 294 csio_memory_rw(struct csio_hw *hw, int mtype, u32 addr, u32 len, 295 uint32_t *buf, int dir) 296 { 297 uint32_t pos, start, end, offset, memoffset; 298 int ret; 299 uint32_t *data; 300 301 /* 302 * Argument sanity checks ... 303 */ 304 if ((addr & 0x3) || (len & 0x3)) 305 return -EINVAL; 306 307 data = kzalloc(MEMWIN0_APERTURE, GFP_KERNEL); 308 if (!data) 309 return -ENOMEM; 310 311 /* Offset into the region of memory which is being accessed 312 * MEM_EDC0 = 0 313 * MEM_EDC1 = 1 314 * MEM_MC = 2 315 */ 316 memoffset = (mtype * (5 * 1024 * 1024)); 317 318 /* Determine the PCIE_MEM_ACCESS_OFFSET */ 319 addr = addr + memoffset; 320 321 /* 322 * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes 323 * at a time so we need to round down the start and round up the end. 324 * We'll start copying out of the first line at (addr - start) a word 325 * at a time. 326 */ 327 start = addr & ~(MEMWIN0_APERTURE-1); 328 end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1); 329 offset = (addr - start)/sizeof(__be32); 330 331 for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) { 332 /* 333 * If we're writing, copy the data from the caller's memory 334 * buffer 335 */ 336 if (!dir) { 337 /* 338 * If we're doing a partial write, then we need to do 339 * a read-modify-write ... 340 */ 341 if (offset || len < MEMWIN0_APERTURE) { 342 ret = csio_mem_win_rw(hw, pos, data, 1); 343 if (ret) { 344 kfree(data); 345 return ret; 346 } 347 } 348 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) && 349 len > 0) { 350 data[offset++] = *buf++; 351 len -= sizeof(__be32); 352 } 353 } 354 355 /* 356 * Transfer a block of memory and bail if there's an error. 357 */ 358 ret = csio_mem_win_rw(hw, pos, data, dir); 359 if (ret) { 360 kfree(data); 361 return ret; 362 } 363 364 /* 365 * If we're reading, copy the data into the caller's memory 366 * buffer. 367 */ 368 if (dir) 369 while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) && 370 len > 0) { 371 *buf++ = data[offset++]; 372 len -= sizeof(__be32); 373 } 374 } 375 376 kfree(data); 377 378 return 0; 379 } 380 381 static int 382 csio_memory_write(struct csio_hw *hw, int mtype, u32 addr, u32 len, u32 *buf) 383 { 384 return csio_memory_rw(hw, mtype, addr, len, buf, 0); 385 } 386 387 /* 388 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 389 */ 390 #define EEPROM_MAX_RD_POLL 40 391 #define EEPROM_MAX_WR_POLL 6 392 #define EEPROM_STAT_ADDR 0x7bfc 393 #define VPD_BASE 0x400 394 #define VPD_BASE_OLD 0 395 #define VPD_LEN 512 396 #define VPD_INFO_FLD_HDR_SIZE 3 397 398 /* 399 * csio_hw_seeprom_read - read a serial EEPROM location 400 * @hw: hw to read 401 * @addr: EEPROM virtual address 402 * @data: where to store the read data 403 * 404 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 405 * VPD capability. Note that this function must be called with a virtual 406 * address. 407 */ 408 static int 409 csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data) 410 { 411 uint16_t val = 0; 412 int attempts = EEPROM_MAX_RD_POLL; 413 uint32_t base = hw->params.pci.vpd_cap_addr; 414 415 if (addr >= EEPROMVSIZE || (addr & 3)) 416 return -EINVAL; 417 418 pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr); 419 420 do { 421 udelay(10); 422 pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val); 423 } while (!(val & PCI_VPD_ADDR_F) && --attempts); 424 425 if (!(val & PCI_VPD_ADDR_F)) { 426 csio_err(hw, "reading EEPROM address 0x%x failed\n", addr); 427 return -EINVAL; 428 } 429 430 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); 431 *data = le32_to_cpu(*data); 432 433 return 0; 434 } 435 436 /* 437 * Partial EEPROM Vital Product Data structure. Includes only the ID and 438 * VPD-R sections. 439 */ 440 struct t4_vpd_hdr { 441 u8 id_tag; 442 u8 id_len[2]; 443 u8 id_data[ID_LEN]; 444 u8 vpdr_tag; 445 u8 vpdr_len[2]; 446 }; 447 448 /* 449 * csio_hw_get_vpd_keyword_val - Locates an information field keyword in 450 * the VPD 451 * @v: Pointer to buffered vpd data structure 452 * @kw: The keyword to search for 453 * 454 * Returns the value of the information field keyword or 455 * -EINVAL otherwise. 456 */ 457 static int 458 csio_hw_get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) 459 { 460 int32_t i; 461 int32_t offset , len; 462 const uint8_t *buf = &v->id_tag; 463 const uint8_t *vpdr_len = &v->vpdr_tag; 464 offset = sizeof(struct t4_vpd_hdr); 465 len = (uint16_t)vpdr_len[1] + ((uint16_t)vpdr_len[2] << 8); 466 467 if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) 468 return -EINVAL; 469 470 for (i = offset; (i + VPD_INFO_FLD_HDR_SIZE) <= (offset + len);) { 471 if (memcmp(buf + i , kw, 2) == 0) { 472 i += VPD_INFO_FLD_HDR_SIZE; 473 return i; 474 } 475 476 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; 477 } 478 479 return -EINVAL; 480 } 481 482 static int 483 csio_pci_capability(struct pci_dev *pdev, int cap, int *pos) 484 { 485 *pos = pci_find_capability(pdev, cap); 486 if (*pos) 487 return 0; 488 489 return -1; 490 } 491 492 /* 493 * csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM 494 * @hw: HW module 495 * @p: where to store the parameters 496 * 497 * Reads card parameters stored in VPD EEPROM. 498 */ 499 static int 500 csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p) 501 { 502 int i, ret, ec, sn, addr; 503 uint8_t *vpd, csum; 504 const struct t4_vpd_hdr *v; 505 /* To get around compilation warning from strstrip */ 506 char *s; 507 508 if (csio_is_valid_vpd(hw)) 509 return 0; 510 511 ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD, 512 &hw->params.pci.vpd_cap_addr); 513 if (ret) 514 return -EINVAL; 515 516 vpd = kzalloc(VPD_LEN, GFP_ATOMIC); 517 if (vpd == NULL) 518 return -ENOMEM; 519 520 /* 521 * Card information normally starts at VPD_BASE but early cards had 522 * it at 0. 523 */ 524 ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd)); 525 addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD; 526 527 for (i = 0; i < VPD_LEN; i += 4) { 528 ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i)); 529 if (ret) { 530 kfree(vpd); 531 return ret; 532 } 533 } 534 535 /* Reset the VPD flag! */ 536 hw->flags &= (~CSIO_HWF_VPD_VALID); 537 538 v = (const struct t4_vpd_hdr *)vpd; 539 540 #define FIND_VPD_KW(var, name) do { \ 541 var = csio_hw_get_vpd_keyword_val(v, name); \ 542 if (var < 0) { \ 543 csio_err(hw, "missing VPD keyword " name "\n"); \ 544 kfree(vpd); \ 545 return -EINVAL; \ 546 } \ 547 } while (0) 548 549 FIND_VPD_KW(i, "RV"); 550 for (csum = 0; i >= 0; i--) 551 csum += vpd[i]; 552 553 if (csum) { 554 csio_err(hw, "corrupted VPD EEPROM, actual csum %u\n", csum); 555 kfree(vpd); 556 return -EINVAL; 557 } 558 FIND_VPD_KW(ec, "EC"); 559 FIND_VPD_KW(sn, "SN"); 560 #undef FIND_VPD_KW 561 562 memcpy(p->id, v->id_data, ID_LEN); 563 s = strstrip(p->id); 564 memcpy(p->ec, vpd + ec, EC_LEN); 565 s = strstrip(p->ec); 566 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 567 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 568 s = strstrip(p->sn); 569 570 csio_valid_vpd_copied(hw); 571 572 kfree(vpd); 573 return 0; 574 } 575 576 /* 577 * csio_hw_sf1_read - read data from the serial flash 578 * @hw: the HW module 579 * @byte_cnt: number of bytes to read 580 * @cont: whether another operation will be chained 581 * @lock: whether to lock SF for PL access only 582 * @valp: where to store the read data 583 * 584 * Reads up to 4 bytes of data from the serial flash. The location of 585 * the read needs to be specified prior to calling this by issuing the 586 * appropriate commands to the serial flash. 587 */ 588 static int 589 csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont, 590 int32_t lock, uint32_t *valp) 591 { 592 int ret; 593 594 if (!byte_cnt || byte_cnt > 4) 595 return -EINVAL; 596 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 597 return -EBUSY; 598 599 cont = cont ? SF_CONT : 0; 600 lock = lock ? SF_LOCK : 0; 601 602 csio_wr_reg32(hw, lock | cont | BYTECNT(byte_cnt - 1), SF_OP); 603 ret = csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 604 10, NULL); 605 if (!ret) 606 *valp = csio_rd_reg32(hw, SF_DATA); 607 return ret; 608 } 609 610 /* 611 * csio_hw_sf1_write - write data to the serial flash 612 * @hw: the HW module 613 * @byte_cnt: number of bytes to write 614 * @cont: whether another operation will be chained 615 * @lock: whether to lock SF for PL access only 616 * @val: value to write 617 * 618 * Writes up to 4 bytes of data to the serial flash. The location of 619 * the write needs to be specified prior to calling this by issuing the 620 * appropriate commands to the serial flash. 621 */ 622 static int 623 csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont, 624 int32_t lock, uint32_t val) 625 { 626 if (!byte_cnt || byte_cnt > 4) 627 return -EINVAL; 628 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 629 return -EBUSY; 630 631 cont = cont ? SF_CONT : 0; 632 lock = lock ? SF_LOCK : 0; 633 634 csio_wr_reg32(hw, val, SF_DATA); 635 csio_wr_reg32(hw, cont | BYTECNT(byte_cnt - 1) | OP_WR | lock, SF_OP); 636 637 return csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 638 10, NULL); 639 } 640 641 /* 642 * csio_hw_flash_wait_op - wait for a flash operation to complete 643 * @hw: the HW module 644 * @attempts: max number of polls of the status register 645 * @delay: delay between polls in ms 646 * 647 * Wait for a flash operation to complete by polling the status register. 648 */ 649 static int 650 csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay) 651 { 652 int ret; 653 uint32_t status; 654 655 while (1) { 656 ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS); 657 if (ret != 0) 658 return ret; 659 660 ret = csio_hw_sf1_read(hw, 1, 0, 1, &status); 661 if (ret != 0) 662 return ret; 663 664 if (!(status & 1)) 665 return 0; 666 if (--attempts == 0) 667 return -EAGAIN; 668 if (delay) 669 msleep(delay); 670 } 671 } 672 673 /* 674 * csio_hw_read_flash - read words from serial flash 675 * @hw: the HW module 676 * @addr: the start address for the read 677 * @nwords: how many 32-bit words to read 678 * @data: where to store the read data 679 * @byte_oriented: whether to store data as bytes or as words 680 * 681 * Read the specified number of 32-bit words from the serial flash. 682 * If @byte_oriented is set the read data is stored as a byte array 683 * (i.e., big-endian), otherwise as 32-bit words in the platform's 684 * natural endianess. 685 */ 686 static int 687 csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords, 688 uint32_t *data, int32_t byte_oriented) 689 { 690 int ret; 691 692 if (addr + nwords * sizeof(uint32_t) > hw->params.sf_size || (addr & 3)) 693 return -EINVAL; 694 695 addr = swab32(addr) | SF_RD_DATA_FAST; 696 697 ret = csio_hw_sf1_write(hw, 4, 1, 0, addr); 698 if (ret != 0) 699 return ret; 700 701 ret = csio_hw_sf1_read(hw, 1, 1, 0, data); 702 if (ret != 0) 703 return ret; 704 705 for ( ; nwords; nwords--, data++) { 706 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); 707 if (nwords == 1) 708 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 709 if (ret) 710 return ret; 711 if (byte_oriented) 712 *data = htonl(*data); 713 } 714 return 0; 715 } 716 717 /* 718 * csio_hw_write_flash - write up to a page of data to the serial flash 719 * @hw: the hw 720 * @addr: the start address to write 721 * @n: length of data to write in bytes 722 * @data: the data to write 723 * 724 * Writes up to a page of data (256 bytes) to the serial flash starting 725 * at the given address. All the data must be written to the same page. 726 */ 727 static int 728 csio_hw_write_flash(struct csio_hw *hw, uint32_t addr, 729 uint32_t n, const uint8_t *data) 730 { 731 int ret = -EINVAL; 732 uint32_t buf[64]; 733 uint32_t i, c, left, val, offset = addr & 0xff; 734 735 if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE) 736 return -EINVAL; 737 738 val = swab32(addr) | SF_PROG_PAGE; 739 740 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); 741 if (ret != 0) 742 goto unlock; 743 744 ret = csio_hw_sf1_write(hw, 4, 1, 1, val); 745 if (ret != 0) 746 goto unlock; 747 748 for (left = n; left; left -= c) { 749 c = min(left, 4U); 750 for (val = 0, i = 0; i < c; ++i) 751 val = (val << 8) + *data++; 752 753 ret = csio_hw_sf1_write(hw, c, c != left, 1, val); 754 if (ret) 755 goto unlock; 756 } 757 ret = csio_hw_flash_wait_op(hw, 8, 1); 758 if (ret) 759 goto unlock; 760 761 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 762 763 /* Read the page to verify the write succeeded */ 764 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 765 if (ret) 766 return ret; 767 768 if (memcmp(data - n, (uint8_t *)buf + offset, n)) { 769 csio_err(hw, 770 "failed to correctly write the flash page at %#x\n", 771 addr); 772 return -EINVAL; 773 } 774 775 return 0; 776 777 unlock: 778 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 779 return ret; 780 } 781 782 /* 783 * csio_hw_flash_erase_sectors - erase a range of flash sectors 784 * @hw: the HW module 785 * @start: the first sector to erase 786 * @end: the last sector to erase 787 * 788 * Erases the sectors in the given inclusive range. 789 */ 790 static int 791 csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end) 792 { 793 int ret = 0; 794 795 while (start <= end) { 796 797 ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); 798 if (ret != 0) 799 goto out; 800 801 ret = csio_hw_sf1_write(hw, 4, 0, 1, 802 SF_ERASE_SECTOR | (start << 8)); 803 if (ret != 0) 804 goto out; 805 806 ret = csio_hw_flash_wait_op(hw, 14, 500); 807 if (ret != 0) 808 goto out; 809 810 start++; 811 } 812 out: 813 if (ret) 814 csio_err(hw, "erase of flash sector %d failed, error %d\n", 815 start, ret); 816 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 817 return 0; 818 } 819 820 /* 821 * csio_hw_flash_cfg_addr - return the address of the flash 822 * configuration file 823 * @hw: the HW module 824 * 825 * Return the address within the flash where the Firmware Configuration 826 * File is stored. 827 */ 828 static unsigned int 829 csio_hw_flash_cfg_addr(struct csio_hw *hw) 830 { 831 if (hw->params.sf_size == 0x100000) 832 return FPGA_FLASH_CFG_OFFSET; 833 else 834 return FLASH_CFG_OFFSET; 835 } 836 837 static void 838 csio_hw_print_fw_version(struct csio_hw *hw, char *str) 839 { 840 csio_info(hw, "%s: %u.%u.%u.%u\n", str, 841 FW_HDR_FW_VER_MAJOR_GET(hw->fwrev), 842 FW_HDR_FW_VER_MINOR_GET(hw->fwrev), 843 FW_HDR_FW_VER_MICRO_GET(hw->fwrev), 844 FW_HDR_FW_VER_BUILD_GET(hw->fwrev)); 845 } 846 847 /* 848 * csio_hw_get_fw_version - read the firmware version 849 * @hw: HW module 850 * @vers: where to place the version 851 * 852 * Reads the FW version from flash. 853 */ 854 static int 855 csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers) 856 { 857 return csio_hw_read_flash(hw, FW_IMG_START + 858 offsetof(struct fw_hdr, fw_ver), 1, 859 vers, 0); 860 } 861 862 /* 863 * csio_hw_get_tp_version - read the TP microcode version 864 * @hw: HW module 865 * @vers: where to place the version 866 * 867 * Reads the TP microcode version from flash. 868 */ 869 static int 870 csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers) 871 { 872 return csio_hw_read_flash(hw, FLASH_FW_START + 873 offsetof(struct fw_hdr, tp_microcode_ver), 1, 874 vers, 0); 875 } 876 877 /* 878 * csio_hw_check_fw_version - check if the FW is compatible with 879 * this driver 880 * @hw: HW module 881 * 882 * Checks if an adapter's FW is compatible with the driver. Returns 0 883 * if there's exact match, a negative error if the version could not be 884 * read or there's a major/minor version mismatch/minor. 885 */ 886 static int 887 csio_hw_check_fw_version(struct csio_hw *hw) 888 { 889 int ret, major, minor, micro; 890 891 ret = csio_hw_get_fw_version(hw, &hw->fwrev); 892 if (!ret) 893 ret = csio_hw_get_tp_version(hw, &hw->tp_vers); 894 if (ret) 895 return ret; 896 897 major = FW_HDR_FW_VER_MAJOR_GET(hw->fwrev); 898 minor = FW_HDR_FW_VER_MINOR_GET(hw->fwrev); 899 micro = FW_HDR_FW_VER_MICRO_GET(hw->fwrev); 900 901 if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */ 902 csio_err(hw, "card FW has major version %u, driver wants %u\n", 903 major, FW_VERSION_MAJOR); 904 return -EINVAL; 905 } 906 907 if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO) 908 return 0; /* perfect match */ 909 910 /* Minor/micro version mismatch */ 911 return -EINVAL; 912 } 913 914 /* 915 * csio_hw_fw_dload - download firmware. 916 * @hw: HW module 917 * @fw_data: firmware image to write. 918 * @size: image size 919 * 920 * Write the supplied firmware image to the card's serial flash. 921 */ 922 static int 923 csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size) 924 { 925 uint32_t csum; 926 int32_t addr; 927 int ret; 928 uint32_t i; 929 uint8_t first_page[SF_PAGE_SIZE]; 930 const __be32 *p = (const __be32 *)fw_data; 931 struct fw_hdr *hdr = (struct fw_hdr *)fw_data; 932 uint32_t sf_sec_size; 933 934 if ((!hw->params.sf_size) || (!hw->params.sf_nsec)) { 935 csio_err(hw, "Serial Flash data invalid\n"); 936 return -EINVAL; 937 } 938 939 if (!size) { 940 csio_err(hw, "FW image has no data\n"); 941 return -EINVAL; 942 } 943 944 if (size & 511) { 945 csio_err(hw, "FW image size not multiple of 512 bytes\n"); 946 return -EINVAL; 947 } 948 949 if (ntohs(hdr->len512) * 512 != size) { 950 csio_err(hw, "FW image size differs from size in FW header\n"); 951 return -EINVAL; 952 } 953 954 if (size > FW_MAX_SIZE) { 955 csio_err(hw, "FW image too large, max is %u bytes\n", 956 FW_MAX_SIZE); 957 return -EINVAL; 958 } 959 960 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 961 csum += ntohl(p[i]); 962 963 if (csum != 0xffffffff) { 964 csio_err(hw, "corrupted firmware image, checksum %#x\n", csum); 965 return -EINVAL; 966 } 967 968 sf_sec_size = hw->params.sf_size / hw->params.sf_nsec; 969 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 970 971 csio_dbg(hw, "Erasing sectors... start:%d end:%d\n", 972 FW_START_SEC, FW_START_SEC + i - 1); 973 974 ret = csio_hw_flash_erase_sectors(hw, FW_START_SEC, 975 FW_START_SEC + i - 1); 976 if (ret) { 977 csio_err(hw, "Flash Erase failed\n"); 978 goto out; 979 } 980 981 /* 982 * We write the correct version at the end so the driver can see a bad 983 * version if the FW write fails. Start by writing a copy of the 984 * first page with a bad version. 985 */ 986 memcpy(first_page, fw_data, SF_PAGE_SIZE); 987 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); 988 ret = csio_hw_write_flash(hw, FW_IMG_START, SF_PAGE_SIZE, first_page); 989 if (ret) 990 goto out; 991 992 csio_dbg(hw, "Writing Flash .. start:%d end:%d\n", 993 FW_IMG_START, FW_IMG_START + size); 994 995 addr = FW_IMG_START; 996 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 997 addr += SF_PAGE_SIZE; 998 fw_data += SF_PAGE_SIZE; 999 ret = csio_hw_write_flash(hw, addr, SF_PAGE_SIZE, fw_data); 1000 if (ret) 1001 goto out; 1002 } 1003 1004 ret = csio_hw_write_flash(hw, 1005 FW_IMG_START + 1006 offsetof(struct fw_hdr, fw_ver), 1007 sizeof(hdr->fw_ver), 1008 (const uint8_t *)&hdr->fw_ver); 1009 1010 out: 1011 if (ret) 1012 csio_err(hw, "firmware download failed, error %d\n", ret); 1013 return ret; 1014 } 1015 1016 static int 1017 csio_hw_get_flash_params(struct csio_hw *hw) 1018 { 1019 int ret; 1020 uint32_t info = 0; 1021 1022 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); 1023 if (!ret) 1024 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info); 1025 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 1026 if (ret != 0) 1027 return ret; 1028 1029 if ((info & 0xff) != 0x20) /* not a Numonix flash */ 1030 return -EINVAL; 1031 info >>= 16; /* log2 of size */ 1032 if (info >= 0x14 && info < 0x18) 1033 hw->params.sf_nsec = 1 << (info - 16); 1034 else if (info == 0x18) 1035 hw->params.sf_nsec = 64; 1036 else 1037 return -EINVAL; 1038 hw->params.sf_size = 1 << info; 1039 1040 return 0; 1041 } 1042 1043 static void 1044 csio_set_pcie_completion_timeout(struct csio_hw *hw, u8 range) 1045 { 1046 uint16_t val; 1047 uint32_t pcie_cap; 1048 1049 if (!csio_pci_capability(hw->pdev, PCI_CAP_ID_EXP, &pcie_cap)) { 1050 pci_read_config_word(hw->pdev, 1051 pcie_cap + PCI_EXP_DEVCTL2, &val); 1052 val &= 0xfff0; 1053 val |= range ; 1054 pci_write_config_word(hw->pdev, 1055 pcie_cap + PCI_EXP_DEVCTL2, val); 1056 } 1057 } 1058 1059 1060 /* 1061 * Return the specified PCI-E Configuration Space register from our Physical 1062 * Function. We try first via a Firmware LDST Command since we prefer to let 1063 * the firmware own all of these registers, but if that fails we go for it 1064 * directly ourselves. 1065 */ 1066 static uint32_t 1067 csio_read_pcie_cfg4(struct csio_hw *hw, int reg) 1068 { 1069 u32 val = 0; 1070 struct csio_mb *mbp; 1071 int rv; 1072 struct fw_ldst_cmd *ldst_cmd; 1073 1074 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1075 if (!mbp) { 1076 CSIO_INC_STATS(hw, n_err_nomem); 1077 pci_read_config_dword(hw->pdev, reg, &val); 1078 return val; 1079 } 1080 1081 csio_mb_ldst(hw, mbp, CSIO_MB_DEFAULT_TMO, reg); 1082 1083 rv = csio_mb_issue(hw, mbp); 1084 1085 /* 1086 * If the LDST Command suucceeded, exctract the returned register 1087 * value. Otherwise read it directly ourself. 1088 */ 1089 if (rv == 0) { 1090 ldst_cmd = (struct fw_ldst_cmd *)(mbp->mb); 1091 val = ntohl(ldst_cmd->u.pcie.data[0]); 1092 } else 1093 pci_read_config_dword(hw->pdev, reg, &val); 1094 1095 mempool_free(mbp, hw->mb_mempool); 1096 1097 return val; 1098 } /* csio_read_pcie_cfg4 */ 1099 1100 static int 1101 csio_hw_set_mem_win(struct csio_hw *hw) 1102 { 1103 u32 bar0; 1104 1105 /* 1106 * Truncation intentional: we only read the bottom 32-bits of the 1107 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to 1108 * read BAR0 instead of using pci_resource_start() because we could be 1109 * operating from within a Virtual Machine which is trapping our 1110 * accesses to our Configuration Space and we need to set up the PCI-E 1111 * Memory Window decoders with the actual addresses which will be 1112 * coming across the PCI-E link. 1113 */ 1114 bar0 = csio_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0); 1115 bar0 &= PCI_BASE_ADDRESS_MEM_MASK; 1116 1117 /* 1118 * Set up memory window for accessing adapter memory ranges. (Read 1119 * back MA register to ensure that changes propagate before we attempt 1120 * to use the new values.) 1121 */ 1122 csio_wr_reg32(hw, (bar0 + MEMWIN0_BASE) | BIR(0) | 1123 WINDOW(ilog2(MEMWIN0_APERTURE) - 10), 1124 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0)); 1125 csio_wr_reg32(hw, (bar0 + MEMWIN1_BASE) | BIR(0) | 1126 WINDOW(ilog2(MEMWIN1_APERTURE) - 10), 1127 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1)); 1128 csio_wr_reg32(hw, (bar0 + MEMWIN2_BASE) | BIR(0) | 1129 WINDOW(ilog2(MEMWIN2_APERTURE) - 10), 1130 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2)); 1131 csio_rd_reg32(hw, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2)); 1132 return 0; 1133 } /* csio_hw_set_mem_win */ 1134 1135 1136 1137 /*****************************************************************************/ 1138 /* HW State machine assists */ 1139 /*****************************************************************************/ 1140 1141 static int 1142 csio_hw_dev_ready(struct csio_hw *hw) 1143 { 1144 uint32_t reg; 1145 int cnt = 6; 1146 1147 while (((reg = csio_rd_reg32(hw, PL_WHOAMI)) == 0xFFFFFFFF) && 1148 (--cnt != 0)) 1149 mdelay(100); 1150 1151 if ((cnt == 0) && (((int32_t)(SOURCEPF_GET(reg)) < 0) || 1152 (SOURCEPF_GET(reg) >= CSIO_MAX_PFN))) { 1153 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); 1154 return -EIO; 1155 } 1156 1157 hw->pfn = SOURCEPF_GET(reg); 1158 1159 return 0; 1160 } 1161 1162 /* 1163 * csio_do_hello - Perform the HELLO FW Mailbox command and process response. 1164 * @hw: HW module 1165 * @state: Device state 1166 * 1167 * FW_HELLO_CMD has to be polled for completion. 1168 */ 1169 static int 1170 csio_do_hello(struct csio_hw *hw, enum csio_dev_state *state) 1171 { 1172 struct csio_mb *mbp; 1173 int rv = 0; 1174 enum csio_dev_master master; 1175 enum fw_retval retval; 1176 uint8_t mpfn; 1177 char state_str[16]; 1178 int retries = FW_CMD_HELLO_RETRIES; 1179 1180 memset(state_str, 0, sizeof(state_str)); 1181 1182 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1183 if (!mbp) { 1184 rv = -ENOMEM; 1185 CSIO_INC_STATS(hw, n_err_nomem); 1186 goto out; 1187 } 1188 1189 master = csio_force_master ? CSIO_MASTER_MUST : CSIO_MASTER_MAY; 1190 1191 retry: 1192 csio_mb_hello(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 1193 hw->pfn, master, NULL); 1194 1195 rv = csio_mb_issue(hw, mbp); 1196 if (rv) { 1197 csio_err(hw, "failed to issue HELLO cmd. ret:%d.\n", rv); 1198 goto out_free_mb; 1199 } 1200 1201 csio_mb_process_hello_rsp(hw, mbp, &retval, state, &mpfn); 1202 if (retval != FW_SUCCESS) { 1203 csio_err(hw, "HELLO cmd failed with ret: %d\n", retval); 1204 rv = -EINVAL; 1205 goto out_free_mb; 1206 } 1207 1208 /* Firmware has designated us to be master */ 1209 if (hw->pfn == mpfn) { 1210 hw->flags |= CSIO_HWF_MASTER; 1211 } else if (*state == CSIO_DEV_STATE_UNINIT) { 1212 /* 1213 * If we're not the Master PF then we need to wait around for 1214 * the Master PF Driver to finish setting up the adapter. 1215 * 1216 * Note that we also do this wait if we're a non-Master-capable 1217 * PF and there is no current Master PF; a Master PF may show up 1218 * momentarily and we wouldn't want to fail pointlessly. (This 1219 * can happen when an OS loads lots of different drivers rapidly 1220 * at the same time). In this case, the Master PF returned by 1221 * the firmware will be PCIE_FW_MASTER_MASK so the test below 1222 * will work ... 1223 */ 1224 1225 int waiting = FW_CMD_HELLO_TIMEOUT; 1226 1227 /* 1228 * Wait for the firmware to either indicate an error or 1229 * initialized state. If we see either of these we bail out 1230 * and report the issue to the caller. If we exhaust the 1231 * "hello timeout" and we haven't exhausted our retries, try 1232 * again. Otherwise bail with a timeout error. 1233 */ 1234 for (;;) { 1235 uint32_t pcie_fw; 1236 1237 msleep(50); 1238 waiting -= 50; 1239 1240 /* 1241 * If neither Error nor Initialialized are indicated 1242 * by the firmware keep waiting till we exaust our 1243 * timeout ... and then retry if we haven't exhausted 1244 * our retries ... 1245 */ 1246 pcie_fw = csio_rd_reg32(hw, PCIE_FW); 1247 if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) { 1248 if (waiting <= 0) { 1249 if (retries-- > 0) 1250 goto retry; 1251 1252 rv = -ETIMEDOUT; 1253 break; 1254 } 1255 continue; 1256 } 1257 1258 /* 1259 * We either have an Error or Initialized condition 1260 * report errors preferentially. 1261 */ 1262 if (state) { 1263 if (pcie_fw & PCIE_FW_ERR) { 1264 *state = CSIO_DEV_STATE_ERR; 1265 rv = -ETIMEDOUT; 1266 } else if (pcie_fw & PCIE_FW_INIT) 1267 *state = CSIO_DEV_STATE_INIT; 1268 } 1269 1270 /* 1271 * If we arrived before a Master PF was selected and 1272 * there's not a valid Master PF, grab its identity 1273 * for our caller. 1274 */ 1275 if (mpfn == PCIE_FW_MASTER_MASK && 1276 (pcie_fw & PCIE_FW_MASTER_VLD)) 1277 mpfn = PCIE_FW_MASTER_GET(pcie_fw); 1278 break; 1279 } 1280 hw->flags &= ~CSIO_HWF_MASTER; 1281 } 1282 1283 switch (*state) { 1284 case CSIO_DEV_STATE_UNINIT: 1285 strcpy(state_str, "Initializing"); 1286 break; 1287 case CSIO_DEV_STATE_INIT: 1288 strcpy(state_str, "Initialized"); 1289 break; 1290 case CSIO_DEV_STATE_ERR: 1291 strcpy(state_str, "Error"); 1292 break; 1293 default: 1294 strcpy(state_str, "Unknown"); 1295 break; 1296 } 1297 1298 if (hw->pfn == mpfn) 1299 csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n", 1300 hw->pfn, state_str); 1301 else 1302 csio_info(hw, 1303 "PF: %d, Coming up as SLAVE, Master PF: %d, HW state: %s\n", 1304 hw->pfn, mpfn, state_str); 1305 1306 out_free_mb: 1307 mempool_free(mbp, hw->mb_mempool); 1308 out: 1309 return rv; 1310 } 1311 1312 /* 1313 * csio_do_bye - Perform the BYE FW Mailbox command and process response. 1314 * @hw: HW module 1315 * 1316 */ 1317 static int 1318 csio_do_bye(struct csio_hw *hw) 1319 { 1320 struct csio_mb *mbp; 1321 enum fw_retval retval; 1322 1323 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1324 if (!mbp) { 1325 CSIO_INC_STATS(hw, n_err_nomem); 1326 return -ENOMEM; 1327 } 1328 1329 csio_mb_bye(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); 1330 1331 if (csio_mb_issue(hw, mbp)) { 1332 csio_err(hw, "Issue of BYE command failed\n"); 1333 mempool_free(mbp, hw->mb_mempool); 1334 return -EINVAL; 1335 } 1336 1337 retval = csio_mb_fw_retval(mbp); 1338 if (retval != FW_SUCCESS) { 1339 mempool_free(mbp, hw->mb_mempool); 1340 return -EINVAL; 1341 } 1342 1343 mempool_free(mbp, hw->mb_mempool); 1344 1345 return 0; 1346 } 1347 1348 /* 1349 * csio_do_reset- Perform the device reset. 1350 * @hw: HW module 1351 * @fw_rst: FW reset 1352 * 1353 * If fw_rst is set, issues FW reset mbox cmd otherwise 1354 * does PIO reset. 1355 * Performs reset of the function. 1356 */ 1357 static int 1358 csio_do_reset(struct csio_hw *hw, bool fw_rst) 1359 { 1360 struct csio_mb *mbp; 1361 enum fw_retval retval; 1362 1363 if (!fw_rst) { 1364 /* PIO reset */ 1365 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1366 mdelay(2000); 1367 return 0; 1368 } 1369 1370 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1371 if (!mbp) { 1372 CSIO_INC_STATS(hw, n_err_nomem); 1373 return -ENOMEM; 1374 } 1375 1376 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1377 PIORSTMODE | PIORST, 0, NULL); 1378 1379 if (csio_mb_issue(hw, mbp)) { 1380 csio_err(hw, "Issue of RESET command failed.n"); 1381 mempool_free(mbp, hw->mb_mempool); 1382 return -EINVAL; 1383 } 1384 1385 retval = csio_mb_fw_retval(mbp); 1386 if (retval != FW_SUCCESS) { 1387 csio_err(hw, "RESET cmd failed with ret:0x%x.\n", retval); 1388 mempool_free(mbp, hw->mb_mempool); 1389 return -EINVAL; 1390 } 1391 1392 mempool_free(mbp, hw->mb_mempool); 1393 1394 return 0; 1395 } 1396 1397 static int 1398 csio_hw_validate_caps(struct csio_hw *hw, struct csio_mb *mbp) 1399 { 1400 struct fw_caps_config_cmd *rsp = (struct fw_caps_config_cmd *)mbp->mb; 1401 uint16_t caps; 1402 1403 caps = ntohs(rsp->fcoecaps); 1404 1405 if (!(caps & FW_CAPS_CONFIG_FCOE_INITIATOR)) { 1406 csio_err(hw, "No FCoE Initiator capability in the firmware.\n"); 1407 return -EINVAL; 1408 } 1409 1410 if (!(caps & FW_CAPS_CONFIG_FCOE_CTRL_OFLD)) { 1411 csio_err(hw, "No FCoE Control Offload capability\n"); 1412 return -EINVAL; 1413 } 1414 1415 return 0; 1416 } 1417 1418 /* 1419 * csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET 1420 * @hw: the HW module 1421 * @mbox: mailbox to use for the FW RESET command (if desired) 1422 * @force: force uP into RESET even if FW RESET command fails 1423 * 1424 * Issues a RESET command to firmware (if desired) with a HALT indication 1425 * and then puts the microprocessor into RESET state. The RESET command 1426 * will only be issued if a legitimate mailbox is provided (mbox <= 1427 * PCIE_FW_MASTER_MASK). 1428 * 1429 * This is generally used in order for the host to safely manipulate the 1430 * adapter without fear of conflicting with whatever the firmware might 1431 * be doing. The only way out of this state is to RESTART the firmware 1432 * ... 1433 */ 1434 static int 1435 csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force) 1436 { 1437 enum fw_retval retval = 0; 1438 1439 /* 1440 * If a legitimate mailbox is provided, issue a RESET command 1441 * with a HALT indication. 1442 */ 1443 if (mbox <= PCIE_FW_MASTER_MASK) { 1444 struct csio_mb *mbp; 1445 1446 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1447 if (!mbp) { 1448 CSIO_INC_STATS(hw, n_err_nomem); 1449 return -ENOMEM; 1450 } 1451 1452 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1453 PIORSTMODE | PIORST, FW_RESET_CMD_HALT(1), 1454 NULL); 1455 1456 if (csio_mb_issue(hw, mbp)) { 1457 csio_err(hw, "Issue of RESET command failed!\n"); 1458 mempool_free(mbp, hw->mb_mempool); 1459 return -EINVAL; 1460 } 1461 1462 retval = csio_mb_fw_retval(mbp); 1463 mempool_free(mbp, hw->mb_mempool); 1464 } 1465 1466 /* 1467 * Normally we won't complete the operation if the firmware RESET 1468 * command fails but if our caller insists we'll go ahead and put the 1469 * uP into RESET. This can be useful if the firmware is hung or even 1470 * missing ... We'll have to take the risk of putting the uP into 1471 * RESET without the cooperation of firmware in that case. 1472 * 1473 * We also force the firmware's HALT flag to be on in case we bypassed 1474 * the firmware RESET command above or we're dealing with old firmware 1475 * which doesn't have the HALT capability. This will serve as a flag 1476 * for the incoming firmware to know that it's coming out of a HALT 1477 * rather than a RESET ... if it's new enough to understand that ... 1478 */ 1479 if (retval == 0 || force) { 1480 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST); 1481 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, PCIE_FW_HALT); 1482 } 1483 1484 /* 1485 * And we always return the result of the firmware RESET command 1486 * even when we force the uP into RESET ... 1487 */ 1488 return retval ? -EINVAL : 0; 1489 } 1490 1491 /* 1492 * csio_hw_fw_restart - restart the firmware by taking the uP out of RESET 1493 * @hw: the HW module 1494 * @reset: if we want to do a RESET to restart things 1495 * 1496 * Restart firmware previously halted by csio_hw_fw_halt(). On successful 1497 * return the previous PF Master remains as the new PF Master and there 1498 * is no need to issue a new HELLO command, etc. 1499 * 1500 * We do this in two ways: 1501 * 1502 * 1. If we're dealing with newer firmware we'll simply want to take 1503 * the chip's microprocessor out of RESET. This will cause the 1504 * firmware to start up from its start vector. And then we'll loop 1505 * until the firmware indicates it's started again (PCIE_FW.HALT 1506 * reset to 0) or we timeout. 1507 * 1508 * 2. If we're dealing with older firmware then we'll need to RESET 1509 * the chip since older firmware won't recognize the PCIE_FW.HALT 1510 * flag and automatically RESET itself on startup. 1511 */ 1512 static int 1513 csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset) 1514 { 1515 if (reset) { 1516 /* 1517 * Since we're directing the RESET instead of the firmware 1518 * doing it automatically, we need to clear the PCIE_FW.HALT 1519 * bit. 1520 */ 1521 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, 0); 1522 1523 /* 1524 * If we've been given a valid mailbox, first try to get the 1525 * firmware to do the RESET. If that works, great and we can 1526 * return success. Otherwise, if we haven't been given a 1527 * valid mailbox or the RESET command failed, fall back to 1528 * hitting the chip with a hammer. 1529 */ 1530 if (mbox <= PCIE_FW_MASTER_MASK) { 1531 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1532 msleep(100); 1533 if (csio_do_reset(hw, true) == 0) 1534 return 0; 1535 } 1536 1537 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1538 msleep(2000); 1539 } else { 1540 int ms; 1541 1542 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1543 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 1544 if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT)) 1545 return 0; 1546 msleep(100); 1547 ms += 100; 1548 } 1549 return -ETIMEDOUT; 1550 } 1551 return 0; 1552 } 1553 1554 /* 1555 * csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW 1556 * @hw: the HW module 1557 * @mbox: mailbox to use for the FW RESET command (if desired) 1558 * @fw_data: the firmware image to write 1559 * @size: image size 1560 * @force: force upgrade even if firmware doesn't cooperate 1561 * 1562 * Perform all of the steps necessary for upgrading an adapter's 1563 * firmware image. Normally this requires the cooperation of the 1564 * existing firmware in order to halt all existing activities 1565 * but if an invalid mailbox token is passed in we skip that step 1566 * (though we'll still put the adapter microprocessor into RESET in 1567 * that case). 1568 * 1569 * On successful return the new firmware will have been loaded and 1570 * the adapter will have been fully RESET losing all previous setup 1571 * state. On unsuccessful return the adapter may be completely hosed ... 1572 * positive errno indicates that the adapter is ~probably~ intact, a 1573 * negative errno indicates that things are looking bad ... 1574 */ 1575 static int 1576 csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox, 1577 const u8 *fw_data, uint32_t size, int32_t force) 1578 { 1579 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 1580 int reset, ret; 1581 1582 ret = csio_hw_fw_halt(hw, mbox, force); 1583 if (ret != 0 && !force) 1584 return ret; 1585 1586 ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size); 1587 if (ret != 0) 1588 return ret; 1589 1590 /* 1591 * Older versions of the firmware don't understand the new 1592 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 1593 * restart. So for newly loaded older firmware we'll have to do the 1594 * RESET for it so it starts up on a clean slate. We can tell if 1595 * the newly loaded firmware will handle this right by checking 1596 * its header flags to see if it advertises the capability. 1597 */ 1598 reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 1599 return csio_hw_fw_restart(hw, mbox, reset); 1600 } 1601 1602 1603 /* 1604 * csio_hw_fw_config_file - setup an adapter via a Configuration File 1605 * @hw: the HW module 1606 * @mbox: mailbox to use for the FW command 1607 * @mtype: the memory type where the Configuration File is located 1608 * @maddr: the memory address where the Configuration File is located 1609 * @finiver: return value for CF [fini] version 1610 * @finicsum: return value for CF [fini] checksum 1611 * @cfcsum: return value for CF computed checksum 1612 * 1613 * Issue a command to get the firmware to process the Configuration 1614 * File located at the specified mtype/maddress. If the Configuration 1615 * File is processed successfully and return value pointers are 1616 * provided, the Configuration File "[fini] section version and 1617 * checksum values will be returned along with the computed checksum. 1618 * It's up to the caller to decide how it wants to respond to the 1619 * checksums not matching but it recommended that a prominant warning 1620 * be emitted in order to help people rapidly identify changed or 1621 * corrupted Configuration Files. 1622 * 1623 * Also note that it's possible to modify things like "niccaps", 1624 * "toecaps",etc. between processing the Configuration File and telling 1625 * the firmware to use the new configuration. Callers which want to 1626 * do this will need to "hand-roll" their own CAPS_CONFIGS commands for 1627 * Configuration Files if they want to do this. 1628 */ 1629 static int 1630 csio_hw_fw_config_file(struct csio_hw *hw, 1631 unsigned int mtype, unsigned int maddr, 1632 uint32_t *finiver, uint32_t *finicsum, uint32_t *cfcsum) 1633 { 1634 struct csio_mb *mbp; 1635 struct fw_caps_config_cmd *caps_cmd; 1636 int rv = -EINVAL; 1637 enum fw_retval ret; 1638 1639 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1640 if (!mbp) { 1641 CSIO_INC_STATS(hw, n_err_nomem); 1642 return -ENOMEM; 1643 } 1644 /* 1645 * Tell the firmware to process the indicated Configuration File. 1646 * If there are no errors and the caller has provided return value 1647 * pointers for the [fini] section version, checksum and computed 1648 * checksum, pass those back to the caller. 1649 */ 1650 caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb); 1651 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); 1652 caps_cmd->op_to_write = 1653 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1654 FW_CMD_REQUEST | 1655 FW_CMD_READ); 1656 caps_cmd->cfvalid_to_len16 = 1657 htonl(FW_CAPS_CONFIG_CMD_CFVALID | 1658 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 1659 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 1660 FW_LEN16(*caps_cmd)); 1661 1662 if (csio_mb_issue(hw, mbp)) { 1663 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n"); 1664 goto out; 1665 } 1666 1667 ret = csio_mb_fw_retval(mbp); 1668 if (ret != FW_SUCCESS) { 1669 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv); 1670 goto out; 1671 } 1672 1673 if (finiver) 1674 *finiver = ntohl(caps_cmd->finiver); 1675 if (finicsum) 1676 *finicsum = ntohl(caps_cmd->finicsum); 1677 if (cfcsum) 1678 *cfcsum = ntohl(caps_cmd->cfcsum); 1679 1680 /* Validate device capabilities */ 1681 if (csio_hw_validate_caps(hw, mbp)) { 1682 rv = -ENOENT; 1683 goto out; 1684 } 1685 1686 /* 1687 * And now tell the firmware to use the configuration we just loaded. 1688 */ 1689 caps_cmd->op_to_write = 1690 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 1691 FW_CMD_REQUEST | 1692 FW_CMD_WRITE); 1693 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); 1694 1695 if (csio_mb_issue(hw, mbp)) { 1696 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n"); 1697 goto out; 1698 } 1699 1700 ret = csio_mb_fw_retval(mbp); 1701 if (ret != FW_SUCCESS) { 1702 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv); 1703 goto out; 1704 } 1705 1706 rv = 0; 1707 out: 1708 mempool_free(mbp, hw->mb_mempool); 1709 return rv; 1710 } 1711 1712 /* 1713 * csio_get_device_params - Get device parameters. 1714 * @hw: HW module 1715 * 1716 */ 1717 static int 1718 csio_get_device_params(struct csio_hw *hw) 1719 { 1720 struct csio_wrm *wrm = csio_hw_to_wrm(hw); 1721 struct csio_mb *mbp; 1722 enum fw_retval retval; 1723 u32 param[6]; 1724 int i, j = 0; 1725 1726 /* Initialize portids to -1 */ 1727 for (i = 0; i < CSIO_MAX_PPORTS; i++) 1728 hw->pport[i].portid = -1; 1729 1730 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1731 if (!mbp) { 1732 CSIO_INC_STATS(hw, n_err_nomem); 1733 return -ENOMEM; 1734 } 1735 1736 /* Get port vec information. */ 1737 param[0] = FW_PARAM_DEV(PORTVEC); 1738 1739 /* Get Core clock. */ 1740 param[1] = FW_PARAM_DEV(CCLK); 1741 1742 /* Get EQ id start and end. */ 1743 param[2] = FW_PARAM_PFVF(EQ_START); 1744 param[3] = FW_PARAM_PFVF(EQ_END); 1745 1746 /* Get IQ id start and end. */ 1747 param[4] = FW_PARAM_PFVF(IQFLINT_START); 1748 param[5] = FW_PARAM_PFVF(IQFLINT_END); 1749 1750 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, 1751 ARRAY_SIZE(param), param, NULL, false, NULL); 1752 if (csio_mb_issue(hw, mbp)) { 1753 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); 1754 mempool_free(mbp, hw->mb_mempool); 1755 return -EINVAL; 1756 } 1757 1758 csio_mb_process_read_params_rsp(hw, mbp, &retval, 1759 ARRAY_SIZE(param), param); 1760 if (retval != FW_SUCCESS) { 1761 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", 1762 retval); 1763 mempool_free(mbp, hw->mb_mempool); 1764 return -EINVAL; 1765 } 1766 1767 /* cache the information. */ 1768 hw->port_vec = param[0]; 1769 hw->vpd.cclk = param[1]; 1770 wrm->fw_eq_start = param[2]; 1771 wrm->fw_iq_start = param[4]; 1772 1773 /* Using FW configured max iqs & eqs */ 1774 if ((hw->flags & CSIO_HWF_USING_SOFT_PARAMS) || 1775 !csio_is_hw_master(hw)) { 1776 hw->cfg_niq = param[5] - param[4] + 1; 1777 hw->cfg_neq = param[3] - param[2] + 1; 1778 csio_dbg(hw, "Using fwconfig max niqs %d neqs %d\n", 1779 hw->cfg_niq, hw->cfg_neq); 1780 } 1781 1782 hw->port_vec &= csio_port_mask; 1783 1784 hw->num_pports = hweight32(hw->port_vec); 1785 1786 csio_dbg(hw, "Port vector: 0x%x, #ports: %d\n", 1787 hw->port_vec, hw->num_pports); 1788 1789 for (i = 0; i < hw->num_pports; i++) { 1790 while ((hw->port_vec & (1 << j)) == 0) 1791 j++; 1792 hw->pport[i].portid = j++; 1793 csio_dbg(hw, "Found Port:%d\n", hw->pport[i].portid); 1794 } 1795 mempool_free(mbp, hw->mb_mempool); 1796 1797 return 0; 1798 } 1799 1800 1801 /* 1802 * csio_config_device_caps - Get and set device capabilities. 1803 * @hw: HW module 1804 * 1805 */ 1806 static int 1807 csio_config_device_caps(struct csio_hw *hw) 1808 { 1809 struct csio_mb *mbp; 1810 enum fw_retval retval; 1811 int rv = -EINVAL; 1812 1813 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1814 if (!mbp) { 1815 CSIO_INC_STATS(hw, n_err_nomem); 1816 return -ENOMEM; 1817 } 1818 1819 /* Get device capabilities */ 1820 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 0, 0, 0, 0, NULL); 1821 1822 if (csio_mb_issue(hw, mbp)) { 1823 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(r) failed!\n"); 1824 goto out; 1825 } 1826 1827 retval = csio_mb_fw_retval(mbp); 1828 if (retval != FW_SUCCESS) { 1829 csio_err(hw, "FW_CAPS_CONFIG_CMD(r) returned %d!\n", retval); 1830 goto out; 1831 } 1832 1833 /* Validate device capabilities */ 1834 if (csio_hw_validate_caps(hw, mbp)) 1835 goto out; 1836 1837 /* Don't config device capabilities if already configured */ 1838 if (hw->fw_state == CSIO_DEV_STATE_INIT) { 1839 rv = 0; 1840 goto out; 1841 } 1842 1843 /* Write back desired device capabilities */ 1844 csio_mb_caps_config(hw, mbp, CSIO_MB_DEFAULT_TMO, true, true, 1845 false, true, NULL); 1846 1847 if (csio_mb_issue(hw, mbp)) { 1848 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD(w) failed!\n"); 1849 goto out; 1850 } 1851 1852 retval = csio_mb_fw_retval(mbp); 1853 if (retval != FW_SUCCESS) { 1854 csio_err(hw, "FW_CAPS_CONFIG_CMD(w) returned %d!\n", retval); 1855 goto out; 1856 } 1857 1858 rv = 0; 1859 out: 1860 mempool_free(mbp, hw->mb_mempool); 1861 return rv; 1862 } 1863 1864 static int 1865 csio_config_global_rss(struct csio_hw *hw) 1866 { 1867 struct csio_mb *mbp; 1868 enum fw_retval retval; 1869 1870 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1871 if (!mbp) { 1872 CSIO_INC_STATS(hw, n_err_nomem); 1873 return -ENOMEM; 1874 } 1875 1876 csio_rss_glb_config(hw, mbp, CSIO_MB_DEFAULT_TMO, 1877 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 1878 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN | 1879 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ | 1880 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP, 1881 NULL); 1882 1883 if (csio_mb_issue(hw, mbp)) { 1884 csio_err(hw, "Issue of FW_RSS_GLB_CONFIG_CMD failed!\n"); 1885 mempool_free(mbp, hw->mb_mempool); 1886 return -EINVAL; 1887 } 1888 1889 retval = csio_mb_fw_retval(mbp); 1890 if (retval != FW_SUCCESS) { 1891 csio_err(hw, "FW_RSS_GLB_CONFIG_CMD returned 0x%x!\n", retval); 1892 mempool_free(mbp, hw->mb_mempool); 1893 return -EINVAL; 1894 } 1895 1896 mempool_free(mbp, hw->mb_mempool); 1897 1898 return 0; 1899 } 1900 1901 /* 1902 * csio_config_pfvf - Configure Physical/Virtual functions settings. 1903 * @hw: HW module 1904 * 1905 */ 1906 static int 1907 csio_config_pfvf(struct csio_hw *hw) 1908 { 1909 struct csio_mb *mbp; 1910 enum fw_retval retval; 1911 1912 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1913 if (!mbp) { 1914 CSIO_INC_STATS(hw, n_err_nomem); 1915 return -ENOMEM; 1916 } 1917 1918 /* 1919 * For now, allow all PFs to access to all ports using a pmask 1920 * value of 0xF (M_FW_PFVF_CMD_PMASK). Once we have VFs, we will 1921 * need to provide access based on some rule. 1922 */ 1923 csio_mb_pfvf(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, CSIO_NEQ, 1924 CSIO_NETH_CTRL, CSIO_NIQ_FLINT, 0, 0, CSIO_NVI, CSIO_CMASK, 1925 CSIO_PMASK, CSIO_NEXACTF, CSIO_R_CAPS, CSIO_WX_CAPS, NULL); 1926 1927 if (csio_mb_issue(hw, mbp)) { 1928 csio_err(hw, "Issue of FW_PFVF_CMD failed!\n"); 1929 mempool_free(mbp, hw->mb_mempool); 1930 return -EINVAL; 1931 } 1932 1933 retval = csio_mb_fw_retval(mbp); 1934 if (retval != FW_SUCCESS) { 1935 csio_err(hw, "FW_PFVF_CMD returned 0x%x!\n", retval); 1936 mempool_free(mbp, hw->mb_mempool); 1937 return -EINVAL; 1938 } 1939 1940 mempool_free(mbp, hw->mb_mempool); 1941 1942 return 0; 1943 } 1944 1945 /* 1946 * csio_enable_ports - Bring up all available ports. 1947 * @hw: HW module. 1948 * 1949 */ 1950 static int 1951 csio_enable_ports(struct csio_hw *hw) 1952 { 1953 struct csio_mb *mbp; 1954 enum fw_retval retval; 1955 uint8_t portid; 1956 int i; 1957 1958 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1959 if (!mbp) { 1960 CSIO_INC_STATS(hw, n_err_nomem); 1961 return -ENOMEM; 1962 } 1963 1964 for (i = 0; i < hw->num_pports; i++) { 1965 portid = hw->pport[i].portid; 1966 1967 /* Read PORT information */ 1968 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, 1969 false, 0, 0, NULL); 1970 1971 if (csio_mb_issue(hw, mbp)) { 1972 csio_err(hw, "failed to issue FW_PORT_CMD(r) port:%d\n", 1973 portid); 1974 mempool_free(mbp, hw->mb_mempool); 1975 return -EINVAL; 1976 } 1977 1978 csio_mb_process_read_port_rsp(hw, mbp, &retval, 1979 &hw->pport[i].pcap); 1980 if (retval != FW_SUCCESS) { 1981 csio_err(hw, "FW_PORT_CMD(r) port:%d failed: 0x%x\n", 1982 portid, retval); 1983 mempool_free(mbp, hw->mb_mempool); 1984 return -EINVAL; 1985 } 1986 1987 /* Write back PORT information */ 1988 csio_mb_port(hw, mbp, CSIO_MB_DEFAULT_TMO, portid, true, 1989 (PAUSE_RX | PAUSE_TX), hw->pport[i].pcap, NULL); 1990 1991 if (csio_mb_issue(hw, mbp)) { 1992 csio_err(hw, "failed to issue FW_PORT_CMD(w) port:%d\n", 1993 portid); 1994 mempool_free(mbp, hw->mb_mempool); 1995 return -EINVAL; 1996 } 1997 1998 retval = csio_mb_fw_retval(mbp); 1999 if (retval != FW_SUCCESS) { 2000 csio_err(hw, "FW_PORT_CMD(w) port:%d failed :0x%x\n", 2001 portid, retval); 2002 mempool_free(mbp, hw->mb_mempool); 2003 return -EINVAL; 2004 } 2005 2006 } /* For all ports */ 2007 2008 mempool_free(mbp, hw->mb_mempool); 2009 2010 return 0; 2011 } 2012 2013 /* 2014 * csio_get_fcoe_resinfo - Read fcoe fw resource info. 2015 * @hw: HW module 2016 * Issued with lock held. 2017 */ 2018 static int 2019 csio_get_fcoe_resinfo(struct csio_hw *hw) 2020 { 2021 struct csio_fcoe_res_info *res_info = &hw->fres_info; 2022 struct fw_fcoe_res_info_cmd *rsp; 2023 struct csio_mb *mbp; 2024 enum fw_retval retval; 2025 2026 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 2027 if (!mbp) { 2028 CSIO_INC_STATS(hw, n_err_nomem); 2029 return -ENOMEM; 2030 } 2031 2032 /* Get FCoE FW resource information */ 2033 csio_fcoe_read_res_info_init_mb(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); 2034 2035 if (csio_mb_issue(hw, mbp)) { 2036 csio_err(hw, "failed to issue FW_FCOE_RES_INFO_CMD\n"); 2037 mempool_free(mbp, hw->mb_mempool); 2038 return -EINVAL; 2039 } 2040 2041 rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb); 2042 retval = FW_CMD_RETVAL_GET(ntohl(rsp->retval_len16)); 2043 if (retval != FW_SUCCESS) { 2044 csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n", 2045 retval); 2046 mempool_free(mbp, hw->mb_mempool); 2047 return -EINVAL; 2048 } 2049 2050 res_info->e_d_tov = ntohs(rsp->e_d_tov); 2051 res_info->r_a_tov_seq = ntohs(rsp->r_a_tov_seq); 2052 res_info->r_a_tov_els = ntohs(rsp->r_a_tov_els); 2053 res_info->r_r_tov = ntohs(rsp->r_r_tov); 2054 res_info->max_xchgs = ntohl(rsp->max_xchgs); 2055 res_info->max_ssns = ntohl(rsp->max_ssns); 2056 res_info->used_xchgs = ntohl(rsp->used_xchgs); 2057 res_info->used_ssns = ntohl(rsp->used_ssns); 2058 res_info->max_fcfs = ntohl(rsp->max_fcfs); 2059 res_info->max_vnps = ntohl(rsp->max_vnps); 2060 res_info->used_fcfs = ntohl(rsp->used_fcfs); 2061 res_info->used_vnps = ntohl(rsp->used_vnps); 2062 2063 csio_dbg(hw, "max ssns:%d max xchgs:%d\n", res_info->max_ssns, 2064 res_info->max_xchgs); 2065 mempool_free(mbp, hw->mb_mempool); 2066 2067 return 0; 2068 } 2069 2070 static int 2071 csio_hw_check_fwconfig(struct csio_hw *hw, u32 *param) 2072 { 2073 struct csio_mb *mbp; 2074 enum fw_retval retval; 2075 u32 _param[1]; 2076 2077 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 2078 if (!mbp) { 2079 CSIO_INC_STATS(hw, n_err_nomem); 2080 return -ENOMEM; 2081 } 2082 2083 /* 2084 * Find out whether we're dealing with a version of 2085 * the firmware which has configuration file support. 2086 */ 2087 _param[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2088 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF)); 2089 2090 csio_mb_params(hw, mbp, CSIO_MB_DEFAULT_TMO, hw->pfn, 0, 2091 ARRAY_SIZE(_param), _param, NULL, false, NULL); 2092 if (csio_mb_issue(hw, mbp)) { 2093 csio_err(hw, "Issue of FW_PARAMS_CMD(read) failed!\n"); 2094 mempool_free(mbp, hw->mb_mempool); 2095 return -EINVAL; 2096 } 2097 2098 csio_mb_process_read_params_rsp(hw, mbp, &retval, 2099 ARRAY_SIZE(_param), _param); 2100 if (retval != FW_SUCCESS) { 2101 csio_err(hw, "FW_PARAMS_CMD(read) failed with ret:0x%x!\n", 2102 retval); 2103 mempool_free(mbp, hw->mb_mempool); 2104 return -EINVAL; 2105 } 2106 2107 mempool_free(mbp, hw->mb_mempool); 2108 *param = _param[0]; 2109 2110 return 0; 2111 } 2112 2113 static int 2114 csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path) 2115 { 2116 int ret = 0; 2117 const struct firmware *cf; 2118 struct pci_dev *pci_dev = hw->pdev; 2119 struct device *dev = &pci_dev->dev; 2120 unsigned int mtype = 0, maddr = 0; 2121 uint32_t *cfg_data; 2122 int value_to_add = 0; 2123 2124 if (request_firmware(&cf, CSIO_CF_FNAME, dev) < 0) { 2125 csio_err(hw, "could not find config file " CSIO_CF_FNAME 2126 ",err: %d\n", ret); 2127 return -ENOENT; 2128 } 2129 2130 if (cf->size%4 != 0) 2131 value_to_add = 4 - (cf->size % 4); 2132 2133 cfg_data = kzalloc(cf->size+value_to_add, GFP_KERNEL); 2134 if (cfg_data == NULL) { 2135 ret = -ENOMEM; 2136 goto leave; 2137 } 2138 2139 memcpy((void *)cfg_data, (const void *)cf->data, cf->size); 2140 if (csio_hw_check_fwconfig(hw, fw_cfg_param) != 0) { 2141 ret = -EINVAL; 2142 goto leave; 2143 } 2144 2145 mtype = FW_PARAMS_PARAM_Y_GET(*fw_cfg_param); 2146 maddr = FW_PARAMS_PARAM_Z_GET(*fw_cfg_param) << 16; 2147 2148 ret = csio_memory_write(hw, mtype, maddr, 2149 cf->size + value_to_add, cfg_data); 2150 if (ret == 0) { 2151 csio_info(hw, "config file upgraded to " CSIO_CF_FNAME "\n"); 2152 strncpy(path, "/lib/firmware/" CSIO_CF_FNAME, 64); 2153 } 2154 2155 leave: 2156 kfree(cfg_data); 2157 release_firmware(cf); 2158 return ret; 2159 } 2160 2161 /* 2162 * HW initialization: contact FW, obtain config, perform basic init. 2163 * 2164 * If the firmware we're dealing with has Configuration File support, then 2165 * we use that to perform all configuration -- either using the configuration 2166 * file stored in flash on the adapter or using a filesystem-local file 2167 * if available. 2168 * 2169 * If we don't have configuration file support in the firmware, then we'll 2170 * have to set things up the old fashioned way with hard-coded register 2171 * writes and firmware commands ... 2172 */ 2173 2174 /* 2175 * Attempt to initialize the HW via a Firmware Configuration File. 2176 */ 2177 static int 2178 csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param) 2179 { 2180 unsigned int mtype, maddr; 2181 int rv; 2182 uint32_t finiver, finicsum, cfcsum; 2183 int using_flash; 2184 char path[64]; 2185 2186 /* 2187 * Reset device if necessary 2188 */ 2189 if (reset) { 2190 rv = csio_do_reset(hw, true); 2191 if (rv != 0) 2192 goto bye; 2193 } 2194 2195 /* 2196 * If we have a configuration file in host , 2197 * then use that. Otherwise, use the configuration file stored 2198 * in the HW flash ... 2199 */ 2200 spin_unlock_irq(&hw->lock); 2201 rv = csio_hw_flash_config(hw, fw_cfg_param, path); 2202 spin_lock_irq(&hw->lock); 2203 if (rv != 0) { 2204 if (rv == -ENOENT) { 2205 /* 2206 * config file was not found. Use default 2207 * config file from flash. 2208 */ 2209 mtype = FW_MEMTYPE_CF_FLASH; 2210 maddr = csio_hw_flash_cfg_addr(hw); 2211 using_flash = 1; 2212 } else { 2213 /* 2214 * we revert back to the hardwired config if 2215 * flashing failed. 2216 */ 2217 goto bye; 2218 } 2219 } else { 2220 mtype = FW_PARAMS_PARAM_Y_GET(*fw_cfg_param); 2221 maddr = FW_PARAMS_PARAM_Z_GET(*fw_cfg_param) << 16; 2222 using_flash = 0; 2223 } 2224 2225 hw->cfg_store = (uint8_t)mtype; 2226 2227 /* 2228 * Issue a Capability Configuration command to the firmware to get it 2229 * to parse the Configuration File. 2230 */ 2231 rv = csio_hw_fw_config_file(hw, mtype, maddr, &finiver, 2232 &finicsum, &cfcsum); 2233 if (rv != 0) 2234 goto bye; 2235 2236 hw->cfg_finiver = finiver; 2237 hw->cfg_finicsum = finicsum; 2238 hw->cfg_cfcsum = cfcsum; 2239 hw->cfg_csum_status = true; 2240 2241 if (finicsum != cfcsum) { 2242 csio_warn(hw, 2243 "Config File checksum mismatch: csum=%#x, computed=%#x\n", 2244 finicsum, cfcsum); 2245 2246 hw->cfg_csum_status = false; 2247 } 2248 2249 /* 2250 * Note that we're operating with parameters 2251 * not supplied by the driver, rather than from hard-wired 2252 * initialization constants buried in the driver. 2253 */ 2254 hw->flags |= CSIO_HWF_USING_SOFT_PARAMS; 2255 2256 /* device parameters */ 2257 rv = csio_get_device_params(hw); 2258 if (rv != 0) 2259 goto bye; 2260 2261 /* Configure SGE */ 2262 csio_wr_sge_init(hw); 2263 2264 /* 2265 * And finally tell the firmware to initialize itself using the 2266 * parameters from the Configuration File. 2267 */ 2268 /* Post event to notify completion of configuration */ 2269 csio_post_event(&hw->sm, CSIO_HWE_INIT); 2270 2271 csio_info(hw, 2272 "Firmware Configuration File %s, version %#x, computed checksum %#x\n", 2273 (using_flash ? "in device FLASH" : path), finiver, cfcsum); 2274 2275 return 0; 2276 2277 /* 2278 * Something bad happened. Return the error ... 2279 */ 2280 bye: 2281 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS; 2282 csio_dbg(hw, "Configuration file error %d\n", rv); 2283 return rv; 2284 } 2285 2286 /* 2287 * Attempt to initialize the adapter via hard-coded, driver supplied 2288 * parameters ... 2289 */ 2290 static int 2291 csio_hw_no_fwconfig(struct csio_hw *hw, int reset) 2292 { 2293 int rv; 2294 /* 2295 * Reset device if necessary 2296 */ 2297 if (reset) { 2298 rv = csio_do_reset(hw, true); 2299 if (rv != 0) 2300 goto out; 2301 } 2302 2303 /* Get and set device capabilities */ 2304 rv = csio_config_device_caps(hw); 2305 if (rv != 0) 2306 goto out; 2307 2308 /* Config Global RSS command */ 2309 rv = csio_config_global_rss(hw); 2310 if (rv != 0) 2311 goto out; 2312 2313 /* Configure PF/VF capabilities of device */ 2314 rv = csio_config_pfvf(hw); 2315 if (rv != 0) 2316 goto out; 2317 2318 /* device parameters */ 2319 rv = csio_get_device_params(hw); 2320 if (rv != 0) 2321 goto out; 2322 2323 /* Configure SGE */ 2324 csio_wr_sge_init(hw); 2325 2326 /* Post event to notify completion of configuration */ 2327 csio_post_event(&hw->sm, CSIO_HWE_INIT); 2328 2329 out: 2330 return rv; 2331 } 2332 2333 /* 2334 * Returns -EINVAL if attempts to flash the firmware failed 2335 * else returns 0, 2336 * if flashing was not attempted because the card had the 2337 * latest firmware ECANCELED is returned 2338 */ 2339 static int 2340 csio_hw_flash_fw(struct csio_hw *hw) 2341 { 2342 int ret = -ECANCELED; 2343 const struct firmware *fw; 2344 const struct fw_hdr *hdr; 2345 u32 fw_ver; 2346 struct pci_dev *pci_dev = hw->pdev; 2347 struct device *dev = &pci_dev->dev ; 2348 2349 if (request_firmware(&fw, CSIO_FW_FNAME, dev) < 0) { 2350 csio_err(hw, "could not find firmware image " CSIO_FW_FNAME 2351 ",err: %d\n", ret); 2352 return -EINVAL; 2353 } 2354 2355 hdr = (const struct fw_hdr *)fw->data; 2356 fw_ver = ntohl(hdr->fw_ver); 2357 if (FW_HDR_FW_VER_MAJOR_GET(fw_ver) != FW_VERSION_MAJOR) 2358 return -EINVAL; /* wrong major version, won't do */ 2359 2360 /* 2361 * If the flash FW is unusable or we found something newer, load it. 2362 */ 2363 if (FW_HDR_FW_VER_MAJOR_GET(hw->fwrev) != FW_VERSION_MAJOR || 2364 fw_ver > hw->fwrev) { 2365 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw->data, fw->size, 2366 /*force=*/false); 2367 if (!ret) 2368 csio_info(hw, "firmware upgraded to version %pI4 from " 2369 CSIO_FW_FNAME "\n", &hdr->fw_ver); 2370 else 2371 csio_err(hw, "firmware upgrade failed! err=%d\n", ret); 2372 } 2373 2374 release_firmware(fw); 2375 2376 return ret; 2377 } 2378 2379 2380 /* 2381 * csio_hw_configure - Configure HW 2382 * @hw - HW module 2383 * 2384 */ 2385 static void 2386 csio_hw_configure(struct csio_hw *hw) 2387 { 2388 int reset = 1; 2389 int rv; 2390 u32 param[1]; 2391 2392 rv = csio_hw_dev_ready(hw); 2393 if (rv != 0) { 2394 CSIO_INC_STATS(hw, n_err_fatal); 2395 csio_post_event(&hw->sm, CSIO_HWE_FATAL); 2396 goto out; 2397 } 2398 2399 /* HW version */ 2400 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV); 2401 2402 /* Needed for FW download */ 2403 rv = csio_hw_get_flash_params(hw); 2404 if (rv != 0) { 2405 csio_err(hw, "Failed to get serial flash params rv:%d\n", rv); 2406 csio_post_event(&hw->sm, CSIO_HWE_FATAL); 2407 goto out; 2408 } 2409 2410 /* Set pci completion timeout value to 4 seconds. */ 2411 csio_set_pcie_completion_timeout(hw, 0xd); 2412 2413 csio_hw_set_mem_win(hw); 2414 2415 rv = csio_hw_get_fw_version(hw, &hw->fwrev); 2416 if (rv != 0) 2417 goto out; 2418 2419 csio_hw_print_fw_version(hw, "Firmware revision"); 2420 2421 rv = csio_do_hello(hw, &hw->fw_state); 2422 if (rv != 0) { 2423 CSIO_INC_STATS(hw, n_err_fatal); 2424 csio_post_event(&hw->sm, CSIO_HWE_FATAL); 2425 goto out; 2426 } 2427 2428 /* Read vpd */ 2429 rv = csio_hw_get_vpd_params(hw, &hw->vpd); 2430 if (rv != 0) 2431 goto out; 2432 2433 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { 2434 rv = csio_hw_check_fw_version(hw); 2435 if (rv == -EINVAL) { 2436 2437 /* Do firmware update */ 2438 spin_unlock_irq(&hw->lock); 2439 rv = csio_hw_flash_fw(hw); 2440 spin_lock_irq(&hw->lock); 2441 2442 if (rv == 0) { 2443 reset = 0; 2444 /* 2445 * Note that the chip was reset as part of the 2446 * firmware upgrade so we don't reset it again 2447 * below and grab the new firmware version. 2448 */ 2449 rv = csio_hw_check_fw_version(hw); 2450 } 2451 } 2452 /* 2453 * If the firmware doesn't support Configuration 2454 * Files, use the old Driver-based, hard-wired 2455 * initialization. Otherwise, try using the 2456 * Configuration File support and fall back to the 2457 * Driver-based initialization if there's no 2458 * Configuration File found. 2459 */ 2460 if (csio_hw_check_fwconfig(hw, param) == 0) { 2461 rv = csio_hw_use_fwconfig(hw, reset, param); 2462 if (rv == -ENOENT) 2463 goto out; 2464 if (rv != 0) { 2465 csio_info(hw, 2466 "No Configuration File present " 2467 "on adapter. Using hard-wired " 2468 "configuration parameters.\n"); 2469 rv = csio_hw_no_fwconfig(hw, reset); 2470 } 2471 } else { 2472 rv = csio_hw_no_fwconfig(hw, reset); 2473 } 2474 2475 if (rv != 0) 2476 goto out; 2477 2478 } else { 2479 if (hw->fw_state == CSIO_DEV_STATE_INIT) { 2480 2481 /* device parameters */ 2482 rv = csio_get_device_params(hw); 2483 if (rv != 0) 2484 goto out; 2485 2486 /* Get device capabilities */ 2487 rv = csio_config_device_caps(hw); 2488 if (rv != 0) 2489 goto out; 2490 2491 /* Configure SGE */ 2492 csio_wr_sge_init(hw); 2493 2494 /* Post event to notify completion of configuration */ 2495 csio_post_event(&hw->sm, CSIO_HWE_INIT); 2496 goto out; 2497 } 2498 } /* if not master */ 2499 2500 out: 2501 return; 2502 } 2503 2504 /* 2505 * csio_hw_initialize - Initialize HW 2506 * @hw - HW module 2507 * 2508 */ 2509 static void 2510 csio_hw_initialize(struct csio_hw *hw) 2511 { 2512 struct csio_mb *mbp; 2513 enum fw_retval retval; 2514 int rv; 2515 int i; 2516 2517 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { 2518 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 2519 if (!mbp) 2520 goto out; 2521 2522 csio_mb_initialize(hw, mbp, CSIO_MB_DEFAULT_TMO, NULL); 2523 2524 if (csio_mb_issue(hw, mbp)) { 2525 csio_err(hw, "Issue of FW_INITIALIZE_CMD failed!\n"); 2526 goto free_and_out; 2527 } 2528 2529 retval = csio_mb_fw_retval(mbp); 2530 if (retval != FW_SUCCESS) { 2531 csio_err(hw, "FW_INITIALIZE_CMD returned 0x%x!\n", 2532 retval); 2533 goto free_and_out; 2534 } 2535 2536 mempool_free(mbp, hw->mb_mempool); 2537 } 2538 2539 rv = csio_get_fcoe_resinfo(hw); 2540 if (rv != 0) { 2541 csio_err(hw, "Failed to read fcoe resource info: %d\n", rv); 2542 goto out; 2543 } 2544 2545 spin_unlock_irq(&hw->lock); 2546 rv = csio_config_queues(hw); 2547 spin_lock_irq(&hw->lock); 2548 2549 if (rv != 0) { 2550 csio_err(hw, "Config of queues failed!: %d\n", rv); 2551 goto out; 2552 } 2553 2554 for (i = 0; i < hw->num_pports; i++) 2555 hw->pport[i].mod_type = FW_PORT_MOD_TYPE_NA; 2556 2557 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { 2558 rv = csio_enable_ports(hw); 2559 if (rv != 0) { 2560 csio_err(hw, "Failed to enable ports: %d\n", rv); 2561 goto out; 2562 } 2563 } 2564 2565 csio_post_event(&hw->sm, CSIO_HWE_INIT_DONE); 2566 return; 2567 2568 free_and_out: 2569 mempool_free(mbp, hw->mb_mempool); 2570 out: 2571 return; 2572 } 2573 2574 #define PF_INTR_MASK (PFSW | PFCIM) 2575 2576 /* 2577 * csio_hw_intr_enable - Enable HW interrupts 2578 * @hw: Pointer to HW module. 2579 * 2580 * Enable interrupts in HW registers. 2581 */ 2582 static void 2583 csio_hw_intr_enable(struct csio_hw *hw) 2584 { 2585 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw)); 2586 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2587 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE); 2588 2589 /* 2590 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up 2591 * by FW, so do nothing for INTX. 2592 */ 2593 if (hw->intr_mode == CSIO_IM_MSIX) 2594 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2595 AIVEC(AIVEC_MASK), vec); 2596 else if (hw->intr_mode == CSIO_IM_MSI) 2597 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2598 AIVEC(AIVEC_MASK), 0); 2599 2600 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE)); 2601 2602 /* Turn on MB interrupts - this will internally flush PIO as well */ 2603 csio_mb_intr_enable(hw); 2604 2605 /* These are common registers - only a master can modify them */ 2606 if (csio_is_hw_master(hw)) { 2607 /* 2608 * Disable the Serial FLASH interrupt, if enabled! 2609 */ 2610 pl &= (~SF); 2611 csio_wr_reg32(hw, pl, PL_INT_ENABLE); 2612 2613 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE | 2614 EGRESS_SIZE_ERR | ERR_INVALID_CIDX_INC | 2615 ERR_CPL_OPCODE_0 | ERR_DROPPED_DB | 2616 ERR_DATA_CPL_ON_HIGH_QID1 | 2617 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 | 2618 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 | 2619 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO | 2620 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR, 2621 SGE_INT_ENABLE3); 2622 csio_set_reg_field(hw, PL_INT_MAP0, 0, 1 << pf); 2623 } 2624 2625 hw->flags |= CSIO_HWF_HW_INTR_ENABLED; 2626 2627 } 2628 2629 /* 2630 * csio_hw_intr_disable - Disable HW interrupts 2631 * @hw: Pointer to HW module. 2632 * 2633 * Turn off Mailbox and PCI_PF_CFG interrupts. 2634 */ 2635 void 2636 csio_hw_intr_disable(struct csio_hw *hw) 2637 { 2638 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2639 2640 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) 2641 return; 2642 2643 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; 2644 2645 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE)); 2646 if (csio_is_hw_master(hw)) 2647 csio_set_reg_field(hw, PL_INT_MAP0, 1 << pf, 0); 2648 2649 /* Turn off MB interrupts */ 2650 csio_mb_intr_disable(hw); 2651 2652 } 2653 2654 static void 2655 csio_hw_fatal_err(struct csio_hw *hw) 2656 { 2657 csio_set_reg_field(hw, SGE_CONTROL, GLOBALENABLE, 0); 2658 csio_hw_intr_disable(hw); 2659 2660 /* Do not reset HW, we may need FW state for debugging */ 2661 csio_fatal(hw, "HW Fatal error encountered!\n"); 2662 } 2663 2664 /*****************************************************************************/ 2665 /* START: HW SM */ 2666 /*****************************************************************************/ 2667 /* 2668 * csio_hws_uninit - Uninit state 2669 * @hw - HW module 2670 * @evt - Event 2671 * 2672 */ 2673 static void 2674 csio_hws_uninit(struct csio_hw *hw, enum csio_hw_ev evt) 2675 { 2676 hw->prev_evt = hw->cur_evt; 2677 hw->cur_evt = evt; 2678 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2679 2680 switch (evt) { 2681 case CSIO_HWE_CFG: 2682 csio_set_state(&hw->sm, csio_hws_configuring); 2683 csio_hw_configure(hw); 2684 break; 2685 2686 default: 2687 CSIO_INC_STATS(hw, n_evt_unexp); 2688 break; 2689 } 2690 } 2691 2692 /* 2693 * csio_hws_configuring - Configuring state 2694 * @hw - HW module 2695 * @evt - Event 2696 * 2697 */ 2698 static void 2699 csio_hws_configuring(struct csio_hw *hw, enum csio_hw_ev evt) 2700 { 2701 hw->prev_evt = hw->cur_evt; 2702 hw->cur_evt = evt; 2703 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2704 2705 switch (evt) { 2706 case CSIO_HWE_INIT: 2707 csio_set_state(&hw->sm, csio_hws_initializing); 2708 csio_hw_initialize(hw); 2709 break; 2710 2711 case CSIO_HWE_INIT_DONE: 2712 csio_set_state(&hw->sm, csio_hws_ready); 2713 /* Fan out event to all lnode SMs */ 2714 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); 2715 break; 2716 2717 case CSIO_HWE_FATAL: 2718 csio_set_state(&hw->sm, csio_hws_uninit); 2719 break; 2720 2721 case CSIO_HWE_PCI_REMOVE: 2722 csio_do_bye(hw); 2723 break; 2724 default: 2725 CSIO_INC_STATS(hw, n_evt_unexp); 2726 break; 2727 } 2728 } 2729 2730 /* 2731 * csio_hws_initializing - Initialiazing state 2732 * @hw - HW module 2733 * @evt - Event 2734 * 2735 */ 2736 static void 2737 csio_hws_initializing(struct csio_hw *hw, enum csio_hw_ev evt) 2738 { 2739 hw->prev_evt = hw->cur_evt; 2740 hw->cur_evt = evt; 2741 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2742 2743 switch (evt) { 2744 case CSIO_HWE_INIT_DONE: 2745 csio_set_state(&hw->sm, csio_hws_ready); 2746 2747 /* Fan out event to all lnode SMs */ 2748 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREADY); 2749 2750 /* Enable interrupts */ 2751 csio_hw_intr_enable(hw); 2752 break; 2753 2754 case CSIO_HWE_FATAL: 2755 csio_set_state(&hw->sm, csio_hws_uninit); 2756 break; 2757 2758 case CSIO_HWE_PCI_REMOVE: 2759 csio_do_bye(hw); 2760 break; 2761 2762 default: 2763 CSIO_INC_STATS(hw, n_evt_unexp); 2764 break; 2765 } 2766 } 2767 2768 /* 2769 * csio_hws_ready - Ready state 2770 * @hw - HW module 2771 * @evt - Event 2772 * 2773 */ 2774 static void 2775 csio_hws_ready(struct csio_hw *hw, enum csio_hw_ev evt) 2776 { 2777 /* Remember the event */ 2778 hw->evtflag = evt; 2779 2780 hw->prev_evt = hw->cur_evt; 2781 hw->cur_evt = evt; 2782 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2783 2784 switch (evt) { 2785 case CSIO_HWE_HBA_RESET: 2786 case CSIO_HWE_FW_DLOAD: 2787 case CSIO_HWE_SUSPEND: 2788 case CSIO_HWE_PCI_REMOVE: 2789 case CSIO_HWE_PCIERR_DETECTED: 2790 csio_set_state(&hw->sm, csio_hws_quiescing); 2791 /* cleanup all outstanding cmds */ 2792 if (evt == CSIO_HWE_HBA_RESET || 2793 evt == CSIO_HWE_PCIERR_DETECTED) 2794 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), false); 2795 else 2796 csio_scsim_cleanup_io(csio_hw_to_scsim(hw), true); 2797 2798 csio_hw_intr_disable(hw); 2799 csio_hw_mbm_cleanup(hw); 2800 csio_evtq_stop(hw); 2801 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWSTOP); 2802 csio_evtq_flush(hw); 2803 csio_mgmtm_cleanup(csio_hw_to_mgmtm(hw)); 2804 csio_post_event(&hw->sm, CSIO_HWE_QUIESCED); 2805 break; 2806 2807 case CSIO_HWE_FATAL: 2808 csio_set_state(&hw->sm, csio_hws_uninit); 2809 break; 2810 2811 default: 2812 CSIO_INC_STATS(hw, n_evt_unexp); 2813 break; 2814 } 2815 } 2816 2817 /* 2818 * csio_hws_quiescing - Quiescing state 2819 * @hw - HW module 2820 * @evt - Event 2821 * 2822 */ 2823 static void 2824 csio_hws_quiescing(struct csio_hw *hw, enum csio_hw_ev evt) 2825 { 2826 hw->prev_evt = hw->cur_evt; 2827 hw->cur_evt = evt; 2828 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2829 2830 switch (evt) { 2831 case CSIO_HWE_QUIESCED: 2832 switch (hw->evtflag) { 2833 case CSIO_HWE_FW_DLOAD: 2834 csio_set_state(&hw->sm, csio_hws_resetting); 2835 /* Download firmware */ 2836 /* Fall through */ 2837 2838 case CSIO_HWE_HBA_RESET: 2839 csio_set_state(&hw->sm, csio_hws_resetting); 2840 /* Start reset of the HBA */ 2841 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWRESET); 2842 csio_wr_destroy_queues(hw, false); 2843 csio_do_reset(hw, false); 2844 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET_DONE); 2845 break; 2846 2847 case CSIO_HWE_PCI_REMOVE: 2848 csio_set_state(&hw->sm, csio_hws_removing); 2849 csio_notify_lnodes(hw, CSIO_LN_NOTIFY_HWREMOVE); 2850 csio_wr_destroy_queues(hw, true); 2851 /* Now send the bye command */ 2852 csio_do_bye(hw); 2853 break; 2854 2855 case CSIO_HWE_SUSPEND: 2856 csio_set_state(&hw->sm, csio_hws_quiesced); 2857 break; 2858 2859 case CSIO_HWE_PCIERR_DETECTED: 2860 csio_set_state(&hw->sm, csio_hws_pcierr); 2861 csio_wr_destroy_queues(hw, false); 2862 break; 2863 2864 default: 2865 CSIO_INC_STATS(hw, n_evt_unexp); 2866 break; 2867 2868 } 2869 break; 2870 2871 default: 2872 CSIO_INC_STATS(hw, n_evt_unexp); 2873 break; 2874 } 2875 } 2876 2877 /* 2878 * csio_hws_quiesced - Quiesced state 2879 * @hw - HW module 2880 * @evt - Event 2881 * 2882 */ 2883 static void 2884 csio_hws_quiesced(struct csio_hw *hw, enum csio_hw_ev evt) 2885 { 2886 hw->prev_evt = hw->cur_evt; 2887 hw->cur_evt = evt; 2888 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2889 2890 switch (evt) { 2891 case CSIO_HWE_RESUME: 2892 csio_set_state(&hw->sm, csio_hws_configuring); 2893 csio_hw_configure(hw); 2894 break; 2895 2896 default: 2897 CSIO_INC_STATS(hw, n_evt_unexp); 2898 break; 2899 } 2900 } 2901 2902 /* 2903 * csio_hws_resetting - HW Resetting state 2904 * @hw - HW module 2905 * @evt - Event 2906 * 2907 */ 2908 static void 2909 csio_hws_resetting(struct csio_hw *hw, enum csio_hw_ev evt) 2910 { 2911 hw->prev_evt = hw->cur_evt; 2912 hw->cur_evt = evt; 2913 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2914 2915 switch (evt) { 2916 case CSIO_HWE_HBA_RESET_DONE: 2917 csio_evtq_start(hw); 2918 csio_set_state(&hw->sm, csio_hws_configuring); 2919 csio_hw_configure(hw); 2920 break; 2921 2922 default: 2923 CSIO_INC_STATS(hw, n_evt_unexp); 2924 break; 2925 } 2926 } 2927 2928 /* 2929 * csio_hws_removing - PCI Hotplug removing state 2930 * @hw - HW module 2931 * @evt - Event 2932 * 2933 */ 2934 static void 2935 csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt) 2936 { 2937 hw->prev_evt = hw->cur_evt; 2938 hw->cur_evt = evt; 2939 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2940 2941 switch (evt) { 2942 case CSIO_HWE_HBA_RESET: 2943 if (!csio_is_hw_master(hw)) 2944 break; 2945 /* 2946 * The BYE should have alerady been issued, so we cant 2947 * use the mailbox interface. Hence we use the PL_RST 2948 * register directly. 2949 */ 2950 csio_err(hw, "Resetting HW and waiting 2 seconds...\n"); 2951 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 2952 mdelay(2000); 2953 break; 2954 2955 /* Should never receive any new events */ 2956 default: 2957 CSIO_INC_STATS(hw, n_evt_unexp); 2958 break; 2959 2960 } 2961 } 2962 2963 /* 2964 * csio_hws_pcierr - PCI Error state 2965 * @hw - HW module 2966 * @evt - Event 2967 * 2968 */ 2969 static void 2970 csio_hws_pcierr(struct csio_hw *hw, enum csio_hw_ev evt) 2971 { 2972 hw->prev_evt = hw->cur_evt; 2973 hw->cur_evt = evt; 2974 CSIO_INC_STATS(hw, n_evt_sm[evt]); 2975 2976 switch (evt) { 2977 case CSIO_HWE_PCIERR_SLOT_RESET: 2978 csio_evtq_start(hw); 2979 csio_set_state(&hw->sm, csio_hws_configuring); 2980 csio_hw_configure(hw); 2981 break; 2982 2983 default: 2984 CSIO_INC_STATS(hw, n_evt_unexp); 2985 break; 2986 } 2987 } 2988 2989 /*****************************************************************************/ 2990 /* END: HW SM */ 2991 /*****************************************************************************/ 2992 2993 /* Slow path handlers */ 2994 struct intr_info { 2995 unsigned int mask; /* bits to check in interrupt status */ 2996 const char *msg; /* message to print or NULL */ 2997 short stat_idx; /* stat counter to increment or -1 */ 2998 unsigned short fatal; /* whether the condition reported is fatal */ 2999 }; 3000 3001 /* 3002 * csio_handle_intr_status - table driven interrupt handler 3003 * @hw: HW instance 3004 * @reg: the interrupt status register to process 3005 * @acts: table of interrupt actions 3006 * 3007 * A table driven interrupt handler that applies a set of masks to an 3008 * interrupt status word and performs the corresponding actions if the 3009 * interrupts described by the mask have occured. The actions include 3010 * optionally emitting a warning or alert message. The table is terminated 3011 * by an entry specifying mask 0. Returns the number of fatal interrupt 3012 * conditions. 3013 */ 3014 static int 3015 csio_handle_intr_status(struct csio_hw *hw, unsigned int reg, 3016 const struct intr_info *acts) 3017 { 3018 int fatal = 0; 3019 unsigned int mask = 0; 3020 unsigned int status = csio_rd_reg32(hw, reg); 3021 3022 for ( ; acts->mask; ++acts) { 3023 if (!(status & acts->mask)) 3024 continue; 3025 if (acts->fatal) { 3026 fatal++; 3027 csio_fatal(hw, "Fatal %s (0x%x)\n", 3028 acts->msg, status & acts->mask); 3029 } else if (acts->msg) 3030 csio_info(hw, "%s (0x%x)\n", 3031 acts->msg, status & acts->mask); 3032 mask |= acts->mask; 3033 } 3034 status &= mask; 3035 if (status) /* clear processed interrupts */ 3036 csio_wr_reg32(hw, status, reg); 3037 return fatal; 3038 } 3039 3040 /* 3041 * Interrupt handler for the PCIE module. 3042 */ 3043 static void 3044 csio_pcie_intr_handler(struct csio_hw *hw) 3045 { 3046 static struct intr_info sysbus_intr_info[] = { 3047 { RNPP, "RXNP array parity error", -1, 1 }, 3048 { RPCP, "RXPC array parity error", -1, 1 }, 3049 { RCIP, "RXCIF array parity error", -1, 1 }, 3050 { RCCP, "Rx completions control array parity error", -1, 1 }, 3051 { RFTP, "RXFT array parity error", -1, 1 }, 3052 { 0, NULL, 0, 0 } 3053 }; 3054 static struct intr_info pcie_port_intr_info[] = { 3055 { TPCP, "TXPC array parity error", -1, 1 }, 3056 { TNPP, "TXNP array parity error", -1, 1 }, 3057 { TFTP, "TXFT array parity error", -1, 1 }, 3058 { TCAP, "TXCA array parity error", -1, 1 }, 3059 { TCIP, "TXCIF array parity error", -1, 1 }, 3060 { RCAP, "RXCA array parity error", -1, 1 }, 3061 { OTDD, "outbound request TLP discarded", -1, 1 }, 3062 { RDPE, "Rx data parity error", -1, 1 }, 3063 { TDUE, "Tx uncorrectable data error", -1, 1 }, 3064 { 0, NULL, 0, 0 } 3065 }; 3066 static struct intr_info pcie_intr_info[] = { 3067 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 3068 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 3069 { MSIDATAPERR, "MSI data parity error", -1, 1 }, 3070 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3071 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3072 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3073 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3074 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 3075 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 3076 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3077 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 3078 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3079 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3080 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 3081 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3082 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3083 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 3084 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3085 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3086 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3087 { FIDPERR, "PCI FID parity error", -1, 1 }, 3088 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 3089 { MATAGPERR, "PCI MA tag parity error", -1, 1 }, 3090 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3091 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 3092 { RXWRPERR, "PCI Rx write parity error", -1, 1 }, 3093 { RPLPERR, "PCI replay buffer parity error", -1, 1 }, 3094 { PCIESINT, "PCI core secondary fault", -1, 1 }, 3095 { PCIEPINT, "PCI core primary fault", -1, 1 }, 3096 { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 3097 0 }, 3098 { 0, NULL, 0, 0 } 3099 }; 3100 3101 int fat; 3102 3103 fat = csio_handle_intr_status(hw, 3104 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 3105 sysbus_intr_info) + 3106 csio_handle_intr_status(hw, 3107 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 3108 pcie_port_intr_info) + 3109 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info); 3110 if (fat) 3111 csio_hw_fatal_err(hw); 3112 } 3113 3114 /* 3115 * TP interrupt handler. 3116 */ 3117 static void csio_tp_intr_handler(struct csio_hw *hw) 3118 { 3119 static struct intr_info tp_intr_info[] = { 3120 { 0x3fffffff, "TP parity error", -1, 1 }, 3121 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 3122 { 0, NULL, 0, 0 } 3123 }; 3124 3125 if (csio_handle_intr_status(hw, TP_INT_CAUSE, tp_intr_info)) 3126 csio_hw_fatal_err(hw); 3127 } 3128 3129 /* 3130 * SGE interrupt handler. 3131 */ 3132 static void csio_sge_intr_handler(struct csio_hw *hw) 3133 { 3134 uint64_t v; 3135 3136 static struct intr_info sge_intr_info[] = { 3137 { ERR_CPL_EXCEED_IQE_SIZE, 3138 "SGE received CPL exceeding IQE size", -1, 1 }, 3139 { ERR_INVALID_CIDX_INC, 3140 "SGE GTS CIDX increment too large", -1, 0 }, 3141 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 3142 { ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 }, 3143 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0, 3144 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 3145 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 3146 0 }, 3147 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 3148 0 }, 3149 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 3150 0 }, 3151 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 3152 0 }, 3153 { ERR_ING_CTXT_PRIO, 3154 "SGE too many priority ingress contexts", -1, 0 }, 3155 { ERR_EGR_CTXT_PRIO, 3156 "SGE too many priority egress contexts", -1, 0 }, 3157 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 3158 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 3159 { 0, NULL, 0, 0 } 3160 }; 3161 3162 v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1) | 3163 ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2) << 32); 3164 if (v) { 3165 csio_fatal(hw, "SGE parity error (%#llx)\n", 3166 (unsigned long long)v); 3167 csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF), 3168 SGE_INT_CAUSE1); 3169 csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2); 3170 } 3171 3172 v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info); 3173 3174 if (csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info) || 3175 v != 0) 3176 csio_hw_fatal_err(hw); 3177 } 3178 3179 #define CIM_OBQ_INTR (OBQULP0PARERR | OBQULP1PARERR | OBQULP2PARERR |\ 3180 OBQULP3PARERR | OBQSGEPARERR | OBQNCSIPARERR) 3181 #define CIM_IBQ_INTR (IBQTP0PARERR | IBQTP1PARERR | IBQULPPARERR |\ 3182 IBQSGEHIPARERR | IBQSGELOPARERR | IBQNCSIPARERR) 3183 3184 /* 3185 * CIM interrupt handler. 3186 */ 3187 static void csio_cim_intr_handler(struct csio_hw *hw) 3188 { 3189 static struct intr_info cim_intr_info[] = { 3190 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 3191 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 3192 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 3193 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 3194 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 3195 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 3196 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 3197 { 0, NULL, 0, 0 } 3198 }; 3199 static struct intr_info cim_upintr_info[] = { 3200 { RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 3201 { ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 3202 { ILLWRINT, "CIM illegal write", -1, 1 }, 3203 { ILLRDINT, "CIM illegal read", -1, 1 }, 3204 { ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 3205 { ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 3206 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 3207 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 3208 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 3209 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 3210 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 3211 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 3212 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 3213 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 3214 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 3215 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 3216 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 3217 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 3218 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 3219 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 3220 { SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 3221 { SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 3222 { BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 3223 { BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 3224 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 3225 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 3226 { TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 3227 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 3228 { 0, NULL, 0, 0 } 3229 }; 3230 3231 int fat; 3232 3233 fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE, 3234 cim_intr_info) + 3235 csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE, 3236 cim_upintr_info); 3237 if (fat) 3238 csio_hw_fatal_err(hw); 3239 } 3240 3241 /* 3242 * ULP RX interrupt handler. 3243 */ 3244 static void csio_ulprx_intr_handler(struct csio_hw *hw) 3245 { 3246 static struct intr_info ulprx_intr_info[] = { 3247 { 0x1800000, "ULPRX context error", -1, 1 }, 3248 { 0x7fffff, "ULPRX parity error", -1, 1 }, 3249 { 0, NULL, 0, 0 } 3250 }; 3251 3252 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE, ulprx_intr_info)) 3253 csio_hw_fatal_err(hw); 3254 } 3255 3256 /* 3257 * ULP TX interrupt handler. 3258 */ 3259 static void csio_ulptx_intr_handler(struct csio_hw *hw) 3260 { 3261 static struct intr_info ulptx_intr_info[] = { 3262 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 3263 0 }, 3264 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 3265 0 }, 3266 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 3267 0 }, 3268 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 3269 0 }, 3270 { 0xfffffff, "ULPTX parity error", -1, 1 }, 3271 { 0, NULL, 0, 0 } 3272 }; 3273 3274 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE, ulptx_intr_info)) 3275 csio_hw_fatal_err(hw); 3276 } 3277 3278 /* 3279 * PM TX interrupt handler. 3280 */ 3281 static void csio_pmtx_intr_handler(struct csio_hw *hw) 3282 { 3283 static struct intr_info pmtx_intr_info[] = { 3284 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 3285 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 3286 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 3287 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 3288 { 0xffffff0, "PMTX framing error", -1, 1 }, 3289 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 3290 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 3291 1 }, 3292 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 3293 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 3294 { 0, NULL, 0, 0 } 3295 }; 3296 3297 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE, pmtx_intr_info)) 3298 csio_hw_fatal_err(hw); 3299 } 3300 3301 /* 3302 * PM RX interrupt handler. 3303 */ 3304 static void csio_pmrx_intr_handler(struct csio_hw *hw) 3305 { 3306 static struct intr_info pmrx_intr_info[] = { 3307 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 3308 { 0x3ffff0, "PMRX framing error", -1, 1 }, 3309 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 3310 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 3311 1 }, 3312 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 3313 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 3314 { 0, NULL, 0, 0 } 3315 }; 3316 3317 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE, pmrx_intr_info)) 3318 csio_hw_fatal_err(hw); 3319 } 3320 3321 /* 3322 * CPL switch interrupt handler. 3323 */ 3324 static void csio_cplsw_intr_handler(struct csio_hw *hw) 3325 { 3326 static struct intr_info cplsw_intr_info[] = { 3327 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 3328 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 3329 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 3330 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 3331 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 3332 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 3333 { 0, NULL, 0, 0 } 3334 }; 3335 3336 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE, cplsw_intr_info)) 3337 csio_hw_fatal_err(hw); 3338 } 3339 3340 /* 3341 * LE interrupt handler. 3342 */ 3343 static void csio_le_intr_handler(struct csio_hw *hw) 3344 { 3345 static struct intr_info le_intr_info[] = { 3346 { LIPMISS, "LE LIP miss", -1, 0 }, 3347 { LIP0, "LE 0 LIP error", -1, 0 }, 3348 { PARITYERR, "LE parity error", -1, 1 }, 3349 { UNKNOWNCMD, "LE unknown command", -1, 1 }, 3350 { REQQPARERR, "LE request queue parity error", -1, 1 }, 3351 { 0, NULL, 0, 0 } 3352 }; 3353 3354 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE, le_intr_info)) 3355 csio_hw_fatal_err(hw); 3356 } 3357 3358 /* 3359 * MPS interrupt handler. 3360 */ 3361 static void csio_mps_intr_handler(struct csio_hw *hw) 3362 { 3363 static struct intr_info mps_rx_intr_info[] = { 3364 { 0xffffff, "MPS Rx parity error", -1, 1 }, 3365 { 0, NULL, 0, 0 } 3366 }; 3367 static struct intr_info mps_tx_intr_info[] = { 3368 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, 3369 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 3370 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, 3371 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, 3372 { BUBBLE, "MPS Tx underflow", -1, 1 }, 3373 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 3374 { FRMERR, "MPS Tx framing error", -1, 1 }, 3375 { 0, NULL, 0, 0 } 3376 }; 3377 static struct intr_info mps_trc_intr_info[] = { 3378 { FILTMEM, "MPS TRC filter parity error", -1, 1 }, 3379 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, 3380 { MISCPERR, "MPS TRC misc parity error", -1, 1 }, 3381 { 0, NULL, 0, 0 } 3382 }; 3383 static struct intr_info mps_stat_sram_intr_info[] = { 3384 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 3385 { 0, NULL, 0, 0 } 3386 }; 3387 static struct intr_info mps_stat_tx_intr_info[] = { 3388 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 3389 { 0, NULL, 0, 0 } 3390 }; 3391 static struct intr_info mps_stat_rx_intr_info[] = { 3392 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 3393 { 0, NULL, 0, 0 } 3394 }; 3395 static struct intr_info mps_cls_intr_info[] = { 3396 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 3397 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 3398 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 3399 { 0, NULL, 0, 0 } 3400 }; 3401 3402 int fat; 3403 3404 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE, 3405 mps_rx_intr_info) + 3406 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE, 3407 mps_tx_intr_info) + 3408 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE, 3409 mps_trc_intr_info) + 3410 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM, 3411 mps_stat_sram_intr_info) + 3412 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 3413 mps_stat_tx_intr_info) + 3414 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 3415 mps_stat_rx_intr_info) + 3416 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE, 3417 mps_cls_intr_info); 3418 3419 csio_wr_reg32(hw, 0, MPS_INT_CAUSE); 3420 csio_rd_reg32(hw, MPS_INT_CAUSE); /* flush */ 3421 if (fat) 3422 csio_hw_fatal_err(hw); 3423 } 3424 3425 #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE) 3426 3427 /* 3428 * EDC/MC interrupt handler. 3429 */ 3430 static void csio_mem_intr_handler(struct csio_hw *hw, int idx) 3431 { 3432 static const char name[3][5] = { "EDC0", "EDC1", "MC" }; 3433 3434 unsigned int addr, cnt_addr, v; 3435 3436 if (idx <= MEM_EDC1) { 3437 addr = EDC_REG(EDC_INT_CAUSE, idx); 3438 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx); 3439 } else { 3440 addr = MC_INT_CAUSE; 3441 cnt_addr = MC_ECC_STATUS; 3442 } 3443 3444 v = csio_rd_reg32(hw, addr) & MEM_INT_MASK; 3445 if (v & PERR_INT_CAUSE) 3446 csio_fatal(hw, "%s FIFO parity error\n", name[idx]); 3447 if (v & ECC_CE_INT_CAUSE) { 3448 uint32_t cnt = ECC_CECNT_GET(csio_rd_reg32(hw, cnt_addr)); 3449 3450 csio_wr_reg32(hw, ECC_CECNT_MASK, cnt_addr); 3451 csio_warn(hw, "%u %s correctable ECC data error%s\n", 3452 cnt, name[idx], cnt > 1 ? "s" : ""); 3453 } 3454 if (v & ECC_UE_INT_CAUSE) 3455 csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]); 3456 3457 csio_wr_reg32(hw, v, addr); 3458 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE)) 3459 csio_hw_fatal_err(hw); 3460 } 3461 3462 /* 3463 * MA interrupt handler. 3464 */ 3465 static void csio_ma_intr_handler(struct csio_hw *hw) 3466 { 3467 uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE); 3468 3469 if (status & MEM_PERR_INT_CAUSE) 3470 csio_fatal(hw, "MA parity error, parity status %#x\n", 3471 csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS)); 3472 if (status & MEM_WRAP_INT_CAUSE) { 3473 v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS); 3474 csio_fatal(hw, 3475 "MA address wrap-around error by client %u to address %#x\n", 3476 MEM_WRAP_CLIENT_NUM_GET(v), MEM_WRAP_ADDRESS_GET(v) << 4); 3477 } 3478 csio_wr_reg32(hw, status, MA_INT_CAUSE); 3479 csio_hw_fatal_err(hw); 3480 } 3481 3482 /* 3483 * SMB interrupt handler. 3484 */ 3485 static void csio_smb_intr_handler(struct csio_hw *hw) 3486 { 3487 static struct intr_info smb_intr_info[] = { 3488 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 3489 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 3490 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 3491 { 0, NULL, 0, 0 } 3492 }; 3493 3494 if (csio_handle_intr_status(hw, SMB_INT_CAUSE, smb_intr_info)) 3495 csio_hw_fatal_err(hw); 3496 } 3497 3498 /* 3499 * NC-SI interrupt handler. 3500 */ 3501 static void csio_ncsi_intr_handler(struct csio_hw *hw) 3502 { 3503 static struct intr_info ncsi_intr_info[] = { 3504 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 3505 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 3506 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 3507 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 3508 { 0, NULL, 0, 0 } 3509 }; 3510 3511 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE, ncsi_intr_info)) 3512 csio_hw_fatal_err(hw); 3513 } 3514 3515 /* 3516 * XGMAC interrupt handler. 3517 */ 3518 static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) 3519 { 3520 uint32_t v = csio_rd_reg32(hw, PORT_REG(port, XGMAC_PORT_INT_CAUSE)); 3521 3522 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; 3523 if (!v) 3524 return; 3525 3526 if (v & TXFIFO_PRTY_ERR) 3527 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); 3528 if (v & RXFIFO_PRTY_ERR) 3529 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); 3530 csio_wr_reg32(hw, v, PORT_REG(port, XGMAC_PORT_INT_CAUSE)); 3531 csio_hw_fatal_err(hw); 3532 } 3533 3534 /* 3535 * PL interrupt handler. 3536 */ 3537 static void csio_pl_intr_handler(struct csio_hw *hw) 3538 { 3539 static struct intr_info pl_intr_info[] = { 3540 { FATALPERR, "T4 fatal parity error", -1, 1 }, 3541 { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 3542 { 0, NULL, 0, 0 } 3543 }; 3544 3545 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE, pl_intr_info)) 3546 csio_hw_fatal_err(hw); 3547 } 3548 3549 /* 3550 * csio_hw_slow_intr_handler - control path interrupt handler 3551 * @hw: HW module 3552 * 3553 * Interrupt handler for non-data global interrupt events, e.g., errors. 3554 * The designation 'slow' is because it involves register reads, while 3555 * data interrupts typically don't involve any MMIOs. 3556 */ 3557 int 3558 csio_hw_slow_intr_handler(struct csio_hw *hw) 3559 { 3560 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE); 3561 3562 if (!(cause & CSIO_GLBL_INTR_MASK)) { 3563 CSIO_INC_STATS(hw, n_plint_unexp); 3564 return 0; 3565 } 3566 3567 csio_dbg(hw, "Slow interrupt! cause: 0x%x\n", cause); 3568 3569 CSIO_INC_STATS(hw, n_plint_cnt); 3570 3571 if (cause & CIM) 3572 csio_cim_intr_handler(hw); 3573 3574 if (cause & MPS) 3575 csio_mps_intr_handler(hw); 3576 3577 if (cause & NCSI) 3578 csio_ncsi_intr_handler(hw); 3579 3580 if (cause & PL) 3581 csio_pl_intr_handler(hw); 3582 3583 if (cause & SMB) 3584 csio_smb_intr_handler(hw); 3585 3586 if (cause & XGMAC0) 3587 csio_xgmac_intr_handler(hw, 0); 3588 3589 if (cause & XGMAC1) 3590 csio_xgmac_intr_handler(hw, 1); 3591 3592 if (cause & XGMAC_KR0) 3593 csio_xgmac_intr_handler(hw, 2); 3594 3595 if (cause & XGMAC_KR1) 3596 csio_xgmac_intr_handler(hw, 3); 3597 3598 if (cause & PCIE) 3599 csio_pcie_intr_handler(hw); 3600 3601 if (cause & MC) 3602 csio_mem_intr_handler(hw, MEM_MC); 3603 3604 if (cause & EDC0) 3605 csio_mem_intr_handler(hw, MEM_EDC0); 3606 3607 if (cause & EDC1) 3608 csio_mem_intr_handler(hw, MEM_EDC1); 3609 3610 if (cause & LE) 3611 csio_le_intr_handler(hw); 3612 3613 if (cause & TP) 3614 csio_tp_intr_handler(hw); 3615 3616 if (cause & MA) 3617 csio_ma_intr_handler(hw); 3618 3619 if (cause & PM_TX) 3620 csio_pmtx_intr_handler(hw); 3621 3622 if (cause & PM_RX) 3623 csio_pmrx_intr_handler(hw); 3624 3625 if (cause & ULP_RX) 3626 csio_ulprx_intr_handler(hw); 3627 3628 if (cause & CPL_SWITCH) 3629 csio_cplsw_intr_handler(hw); 3630 3631 if (cause & SGE) 3632 csio_sge_intr_handler(hw); 3633 3634 if (cause & ULP_TX) 3635 csio_ulptx_intr_handler(hw); 3636 3637 /* Clear the interrupts just processed for which we are the master. */ 3638 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE); 3639 csio_rd_reg32(hw, PL_INT_CAUSE); /* flush */ 3640 3641 return 1; 3642 } 3643 3644 /***************************************************************************** 3645 * HW <--> mailbox interfacing routines. 3646 ****************************************************************************/ 3647 /* 3648 * csio_mberr_worker - Worker thread (dpc) for mailbox/error completions 3649 * 3650 * @data: Private data pointer. 3651 * 3652 * Called from worker thread context. 3653 */ 3654 static void 3655 csio_mberr_worker(void *data) 3656 { 3657 struct csio_hw *hw = (struct csio_hw *)data; 3658 struct csio_mbm *mbm = &hw->mbm; 3659 LIST_HEAD(cbfn_q); 3660 struct csio_mb *mbp_next; 3661 int rv; 3662 3663 del_timer_sync(&mbm->timer); 3664 3665 spin_lock_irq(&hw->lock); 3666 if (list_empty(&mbm->cbfn_q)) { 3667 spin_unlock_irq(&hw->lock); 3668 return; 3669 } 3670 3671 list_splice_tail_init(&mbm->cbfn_q, &cbfn_q); 3672 mbm->stats.n_cbfnq = 0; 3673 3674 /* Try to start waiting mailboxes */ 3675 if (!list_empty(&mbm->req_q)) { 3676 mbp_next = list_first_entry(&mbm->req_q, struct csio_mb, list); 3677 list_del_init(&mbp_next->list); 3678 3679 rv = csio_mb_issue(hw, mbp_next); 3680 if (rv != 0) 3681 list_add_tail(&mbp_next->list, &mbm->req_q); 3682 else 3683 CSIO_DEC_STATS(mbm, n_activeq); 3684 } 3685 spin_unlock_irq(&hw->lock); 3686 3687 /* Now callback completions */ 3688 csio_mb_completions(hw, &cbfn_q); 3689 } 3690 3691 /* 3692 * csio_hw_mb_timer - Top-level Mailbox timeout handler. 3693 * 3694 * @data: private data pointer 3695 * 3696 **/ 3697 static void 3698 csio_hw_mb_timer(uintptr_t data) 3699 { 3700 struct csio_hw *hw = (struct csio_hw *)data; 3701 struct csio_mb *mbp = NULL; 3702 3703 spin_lock_irq(&hw->lock); 3704 mbp = csio_mb_tmo_handler(hw); 3705 spin_unlock_irq(&hw->lock); 3706 3707 /* Call back the function for the timed-out Mailbox */ 3708 if (mbp) 3709 mbp->mb_cbfn(hw, mbp); 3710 3711 } 3712 3713 /* 3714 * csio_hw_mbm_cleanup - Cleanup Mailbox module. 3715 * @hw: HW module 3716 * 3717 * Called with lock held, should exit with lock held. 3718 * Cancels outstanding mailboxes (waiting, in-flight) and gathers them 3719 * into a local queue. Drops lock and calls the completions. Holds 3720 * lock and returns. 3721 */ 3722 static void 3723 csio_hw_mbm_cleanup(struct csio_hw *hw) 3724 { 3725 LIST_HEAD(cbfn_q); 3726 3727 csio_mb_cancel_all(hw, &cbfn_q); 3728 3729 spin_unlock_irq(&hw->lock); 3730 csio_mb_completions(hw, &cbfn_q); 3731 spin_lock_irq(&hw->lock); 3732 } 3733 3734 /***************************************************************************** 3735 * Event handling 3736 ****************************************************************************/ 3737 int 3738 csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, void *evt_msg, 3739 uint16_t len) 3740 { 3741 struct csio_evt_msg *evt_entry = NULL; 3742 3743 if (type >= CSIO_EVT_MAX) 3744 return -EINVAL; 3745 3746 if (len > CSIO_EVT_MSG_SIZE) 3747 return -EINVAL; 3748 3749 if (hw->flags & CSIO_HWF_FWEVT_STOP) 3750 return -EINVAL; 3751 3752 if (list_empty(&hw->evt_free_q)) { 3753 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", 3754 type, len); 3755 return -ENOMEM; 3756 } 3757 3758 evt_entry = list_first_entry(&hw->evt_free_q, 3759 struct csio_evt_msg, list); 3760 list_del_init(&evt_entry->list); 3761 3762 /* copy event msg and queue the event */ 3763 evt_entry->type = type; 3764 memcpy((void *)evt_entry->data, evt_msg, len); 3765 list_add_tail(&evt_entry->list, &hw->evt_active_q); 3766 3767 CSIO_DEC_STATS(hw, n_evt_freeq); 3768 CSIO_INC_STATS(hw, n_evt_activeq); 3769 3770 return 0; 3771 } 3772 3773 static int 3774 csio_enqueue_evt_lock(struct csio_hw *hw, enum csio_evt type, void *evt_msg, 3775 uint16_t len, bool msg_sg) 3776 { 3777 struct csio_evt_msg *evt_entry = NULL; 3778 struct csio_fl_dma_buf *fl_sg; 3779 uint32_t off = 0; 3780 unsigned long flags; 3781 int n, ret = 0; 3782 3783 if (type >= CSIO_EVT_MAX) 3784 return -EINVAL; 3785 3786 if (len > CSIO_EVT_MSG_SIZE) 3787 return -EINVAL; 3788 3789 spin_lock_irqsave(&hw->lock, flags); 3790 if (hw->flags & CSIO_HWF_FWEVT_STOP) { 3791 ret = -EINVAL; 3792 goto out; 3793 } 3794 3795 if (list_empty(&hw->evt_free_q)) { 3796 csio_err(hw, "Failed to alloc evt entry, msg type %d len %d\n", 3797 type, len); 3798 ret = -ENOMEM; 3799 goto out; 3800 } 3801 3802 evt_entry = list_first_entry(&hw->evt_free_q, 3803 struct csio_evt_msg, list); 3804 list_del_init(&evt_entry->list); 3805 3806 /* copy event msg and queue the event */ 3807 evt_entry->type = type; 3808 3809 /* If Payload in SG list*/ 3810 if (msg_sg) { 3811 fl_sg = (struct csio_fl_dma_buf *) evt_msg; 3812 for (n = 0; (n < CSIO_MAX_FLBUF_PER_IQWR && off < len); n++) { 3813 memcpy((void *)((uintptr_t)evt_entry->data + off), 3814 fl_sg->flbufs[n].vaddr, 3815 fl_sg->flbufs[n].len); 3816 off += fl_sg->flbufs[n].len; 3817 } 3818 } else 3819 memcpy((void *)evt_entry->data, evt_msg, len); 3820 3821 list_add_tail(&evt_entry->list, &hw->evt_active_q); 3822 CSIO_DEC_STATS(hw, n_evt_freeq); 3823 CSIO_INC_STATS(hw, n_evt_activeq); 3824 out: 3825 spin_unlock_irqrestore(&hw->lock, flags); 3826 return ret; 3827 } 3828 3829 static void 3830 csio_free_evt(struct csio_hw *hw, struct csio_evt_msg *evt_entry) 3831 { 3832 if (evt_entry) { 3833 spin_lock_irq(&hw->lock); 3834 list_del_init(&evt_entry->list); 3835 list_add_tail(&evt_entry->list, &hw->evt_free_q); 3836 CSIO_DEC_STATS(hw, n_evt_activeq); 3837 CSIO_INC_STATS(hw, n_evt_freeq); 3838 spin_unlock_irq(&hw->lock); 3839 } 3840 } 3841 3842 void 3843 csio_evtq_flush(struct csio_hw *hw) 3844 { 3845 uint32_t count; 3846 count = 30; 3847 while (hw->flags & CSIO_HWF_FWEVT_PENDING && count--) { 3848 spin_unlock_irq(&hw->lock); 3849 msleep(2000); 3850 spin_lock_irq(&hw->lock); 3851 } 3852 3853 CSIO_DB_ASSERT(!(hw->flags & CSIO_HWF_FWEVT_PENDING)); 3854 } 3855 3856 static void 3857 csio_evtq_stop(struct csio_hw *hw) 3858 { 3859 hw->flags |= CSIO_HWF_FWEVT_STOP; 3860 } 3861 3862 static void 3863 csio_evtq_start(struct csio_hw *hw) 3864 { 3865 hw->flags &= ~CSIO_HWF_FWEVT_STOP; 3866 } 3867 3868 static void 3869 csio_evtq_cleanup(struct csio_hw *hw) 3870 { 3871 struct list_head *evt_entry, *next_entry; 3872 3873 /* Release outstanding events from activeq to freeq*/ 3874 if (!list_empty(&hw->evt_active_q)) 3875 list_splice_tail_init(&hw->evt_active_q, &hw->evt_free_q); 3876 3877 hw->stats.n_evt_activeq = 0; 3878 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; 3879 3880 /* Freeup event entry */ 3881 list_for_each_safe(evt_entry, next_entry, &hw->evt_free_q) { 3882 kfree(evt_entry); 3883 CSIO_DEC_STATS(hw, n_evt_freeq); 3884 } 3885 3886 hw->stats.n_evt_freeq = 0; 3887 } 3888 3889 3890 static void 3891 csio_process_fwevtq_entry(struct csio_hw *hw, void *wr, uint32_t len, 3892 struct csio_fl_dma_buf *flb, void *priv) 3893 { 3894 __u8 op; 3895 __be64 *data; 3896 void *msg = NULL; 3897 uint32_t msg_len = 0; 3898 bool msg_sg = 0; 3899 3900 op = ((struct rss_header *) wr)->opcode; 3901 if (op == CPL_FW6_PLD) { 3902 CSIO_INC_STATS(hw, n_cpl_fw6_pld); 3903 if (!flb || !flb->totlen) { 3904 CSIO_INC_STATS(hw, n_cpl_unexp); 3905 return; 3906 } 3907 3908 msg = (void *) flb; 3909 msg_len = flb->totlen; 3910 msg_sg = 1; 3911 3912 data = (__be64 *) msg; 3913 } else if (op == CPL_FW6_MSG || op == CPL_FW4_MSG) { 3914 3915 CSIO_INC_STATS(hw, n_cpl_fw6_msg); 3916 /* skip RSS header */ 3917 msg = (void *)((uintptr_t)wr + sizeof(__be64)); 3918 msg_len = (op == CPL_FW6_MSG) ? sizeof(struct cpl_fw6_msg) : 3919 sizeof(struct cpl_fw4_msg); 3920 3921 data = (__be64 *) msg; 3922 } else { 3923 csio_warn(hw, "unexpected CPL %#x on FW event queue\n", op); 3924 CSIO_INC_STATS(hw, n_cpl_unexp); 3925 return; 3926 } 3927 3928 /* 3929 * Enqueue event to EventQ. Events processing happens 3930 * in Event worker thread context 3931 */ 3932 if (csio_enqueue_evt_lock(hw, CSIO_EVT_FW, msg, 3933 (uint16_t)msg_len, msg_sg)) 3934 CSIO_INC_STATS(hw, n_evt_drop); 3935 } 3936 3937 void 3938 csio_evtq_worker(struct work_struct *work) 3939 { 3940 struct csio_hw *hw = container_of(work, struct csio_hw, evtq_work); 3941 struct list_head *evt_entry, *next_entry; 3942 LIST_HEAD(evt_q); 3943 struct csio_evt_msg *evt_msg; 3944 struct cpl_fw6_msg *msg; 3945 struct csio_rnode *rn; 3946 int rv = 0; 3947 uint8_t evtq_stop = 0; 3948 3949 csio_dbg(hw, "event worker thread active evts#%d\n", 3950 hw->stats.n_evt_activeq); 3951 3952 spin_lock_irq(&hw->lock); 3953 while (!list_empty(&hw->evt_active_q)) { 3954 list_splice_tail_init(&hw->evt_active_q, &evt_q); 3955 spin_unlock_irq(&hw->lock); 3956 3957 list_for_each_safe(evt_entry, next_entry, &evt_q) { 3958 evt_msg = (struct csio_evt_msg *) evt_entry; 3959 3960 /* Drop events if queue is STOPPED */ 3961 spin_lock_irq(&hw->lock); 3962 if (hw->flags & CSIO_HWF_FWEVT_STOP) 3963 evtq_stop = 1; 3964 spin_unlock_irq(&hw->lock); 3965 if (evtq_stop) { 3966 CSIO_INC_STATS(hw, n_evt_drop); 3967 goto free_evt; 3968 } 3969 3970 switch (evt_msg->type) { 3971 case CSIO_EVT_FW: 3972 msg = (struct cpl_fw6_msg *)(evt_msg->data); 3973 3974 if ((msg->opcode == CPL_FW6_MSG || 3975 msg->opcode == CPL_FW4_MSG) && 3976 !msg->type) { 3977 rv = csio_mb_fwevt_handler(hw, 3978 msg->data); 3979 if (!rv) 3980 break; 3981 /* Handle any remaining fw events */ 3982 csio_fcoe_fwevt_handler(hw, 3983 msg->opcode, msg->data); 3984 } else if (msg->opcode == CPL_FW6_PLD) { 3985 3986 csio_fcoe_fwevt_handler(hw, 3987 msg->opcode, msg->data); 3988 } else { 3989 csio_warn(hw, 3990 "Unhandled FW msg op %x type %x\n", 3991 msg->opcode, msg->type); 3992 CSIO_INC_STATS(hw, n_evt_drop); 3993 } 3994 break; 3995 3996 case CSIO_EVT_MBX: 3997 csio_mberr_worker(hw); 3998 break; 3999 4000 case CSIO_EVT_DEV_LOSS: 4001 memcpy(&rn, evt_msg->data, sizeof(rn)); 4002 csio_rnode_devloss_handler(rn); 4003 break; 4004 4005 default: 4006 csio_warn(hw, "Unhandled event %x on evtq\n", 4007 evt_msg->type); 4008 CSIO_INC_STATS(hw, n_evt_unexp); 4009 break; 4010 } 4011 free_evt: 4012 csio_free_evt(hw, evt_msg); 4013 } 4014 4015 spin_lock_irq(&hw->lock); 4016 } 4017 hw->flags &= ~CSIO_HWF_FWEVT_PENDING; 4018 spin_unlock_irq(&hw->lock); 4019 } 4020 4021 int 4022 csio_fwevtq_handler(struct csio_hw *hw) 4023 { 4024 int rv; 4025 4026 if (csio_q_iqid(hw, hw->fwevt_iq_idx) == CSIO_MAX_QID) { 4027 CSIO_INC_STATS(hw, n_int_stray); 4028 return -EINVAL; 4029 } 4030 4031 rv = csio_wr_process_iq_idx(hw, hw->fwevt_iq_idx, 4032 csio_process_fwevtq_entry, NULL); 4033 return rv; 4034 } 4035 4036 /**************************************************************************** 4037 * Entry points 4038 ****************************************************************************/ 4039 4040 /* Management module */ 4041 /* 4042 * csio_mgmt_req_lookup - Lookup the given IO req exist in Active Q. 4043 * mgmt - mgmt module 4044 * @io_req - io request 4045 * 4046 * Return - 0:if given IO Req exists in active Q. 4047 * -EINVAL :if lookup fails. 4048 */ 4049 int 4050 csio_mgmt_req_lookup(struct csio_mgmtm *mgmtm, struct csio_ioreq *io_req) 4051 { 4052 struct list_head *tmp; 4053 4054 /* Lookup ioreq in the ACTIVEQ */ 4055 list_for_each(tmp, &mgmtm->active_q) { 4056 if (io_req == (struct csio_ioreq *)tmp) 4057 return 0; 4058 } 4059 return -EINVAL; 4060 } 4061 4062 #define ECM_MIN_TMO 1000 /* Minimum timeout value for req */ 4063 4064 /* 4065 * csio_mgmts_tmo_handler - MGMT IO Timeout handler. 4066 * @data - Event data. 4067 * 4068 * Return - none. 4069 */ 4070 static void 4071 csio_mgmt_tmo_handler(uintptr_t data) 4072 { 4073 struct csio_mgmtm *mgmtm = (struct csio_mgmtm *) data; 4074 struct list_head *tmp; 4075 struct csio_ioreq *io_req; 4076 4077 csio_dbg(mgmtm->hw, "Mgmt timer invoked!\n"); 4078 4079 spin_lock_irq(&mgmtm->hw->lock); 4080 4081 list_for_each(tmp, &mgmtm->active_q) { 4082 io_req = (struct csio_ioreq *) tmp; 4083 io_req->tmo -= min_t(uint32_t, io_req->tmo, ECM_MIN_TMO); 4084 4085 if (!io_req->tmo) { 4086 /* Dequeue the request from retry Q. */ 4087 tmp = csio_list_prev(tmp); 4088 list_del_init(&io_req->sm.sm_list); 4089 if (io_req->io_cbfn) { 4090 /* io_req will be freed by completion handler */ 4091 io_req->wr_status = -ETIMEDOUT; 4092 io_req->io_cbfn(mgmtm->hw, io_req); 4093 } else { 4094 CSIO_DB_ASSERT(0); 4095 } 4096 } 4097 } 4098 4099 /* If retry queue is not empty, re-arm timer */ 4100 if (!list_empty(&mgmtm->active_q)) 4101 mod_timer(&mgmtm->mgmt_timer, 4102 jiffies + msecs_to_jiffies(ECM_MIN_TMO)); 4103 spin_unlock_irq(&mgmtm->hw->lock); 4104 } 4105 4106 static void 4107 csio_mgmtm_cleanup(struct csio_mgmtm *mgmtm) 4108 { 4109 struct csio_hw *hw = mgmtm->hw; 4110 struct csio_ioreq *io_req; 4111 struct list_head *tmp; 4112 uint32_t count; 4113 4114 count = 30; 4115 /* Wait for all outstanding req to complete gracefully */ 4116 while ((!list_empty(&mgmtm->active_q)) && count--) { 4117 spin_unlock_irq(&hw->lock); 4118 msleep(2000); 4119 spin_lock_irq(&hw->lock); 4120 } 4121 4122 /* release outstanding req from ACTIVEQ */ 4123 list_for_each(tmp, &mgmtm->active_q) { 4124 io_req = (struct csio_ioreq *) tmp; 4125 tmp = csio_list_prev(tmp); 4126 list_del_init(&io_req->sm.sm_list); 4127 mgmtm->stats.n_active--; 4128 if (io_req->io_cbfn) { 4129 /* io_req will be freed by completion handler */ 4130 io_req->wr_status = -ETIMEDOUT; 4131 io_req->io_cbfn(mgmtm->hw, io_req); 4132 } 4133 } 4134 } 4135 4136 /* 4137 * csio_mgmt_init - Mgmt module init entry point 4138 * @mgmtsm - mgmt module 4139 * @hw - HW module 4140 * 4141 * Initialize mgmt timer, resource wait queue, active queue, 4142 * completion q. Allocate Egress and Ingress 4143 * WR queues and save off the queue index returned by the WR 4144 * module for future use. Allocate and save off mgmt reqs in the 4145 * mgmt_req_freelist for future use. Make sure their SM is initialized 4146 * to uninit state. 4147 * Returns: 0 - on success 4148 * -ENOMEM - on error. 4149 */ 4150 static int 4151 csio_mgmtm_init(struct csio_mgmtm *mgmtm, struct csio_hw *hw) 4152 { 4153 struct timer_list *timer = &mgmtm->mgmt_timer; 4154 4155 init_timer(timer); 4156 timer->function = csio_mgmt_tmo_handler; 4157 timer->data = (unsigned long)mgmtm; 4158 4159 INIT_LIST_HEAD(&mgmtm->active_q); 4160 INIT_LIST_HEAD(&mgmtm->cbfn_q); 4161 4162 mgmtm->hw = hw; 4163 /*mgmtm->iq_idx = hw->fwevt_iq_idx;*/ 4164 4165 return 0; 4166 } 4167 4168 /* 4169 * csio_mgmtm_exit - MGMT module exit entry point 4170 * @mgmtsm - mgmt module 4171 * 4172 * This function called during MGMT module uninit. 4173 * Stop timers, free ioreqs allocated. 4174 * Returns: None 4175 * 4176 */ 4177 static void 4178 csio_mgmtm_exit(struct csio_mgmtm *mgmtm) 4179 { 4180 del_timer_sync(&mgmtm->mgmt_timer); 4181 } 4182 4183 4184 /** 4185 * csio_hw_start - Kicks off the HW State machine 4186 * @hw: Pointer to HW module. 4187 * 4188 * It is assumed that the initialization is a synchronous operation. 4189 * So when we return afer posting the event, the HW SM should be in 4190 * the ready state, if there were no errors during init. 4191 */ 4192 int 4193 csio_hw_start(struct csio_hw *hw) 4194 { 4195 spin_lock_irq(&hw->lock); 4196 csio_post_event(&hw->sm, CSIO_HWE_CFG); 4197 spin_unlock_irq(&hw->lock); 4198 4199 if (csio_is_hw_ready(hw)) 4200 return 0; 4201 else 4202 return -EINVAL; 4203 } 4204 4205 int 4206 csio_hw_stop(struct csio_hw *hw) 4207 { 4208 csio_post_event(&hw->sm, CSIO_HWE_PCI_REMOVE); 4209 4210 if (csio_is_hw_removing(hw)) 4211 return 0; 4212 else 4213 return -EINVAL; 4214 } 4215 4216 /* Max reset retries */ 4217 #define CSIO_MAX_RESET_RETRIES 3 4218 4219 /** 4220 * csio_hw_reset - Reset the hardware 4221 * @hw: HW module. 4222 * 4223 * Caller should hold lock across this function. 4224 */ 4225 int 4226 csio_hw_reset(struct csio_hw *hw) 4227 { 4228 if (!csio_is_hw_master(hw)) 4229 return -EPERM; 4230 4231 if (hw->rst_retries >= CSIO_MAX_RESET_RETRIES) { 4232 csio_dbg(hw, "Max hw reset attempts reached.."); 4233 return -EINVAL; 4234 } 4235 4236 hw->rst_retries++; 4237 csio_post_event(&hw->sm, CSIO_HWE_HBA_RESET); 4238 4239 if (csio_is_hw_ready(hw)) { 4240 hw->rst_retries = 0; 4241 hw->stats.n_reset_start = jiffies_to_msecs(jiffies); 4242 return 0; 4243 } else 4244 return -EINVAL; 4245 } 4246 4247 /* 4248 * csio_hw_get_device_id - Caches the Adapter's vendor & device id. 4249 * @hw: HW module. 4250 */ 4251 static void 4252 csio_hw_get_device_id(struct csio_hw *hw) 4253 { 4254 /* Is the adapter device id cached already ?*/ 4255 if (csio_is_dev_id_cached(hw)) 4256 return; 4257 4258 /* Get the PCI vendor & device id */ 4259 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, 4260 &hw->params.pci.vendor_id); 4261 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, 4262 &hw->params.pci.device_id); 4263 4264 csio_dev_id_cached(hw); 4265 4266 } /* csio_hw_get_device_id */ 4267 4268 /* 4269 * csio_hw_set_description - Set the model, description of the hw. 4270 * @hw: HW module. 4271 * @ven_id: PCI Vendor ID 4272 * @dev_id: PCI Device ID 4273 */ 4274 static void 4275 csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id) 4276 { 4277 uint32_t adap_type, prot_type; 4278 4279 if (ven_id == CSIO_VENDOR_ID) { 4280 prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK); 4281 adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK); 4282 4283 if (prot_type == CSIO_FPGA) { 4284 memcpy(hw->model_desc, 4285 csio_fcoe_adapters[13].description, 32); 4286 } else if (prot_type == CSIO_T4_FCOE_ASIC) { 4287 memcpy(hw->hw_ver, 4288 csio_fcoe_adapters[adap_type].model_no, 16); 4289 memcpy(hw->model_desc, 4290 csio_fcoe_adapters[adap_type].description, 32); 4291 } else { 4292 char tempName[32] = "Chelsio FCoE Controller"; 4293 memcpy(hw->model_desc, tempName, 32); 4294 4295 CSIO_DB_ASSERT(0); 4296 } 4297 } 4298 } /* csio_hw_set_description */ 4299 4300 /** 4301 * csio_hw_init - Initialize HW module. 4302 * @hw: Pointer to HW module. 4303 * 4304 * Initialize the members of the HW module. 4305 */ 4306 int 4307 csio_hw_init(struct csio_hw *hw) 4308 { 4309 int rv = -EINVAL; 4310 uint32_t i; 4311 uint16_t ven_id, dev_id; 4312 struct csio_evt_msg *evt_entry; 4313 4314 INIT_LIST_HEAD(&hw->sm.sm_list); 4315 csio_init_state(&hw->sm, csio_hws_uninit); 4316 spin_lock_init(&hw->lock); 4317 INIT_LIST_HEAD(&hw->sln_head); 4318 4319 /* Get the PCI vendor & device id */ 4320 csio_hw_get_device_id(hw); 4321 4322 strcpy(hw->name, CSIO_HW_NAME); 4323 4324 /* Set the model & its description */ 4325 4326 ven_id = hw->params.pci.vendor_id; 4327 dev_id = hw->params.pci.device_id; 4328 4329 csio_hw_set_description(hw, ven_id, dev_id); 4330 4331 /* Initialize default log level */ 4332 hw->params.log_level = (uint32_t) csio_dbg_level; 4333 4334 csio_set_fwevt_intr_idx(hw, -1); 4335 csio_set_nondata_intr_idx(hw, -1); 4336 4337 /* Init all the modules: Mailbox, WorkRequest and Transport */ 4338 if (csio_mbm_init(csio_hw_to_mbm(hw), hw, csio_hw_mb_timer)) 4339 goto err; 4340 4341 rv = csio_wrm_init(csio_hw_to_wrm(hw), hw); 4342 if (rv) 4343 goto err_mbm_exit; 4344 4345 rv = csio_scsim_init(csio_hw_to_scsim(hw), hw); 4346 if (rv) 4347 goto err_wrm_exit; 4348 4349 rv = csio_mgmtm_init(csio_hw_to_mgmtm(hw), hw); 4350 if (rv) 4351 goto err_scsim_exit; 4352 /* Pre-allocate evtq and initialize them */ 4353 INIT_LIST_HEAD(&hw->evt_active_q); 4354 INIT_LIST_HEAD(&hw->evt_free_q); 4355 for (i = 0; i < csio_evtq_sz; i++) { 4356 4357 evt_entry = kzalloc(sizeof(struct csio_evt_msg), GFP_KERNEL); 4358 if (!evt_entry) { 4359 csio_err(hw, "Failed to initialize eventq"); 4360 goto err_evtq_cleanup; 4361 } 4362 4363 list_add_tail(&evt_entry->list, &hw->evt_free_q); 4364 CSIO_INC_STATS(hw, n_evt_freeq); 4365 } 4366 4367 hw->dev_num = dev_num; 4368 dev_num++; 4369 4370 return 0; 4371 4372 err_evtq_cleanup: 4373 csio_evtq_cleanup(hw); 4374 csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); 4375 err_scsim_exit: 4376 csio_scsim_exit(csio_hw_to_scsim(hw)); 4377 err_wrm_exit: 4378 csio_wrm_exit(csio_hw_to_wrm(hw), hw); 4379 err_mbm_exit: 4380 csio_mbm_exit(csio_hw_to_mbm(hw)); 4381 err: 4382 return rv; 4383 } 4384 4385 /** 4386 * csio_hw_exit - Un-initialize HW module. 4387 * @hw: Pointer to HW module. 4388 * 4389 */ 4390 void 4391 csio_hw_exit(struct csio_hw *hw) 4392 { 4393 csio_evtq_cleanup(hw); 4394 csio_mgmtm_exit(csio_hw_to_mgmtm(hw)); 4395 csio_scsim_exit(csio_hw_to_scsim(hw)); 4396 csio_wrm_exit(csio_hw_to_wrm(hw), hw); 4397 csio_mbm_exit(csio_hw_to_mbm(hw)); 4398 } 4399