1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Car PWM Timer driver 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/log2.h> 12 #include <linux/math64.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pwm.h> 18 #include <linux/slab.h> 19 20 #define RCAR_PWM_MAX_DIVISION 24 21 #define RCAR_PWM_MAX_CYCLE 1023 22 23 #define RCAR_PWMCR 0x00 24 #define RCAR_PWMCR_CC0_MASK 0x000f0000 25 #define RCAR_PWMCR_CC0_SHIFT 16 26 #define RCAR_PWMCR_CCMD BIT(15) 27 #define RCAR_PWMCR_SYNC BIT(11) 28 #define RCAR_PWMCR_SS0 BIT(4) 29 #define RCAR_PWMCR_EN0 BIT(0) 30 31 #define RCAR_PWMCNT 0x04 32 #define RCAR_PWMCNT_CYC0_MASK 0x03ff0000 33 #define RCAR_PWMCNT_CYC0_SHIFT 16 34 #define RCAR_PWMCNT_PH0_MASK 0x000003ff 35 #define RCAR_PWMCNT_PH0_SHIFT 0 36 37 struct rcar_pwm_chip { 38 struct pwm_chip chip; 39 void __iomem *base; 40 struct clk *clk; 41 }; 42 43 static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip) 44 { 45 return container_of(chip, struct rcar_pwm_chip, chip); 46 } 47 48 static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data, 49 unsigned int offset) 50 { 51 writel(data, rp->base + offset); 52 } 53 54 static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset) 55 { 56 return readl(rp->base + offset); 57 } 58 59 static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data, 60 unsigned int offset) 61 { 62 u32 value; 63 64 value = rcar_pwm_read(rp, offset); 65 value &= ~mask; 66 value |= data & mask; 67 rcar_pwm_write(rp, value, offset); 68 } 69 70 static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns) 71 { 72 unsigned long clk_rate = clk_get_rate(rp->clk); 73 u64 div, tmp; 74 75 if (clk_rate == 0) 76 return -EINVAL; 77 78 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE; 79 tmp = (u64)period_ns * clk_rate + div - 1; 80 tmp = div64_u64(tmp, div); 81 div = ilog2(tmp - 1) + 1; 82 83 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE; 84 } 85 86 static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp, 87 unsigned int div) 88 { 89 u32 value; 90 91 value = rcar_pwm_read(rp, RCAR_PWMCR); 92 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK); 93 94 if (div & 1) 95 value |= RCAR_PWMCR_CCMD; 96 97 div >>= 1; 98 99 value |= div << RCAR_PWMCR_CC0_SHIFT; 100 rcar_pwm_write(rp, value, RCAR_PWMCR); 101 } 102 103 static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns, 104 int period_ns) 105 { 106 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */ 107 unsigned long clk_rate = clk_get_rate(rp->clk); 108 u32 cyc, ph; 109 110 one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div); 111 do_div(one_cycle, clk_rate); 112 113 tmp = period_ns * 100ULL; 114 do_div(tmp, one_cycle); 115 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK; 116 117 tmp = duty_ns * 100ULL; 118 do_div(tmp, one_cycle); 119 ph = tmp & RCAR_PWMCNT_PH0_MASK; 120 121 /* Avoid prohibited setting */ 122 if (cyc == 0 || ph == 0) 123 return -EINVAL; 124 125 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT); 126 127 return 0; 128 } 129 130 static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 131 { 132 return pm_runtime_get_sync(chip->dev); 133 } 134 135 static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 136 { 137 pm_runtime_put(chip->dev); 138 } 139 140 static int rcar_pwm_enable(struct rcar_pwm_chip *rp) 141 { 142 u32 value; 143 144 /* Don't enable the PWM device if CYC0 or PH0 is 0 */ 145 value = rcar_pwm_read(rp, RCAR_PWMCNT); 146 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 || 147 (value & RCAR_PWMCNT_PH0_MASK) == 0) 148 return -EINVAL; 149 150 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR); 151 152 return 0; 153 } 154 155 static void rcar_pwm_disable(struct rcar_pwm_chip *rp) 156 { 157 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR); 158 } 159 160 static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 161 struct pwm_state *state) 162 { 163 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip); 164 struct pwm_state cur_state; 165 int div, ret; 166 167 /* This HW/driver only supports normal polarity */ 168 pwm_get_state(pwm, &cur_state); 169 if (state->polarity != PWM_POLARITY_NORMAL) 170 return -ENOTSUPP; 171 172 if (!state->enabled) { 173 rcar_pwm_disable(rp); 174 return 0; 175 } 176 177 div = rcar_pwm_get_clock_division(rp, state->period); 178 if (div < 0) 179 return div; 180 181 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR); 182 183 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period); 184 if (!ret) 185 rcar_pwm_set_clock_control(rp, div); 186 187 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */ 188 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR); 189 190 if (!ret && state->enabled) 191 ret = rcar_pwm_enable(rp); 192 193 return ret; 194 } 195 196 static const struct pwm_ops rcar_pwm_ops = { 197 .request = rcar_pwm_request, 198 .free = rcar_pwm_free, 199 .apply = rcar_pwm_apply, 200 .owner = THIS_MODULE, 201 }; 202 203 static int rcar_pwm_probe(struct platform_device *pdev) 204 { 205 struct rcar_pwm_chip *rcar_pwm; 206 struct resource *res; 207 int ret; 208 209 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL); 210 if (rcar_pwm == NULL) 211 return -ENOMEM; 212 213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 214 rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res); 215 if (IS_ERR(rcar_pwm->base)) 216 return PTR_ERR(rcar_pwm->base); 217 218 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL); 219 if (IS_ERR(rcar_pwm->clk)) { 220 dev_err(&pdev->dev, "cannot get clock\n"); 221 return PTR_ERR(rcar_pwm->clk); 222 } 223 224 platform_set_drvdata(pdev, rcar_pwm); 225 226 rcar_pwm->chip.dev = &pdev->dev; 227 rcar_pwm->chip.ops = &rcar_pwm_ops; 228 rcar_pwm->chip.base = -1; 229 rcar_pwm->chip.npwm = 1; 230 231 ret = pwmchip_add(&rcar_pwm->chip); 232 if (ret < 0) { 233 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret); 234 return ret; 235 } 236 237 pm_runtime_enable(&pdev->dev); 238 239 return 0; 240 } 241 242 static int rcar_pwm_remove(struct platform_device *pdev) 243 { 244 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev); 245 246 pm_runtime_disable(&pdev->dev); 247 248 return pwmchip_remove(&rcar_pwm->chip); 249 } 250 251 static const struct of_device_id rcar_pwm_of_table[] = { 252 { .compatible = "renesas,pwm-rcar", }, 253 { }, 254 }; 255 MODULE_DEVICE_TABLE(of, rcar_pwm_of_table); 256 257 #ifdef CONFIG_PM_SLEEP 258 static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev) 259 { 260 struct rcar_pwm_chip *rcar_pwm = dev_get_drvdata(dev); 261 struct pwm_chip *chip = &rcar_pwm->chip; 262 263 return &chip->pwms[0]; 264 } 265 266 static int rcar_pwm_suspend(struct device *dev) 267 { 268 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev); 269 270 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 271 return 0; 272 273 pm_runtime_put(dev); 274 275 return 0; 276 } 277 278 static int rcar_pwm_resume(struct device *dev) 279 { 280 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev); 281 struct pwm_state state; 282 283 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 284 return 0; 285 286 pm_runtime_get_sync(dev); 287 288 pwm_get_state(pwm, &state); 289 290 return rcar_pwm_apply(pwm->chip, pwm, &state); 291 } 292 #endif /* CONFIG_PM_SLEEP */ 293 static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume); 294 295 static struct platform_driver rcar_pwm_driver = { 296 .probe = rcar_pwm_probe, 297 .remove = rcar_pwm_remove, 298 .driver = { 299 .name = "pwm-rcar", 300 .pm = &rcar_pwm_pm_ops, 301 .of_match_table = of_match_ptr(rcar_pwm_of_table), 302 } 303 }; 304 module_platform_driver(rcar_pwm_driver); 305 306 MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>"); 307 MODULE_DESCRIPTION("Renesas PWM Timer Driver"); 308 MODULE_LICENSE("GPL v2"); 309 MODULE_ALIAS("platform:pwm-rcar"); 310