1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Pinctrl driver for Rockchip SoCs 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * http://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/bitops.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/pinctrl/machine.h> 26 #include <linux/pinctrl/pinconf.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/pinctrl/pinmux.h> 29 #include <linux/pinctrl/pinconf-generic.h> 30 #include <linux/irqchip/chained_irq.h> 31 #include <linux/clk.h> 32 #include <linux/regmap.h> 33 #include <linux/mfd/syscon.h> 34 #include <dt-bindings/pinctrl/rockchip.h> 35 36 #include "core.h" 37 #include "pinconf.h" 38 39 /* GPIO control registers */ 40 #define GPIO_SWPORT_DR 0x00 41 #define GPIO_SWPORT_DDR 0x04 42 #define GPIO_INTEN 0x30 43 #define GPIO_INTMASK 0x34 44 #define GPIO_INTTYPE_LEVEL 0x38 45 #define GPIO_INT_POLARITY 0x3c 46 #define GPIO_INT_STATUS 0x40 47 #define GPIO_INT_RAWSTATUS 0x44 48 #define GPIO_DEBOUNCE 0x48 49 #define GPIO_PORTS_EOI 0x4c 50 #define GPIO_EXT_PORT 0x50 51 #define GPIO_LS_SYNC 0x60 52 53 enum rockchip_pinctrl_type { 54 PX30, 55 RV1108, 56 RK2928, 57 RK3066B, 58 RK3128, 59 RK3188, 60 RK3288, 61 RK3308, 62 RK3368, 63 RK3399, 64 }; 65 66 /** 67 * Encode variants of iomux registers into a type variable 68 */ 69 #define IOMUX_GPIO_ONLY BIT(0) 70 #define IOMUX_WIDTH_4BIT BIT(1) 71 #define IOMUX_SOURCE_PMU BIT(2) 72 #define IOMUX_UNROUTED BIT(3) 73 #define IOMUX_WIDTH_3BIT BIT(4) 74 #define IOMUX_WIDTH_2BIT BIT(5) 75 76 /** 77 * @type: iomux variant using IOMUX_* constants 78 * @offset: if initialized to -1 it will be autocalculated, by specifying 79 * an initial offset value the relevant source offset can be reset 80 * to a new value for autocalculating the following iomux registers. 81 */ 82 struct rockchip_iomux { 83 int type; 84 int offset; 85 }; 86 87 /** 88 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 89 */ 90 enum rockchip_pin_drv_type { 91 DRV_TYPE_IO_DEFAULT = 0, 92 DRV_TYPE_IO_1V8_OR_3V0, 93 DRV_TYPE_IO_1V8_ONLY, 94 DRV_TYPE_IO_1V8_3V0_AUTO, 95 DRV_TYPE_IO_3V3_ONLY, 96 DRV_TYPE_MAX 97 }; 98 99 /** 100 * enum type index corresponding to rockchip_pull_list arrays index. 101 */ 102 enum rockchip_pin_pull_type { 103 PULL_TYPE_IO_DEFAULT = 0, 104 PULL_TYPE_IO_1V8_ONLY, 105 PULL_TYPE_MAX 106 }; 107 108 /** 109 * @drv_type: drive strength variant using rockchip_perpin_drv_type 110 * @offset: if initialized to -1 it will be autocalculated, by specifying 111 * an initial offset value the relevant source offset can be reset 112 * to a new value for autocalculating the following drive strength 113 * registers. if used chips own cal_drv func instead to calculate 114 * registers offset, the variant could be ignored. 115 */ 116 struct rockchip_drv { 117 enum rockchip_pin_drv_type drv_type; 118 int offset; 119 }; 120 121 /** 122 * @reg_base: register base of the gpio bank 123 * @reg_pull: optional separate register for additional pull settings 124 * @clk: clock of the gpio bank 125 * @irq: interrupt of the gpio bank 126 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 127 * @pin_base: first pin number 128 * @nr_pins: number of pins in this bank 129 * @name: name of the bank 130 * @bank_num: number of the bank, to account for holes 131 * @iomux: array describing the 4 iomux sources of the bank 132 * @drv: array describing the 4 drive strength sources of the bank 133 * @pull_type: array describing the 4 pull type sources of the bank 134 * @valid: is all necessary information present 135 * @of_node: dt node of this bank 136 * @drvdata: common pinctrl basedata 137 * @domain: irqdomain of the gpio bank 138 * @gpio_chip: gpiolib chip 139 * @grange: gpio range 140 * @slock: spinlock for the gpio bank 141 * @route_mask: bits describing the routing pins of per bank 142 */ 143 struct rockchip_pin_bank { 144 void __iomem *reg_base; 145 struct regmap *regmap_pull; 146 struct clk *clk; 147 int irq; 148 u32 saved_masks; 149 u32 pin_base; 150 u8 nr_pins; 151 char *name; 152 u8 bank_num; 153 struct rockchip_iomux iomux[4]; 154 struct rockchip_drv drv[4]; 155 enum rockchip_pin_pull_type pull_type[4]; 156 bool valid; 157 struct device_node *of_node; 158 struct rockchip_pinctrl *drvdata; 159 struct irq_domain *domain; 160 struct gpio_chip gpio_chip; 161 struct pinctrl_gpio_range grange; 162 raw_spinlock_t slock; 163 u32 toggle_edge_mode; 164 u32 recalced_mask; 165 u32 route_mask; 166 }; 167 168 #define PIN_BANK(id, pins, label) \ 169 { \ 170 .bank_num = id, \ 171 .nr_pins = pins, \ 172 .name = label, \ 173 .iomux = { \ 174 { .offset = -1 }, \ 175 { .offset = -1 }, \ 176 { .offset = -1 }, \ 177 { .offset = -1 }, \ 178 }, \ 179 } 180 181 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 182 { \ 183 .bank_num = id, \ 184 .nr_pins = pins, \ 185 .name = label, \ 186 .iomux = { \ 187 { .type = iom0, .offset = -1 }, \ 188 { .type = iom1, .offset = -1 }, \ 189 { .type = iom2, .offset = -1 }, \ 190 { .type = iom3, .offset = -1 }, \ 191 }, \ 192 } 193 194 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 195 { \ 196 .bank_num = id, \ 197 .nr_pins = pins, \ 198 .name = label, \ 199 .iomux = { \ 200 { .offset = -1 }, \ 201 { .offset = -1 }, \ 202 { .offset = -1 }, \ 203 { .offset = -1 }, \ 204 }, \ 205 .drv = { \ 206 { .drv_type = type0, .offset = -1 }, \ 207 { .drv_type = type1, .offset = -1 }, \ 208 { .drv_type = type2, .offset = -1 }, \ 209 { .drv_type = type3, .offset = -1 }, \ 210 }, \ 211 } 212 213 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 214 drv2, drv3, pull0, pull1, \ 215 pull2, pull3) \ 216 { \ 217 .bank_num = id, \ 218 .nr_pins = pins, \ 219 .name = label, \ 220 .iomux = { \ 221 { .offset = -1 }, \ 222 { .offset = -1 }, \ 223 { .offset = -1 }, \ 224 { .offset = -1 }, \ 225 }, \ 226 .drv = { \ 227 { .drv_type = drv0, .offset = -1 }, \ 228 { .drv_type = drv1, .offset = -1 }, \ 229 { .drv_type = drv2, .offset = -1 }, \ 230 { .drv_type = drv3, .offset = -1 }, \ 231 }, \ 232 .pull_type[0] = pull0, \ 233 .pull_type[1] = pull1, \ 234 .pull_type[2] = pull2, \ 235 .pull_type[3] = pull3, \ 236 } 237 238 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 239 iom2, iom3, drv0, drv1, drv2, \ 240 drv3, offset0, offset1, \ 241 offset2, offset3) \ 242 { \ 243 .bank_num = id, \ 244 .nr_pins = pins, \ 245 .name = label, \ 246 .iomux = { \ 247 { .type = iom0, .offset = -1 }, \ 248 { .type = iom1, .offset = -1 }, \ 249 { .type = iom2, .offset = -1 }, \ 250 { .type = iom3, .offset = -1 }, \ 251 }, \ 252 .drv = { \ 253 { .drv_type = drv0, .offset = offset0 }, \ 254 { .drv_type = drv1, .offset = offset1 }, \ 255 { .drv_type = drv2, .offset = offset2 }, \ 256 { .drv_type = drv3, .offset = offset3 }, \ 257 }, \ 258 } 259 260 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 261 label, iom0, iom1, iom2, \ 262 iom3, drv0, drv1, drv2, \ 263 drv3, offset0, offset1, \ 264 offset2, offset3, pull0, \ 265 pull1, pull2, pull3) \ 266 { \ 267 .bank_num = id, \ 268 .nr_pins = pins, \ 269 .name = label, \ 270 .iomux = { \ 271 { .type = iom0, .offset = -1 }, \ 272 { .type = iom1, .offset = -1 }, \ 273 { .type = iom2, .offset = -1 }, \ 274 { .type = iom3, .offset = -1 }, \ 275 }, \ 276 .drv = { \ 277 { .drv_type = drv0, .offset = offset0 }, \ 278 { .drv_type = drv1, .offset = offset1 }, \ 279 { .drv_type = drv2, .offset = offset2 }, \ 280 { .drv_type = drv3, .offset = offset3 }, \ 281 }, \ 282 .pull_type[0] = pull0, \ 283 .pull_type[1] = pull1, \ 284 .pull_type[2] = pull2, \ 285 .pull_type[3] = pull3, \ 286 } 287 288 /** 289 * struct rockchip_mux_recalced_data: represent a pin iomux data. 290 * @num: bank number. 291 * @pin: pin number. 292 * @bit: index at register. 293 * @reg: register offset. 294 * @mask: mask bit 295 */ 296 struct rockchip_mux_recalced_data { 297 u8 num; 298 u8 pin; 299 u32 reg; 300 u8 bit; 301 u8 mask; 302 }; 303 304 enum rockchip_mux_route_location { 305 ROCKCHIP_ROUTE_SAME = 0, 306 ROCKCHIP_ROUTE_PMU, 307 ROCKCHIP_ROUTE_GRF, 308 }; 309 310 /** 311 * struct rockchip_mux_recalced_data: represent a pin iomux data. 312 * @bank_num: bank number. 313 * @pin: index at register or used to calc index. 314 * @func: the min pin. 315 * @route_offset: the max pin. 316 * @route_val: the register offset. 317 */ 318 struct rockchip_mux_route_data { 319 u8 bank_num; 320 u8 pin; 321 u8 func; 322 enum rockchip_mux_route_location route_location; 323 u32 route_offset; 324 u32 route_val; 325 }; 326 327 /** 328 */ 329 struct rockchip_pin_ctrl { 330 struct rockchip_pin_bank *pin_banks; 331 u32 nr_banks; 332 u32 nr_pins; 333 char *label; 334 enum rockchip_pinctrl_type type; 335 int grf_mux_offset; 336 int pmu_mux_offset; 337 int grf_drv_offset; 338 int pmu_drv_offset; 339 struct rockchip_mux_recalced_data *iomux_recalced; 340 u32 niomux_recalced; 341 struct rockchip_mux_route_data *iomux_routes; 342 u32 niomux_routes; 343 344 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 345 int pin_num, struct regmap **regmap, 346 int *reg, u8 *bit); 347 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 348 int pin_num, struct regmap **regmap, 349 int *reg, u8 *bit); 350 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 351 int pin_num, struct regmap **regmap, 352 int *reg, u8 *bit); 353 }; 354 355 struct rockchip_pin_config { 356 unsigned int func; 357 unsigned long *configs; 358 unsigned int nconfigs; 359 }; 360 361 /** 362 * struct rockchip_pin_group: represent group of pins of a pinmux function. 363 * @name: name of the pin group, used to lookup the group. 364 * @pins: the pins included in this group. 365 * @npins: number of pins included in this group. 366 * @func: the mux function number to be programmed when selected. 367 * @configs: the config values to be set for each pin 368 * @nconfigs: number of configs for each pin 369 */ 370 struct rockchip_pin_group { 371 const char *name; 372 unsigned int npins; 373 unsigned int *pins; 374 struct rockchip_pin_config *data; 375 }; 376 377 /** 378 * struct rockchip_pmx_func: represent a pin function. 379 * @name: name of the pin function, used to lookup the function. 380 * @groups: one or more names of pin groups that provide this function. 381 * @num_groups: number of groups included in @groups. 382 */ 383 struct rockchip_pmx_func { 384 const char *name; 385 const char **groups; 386 u8 ngroups; 387 }; 388 389 struct rockchip_pinctrl { 390 struct regmap *regmap_base; 391 int reg_size; 392 struct regmap *regmap_pull; 393 struct regmap *regmap_pmu; 394 struct device *dev; 395 struct rockchip_pin_ctrl *ctrl; 396 struct pinctrl_desc pctl; 397 struct pinctrl_dev *pctl_dev; 398 struct rockchip_pin_group *groups; 399 unsigned int ngroups; 400 struct rockchip_pmx_func *functions; 401 unsigned int nfunctions; 402 }; 403 404 static struct regmap_config rockchip_regmap_config = { 405 .reg_bits = 32, 406 .val_bits = 32, 407 .reg_stride = 4, 408 }; 409 410 static inline const struct rockchip_pin_group *pinctrl_name_to_group( 411 const struct rockchip_pinctrl *info, 412 const char *name) 413 { 414 int i; 415 416 for (i = 0; i < info->ngroups; i++) { 417 if (!strcmp(info->groups[i].name, name)) 418 return &info->groups[i]; 419 } 420 421 return NULL; 422 } 423 424 /* 425 * given a pin number that is local to a pin controller, find out the pin bank 426 * and the register base of the pin bank. 427 */ 428 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, 429 unsigned pin) 430 { 431 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 432 433 while (pin >= (b->pin_base + b->nr_pins)) 434 b++; 435 436 return b; 437 } 438 439 static struct rockchip_pin_bank *bank_num_to_bank( 440 struct rockchip_pinctrl *info, 441 unsigned num) 442 { 443 struct rockchip_pin_bank *b = info->ctrl->pin_banks; 444 int i; 445 446 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { 447 if (b->bank_num == num) 448 return b; 449 } 450 451 return ERR_PTR(-EINVAL); 452 } 453 454 /* 455 * Pinctrl_ops handling 456 */ 457 458 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) 459 { 460 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 461 462 return info->ngroups; 463 } 464 465 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, 466 unsigned selector) 467 { 468 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 469 470 return info->groups[selector].name; 471 } 472 473 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, 474 unsigned selector, const unsigned **pins, 475 unsigned *npins) 476 { 477 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 478 479 if (selector >= info->ngroups) 480 return -EINVAL; 481 482 *pins = info->groups[selector].pins; 483 *npins = info->groups[selector].npins; 484 485 return 0; 486 } 487 488 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, 489 struct device_node *np, 490 struct pinctrl_map **map, unsigned *num_maps) 491 { 492 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 493 const struct rockchip_pin_group *grp; 494 struct pinctrl_map *new_map; 495 struct device_node *parent; 496 int map_num = 1; 497 int i; 498 499 /* 500 * first find the group of this node and check if we need to create 501 * config maps for pins 502 */ 503 grp = pinctrl_name_to_group(info, np->name); 504 if (!grp) { 505 dev_err(info->dev, "unable to find group for node %pOFn\n", 506 np); 507 return -EINVAL; 508 } 509 510 map_num += grp->npins; 511 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), 512 GFP_KERNEL); 513 if (!new_map) 514 return -ENOMEM; 515 516 *map = new_map; 517 *num_maps = map_num; 518 519 /* create mux map */ 520 parent = of_get_parent(np); 521 if (!parent) { 522 devm_kfree(pctldev->dev, new_map); 523 return -EINVAL; 524 } 525 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; 526 new_map[0].data.mux.function = parent->name; 527 new_map[0].data.mux.group = np->name; 528 of_node_put(parent); 529 530 /* create config map */ 531 new_map++; 532 for (i = 0; i < grp->npins; i++) { 533 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; 534 new_map[i].data.configs.group_or_pin = 535 pin_get_name(pctldev, grp->pins[i]); 536 new_map[i].data.configs.configs = grp->data[i].configs; 537 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; 538 } 539 540 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", 541 (*map)->data.mux.function, (*map)->data.mux.group, map_num); 542 543 return 0; 544 } 545 546 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, 547 struct pinctrl_map *map, unsigned num_maps) 548 { 549 } 550 551 static const struct pinctrl_ops rockchip_pctrl_ops = { 552 .get_groups_count = rockchip_get_groups_count, 553 .get_group_name = rockchip_get_group_name, 554 .get_group_pins = rockchip_get_group_pins, 555 .dt_node_to_map = rockchip_dt_node_to_map, 556 .dt_free_map = rockchip_dt_free_map, 557 }; 558 559 /* 560 * Hardware access 561 */ 562 563 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 564 { 565 .num = 1, 566 .pin = 0, 567 .reg = 0x418, 568 .bit = 0, 569 .mask = 0x3 570 }, { 571 .num = 1, 572 .pin = 1, 573 .reg = 0x418, 574 .bit = 2, 575 .mask = 0x3 576 }, { 577 .num = 1, 578 .pin = 2, 579 .reg = 0x418, 580 .bit = 4, 581 .mask = 0x3 582 }, { 583 .num = 1, 584 .pin = 3, 585 .reg = 0x418, 586 .bit = 6, 587 .mask = 0x3 588 }, { 589 .num = 1, 590 .pin = 4, 591 .reg = 0x418, 592 .bit = 8, 593 .mask = 0x3 594 }, { 595 .num = 1, 596 .pin = 5, 597 .reg = 0x418, 598 .bit = 10, 599 .mask = 0x3 600 }, { 601 .num = 1, 602 .pin = 6, 603 .reg = 0x418, 604 .bit = 12, 605 .mask = 0x3 606 }, { 607 .num = 1, 608 .pin = 7, 609 .reg = 0x418, 610 .bit = 14, 611 .mask = 0x3 612 }, { 613 .num = 1, 614 .pin = 8, 615 .reg = 0x41c, 616 .bit = 0, 617 .mask = 0x3 618 }, { 619 .num = 1, 620 .pin = 9, 621 .reg = 0x41c, 622 .bit = 2, 623 .mask = 0x3 624 }, 625 }; 626 627 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 628 { 629 .num = 2, 630 .pin = 20, 631 .reg = 0xe8, 632 .bit = 0, 633 .mask = 0x7 634 }, { 635 .num = 2, 636 .pin = 21, 637 .reg = 0xe8, 638 .bit = 4, 639 .mask = 0x7 640 }, { 641 .num = 2, 642 .pin = 22, 643 .reg = 0xe8, 644 .bit = 8, 645 .mask = 0x7 646 }, { 647 .num = 2, 648 .pin = 23, 649 .reg = 0xe8, 650 .bit = 12, 651 .mask = 0x7 652 }, { 653 .num = 2, 654 .pin = 24, 655 .reg = 0xd4, 656 .bit = 12, 657 .mask = 0x7 658 }, 659 }; 660 661 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 662 { 663 .num = 1, 664 .pin = 14, 665 .reg = 0x28, 666 .bit = 12, 667 .mask = 0xf 668 }, { 669 .num = 1, 670 .pin = 15, 671 .reg = 0x2c, 672 .bit = 0, 673 .mask = 0x3 674 }, { 675 .num = 1, 676 .pin = 18, 677 .reg = 0x30, 678 .bit = 4, 679 .mask = 0xf 680 }, { 681 .num = 1, 682 .pin = 19, 683 .reg = 0x30, 684 .bit = 8, 685 .mask = 0xf 686 }, { 687 .num = 1, 688 .pin = 20, 689 .reg = 0x30, 690 .bit = 12, 691 .mask = 0xf 692 }, { 693 .num = 1, 694 .pin = 21, 695 .reg = 0x34, 696 .bit = 0, 697 .mask = 0xf 698 }, { 699 .num = 1, 700 .pin = 22, 701 .reg = 0x34, 702 .bit = 4, 703 .mask = 0xf 704 }, { 705 .num = 1, 706 .pin = 23, 707 .reg = 0x34, 708 .bit = 8, 709 .mask = 0xf 710 }, { 711 .num = 3, 712 .pin = 12, 713 .reg = 0x68, 714 .bit = 8, 715 .mask = 0xf 716 }, { 717 .num = 3, 718 .pin = 13, 719 .reg = 0x68, 720 .bit = 12, 721 .mask = 0xf 722 }, { 723 .num = 2, 724 .pin = 2, 725 .reg = 0x608, 726 .bit = 0, 727 .mask = 0x7 728 }, { 729 .num = 2, 730 .pin = 3, 731 .reg = 0x608, 732 .bit = 4, 733 .mask = 0x7 734 }, { 735 .num = 2, 736 .pin = 16, 737 .reg = 0x610, 738 .bit = 8, 739 .mask = 0x7 740 }, { 741 .num = 3, 742 .pin = 10, 743 .reg = 0x610, 744 .bit = 0, 745 .mask = 0x7 746 }, { 747 .num = 3, 748 .pin = 11, 749 .reg = 0x610, 750 .bit = 4, 751 .mask = 0x7 752 }, 753 }; 754 755 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 756 { 757 .num = 2, 758 .pin = 12, 759 .reg = 0x24, 760 .bit = 8, 761 .mask = 0x3 762 }, { 763 .num = 2, 764 .pin = 15, 765 .reg = 0x28, 766 .bit = 0, 767 .mask = 0x7 768 }, { 769 .num = 2, 770 .pin = 23, 771 .reg = 0x30, 772 .bit = 14, 773 .mask = 0x3 774 }, 775 }; 776 777 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 778 int *reg, u8 *bit, int *mask) 779 { 780 struct rockchip_pinctrl *info = bank->drvdata; 781 struct rockchip_pin_ctrl *ctrl = info->ctrl; 782 struct rockchip_mux_recalced_data *data; 783 int i; 784 785 for (i = 0; i < ctrl->niomux_recalced; i++) { 786 data = &ctrl->iomux_recalced[i]; 787 if (data->num == bank->bank_num && 788 data->pin == pin) 789 break; 790 } 791 792 if (i >= ctrl->niomux_recalced) 793 return; 794 795 *reg = data->reg; 796 *mask = data->mask; 797 *bit = data->bit; 798 } 799 800 static struct rockchip_mux_route_data px30_mux_route_data[] = { 801 { 802 /* cif-d2m0 */ 803 .bank_num = 2, 804 .pin = 0, 805 .func = 1, 806 .route_offset = 0x184, 807 .route_val = BIT(16 + 7), 808 }, { 809 /* cif-d2m1 */ 810 .bank_num = 3, 811 .pin = 3, 812 .func = 3, 813 .route_offset = 0x184, 814 .route_val = BIT(16 + 7) | BIT(7), 815 }, { 816 /* pdm-m0 */ 817 .bank_num = 3, 818 .pin = 22, 819 .func = 2, 820 .route_offset = 0x184, 821 .route_val = BIT(16 + 8), 822 }, { 823 /* pdm-m1 */ 824 .bank_num = 2, 825 .pin = 22, 826 .func = 1, 827 .route_offset = 0x184, 828 .route_val = BIT(16 + 8) | BIT(8), 829 }, { 830 /* uart2-rxm0 */ 831 .bank_num = 1, 832 .pin = 27, 833 .func = 2, 834 .route_offset = 0x184, 835 .route_val = BIT(16 + 10), 836 }, { 837 /* uart2-rxm1 */ 838 .bank_num = 2, 839 .pin = 14, 840 .func = 2, 841 .route_offset = 0x184, 842 .route_val = BIT(16 + 10) | BIT(10), 843 }, { 844 /* uart3-rxm0 */ 845 .bank_num = 0, 846 .pin = 17, 847 .func = 2, 848 .route_offset = 0x184, 849 .route_val = BIT(16 + 9), 850 }, { 851 /* uart3-rxm1 */ 852 .bank_num = 1, 853 .pin = 15, 854 .func = 2, 855 .route_offset = 0x184, 856 .route_val = BIT(16 + 9) | BIT(9), 857 }, 858 }; 859 860 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 861 { 862 /* spi-0 */ 863 .bank_num = 1, 864 .pin = 10, 865 .func = 1, 866 .route_offset = 0x144, 867 .route_val = BIT(16 + 3) | BIT(16 + 4), 868 }, { 869 /* spi-1 */ 870 .bank_num = 1, 871 .pin = 27, 872 .func = 3, 873 .route_offset = 0x144, 874 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 875 }, { 876 /* spi-2 */ 877 .bank_num = 0, 878 .pin = 13, 879 .func = 2, 880 .route_offset = 0x144, 881 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 882 }, { 883 /* i2s-0 */ 884 .bank_num = 1, 885 .pin = 5, 886 .func = 1, 887 .route_offset = 0x144, 888 .route_val = BIT(16 + 5), 889 }, { 890 /* i2s-1 */ 891 .bank_num = 0, 892 .pin = 14, 893 .func = 1, 894 .route_offset = 0x144, 895 .route_val = BIT(16 + 5) | BIT(5), 896 }, { 897 /* emmc-0 */ 898 .bank_num = 1, 899 .pin = 22, 900 .func = 2, 901 .route_offset = 0x144, 902 .route_val = BIT(16 + 6), 903 }, { 904 /* emmc-1 */ 905 .bank_num = 2, 906 .pin = 4, 907 .func = 2, 908 .route_offset = 0x144, 909 .route_val = BIT(16 + 6) | BIT(6), 910 }, 911 }; 912 913 static struct rockchip_mux_route_data rk3188_mux_route_data[] = { 914 { 915 /* non-iomuxed emmc/flash pins on flash-dqs */ 916 .bank_num = 0, 917 .pin = 24, 918 .func = 1, 919 .route_location = ROCKCHIP_ROUTE_GRF, 920 .route_offset = 0xa0, 921 .route_val = BIT(16 + 11), 922 }, { 923 /* non-iomuxed emmc/flash pins on emmc-clk */ 924 .bank_num = 0, 925 .pin = 24, 926 .func = 2, 927 .route_location = ROCKCHIP_ROUTE_GRF, 928 .route_offset = 0xa0, 929 .route_val = BIT(16 + 11) | BIT(11), 930 }, 931 }; 932 933 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 934 { 935 /* pwm0-0 */ 936 .bank_num = 0, 937 .pin = 26, 938 .func = 1, 939 .route_offset = 0x50, 940 .route_val = BIT(16), 941 }, { 942 /* pwm0-1 */ 943 .bank_num = 3, 944 .pin = 21, 945 .func = 1, 946 .route_offset = 0x50, 947 .route_val = BIT(16) | BIT(0), 948 }, { 949 /* pwm1-0 */ 950 .bank_num = 0, 951 .pin = 27, 952 .func = 1, 953 .route_offset = 0x50, 954 .route_val = BIT(16 + 1), 955 }, { 956 /* pwm1-1 */ 957 .bank_num = 0, 958 .pin = 30, 959 .func = 2, 960 .route_offset = 0x50, 961 .route_val = BIT(16 + 1) | BIT(1), 962 }, { 963 /* pwm2-0 */ 964 .bank_num = 0, 965 .pin = 28, 966 .func = 1, 967 .route_offset = 0x50, 968 .route_val = BIT(16 + 2), 969 }, { 970 /* pwm2-1 */ 971 .bank_num = 1, 972 .pin = 12, 973 .func = 2, 974 .route_offset = 0x50, 975 .route_val = BIT(16 + 2) | BIT(2), 976 }, { 977 /* pwm3-0 */ 978 .bank_num = 3, 979 .pin = 26, 980 .func = 1, 981 .route_offset = 0x50, 982 .route_val = BIT(16 + 3), 983 }, { 984 /* pwm3-1 */ 985 .bank_num = 1, 986 .pin = 11, 987 .func = 2, 988 .route_offset = 0x50, 989 .route_val = BIT(16 + 3) | BIT(3), 990 }, { 991 /* sdio-0_d0 */ 992 .bank_num = 1, 993 .pin = 1, 994 .func = 1, 995 .route_offset = 0x50, 996 .route_val = BIT(16 + 4), 997 }, { 998 /* sdio-1_d0 */ 999 .bank_num = 3, 1000 .pin = 2, 1001 .func = 1, 1002 .route_offset = 0x50, 1003 .route_val = BIT(16 + 4) | BIT(4), 1004 }, { 1005 /* spi-0_rx */ 1006 .bank_num = 0, 1007 .pin = 13, 1008 .func = 2, 1009 .route_offset = 0x50, 1010 .route_val = BIT(16 + 5), 1011 }, { 1012 /* spi-1_rx */ 1013 .bank_num = 2, 1014 .pin = 0, 1015 .func = 2, 1016 .route_offset = 0x50, 1017 .route_val = BIT(16 + 5) | BIT(5), 1018 }, { 1019 /* emmc-0_cmd */ 1020 .bank_num = 1, 1021 .pin = 22, 1022 .func = 2, 1023 .route_offset = 0x50, 1024 .route_val = BIT(16 + 7), 1025 }, { 1026 /* emmc-1_cmd */ 1027 .bank_num = 2, 1028 .pin = 4, 1029 .func = 2, 1030 .route_offset = 0x50, 1031 .route_val = BIT(16 + 7) | BIT(7), 1032 }, { 1033 /* uart2-0_rx */ 1034 .bank_num = 1, 1035 .pin = 19, 1036 .func = 2, 1037 .route_offset = 0x50, 1038 .route_val = BIT(16 + 8), 1039 }, { 1040 /* uart2-1_rx */ 1041 .bank_num = 1, 1042 .pin = 10, 1043 .func = 2, 1044 .route_offset = 0x50, 1045 .route_val = BIT(16 + 8) | BIT(8), 1046 }, { 1047 /* uart1-0_rx */ 1048 .bank_num = 1, 1049 .pin = 10, 1050 .func = 1, 1051 .route_offset = 0x50, 1052 .route_val = BIT(16 + 11), 1053 }, { 1054 /* uart1-1_rx */ 1055 .bank_num = 3, 1056 .pin = 13, 1057 .func = 1, 1058 .route_offset = 0x50, 1059 .route_val = BIT(16 + 11) | BIT(11), 1060 }, 1061 }; 1062 1063 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 1064 { 1065 /* edphdmi_cecinoutt1 */ 1066 .bank_num = 7, 1067 .pin = 16, 1068 .func = 2, 1069 .route_offset = 0x264, 1070 .route_val = BIT(16 + 12) | BIT(12), 1071 }, { 1072 /* edphdmi_cecinout */ 1073 .bank_num = 7, 1074 .pin = 23, 1075 .func = 4, 1076 .route_offset = 0x264, 1077 .route_val = BIT(16 + 12), 1078 }, 1079 }; 1080 1081 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 1082 { 1083 /* rtc_clk */ 1084 .bank_num = 0, 1085 .pin = 19, 1086 .func = 1, 1087 .route_offset = 0x314, 1088 .route_val = BIT(16 + 0) | BIT(0), 1089 }, { 1090 /* uart2_rxm0 */ 1091 .bank_num = 1, 1092 .pin = 22, 1093 .func = 2, 1094 .route_offset = 0x314, 1095 .route_val = BIT(16 + 2) | BIT(16 + 3), 1096 }, { 1097 /* uart2_rxm1 */ 1098 .bank_num = 4, 1099 .pin = 26, 1100 .func = 2, 1101 .route_offset = 0x314, 1102 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 1103 }, { 1104 /* i2c3_sdam0 */ 1105 .bank_num = 0, 1106 .pin = 15, 1107 .func = 2, 1108 .route_offset = 0x608, 1109 .route_val = BIT(16 + 8) | BIT(16 + 9), 1110 }, { 1111 /* i2c3_sdam1 */ 1112 .bank_num = 3, 1113 .pin = 12, 1114 .func = 2, 1115 .route_offset = 0x608, 1116 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), 1117 }, { 1118 /* i2c3_sdam2 */ 1119 .bank_num = 2, 1120 .pin = 0, 1121 .func = 3, 1122 .route_offset = 0x608, 1123 .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), 1124 }, { 1125 /* i2s-8ch-1-sclktxm0 */ 1126 .bank_num = 1, 1127 .pin = 3, 1128 .func = 2, 1129 .route_offset = 0x308, 1130 .route_val = BIT(16 + 3), 1131 }, { 1132 /* i2s-8ch-1-sclkrxm0 */ 1133 .bank_num = 1, 1134 .pin = 4, 1135 .func = 2, 1136 .route_offset = 0x308, 1137 .route_val = BIT(16 + 3), 1138 }, { 1139 /* i2s-8ch-1-sclktxm1 */ 1140 .bank_num = 1, 1141 .pin = 13, 1142 .func = 2, 1143 .route_offset = 0x308, 1144 .route_val = BIT(16 + 3) | BIT(3), 1145 }, { 1146 /* i2s-8ch-1-sclkrxm1 */ 1147 .bank_num = 1, 1148 .pin = 14, 1149 .func = 2, 1150 .route_offset = 0x308, 1151 .route_val = BIT(16 + 3) | BIT(3), 1152 }, { 1153 /* pdm-clkm0 */ 1154 .bank_num = 1, 1155 .pin = 4, 1156 .func = 3, 1157 .route_offset = 0x308, 1158 .route_val = BIT(16 + 12) | BIT(16 + 13), 1159 }, { 1160 /* pdm-clkm1 */ 1161 .bank_num = 1, 1162 .pin = 14, 1163 .func = 4, 1164 .route_offset = 0x308, 1165 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1166 }, { 1167 /* pdm-clkm2 */ 1168 .bank_num = 2, 1169 .pin = 6, 1170 .func = 2, 1171 .route_offset = 0x308, 1172 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1173 }, { 1174 /* pdm-clkm-m2 */ 1175 .bank_num = 2, 1176 .pin = 4, 1177 .func = 3, 1178 .route_offset = 0x600, 1179 .route_val = BIT(16 + 2) | BIT(2), 1180 }, { 1181 /* spi1_miso */ 1182 .bank_num = 3, 1183 .pin = 10, 1184 .func = 3, 1185 .route_offset = 0x314, 1186 .route_val = BIT(16 + 9), 1187 }, { 1188 /* spi1_miso_m1 */ 1189 .bank_num = 2, 1190 .pin = 4, 1191 .func = 2, 1192 .route_offset = 0x314, 1193 .route_val = BIT(16 + 9) | BIT(9), 1194 }, { 1195 /* owire_m0 */ 1196 .bank_num = 0, 1197 .pin = 11, 1198 .func = 3, 1199 .route_offset = 0x314, 1200 .route_val = BIT(16 + 10) | BIT(16 + 11), 1201 }, { 1202 /* owire_m1 */ 1203 .bank_num = 1, 1204 .pin = 22, 1205 .func = 7, 1206 .route_offset = 0x314, 1207 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1208 }, { 1209 /* owire_m2 */ 1210 .bank_num = 2, 1211 .pin = 2, 1212 .func = 5, 1213 .route_offset = 0x314, 1214 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1215 }, { 1216 /* can_rxd_m0 */ 1217 .bank_num = 0, 1218 .pin = 11, 1219 .func = 2, 1220 .route_offset = 0x314, 1221 .route_val = BIT(16 + 12) | BIT(16 + 13), 1222 }, { 1223 /* can_rxd_m1 */ 1224 .bank_num = 1, 1225 .pin = 22, 1226 .func = 5, 1227 .route_offset = 0x314, 1228 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), 1229 }, { 1230 /* can_rxd_m2 */ 1231 .bank_num = 2, 1232 .pin = 2, 1233 .func = 4, 1234 .route_offset = 0x314, 1235 .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), 1236 }, { 1237 /* mac_rxd0_m0 */ 1238 .bank_num = 1, 1239 .pin = 20, 1240 .func = 3, 1241 .route_offset = 0x314, 1242 .route_val = BIT(16 + 14), 1243 }, { 1244 /* mac_rxd0_m1 */ 1245 .bank_num = 4, 1246 .pin = 2, 1247 .func = 2, 1248 .route_offset = 0x314, 1249 .route_val = BIT(16 + 14) | BIT(14), 1250 }, { 1251 /* uart3_rx */ 1252 .bank_num = 3, 1253 .pin = 12, 1254 .func = 4, 1255 .route_offset = 0x314, 1256 .route_val = BIT(16 + 15), 1257 }, { 1258 /* uart3_rx_m1 */ 1259 .bank_num = 0, 1260 .pin = 17, 1261 .func = 3, 1262 .route_offset = 0x314, 1263 .route_val = BIT(16 + 15) | BIT(15), 1264 }, 1265 }; 1266 1267 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 1268 { 1269 /* uart2dbg_rxm0 */ 1270 .bank_num = 1, 1271 .pin = 1, 1272 .func = 2, 1273 .route_offset = 0x50, 1274 .route_val = BIT(16) | BIT(16 + 1), 1275 }, { 1276 /* uart2dbg_rxm1 */ 1277 .bank_num = 2, 1278 .pin = 1, 1279 .func = 1, 1280 .route_offset = 0x50, 1281 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 1282 }, { 1283 /* gmac-m1_rxd0 */ 1284 .bank_num = 1, 1285 .pin = 11, 1286 .func = 2, 1287 .route_offset = 0x50, 1288 .route_val = BIT(16 + 2) | BIT(2), 1289 }, { 1290 /* gmac-m1-optimized_rxd3 */ 1291 .bank_num = 1, 1292 .pin = 14, 1293 .func = 2, 1294 .route_offset = 0x50, 1295 .route_val = BIT(16 + 10) | BIT(10), 1296 }, { 1297 /* pdm_sdi0m0 */ 1298 .bank_num = 2, 1299 .pin = 19, 1300 .func = 2, 1301 .route_offset = 0x50, 1302 .route_val = BIT(16 + 3), 1303 }, { 1304 /* pdm_sdi0m1 */ 1305 .bank_num = 1, 1306 .pin = 23, 1307 .func = 3, 1308 .route_offset = 0x50, 1309 .route_val = BIT(16 + 3) | BIT(3), 1310 }, { 1311 /* spi_rxdm2 */ 1312 .bank_num = 3, 1313 .pin = 2, 1314 .func = 4, 1315 .route_offset = 0x50, 1316 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 1317 }, { 1318 /* i2s2_sdim0 */ 1319 .bank_num = 1, 1320 .pin = 24, 1321 .func = 1, 1322 .route_offset = 0x50, 1323 .route_val = BIT(16 + 6), 1324 }, { 1325 /* i2s2_sdim1 */ 1326 .bank_num = 3, 1327 .pin = 2, 1328 .func = 6, 1329 .route_offset = 0x50, 1330 .route_val = BIT(16 + 6) | BIT(6), 1331 }, { 1332 /* card_iom1 */ 1333 .bank_num = 2, 1334 .pin = 22, 1335 .func = 3, 1336 .route_offset = 0x50, 1337 .route_val = BIT(16 + 7) | BIT(7), 1338 }, { 1339 /* tsp_d5m1 */ 1340 .bank_num = 2, 1341 .pin = 16, 1342 .func = 3, 1343 .route_offset = 0x50, 1344 .route_val = BIT(16 + 8) | BIT(8), 1345 }, { 1346 /* cif_data5m1 */ 1347 .bank_num = 2, 1348 .pin = 16, 1349 .func = 4, 1350 .route_offset = 0x50, 1351 .route_val = BIT(16 + 9) | BIT(9), 1352 }, 1353 }; 1354 1355 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 1356 { 1357 /* uart2dbga_rx */ 1358 .bank_num = 4, 1359 .pin = 8, 1360 .func = 2, 1361 .route_offset = 0xe21c, 1362 .route_val = BIT(16 + 10) | BIT(16 + 11), 1363 }, { 1364 /* uart2dbgb_rx */ 1365 .bank_num = 4, 1366 .pin = 16, 1367 .func = 2, 1368 .route_offset = 0xe21c, 1369 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 1370 }, { 1371 /* uart2dbgc_rx */ 1372 .bank_num = 4, 1373 .pin = 19, 1374 .func = 1, 1375 .route_offset = 0xe21c, 1376 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 1377 }, { 1378 /* pcie_clkreqn */ 1379 .bank_num = 2, 1380 .pin = 26, 1381 .func = 2, 1382 .route_offset = 0xe21c, 1383 .route_val = BIT(16 + 14), 1384 }, { 1385 /* pcie_clkreqnb */ 1386 .bank_num = 4, 1387 .pin = 24, 1388 .func = 1, 1389 .route_offset = 0xe21c, 1390 .route_val = BIT(16 + 14) | BIT(14), 1391 }, 1392 }; 1393 1394 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 1395 int mux, u32 *loc, u32 *reg, u32 *value) 1396 { 1397 struct rockchip_pinctrl *info = bank->drvdata; 1398 struct rockchip_pin_ctrl *ctrl = info->ctrl; 1399 struct rockchip_mux_route_data *data; 1400 int i; 1401 1402 for (i = 0; i < ctrl->niomux_routes; i++) { 1403 data = &ctrl->iomux_routes[i]; 1404 if ((data->bank_num == bank->bank_num) && 1405 (data->pin == pin) && (data->func == mux)) 1406 break; 1407 } 1408 1409 if (i >= ctrl->niomux_routes) 1410 return false; 1411 1412 *loc = data->route_location; 1413 *reg = data->route_offset; 1414 *value = data->route_val; 1415 1416 return true; 1417 } 1418 1419 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 1420 { 1421 struct rockchip_pinctrl *info = bank->drvdata; 1422 int iomux_num = (pin / 8); 1423 struct regmap *regmap; 1424 unsigned int val; 1425 int reg, ret, mask, mux_type; 1426 u8 bit; 1427 1428 if (iomux_num > 3) 1429 return -EINVAL; 1430 1431 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1432 dev_err(info->dev, "pin %d is unrouted\n", pin); 1433 return -EINVAL; 1434 } 1435 1436 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1437 return RK_FUNC_GPIO; 1438 1439 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1440 ? info->regmap_pmu : info->regmap_base; 1441 1442 /* get basic quadrupel of mux registers and the correct reg inside */ 1443 mux_type = bank->iomux[iomux_num].type; 1444 reg = bank->iomux[iomux_num].offset; 1445 if (mux_type & IOMUX_WIDTH_4BIT) { 1446 if ((pin % 8) >= 4) 1447 reg += 0x4; 1448 bit = (pin % 4) * 4; 1449 mask = 0xf; 1450 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1451 if ((pin % 8) >= 5) 1452 reg += 0x4; 1453 bit = (pin % 8 % 5) * 3; 1454 mask = 0x7; 1455 } else { 1456 bit = (pin % 8) * 2; 1457 mask = 0x3; 1458 } 1459 1460 if (bank->recalced_mask & BIT(pin)) 1461 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1462 1463 ret = regmap_read(regmap, reg, &val); 1464 if (ret) 1465 return ret; 1466 1467 return ((val >> bit) & mask); 1468 } 1469 1470 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1471 int pin, int mux) 1472 { 1473 struct rockchip_pinctrl *info = bank->drvdata; 1474 int iomux_num = (pin / 8); 1475 1476 if (iomux_num > 3) 1477 return -EINVAL; 1478 1479 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1480 dev_err(info->dev, "pin %d is unrouted\n", pin); 1481 return -EINVAL; 1482 } 1483 1484 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1485 if (mux != RK_FUNC_GPIO) { 1486 dev_err(info->dev, 1487 "pin %d only supports a gpio mux\n", pin); 1488 return -ENOTSUPP; 1489 } 1490 } 1491 1492 return 0; 1493 } 1494 1495 /* 1496 * Set a new mux function for a pin. 1497 * 1498 * The register is divided into the upper and lower 16 bit. When changing 1499 * a value, the previous register value is not read and changed. Instead 1500 * it seems the changed bits are marked in the upper 16 bit, while the 1501 * changed value gets set in the same offset in the lower 16 bit. 1502 * All pin settings seem to be 2 bit wide in both the upper and lower 1503 * parts. 1504 * @bank: pin bank to change 1505 * @pin: pin to change 1506 * @mux: new mux function to set 1507 */ 1508 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1509 { 1510 struct rockchip_pinctrl *info = bank->drvdata; 1511 int iomux_num = (pin / 8); 1512 struct regmap *regmap; 1513 int reg, ret, mask, mux_type; 1514 u8 bit; 1515 u32 data, rmask, route_location, route_reg, route_val; 1516 1517 ret = rockchip_verify_mux(bank, pin, mux); 1518 if (ret < 0) 1519 return ret; 1520 1521 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1522 return 0; 1523 1524 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", 1525 bank->bank_num, pin, mux); 1526 1527 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1528 ? info->regmap_pmu : info->regmap_base; 1529 1530 /* get basic quadrupel of mux registers and the correct reg inside */ 1531 mux_type = bank->iomux[iomux_num].type; 1532 reg = bank->iomux[iomux_num].offset; 1533 if (mux_type & IOMUX_WIDTH_4BIT) { 1534 if ((pin % 8) >= 4) 1535 reg += 0x4; 1536 bit = (pin % 4) * 4; 1537 mask = 0xf; 1538 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1539 if ((pin % 8) >= 5) 1540 reg += 0x4; 1541 bit = (pin % 8 % 5) * 3; 1542 mask = 0x7; 1543 } else { 1544 bit = (pin % 8) * 2; 1545 mask = 0x3; 1546 } 1547 1548 if (bank->recalced_mask & BIT(pin)) 1549 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1550 1551 if (bank->route_mask & BIT(pin)) { 1552 if (rockchip_get_mux_route(bank, pin, mux, &route_location, 1553 &route_reg, &route_val)) { 1554 struct regmap *route_regmap = regmap; 1555 1556 /* handle special locations */ 1557 switch (route_location) { 1558 case ROCKCHIP_ROUTE_PMU: 1559 route_regmap = info->regmap_pmu; 1560 break; 1561 case ROCKCHIP_ROUTE_GRF: 1562 route_regmap = info->regmap_base; 1563 break; 1564 } 1565 1566 ret = regmap_write(route_regmap, route_reg, route_val); 1567 if (ret) 1568 return ret; 1569 } 1570 } 1571 1572 data = (mask << (bit + 16)); 1573 rmask = data | (data >> 16); 1574 data |= (mux & mask) << bit; 1575 ret = regmap_update_bits(regmap, reg, rmask, data); 1576 1577 return ret; 1578 } 1579 1580 #define PX30_PULL_PMU_OFFSET 0x10 1581 #define PX30_PULL_GRF_OFFSET 0x60 1582 #define PX30_PULL_BITS_PER_PIN 2 1583 #define PX30_PULL_PINS_PER_REG 8 1584 #define PX30_PULL_BANK_STRIDE 16 1585 1586 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1587 int pin_num, struct regmap **regmap, 1588 int *reg, u8 *bit) 1589 { 1590 struct rockchip_pinctrl *info = bank->drvdata; 1591 1592 /* The first 32 pins of the first bank are located in PMU */ 1593 if (bank->bank_num == 0) { 1594 *regmap = info->regmap_pmu; 1595 *reg = PX30_PULL_PMU_OFFSET; 1596 } else { 1597 *regmap = info->regmap_base; 1598 *reg = PX30_PULL_GRF_OFFSET; 1599 1600 /* correct the offset, as we're starting with the 2nd bank */ 1601 *reg -= 0x10; 1602 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1603 } 1604 1605 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1606 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1607 *bit *= PX30_PULL_BITS_PER_PIN; 1608 } 1609 1610 #define PX30_DRV_PMU_OFFSET 0x20 1611 #define PX30_DRV_GRF_OFFSET 0xf0 1612 #define PX30_DRV_BITS_PER_PIN 2 1613 #define PX30_DRV_PINS_PER_REG 8 1614 #define PX30_DRV_BANK_STRIDE 16 1615 1616 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1617 int pin_num, struct regmap **regmap, 1618 int *reg, u8 *bit) 1619 { 1620 struct rockchip_pinctrl *info = bank->drvdata; 1621 1622 /* The first 32 pins of the first bank are located in PMU */ 1623 if (bank->bank_num == 0) { 1624 *regmap = info->regmap_pmu; 1625 *reg = PX30_DRV_PMU_OFFSET; 1626 } else { 1627 *regmap = info->regmap_base; 1628 *reg = PX30_DRV_GRF_OFFSET; 1629 1630 /* correct the offset, as we're starting with the 2nd bank */ 1631 *reg -= 0x10; 1632 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1633 } 1634 1635 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1636 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1637 *bit *= PX30_DRV_BITS_PER_PIN; 1638 } 1639 1640 #define PX30_SCHMITT_PMU_OFFSET 0x38 1641 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1642 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1643 #define PX30_SCHMITT_BANK_STRIDE 16 1644 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1645 1646 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1647 int pin_num, 1648 struct regmap **regmap, 1649 int *reg, u8 *bit) 1650 { 1651 struct rockchip_pinctrl *info = bank->drvdata; 1652 int pins_per_reg; 1653 1654 if (bank->bank_num == 0) { 1655 *regmap = info->regmap_pmu; 1656 *reg = PX30_SCHMITT_PMU_OFFSET; 1657 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1658 } else { 1659 *regmap = info->regmap_base; 1660 *reg = PX30_SCHMITT_GRF_OFFSET; 1661 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1662 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1663 } 1664 1665 *reg += ((pin_num / pins_per_reg) * 4); 1666 *bit = pin_num % pins_per_reg; 1667 1668 return 0; 1669 } 1670 1671 #define RV1108_PULL_PMU_OFFSET 0x10 1672 #define RV1108_PULL_OFFSET 0x110 1673 #define RV1108_PULL_PINS_PER_REG 8 1674 #define RV1108_PULL_BITS_PER_PIN 2 1675 #define RV1108_PULL_BANK_STRIDE 16 1676 1677 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1678 int pin_num, struct regmap **regmap, 1679 int *reg, u8 *bit) 1680 { 1681 struct rockchip_pinctrl *info = bank->drvdata; 1682 1683 /* The first 24 pins of the first bank are located in PMU */ 1684 if (bank->bank_num == 0) { 1685 *regmap = info->regmap_pmu; 1686 *reg = RV1108_PULL_PMU_OFFSET; 1687 } else { 1688 *reg = RV1108_PULL_OFFSET; 1689 *regmap = info->regmap_base; 1690 /* correct the offset, as we're starting with the 2nd bank */ 1691 *reg -= 0x10; 1692 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1693 } 1694 1695 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1696 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1697 *bit *= RV1108_PULL_BITS_PER_PIN; 1698 } 1699 1700 #define RV1108_DRV_PMU_OFFSET 0x20 1701 #define RV1108_DRV_GRF_OFFSET 0x210 1702 #define RV1108_DRV_BITS_PER_PIN 2 1703 #define RV1108_DRV_PINS_PER_REG 8 1704 #define RV1108_DRV_BANK_STRIDE 16 1705 1706 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1707 int pin_num, struct regmap **regmap, 1708 int *reg, u8 *bit) 1709 { 1710 struct rockchip_pinctrl *info = bank->drvdata; 1711 1712 /* The first 24 pins of the first bank are located in PMU */ 1713 if (bank->bank_num == 0) { 1714 *regmap = info->regmap_pmu; 1715 *reg = RV1108_DRV_PMU_OFFSET; 1716 } else { 1717 *regmap = info->regmap_base; 1718 *reg = RV1108_DRV_GRF_OFFSET; 1719 1720 /* correct the offset, as we're starting with the 2nd bank */ 1721 *reg -= 0x10; 1722 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1723 } 1724 1725 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1726 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1727 *bit *= RV1108_DRV_BITS_PER_PIN; 1728 } 1729 1730 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1731 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1732 #define RV1108_SCHMITT_BANK_STRIDE 8 1733 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1734 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1735 1736 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1737 int pin_num, 1738 struct regmap **regmap, 1739 int *reg, u8 *bit) 1740 { 1741 struct rockchip_pinctrl *info = bank->drvdata; 1742 int pins_per_reg; 1743 1744 if (bank->bank_num == 0) { 1745 *regmap = info->regmap_pmu; 1746 *reg = RV1108_SCHMITT_PMU_OFFSET; 1747 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1748 } else { 1749 *regmap = info->regmap_base; 1750 *reg = RV1108_SCHMITT_GRF_OFFSET; 1751 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1752 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1753 } 1754 *reg += ((pin_num / pins_per_reg) * 4); 1755 *bit = pin_num % pins_per_reg; 1756 1757 return 0; 1758 } 1759 1760 #define RK3308_SCHMITT_PINS_PER_REG 8 1761 #define RK3308_SCHMITT_BANK_STRIDE 16 1762 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1763 1764 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1765 int pin_num, struct regmap **regmap, 1766 int *reg, u8 *bit) 1767 { 1768 struct rockchip_pinctrl *info = bank->drvdata; 1769 1770 *regmap = info->regmap_base; 1771 *reg = RK3308_SCHMITT_GRF_OFFSET; 1772 1773 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1774 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1775 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1776 1777 return 0; 1778 } 1779 1780 #define RK2928_PULL_OFFSET 0x118 1781 #define RK2928_PULL_PINS_PER_REG 16 1782 #define RK2928_PULL_BANK_STRIDE 8 1783 1784 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1785 int pin_num, struct regmap **regmap, 1786 int *reg, u8 *bit) 1787 { 1788 struct rockchip_pinctrl *info = bank->drvdata; 1789 1790 *regmap = info->regmap_base; 1791 *reg = RK2928_PULL_OFFSET; 1792 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1793 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1794 1795 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1796 }; 1797 1798 #define RK3128_PULL_OFFSET 0x118 1799 1800 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1801 int pin_num, struct regmap **regmap, 1802 int *reg, u8 *bit) 1803 { 1804 struct rockchip_pinctrl *info = bank->drvdata; 1805 1806 *regmap = info->regmap_base; 1807 *reg = RK3128_PULL_OFFSET; 1808 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1809 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1810 1811 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1812 } 1813 1814 #define RK3188_PULL_OFFSET 0x164 1815 #define RK3188_PULL_BITS_PER_PIN 2 1816 #define RK3188_PULL_PINS_PER_REG 8 1817 #define RK3188_PULL_BANK_STRIDE 16 1818 #define RK3188_PULL_PMU_OFFSET 0x64 1819 1820 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1821 int pin_num, struct regmap **regmap, 1822 int *reg, u8 *bit) 1823 { 1824 struct rockchip_pinctrl *info = bank->drvdata; 1825 1826 /* The first 12 pins of the first bank are located elsewhere */ 1827 if (bank->bank_num == 0 && pin_num < 12) { 1828 *regmap = info->regmap_pmu ? info->regmap_pmu 1829 : bank->regmap_pull; 1830 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; 1831 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1832 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1833 *bit *= RK3188_PULL_BITS_PER_PIN; 1834 } else { 1835 *regmap = info->regmap_pull ? info->regmap_pull 1836 : info->regmap_base; 1837 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; 1838 1839 /* correct the offset, as it is the 2nd pull register */ 1840 *reg -= 4; 1841 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1842 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1843 1844 /* 1845 * The bits in these registers have an inverse ordering 1846 * with the lowest pin being in bits 15:14 and the highest 1847 * pin in bits 1:0 1848 */ 1849 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1850 *bit *= RK3188_PULL_BITS_PER_PIN; 1851 } 1852 } 1853 1854 #define RK3288_PULL_OFFSET 0x140 1855 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1856 int pin_num, struct regmap **regmap, 1857 int *reg, u8 *bit) 1858 { 1859 struct rockchip_pinctrl *info = bank->drvdata; 1860 1861 /* The first 24 pins of the first bank are located in PMU */ 1862 if (bank->bank_num == 0) { 1863 *regmap = info->regmap_pmu; 1864 *reg = RK3188_PULL_PMU_OFFSET; 1865 1866 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1867 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1868 *bit *= RK3188_PULL_BITS_PER_PIN; 1869 } else { 1870 *regmap = info->regmap_base; 1871 *reg = RK3288_PULL_OFFSET; 1872 1873 /* correct the offset, as we're starting with the 2nd bank */ 1874 *reg -= 0x10; 1875 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1876 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1877 1878 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1879 *bit *= RK3188_PULL_BITS_PER_PIN; 1880 } 1881 } 1882 1883 #define RK3288_DRV_PMU_OFFSET 0x70 1884 #define RK3288_DRV_GRF_OFFSET 0x1c0 1885 #define RK3288_DRV_BITS_PER_PIN 2 1886 #define RK3288_DRV_PINS_PER_REG 8 1887 #define RK3288_DRV_BANK_STRIDE 16 1888 1889 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1890 int pin_num, struct regmap **regmap, 1891 int *reg, u8 *bit) 1892 { 1893 struct rockchip_pinctrl *info = bank->drvdata; 1894 1895 /* The first 24 pins of the first bank are located in PMU */ 1896 if (bank->bank_num == 0) { 1897 *regmap = info->regmap_pmu; 1898 *reg = RK3288_DRV_PMU_OFFSET; 1899 1900 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1901 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1902 *bit *= RK3288_DRV_BITS_PER_PIN; 1903 } else { 1904 *regmap = info->regmap_base; 1905 *reg = RK3288_DRV_GRF_OFFSET; 1906 1907 /* correct the offset, as we're starting with the 2nd bank */ 1908 *reg -= 0x10; 1909 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1910 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1911 1912 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1913 *bit *= RK3288_DRV_BITS_PER_PIN; 1914 } 1915 } 1916 1917 #define RK3228_PULL_OFFSET 0x100 1918 1919 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1920 int pin_num, struct regmap **regmap, 1921 int *reg, u8 *bit) 1922 { 1923 struct rockchip_pinctrl *info = bank->drvdata; 1924 1925 *regmap = info->regmap_base; 1926 *reg = RK3228_PULL_OFFSET; 1927 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1928 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1929 1930 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1931 *bit *= RK3188_PULL_BITS_PER_PIN; 1932 } 1933 1934 #define RK3228_DRV_GRF_OFFSET 0x200 1935 1936 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1937 int pin_num, struct regmap **regmap, 1938 int *reg, u8 *bit) 1939 { 1940 struct rockchip_pinctrl *info = bank->drvdata; 1941 1942 *regmap = info->regmap_base; 1943 *reg = RK3228_DRV_GRF_OFFSET; 1944 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1945 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1946 1947 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1948 *bit *= RK3288_DRV_BITS_PER_PIN; 1949 } 1950 1951 #define RK3308_PULL_OFFSET 0xa0 1952 1953 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1954 int pin_num, struct regmap **regmap, 1955 int *reg, u8 *bit) 1956 { 1957 struct rockchip_pinctrl *info = bank->drvdata; 1958 1959 *regmap = info->regmap_base; 1960 *reg = RK3308_PULL_OFFSET; 1961 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1962 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1963 1964 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1965 *bit *= RK3188_PULL_BITS_PER_PIN; 1966 } 1967 1968 #define RK3308_DRV_GRF_OFFSET 0x100 1969 1970 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1971 int pin_num, struct regmap **regmap, 1972 int *reg, u8 *bit) 1973 { 1974 struct rockchip_pinctrl *info = bank->drvdata; 1975 1976 *regmap = info->regmap_base; 1977 *reg = RK3308_DRV_GRF_OFFSET; 1978 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1979 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1980 1981 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1982 *bit *= RK3288_DRV_BITS_PER_PIN; 1983 } 1984 1985 #define RK3368_PULL_GRF_OFFSET 0x100 1986 #define RK3368_PULL_PMU_OFFSET 0x10 1987 1988 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1989 int pin_num, struct regmap **regmap, 1990 int *reg, u8 *bit) 1991 { 1992 struct rockchip_pinctrl *info = bank->drvdata; 1993 1994 /* The first 32 pins of the first bank are located in PMU */ 1995 if (bank->bank_num == 0) { 1996 *regmap = info->regmap_pmu; 1997 *reg = RK3368_PULL_PMU_OFFSET; 1998 1999 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2000 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2001 *bit *= RK3188_PULL_BITS_PER_PIN; 2002 } else { 2003 *regmap = info->regmap_base; 2004 *reg = RK3368_PULL_GRF_OFFSET; 2005 2006 /* correct the offset, as we're starting with the 2nd bank */ 2007 *reg -= 0x10; 2008 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2009 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2010 2011 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2012 *bit *= RK3188_PULL_BITS_PER_PIN; 2013 } 2014 } 2015 2016 #define RK3368_DRV_PMU_OFFSET 0x20 2017 #define RK3368_DRV_GRF_OFFSET 0x200 2018 2019 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2020 int pin_num, struct regmap **regmap, 2021 int *reg, u8 *bit) 2022 { 2023 struct rockchip_pinctrl *info = bank->drvdata; 2024 2025 /* The first 32 pins of the first bank are located in PMU */ 2026 if (bank->bank_num == 0) { 2027 *regmap = info->regmap_pmu; 2028 *reg = RK3368_DRV_PMU_OFFSET; 2029 2030 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2031 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 2032 *bit *= RK3288_DRV_BITS_PER_PIN; 2033 } else { 2034 *regmap = info->regmap_base; 2035 *reg = RK3368_DRV_GRF_OFFSET; 2036 2037 /* correct the offset, as we're starting with the 2nd bank */ 2038 *reg -= 0x10; 2039 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 2040 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 2041 2042 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 2043 *bit *= RK3288_DRV_BITS_PER_PIN; 2044 } 2045 } 2046 2047 #define RK3399_PULL_GRF_OFFSET 0xe040 2048 #define RK3399_PULL_PMU_OFFSET 0x40 2049 #define RK3399_DRV_3BITS_PER_PIN 3 2050 2051 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 2052 int pin_num, struct regmap **regmap, 2053 int *reg, u8 *bit) 2054 { 2055 struct rockchip_pinctrl *info = bank->drvdata; 2056 2057 /* The bank0:16 and bank1:32 pins are located in PMU */ 2058 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 2059 *regmap = info->regmap_pmu; 2060 *reg = RK3399_PULL_PMU_OFFSET; 2061 2062 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2063 2064 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2065 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 2066 *bit *= RK3188_PULL_BITS_PER_PIN; 2067 } else { 2068 *regmap = info->regmap_base; 2069 *reg = RK3399_PULL_GRF_OFFSET; 2070 2071 /* correct the offset, as we're starting with the 3rd bank */ 2072 *reg -= 0x20; 2073 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 2074 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 2075 2076 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 2077 *bit *= RK3188_PULL_BITS_PER_PIN; 2078 } 2079 } 2080 2081 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 2082 int pin_num, struct regmap **regmap, 2083 int *reg, u8 *bit) 2084 { 2085 struct rockchip_pinctrl *info = bank->drvdata; 2086 int drv_num = (pin_num / 8); 2087 2088 /* The bank0:16 and bank1:32 pins are located in PMU */ 2089 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 2090 *regmap = info->regmap_pmu; 2091 else 2092 *regmap = info->regmap_base; 2093 2094 *reg = bank->drv[drv_num].offset; 2095 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2096 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 2097 *bit = (pin_num % 8) * 3; 2098 else 2099 *bit = (pin_num % 8) * 2; 2100 } 2101 2102 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 2103 { 2, 4, 8, 12, -1, -1, -1, -1 }, 2104 { 3, 6, 9, 12, -1, -1, -1, -1 }, 2105 { 5, 10, 15, 20, -1, -1, -1, -1 }, 2106 { 4, 6, 8, 10, 12, 14, 16, 18 }, 2107 { 4, 7, 10, 13, 16, 19, 22, 26 } 2108 }; 2109 2110 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, 2111 int pin_num) 2112 { 2113 struct rockchip_pinctrl *info = bank->drvdata; 2114 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2115 struct regmap *regmap; 2116 int reg, ret; 2117 u32 data, temp, rmask_bits; 2118 u8 bit; 2119 int drv_type = bank->drv[pin_num / 8].drv_type; 2120 2121 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2122 2123 switch (drv_type) { 2124 case DRV_TYPE_IO_1V8_3V0_AUTO: 2125 case DRV_TYPE_IO_3V3_ONLY: 2126 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2127 switch (bit) { 2128 case 0 ... 12: 2129 /* regular case, nothing to do */ 2130 break; 2131 case 15: 2132 /* 2133 * drive-strength offset is special, as it is 2134 * spread over 2 registers 2135 */ 2136 ret = regmap_read(regmap, reg, &data); 2137 if (ret) 2138 return ret; 2139 2140 ret = regmap_read(regmap, reg + 0x4, &temp); 2141 if (ret) 2142 return ret; 2143 2144 /* 2145 * the bit data[15] contains bit 0 of the value 2146 * while temp[1:0] contains bits 2 and 1 2147 */ 2148 data >>= 15; 2149 temp &= 0x3; 2150 temp <<= 1; 2151 data |= temp; 2152 2153 return rockchip_perpin_drv_list[drv_type][data]; 2154 case 18 ... 21: 2155 /* setting fully enclosed in the second register */ 2156 reg += 4; 2157 bit -= 16; 2158 break; 2159 default: 2160 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2161 bit, drv_type); 2162 return -EINVAL; 2163 } 2164 2165 break; 2166 case DRV_TYPE_IO_DEFAULT: 2167 case DRV_TYPE_IO_1V8_OR_3V0: 2168 case DRV_TYPE_IO_1V8_ONLY: 2169 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2170 break; 2171 default: 2172 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 2173 drv_type); 2174 return -EINVAL; 2175 } 2176 2177 ret = regmap_read(regmap, reg, &data); 2178 if (ret) 2179 return ret; 2180 2181 data >>= bit; 2182 data &= (1 << rmask_bits) - 1; 2183 2184 return rockchip_perpin_drv_list[drv_type][data]; 2185 } 2186 2187 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 2188 int pin_num, int strength) 2189 { 2190 struct rockchip_pinctrl *info = bank->drvdata; 2191 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2192 struct regmap *regmap; 2193 int reg, ret, i; 2194 u32 data, rmask, rmask_bits, temp; 2195 u8 bit; 2196 int drv_type = bank->drv[pin_num / 8].drv_type; 2197 2198 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", 2199 bank->bank_num, pin_num, strength); 2200 2201 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 2202 2203 ret = -EINVAL; 2204 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 2205 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 2206 ret = i; 2207 break; 2208 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 2209 ret = rockchip_perpin_drv_list[drv_type][i]; 2210 break; 2211 } 2212 } 2213 2214 if (ret < 0) { 2215 dev_err(info->dev, "unsupported driver strength %d\n", 2216 strength); 2217 return ret; 2218 } 2219 2220 switch (drv_type) { 2221 case DRV_TYPE_IO_1V8_3V0_AUTO: 2222 case DRV_TYPE_IO_3V3_ONLY: 2223 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 2224 switch (bit) { 2225 case 0 ... 12: 2226 /* regular case, nothing to do */ 2227 break; 2228 case 15: 2229 /* 2230 * drive-strength offset is special, as it is spread 2231 * over 2 registers, the bit data[15] contains bit 0 2232 * of the value while temp[1:0] contains bits 2 and 1 2233 */ 2234 data = (ret & 0x1) << 15; 2235 temp = (ret >> 0x1) & 0x3; 2236 2237 rmask = BIT(15) | BIT(31); 2238 data |= BIT(31); 2239 ret = regmap_update_bits(regmap, reg, rmask, data); 2240 if (ret) 2241 return ret; 2242 2243 rmask = 0x3 | (0x3 << 16); 2244 temp |= (0x3 << 16); 2245 reg += 0x4; 2246 ret = regmap_update_bits(regmap, reg, rmask, temp); 2247 2248 return ret; 2249 case 18 ... 21: 2250 /* setting fully enclosed in the second register */ 2251 reg += 4; 2252 bit -= 16; 2253 break; 2254 default: 2255 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", 2256 bit, drv_type); 2257 return -EINVAL; 2258 } 2259 break; 2260 case DRV_TYPE_IO_DEFAULT: 2261 case DRV_TYPE_IO_1V8_OR_3V0: 2262 case DRV_TYPE_IO_1V8_ONLY: 2263 rmask_bits = RK3288_DRV_BITS_PER_PIN; 2264 break; 2265 default: 2266 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", 2267 drv_type); 2268 return -EINVAL; 2269 } 2270 2271 /* enable the write to the equivalent lower bits */ 2272 data = ((1 << rmask_bits) - 1) << (bit + 16); 2273 rmask = data | (data >> 16); 2274 data |= (ret << bit); 2275 2276 ret = regmap_update_bits(regmap, reg, rmask, data); 2277 2278 return ret; 2279 } 2280 2281 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 2282 { 2283 PIN_CONFIG_BIAS_DISABLE, 2284 PIN_CONFIG_BIAS_PULL_UP, 2285 PIN_CONFIG_BIAS_PULL_DOWN, 2286 PIN_CONFIG_BIAS_BUS_HOLD 2287 }, 2288 { 2289 PIN_CONFIG_BIAS_DISABLE, 2290 PIN_CONFIG_BIAS_PULL_DOWN, 2291 PIN_CONFIG_BIAS_DISABLE, 2292 PIN_CONFIG_BIAS_PULL_UP 2293 }, 2294 }; 2295 2296 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 2297 { 2298 struct rockchip_pinctrl *info = bank->drvdata; 2299 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2300 struct regmap *regmap; 2301 int reg, ret, pull_type; 2302 u8 bit; 2303 u32 data; 2304 2305 /* rk3066b does support any pulls */ 2306 if (ctrl->type == RK3066B) 2307 return PIN_CONFIG_BIAS_DISABLE; 2308 2309 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2310 2311 ret = regmap_read(regmap, reg, &data); 2312 if (ret) 2313 return ret; 2314 2315 switch (ctrl->type) { 2316 case RK2928: 2317 case RK3128: 2318 return !(data & BIT(bit)) 2319 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 2320 : PIN_CONFIG_BIAS_DISABLE; 2321 case PX30: 2322 case RV1108: 2323 case RK3188: 2324 case RK3288: 2325 case RK3308: 2326 case RK3368: 2327 case RK3399: 2328 pull_type = bank->pull_type[pin_num / 8]; 2329 data >>= bit; 2330 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; 2331 2332 return rockchip_pull_list[pull_type][data]; 2333 default: 2334 dev_err(info->dev, "unsupported pinctrl type\n"); 2335 return -EINVAL; 2336 }; 2337 } 2338 2339 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 2340 int pin_num, int pull) 2341 { 2342 struct rockchip_pinctrl *info = bank->drvdata; 2343 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2344 struct regmap *regmap; 2345 int reg, ret, i, pull_type; 2346 u8 bit; 2347 u32 data, rmask; 2348 2349 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", 2350 bank->bank_num, pin_num, pull); 2351 2352 /* rk3066b does support any pulls */ 2353 if (ctrl->type == RK3066B) 2354 return pull ? -EINVAL : 0; 2355 2356 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 2357 2358 switch (ctrl->type) { 2359 case RK2928: 2360 case RK3128: 2361 data = BIT(bit + 16); 2362 if (pull == PIN_CONFIG_BIAS_DISABLE) 2363 data |= BIT(bit); 2364 ret = regmap_write(regmap, reg, data); 2365 break; 2366 case PX30: 2367 case RV1108: 2368 case RK3188: 2369 case RK3288: 2370 case RK3308: 2371 case RK3368: 2372 case RK3399: 2373 pull_type = bank->pull_type[pin_num / 8]; 2374 ret = -EINVAL; 2375 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 2376 i++) { 2377 if (rockchip_pull_list[pull_type][i] == pull) { 2378 ret = i; 2379 break; 2380 } 2381 } 2382 2383 if (ret < 0) { 2384 dev_err(info->dev, "unsupported pull setting %d\n", 2385 pull); 2386 return ret; 2387 } 2388 2389 /* enable the write to the equivalent lower bits */ 2390 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 2391 rmask = data | (data >> 16); 2392 data |= (ret << bit); 2393 2394 ret = regmap_update_bits(regmap, reg, rmask, data); 2395 break; 2396 default: 2397 dev_err(info->dev, "unsupported pinctrl type\n"); 2398 return -EINVAL; 2399 } 2400 2401 return ret; 2402 } 2403 2404 #define RK3328_SCHMITT_BITS_PER_PIN 1 2405 #define RK3328_SCHMITT_PINS_PER_REG 16 2406 #define RK3328_SCHMITT_BANK_STRIDE 8 2407 #define RK3328_SCHMITT_GRF_OFFSET 0x380 2408 2409 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 2410 int pin_num, 2411 struct regmap **regmap, 2412 int *reg, u8 *bit) 2413 { 2414 struct rockchip_pinctrl *info = bank->drvdata; 2415 2416 *regmap = info->regmap_base; 2417 *reg = RK3328_SCHMITT_GRF_OFFSET; 2418 2419 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 2420 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 2421 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 2422 2423 return 0; 2424 } 2425 2426 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) 2427 { 2428 struct rockchip_pinctrl *info = bank->drvdata; 2429 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2430 struct regmap *regmap; 2431 int reg, ret; 2432 u8 bit; 2433 u32 data; 2434 2435 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2436 if (ret) 2437 return ret; 2438 2439 ret = regmap_read(regmap, reg, &data); 2440 if (ret) 2441 return ret; 2442 2443 data >>= bit; 2444 return data & 0x1; 2445 } 2446 2447 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 2448 int pin_num, int enable) 2449 { 2450 struct rockchip_pinctrl *info = bank->drvdata; 2451 struct rockchip_pin_ctrl *ctrl = info->ctrl; 2452 struct regmap *regmap; 2453 int reg, ret; 2454 u8 bit; 2455 u32 data, rmask; 2456 2457 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", 2458 bank->bank_num, pin_num, enable); 2459 2460 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 2461 if (ret) 2462 return ret; 2463 2464 /* enable the write to the equivalent lower bits */ 2465 data = BIT(bit + 16) | (enable << bit); 2466 rmask = BIT(bit + 16) | BIT(bit); 2467 2468 return regmap_update_bits(regmap, reg, rmask, data); 2469 } 2470 2471 /* 2472 * Pinmux_ops handling 2473 */ 2474 2475 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2476 { 2477 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2478 2479 return info->nfunctions; 2480 } 2481 2482 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, 2483 unsigned selector) 2484 { 2485 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2486 2487 return info->functions[selector].name; 2488 } 2489 2490 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, 2491 unsigned selector, const char * const **groups, 2492 unsigned * const num_groups) 2493 { 2494 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2495 2496 *groups = info->functions[selector].groups; 2497 *num_groups = info->functions[selector].ngroups; 2498 2499 return 0; 2500 } 2501 2502 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, 2503 unsigned group) 2504 { 2505 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2506 const unsigned int *pins = info->groups[group].pins; 2507 const struct rockchip_pin_config *data = info->groups[group].data; 2508 struct rockchip_pin_bank *bank; 2509 int cnt, ret = 0; 2510 2511 dev_dbg(info->dev, "enable function %s group %s\n", 2512 info->functions[selector].name, info->groups[group].name); 2513 2514 /* 2515 * for each pin in the pin group selected, program the corresponding 2516 * pin function number in the config register. 2517 */ 2518 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { 2519 bank = pin_to_bank(info, pins[cnt]); 2520 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 2521 data[cnt].func); 2522 if (ret) 2523 break; 2524 } 2525 2526 if (ret) { 2527 /* revert the already done pin settings */ 2528 for (cnt--; cnt >= 0; cnt--) 2529 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); 2530 2531 return ret; 2532 } 2533 2534 return 0; 2535 } 2536 2537 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 2538 { 2539 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 2540 u32 data; 2541 int ret; 2542 2543 ret = clk_enable(bank->clk); 2544 if (ret < 0) { 2545 dev_err(bank->drvdata->dev, 2546 "failed to enable clock for bank %s\n", bank->name); 2547 return ret; 2548 } 2549 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2550 clk_disable(bank->clk); 2551 2552 if (data & BIT(offset)) 2553 return GPIO_LINE_DIRECTION_OUT; 2554 2555 return GPIO_LINE_DIRECTION_IN; 2556 } 2557 2558 /* 2559 * The calls to gpio_direction_output() and gpio_direction_input() 2560 * leads to this function call (via the pinctrl_gpio_direction_{input|output}() 2561 * function called from the gpiolib interface). 2562 */ 2563 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, 2564 int pin, bool input) 2565 { 2566 struct rockchip_pin_bank *bank; 2567 int ret; 2568 unsigned long flags; 2569 u32 data; 2570 2571 bank = gpiochip_get_data(chip); 2572 2573 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); 2574 if (ret < 0) 2575 return ret; 2576 2577 clk_enable(bank->clk); 2578 raw_spin_lock_irqsave(&bank->slock, flags); 2579 2580 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 2581 /* set bit to 1 for output, 0 for input */ 2582 if (!input) 2583 data |= BIT(pin); 2584 else 2585 data &= ~BIT(pin); 2586 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 2587 2588 raw_spin_unlock_irqrestore(&bank->slock, flags); 2589 clk_disable(bank->clk); 2590 2591 return 0; 2592 } 2593 2594 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 2595 struct pinctrl_gpio_range *range, 2596 unsigned offset, bool input) 2597 { 2598 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2599 struct gpio_chip *chip; 2600 int pin; 2601 2602 chip = range->gc; 2603 pin = offset - chip->base; 2604 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 2605 offset, range->name, pin, input ? "input" : "output"); 2606 2607 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, 2608 input); 2609 } 2610 2611 static const struct pinmux_ops rockchip_pmx_ops = { 2612 .get_functions_count = rockchip_pmx_get_funcs_count, 2613 .get_function_name = rockchip_pmx_get_func_name, 2614 .get_function_groups = rockchip_pmx_get_groups, 2615 .set_mux = rockchip_pmx_set, 2616 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 2617 }; 2618 2619 /* 2620 * Pinconf_ops handling 2621 */ 2622 2623 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 2624 enum pin_config_param pull) 2625 { 2626 switch (ctrl->type) { 2627 case RK2928: 2628 case RK3128: 2629 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 2630 pull == PIN_CONFIG_BIAS_DISABLE); 2631 case RK3066B: 2632 return pull ? false : true; 2633 case PX30: 2634 case RV1108: 2635 case RK3188: 2636 case RK3288: 2637 case RK3308: 2638 case RK3368: 2639 case RK3399: 2640 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 2641 } 2642 2643 return false; 2644 } 2645 2646 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); 2647 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); 2648 2649 /* set the pin config settings for a specified pin */ 2650 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2651 unsigned long *configs, unsigned num_configs) 2652 { 2653 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2654 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2655 enum pin_config_param param; 2656 u32 arg; 2657 int i; 2658 int rc; 2659 2660 for (i = 0; i < num_configs; i++) { 2661 param = pinconf_to_config_param(configs[i]); 2662 arg = pinconf_to_config_argument(configs[i]); 2663 2664 switch (param) { 2665 case PIN_CONFIG_BIAS_DISABLE: 2666 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2667 param); 2668 if (rc) 2669 return rc; 2670 break; 2671 case PIN_CONFIG_BIAS_PULL_UP: 2672 case PIN_CONFIG_BIAS_PULL_DOWN: 2673 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2674 case PIN_CONFIG_BIAS_BUS_HOLD: 2675 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2676 return -ENOTSUPP; 2677 2678 if (!arg) 2679 return -EINVAL; 2680 2681 rc = rockchip_set_pull(bank, pin - bank->pin_base, 2682 param); 2683 if (rc) 2684 return rc; 2685 break; 2686 case PIN_CONFIG_OUTPUT: 2687 rockchip_gpio_set(&bank->gpio_chip, 2688 pin - bank->pin_base, arg); 2689 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, 2690 pin - bank->pin_base, false); 2691 if (rc) 2692 return rc; 2693 break; 2694 case PIN_CONFIG_DRIVE_STRENGTH: 2695 /* rk3288 is the first with per-pin drive-strength */ 2696 if (!info->ctrl->drv_calc_reg) 2697 return -ENOTSUPP; 2698 2699 rc = rockchip_set_drive_perpin(bank, 2700 pin - bank->pin_base, arg); 2701 if (rc < 0) 2702 return rc; 2703 break; 2704 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2705 if (!info->ctrl->schmitt_calc_reg) 2706 return -ENOTSUPP; 2707 2708 rc = rockchip_set_schmitt(bank, 2709 pin - bank->pin_base, arg); 2710 if (rc < 0) 2711 return rc; 2712 break; 2713 default: 2714 return -ENOTSUPP; 2715 break; 2716 } 2717 } /* for each config */ 2718 2719 return 0; 2720 } 2721 2722 /* get the pin config settings for a specified pin */ 2723 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 2724 unsigned long *config) 2725 { 2726 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 2727 struct rockchip_pin_bank *bank = pin_to_bank(info, pin); 2728 enum pin_config_param param = pinconf_to_config_param(*config); 2729 u16 arg; 2730 int rc; 2731 2732 switch (param) { 2733 case PIN_CONFIG_BIAS_DISABLE: 2734 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2735 return -EINVAL; 2736 2737 arg = 0; 2738 break; 2739 case PIN_CONFIG_BIAS_PULL_UP: 2740 case PIN_CONFIG_BIAS_PULL_DOWN: 2741 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 2742 case PIN_CONFIG_BIAS_BUS_HOLD: 2743 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 2744 return -ENOTSUPP; 2745 2746 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) 2747 return -EINVAL; 2748 2749 arg = 1; 2750 break; 2751 case PIN_CONFIG_OUTPUT: 2752 rc = rockchip_get_mux(bank, pin - bank->pin_base); 2753 if (rc != RK_FUNC_GPIO) 2754 return -EINVAL; 2755 2756 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); 2757 if (rc < 0) 2758 return rc; 2759 2760 arg = rc ? 1 : 0; 2761 break; 2762 case PIN_CONFIG_DRIVE_STRENGTH: 2763 /* rk3288 is the first with per-pin drive-strength */ 2764 if (!info->ctrl->drv_calc_reg) 2765 return -ENOTSUPP; 2766 2767 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); 2768 if (rc < 0) 2769 return rc; 2770 2771 arg = rc; 2772 break; 2773 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 2774 if (!info->ctrl->schmitt_calc_reg) 2775 return -ENOTSUPP; 2776 2777 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); 2778 if (rc < 0) 2779 return rc; 2780 2781 arg = rc; 2782 break; 2783 default: 2784 return -ENOTSUPP; 2785 break; 2786 } 2787 2788 *config = pinconf_to_config_packed(param, arg); 2789 2790 return 0; 2791 } 2792 2793 static const struct pinconf_ops rockchip_pinconf_ops = { 2794 .pin_config_get = rockchip_pinconf_get, 2795 .pin_config_set = rockchip_pinconf_set, 2796 .is_generic = true, 2797 }; 2798 2799 static const struct of_device_id rockchip_bank_match[] = { 2800 { .compatible = "rockchip,gpio-bank" }, 2801 { .compatible = "rockchip,rk3188-gpio-bank0" }, 2802 {}, 2803 }; 2804 2805 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 2806 struct device_node *np) 2807 { 2808 struct device_node *child; 2809 2810 for_each_child_of_node(np, child) { 2811 if (of_match_node(rockchip_bank_match, child)) 2812 continue; 2813 2814 info->nfunctions++; 2815 info->ngroups += of_get_child_count(child); 2816 } 2817 } 2818 2819 static int rockchip_pinctrl_parse_groups(struct device_node *np, 2820 struct rockchip_pin_group *grp, 2821 struct rockchip_pinctrl *info, 2822 u32 index) 2823 { 2824 struct rockchip_pin_bank *bank; 2825 int size; 2826 const __be32 *list; 2827 int num; 2828 int i, j; 2829 int ret; 2830 2831 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); 2832 2833 /* Initialise group */ 2834 grp->name = np->name; 2835 2836 /* 2837 * the binding format is rockchip,pins = <bank pin mux CONFIG>, 2838 * do sanity check and calculate pins number 2839 */ 2840 list = of_get_property(np, "rockchip,pins", &size); 2841 /* we do not check return since it's safe node passed down */ 2842 size /= sizeof(*list); 2843 if (!size || size % 4) { 2844 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); 2845 return -EINVAL; 2846 } 2847 2848 grp->npins = size / 4; 2849 2850 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), 2851 GFP_KERNEL); 2852 grp->data = devm_kcalloc(info->dev, 2853 grp->npins, 2854 sizeof(struct rockchip_pin_config), 2855 GFP_KERNEL); 2856 if (!grp->pins || !grp->data) 2857 return -ENOMEM; 2858 2859 for (i = 0, j = 0; i < size; i += 4, j++) { 2860 const __be32 *phandle; 2861 struct device_node *np_config; 2862 2863 num = be32_to_cpu(*list++); 2864 bank = bank_num_to_bank(info, num); 2865 if (IS_ERR(bank)) 2866 return PTR_ERR(bank); 2867 2868 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); 2869 grp->data[j].func = be32_to_cpu(*list++); 2870 2871 phandle = list++; 2872 if (!phandle) 2873 return -EINVAL; 2874 2875 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 2876 ret = pinconf_generic_parse_dt_config(np_config, NULL, 2877 &grp->data[j].configs, &grp->data[j].nconfigs); 2878 if (ret) 2879 return ret; 2880 } 2881 2882 return 0; 2883 } 2884 2885 static int rockchip_pinctrl_parse_functions(struct device_node *np, 2886 struct rockchip_pinctrl *info, 2887 u32 index) 2888 { 2889 struct device_node *child; 2890 struct rockchip_pmx_func *func; 2891 struct rockchip_pin_group *grp; 2892 int ret; 2893 static u32 grp_index; 2894 u32 i = 0; 2895 2896 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); 2897 2898 func = &info->functions[index]; 2899 2900 /* Initialise function */ 2901 func->name = np->name; 2902 func->ngroups = of_get_child_count(np); 2903 if (func->ngroups <= 0) 2904 return 0; 2905 2906 func->groups = devm_kcalloc(info->dev, 2907 func->ngroups, sizeof(char *), GFP_KERNEL); 2908 if (!func->groups) 2909 return -ENOMEM; 2910 2911 for_each_child_of_node(np, child) { 2912 func->groups[i] = child->name; 2913 grp = &info->groups[grp_index++]; 2914 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); 2915 if (ret) { 2916 of_node_put(child); 2917 return ret; 2918 } 2919 } 2920 2921 return 0; 2922 } 2923 2924 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, 2925 struct rockchip_pinctrl *info) 2926 { 2927 struct device *dev = &pdev->dev; 2928 struct device_node *np = dev->of_node; 2929 struct device_node *child; 2930 int ret; 2931 int i; 2932 2933 rockchip_pinctrl_child_count(info, np); 2934 2935 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); 2936 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); 2937 2938 info->functions = devm_kcalloc(dev, 2939 info->nfunctions, 2940 sizeof(struct rockchip_pmx_func), 2941 GFP_KERNEL); 2942 if (!info->functions) 2943 return -EINVAL; 2944 2945 info->groups = devm_kcalloc(dev, 2946 info->ngroups, 2947 sizeof(struct rockchip_pin_group), 2948 GFP_KERNEL); 2949 if (!info->groups) 2950 return -EINVAL; 2951 2952 i = 0; 2953 2954 for_each_child_of_node(np, child) { 2955 if (of_match_node(rockchip_bank_match, child)) 2956 continue; 2957 2958 ret = rockchip_pinctrl_parse_functions(child, info, i++); 2959 if (ret) { 2960 dev_err(&pdev->dev, "failed to parse function\n"); 2961 of_node_put(child); 2962 return ret; 2963 } 2964 } 2965 2966 return 0; 2967 } 2968 2969 static int rockchip_pinctrl_register(struct platform_device *pdev, 2970 struct rockchip_pinctrl *info) 2971 { 2972 struct pinctrl_desc *ctrldesc = &info->pctl; 2973 struct pinctrl_pin_desc *pindesc, *pdesc; 2974 struct rockchip_pin_bank *pin_bank; 2975 int pin, bank, ret; 2976 int k; 2977 2978 ctrldesc->name = "rockchip-pinctrl"; 2979 ctrldesc->owner = THIS_MODULE; 2980 ctrldesc->pctlops = &rockchip_pctrl_ops; 2981 ctrldesc->pmxops = &rockchip_pmx_ops; 2982 ctrldesc->confops = &rockchip_pinconf_ops; 2983 2984 pindesc = devm_kcalloc(&pdev->dev, 2985 info->ctrl->nr_pins, sizeof(*pindesc), 2986 GFP_KERNEL); 2987 if (!pindesc) 2988 return -ENOMEM; 2989 2990 ctrldesc->pins = pindesc; 2991 ctrldesc->npins = info->ctrl->nr_pins; 2992 2993 pdesc = pindesc; 2994 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { 2995 pin_bank = &info->ctrl->pin_banks[bank]; 2996 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { 2997 pdesc->number = k; 2998 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", 2999 pin_bank->name, pin); 3000 pdesc++; 3001 } 3002 } 3003 3004 ret = rockchip_pinctrl_parse_dt(pdev, info); 3005 if (ret) 3006 return ret; 3007 3008 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); 3009 if (IS_ERR(info->pctl_dev)) { 3010 dev_err(&pdev->dev, "could not register pinctrl driver\n"); 3011 return PTR_ERR(info->pctl_dev); 3012 } 3013 3014 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { 3015 pin_bank = &info->ctrl->pin_banks[bank]; 3016 pin_bank->grange.name = pin_bank->name; 3017 pin_bank->grange.id = bank; 3018 pin_bank->grange.pin_base = pin_bank->pin_base; 3019 pin_bank->grange.base = pin_bank->gpio_chip.base; 3020 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 3021 pin_bank->grange.gc = &pin_bank->gpio_chip; 3022 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); 3023 } 3024 3025 return 0; 3026 } 3027 3028 /* 3029 * GPIO handling 3030 */ 3031 3032 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 3033 { 3034 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3035 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; 3036 unsigned long flags; 3037 u32 data; 3038 3039 clk_enable(bank->clk); 3040 raw_spin_lock_irqsave(&bank->slock, flags); 3041 3042 data = readl(reg); 3043 data &= ~BIT(offset); 3044 if (value) 3045 data |= BIT(offset); 3046 writel(data, reg); 3047 3048 raw_spin_unlock_irqrestore(&bank->slock, flags); 3049 clk_disable(bank->clk); 3050 } 3051 3052 /* 3053 * Returns the level of the pin for input direction and setting of the DR 3054 * register for output gpios. 3055 */ 3056 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) 3057 { 3058 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3059 u32 data; 3060 3061 clk_enable(bank->clk); 3062 data = readl(bank->reg_base + GPIO_EXT_PORT); 3063 clk_disable(bank->clk); 3064 data >>= offset; 3065 data &= 1; 3066 return data; 3067 } 3068 3069 /* 3070 * gpiolib gpio_direction_input callback function. The setting of the pin 3071 * mux function as 'gpio input' will be handled by the pinctrl subsystem 3072 * interface. 3073 */ 3074 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 3075 { 3076 return pinctrl_gpio_direction_input(gc->base + offset); 3077 } 3078 3079 /* 3080 * gpiolib gpio_direction_output callback function. The setting of the pin 3081 * mux function as 'gpio output' will be handled by the pinctrl subsystem 3082 * interface. 3083 */ 3084 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 3085 unsigned offset, int value) 3086 { 3087 rockchip_gpio_set(gc, offset, value); 3088 return pinctrl_gpio_direction_output(gc->base + offset); 3089 } 3090 3091 static void rockchip_gpio_set_debounce(struct gpio_chip *gc, 3092 unsigned int offset, bool enable) 3093 { 3094 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3095 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; 3096 unsigned long flags; 3097 u32 data; 3098 3099 clk_enable(bank->clk); 3100 raw_spin_lock_irqsave(&bank->slock, flags); 3101 3102 data = readl(reg); 3103 if (enable) 3104 data |= BIT(offset); 3105 else 3106 data &= ~BIT(offset); 3107 writel(data, reg); 3108 3109 raw_spin_unlock_irqrestore(&bank->slock, flags); 3110 clk_disable(bank->clk); 3111 } 3112 3113 /* 3114 * gpiolib set_config callback function. The setting of the pin 3115 * mux function as 'gpio output' will be handled by the pinctrl subsystem 3116 * interface. 3117 */ 3118 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 3119 unsigned long config) 3120 { 3121 enum pin_config_param param = pinconf_to_config_param(config); 3122 3123 switch (param) { 3124 case PIN_CONFIG_INPUT_DEBOUNCE: 3125 rockchip_gpio_set_debounce(gc, offset, true); 3126 /* 3127 * Rockchip's gpio could only support up to one period 3128 * of the debounce clock(pclk), which is far away from 3129 * satisftying the requirement, as pclk is usually near 3130 * 100MHz shared by all peripherals. So the fact is it 3131 * has crippled debounce capability could only be useful 3132 * to prevent any spurious glitches from waking up the system 3133 * if the gpio is conguired as wakeup interrupt source. Let's 3134 * still return -ENOTSUPP as before, to make sure the caller 3135 * of gpiod_set_debounce won't change its behaviour. 3136 */ 3137 return -ENOTSUPP; 3138 default: 3139 return -ENOTSUPP; 3140 } 3141 } 3142 3143 /* 3144 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin 3145 * and a virtual IRQ, if not already present. 3146 */ 3147 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 3148 { 3149 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 3150 unsigned int virq; 3151 3152 if (!bank->domain) 3153 return -ENXIO; 3154 3155 virq = irq_create_mapping(bank->domain, offset); 3156 3157 return (virq) ? : -ENXIO; 3158 } 3159 3160 static const struct gpio_chip rockchip_gpiolib_chip = { 3161 .request = gpiochip_generic_request, 3162 .free = gpiochip_generic_free, 3163 .set = rockchip_gpio_set, 3164 .get = rockchip_gpio_get, 3165 .get_direction = rockchip_gpio_get_direction, 3166 .direction_input = rockchip_gpio_direction_input, 3167 .direction_output = rockchip_gpio_direction_output, 3168 .set_config = rockchip_gpio_set_config, 3169 .to_irq = rockchip_gpio_to_irq, 3170 .owner = THIS_MODULE, 3171 }; 3172 3173 /* 3174 * Interrupt handling 3175 */ 3176 3177 static void rockchip_irq_demux(struct irq_desc *desc) 3178 { 3179 struct irq_chip *chip = irq_desc_get_chip(desc); 3180 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 3181 u32 pend; 3182 3183 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 3184 3185 chained_irq_enter(chip, desc); 3186 3187 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 3188 3189 while (pend) { 3190 unsigned int irq, virq; 3191 3192 irq = __ffs(pend); 3193 pend &= ~BIT(irq); 3194 virq = irq_linear_revmap(bank->domain, irq); 3195 3196 if (!virq) { 3197 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); 3198 continue; 3199 } 3200 3201 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 3202 3203 /* 3204 * Triggering IRQ on both rising and falling edge 3205 * needs manual intervention. 3206 */ 3207 if (bank->toggle_edge_mode & BIT(irq)) { 3208 u32 data, data_old, polarity; 3209 unsigned long flags; 3210 3211 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); 3212 do { 3213 raw_spin_lock_irqsave(&bank->slock, flags); 3214 3215 polarity = readl_relaxed(bank->reg_base + 3216 GPIO_INT_POLARITY); 3217 if (data & BIT(irq)) 3218 polarity &= ~BIT(irq); 3219 else 3220 polarity |= BIT(irq); 3221 writel(polarity, 3222 bank->reg_base + GPIO_INT_POLARITY); 3223 3224 raw_spin_unlock_irqrestore(&bank->slock, flags); 3225 3226 data_old = data; 3227 data = readl_relaxed(bank->reg_base + 3228 GPIO_EXT_PORT); 3229 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 3230 } 3231 3232 generic_handle_irq(virq); 3233 } 3234 3235 chained_irq_exit(chip, desc); 3236 } 3237 3238 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 3239 { 3240 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3241 struct rockchip_pin_bank *bank = gc->private; 3242 u32 mask = BIT(d->hwirq); 3243 u32 polarity; 3244 u32 level; 3245 u32 data; 3246 unsigned long flags; 3247 int ret; 3248 3249 /* make sure the pin is configured as gpio input */ 3250 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); 3251 if (ret < 0) 3252 return ret; 3253 3254 clk_enable(bank->clk); 3255 raw_spin_lock_irqsave(&bank->slock, flags); 3256 3257 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 3258 data &= ~mask; 3259 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 3260 3261 raw_spin_unlock_irqrestore(&bank->slock, flags); 3262 3263 if (type & IRQ_TYPE_EDGE_BOTH) 3264 irq_set_handler_locked(d, handle_edge_irq); 3265 else 3266 irq_set_handler_locked(d, handle_level_irq); 3267 3268 raw_spin_lock_irqsave(&bank->slock, flags); 3269 irq_gc_lock(gc); 3270 3271 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); 3272 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 3273 3274 switch (type) { 3275 case IRQ_TYPE_EDGE_BOTH: 3276 bank->toggle_edge_mode |= mask; 3277 level |= mask; 3278 3279 /* 3280 * Determine gpio state. If 1 next interrupt should be falling 3281 * otherwise rising. 3282 */ 3283 data = readl(bank->reg_base + GPIO_EXT_PORT); 3284 if (data & mask) 3285 polarity &= ~mask; 3286 else 3287 polarity |= mask; 3288 break; 3289 case IRQ_TYPE_EDGE_RISING: 3290 bank->toggle_edge_mode &= ~mask; 3291 level |= mask; 3292 polarity |= mask; 3293 break; 3294 case IRQ_TYPE_EDGE_FALLING: 3295 bank->toggle_edge_mode &= ~mask; 3296 level |= mask; 3297 polarity &= ~mask; 3298 break; 3299 case IRQ_TYPE_LEVEL_HIGH: 3300 bank->toggle_edge_mode &= ~mask; 3301 level &= ~mask; 3302 polarity |= mask; 3303 break; 3304 case IRQ_TYPE_LEVEL_LOW: 3305 bank->toggle_edge_mode &= ~mask; 3306 level &= ~mask; 3307 polarity &= ~mask; 3308 break; 3309 default: 3310 irq_gc_unlock(gc); 3311 raw_spin_unlock_irqrestore(&bank->slock, flags); 3312 clk_disable(bank->clk); 3313 return -EINVAL; 3314 } 3315 3316 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); 3317 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); 3318 3319 irq_gc_unlock(gc); 3320 raw_spin_unlock_irqrestore(&bank->slock, flags); 3321 clk_disable(bank->clk); 3322 3323 return 0; 3324 } 3325 3326 static void rockchip_irq_suspend(struct irq_data *d) 3327 { 3328 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3329 struct rockchip_pin_bank *bank = gc->private; 3330 3331 clk_enable(bank->clk); 3332 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 3333 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 3334 clk_disable(bank->clk); 3335 } 3336 3337 static void rockchip_irq_resume(struct irq_data *d) 3338 { 3339 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3340 struct rockchip_pin_bank *bank = gc->private; 3341 3342 clk_enable(bank->clk); 3343 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 3344 clk_disable(bank->clk); 3345 } 3346 3347 static void rockchip_irq_enable(struct irq_data *d) 3348 { 3349 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3350 struct rockchip_pin_bank *bank = gc->private; 3351 3352 clk_enable(bank->clk); 3353 irq_gc_mask_clr_bit(d); 3354 } 3355 3356 static void rockchip_irq_disable(struct irq_data *d) 3357 { 3358 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 3359 struct rockchip_pin_bank *bank = gc->private; 3360 3361 irq_gc_mask_set_bit(d); 3362 clk_disable(bank->clk); 3363 } 3364 3365 static int rockchip_interrupts_register(struct platform_device *pdev, 3366 struct rockchip_pinctrl *info) 3367 { 3368 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3369 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3370 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 3371 struct irq_chip_generic *gc; 3372 int ret; 3373 int i, j; 3374 3375 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3376 if (!bank->valid) { 3377 dev_warn(&pdev->dev, "bank %s is not valid\n", 3378 bank->name); 3379 continue; 3380 } 3381 3382 ret = clk_enable(bank->clk); 3383 if (ret) { 3384 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", 3385 bank->name); 3386 continue; 3387 } 3388 3389 bank->domain = irq_domain_add_linear(bank->of_node, 32, 3390 &irq_generic_chip_ops, NULL); 3391 if (!bank->domain) { 3392 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 3393 bank->name); 3394 clk_disable(bank->clk); 3395 continue; 3396 } 3397 3398 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 3399 "rockchip_gpio_irq", handle_level_irq, 3400 clr, 0, IRQ_GC_INIT_MASK_CACHE); 3401 if (ret) { 3402 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 3403 bank->name); 3404 irq_domain_remove(bank->domain); 3405 clk_disable(bank->clk); 3406 continue; 3407 } 3408 3409 /* 3410 * Linux assumes that all interrupts start out disabled/masked. 3411 * Our driver only uses the concept of masked and always keeps 3412 * things enabled, so for us that's all masked and all enabled. 3413 */ 3414 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); 3415 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); 3416 3417 gc = irq_get_domain_generic_chip(bank->domain, 0); 3418 gc->reg_base = bank->reg_base; 3419 gc->private = bank; 3420 gc->chip_types[0].regs.mask = GPIO_INTMASK; 3421 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 3422 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 3423 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 3424 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 3425 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 3426 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 3427 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 3428 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 3429 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 3430 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 3431 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 3432 3433 irq_set_chained_handler_and_data(bank->irq, 3434 rockchip_irq_demux, bank); 3435 3436 /* map the gpio irqs here, when the clock is still running */ 3437 for (j = 0 ; j < 32 ; j++) 3438 irq_create_mapping(bank->domain, j); 3439 3440 clk_disable(bank->clk); 3441 } 3442 3443 return 0; 3444 } 3445 3446 static int rockchip_gpiolib_register(struct platform_device *pdev, 3447 struct rockchip_pinctrl *info) 3448 { 3449 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3450 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3451 struct gpio_chip *gc; 3452 int ret; 3453 int i; 3454 3455 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3456 if (!bank->valid) { 3457 dev_warn(&pdev->dev, "bank %s is not valid\n", 3458 bank->name); 3459 continue; 3460 } 3461 3462 bank->gpio_chip = rockchip_gpiolib_chip; 3463 3464 gc = &bank->gpio_chip; 3465 gc->base = bank->pin_base; 3466 gc->ngpio = bank->nr_pins; 3467 gc->parent = &pdev->dev; 3468 gc->of_node = bank->of_node; 3469 gc->label = bank->name; 3470 3471 ret = gpiochip_add_data(gc, bank); 3472 if (ret) { 3473 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", 3474 gc->label, ret); 3475 goto fail; 3476 } 3477 } 3478 3479 rockchip_interrupts_register(pdev, info); 3480 3481 return 0; 3482 3483 fail: 3484 for (--i, --bank; i >= 0; --i, --bank) { 3485 if (!bank->valid) 3486 continue; 3487 gpiochip_remove(&bank->gpio_chip); 3488 } 3489 return ret; 3490 } 3491 3492 static int rockchip_gpiolib_unregister(struct platform_device *pdev, 3493 struct rockchip_pinctrl *info) 3494 { 3495 struct rockchip_pin_ctrl *ctrl = info->ctrl; 3496 struct rockchip_pin_bank *bank = ctrl->pin_banks; 3497 int i; 3498 3499 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3500 if (!bank->valid) 3501 continue; 3502 gpiochip_remove(&bank->gpio_chip); 3503 } 3504 3505 return 0; 3506 } 3507 3508 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, 3509 struct rockchip_pinctrl *info) 3510 { 3511 struct resource res; 3512 void __iomem *base; 3513 3514 if (of_address_to_resource(bank->of_node, 0, &res)) { 3515 dev_err(info->dev, "cannot find IO resource for bank\n"); 3516 return -ENOENT; 3517 } 3518 3519 bank->reg_base = devm_ioremap_resource(info->dev, &res); 3520 if (IS_ERR(bank->reg_base)) 3521 return PTR_ERR(bank->reg_base); 3522 3523 /* 3524 * special case, where parts of the pull setting-registers are 3525 * part of the PMU register space 3526 */ 3527 if (of_device_is_compatible(bank->of_node, 3528 "rockchip,rk3188-gpio-bank0")) { 3529 struct device_node *node; 3530 3531 node = of_parse_phandle(bank->of_node->parent, 3532 "rockchip,pmu", 0); 3533 if (!node) { 3534 if (of_address_to_resource(bank->of_node, 1, &res)) { 3535 dev_err(info->dev, "cannot find IO resource for bank\n"); 3536 return -ENOENT; 3537 } 3538 3539 base = devm_ioremap_resource(info->dev, &res); 3540 if (IS_ERR(base)) 3541 return PTR_ERR(base); 3542 rockchip_regmap_config.max_register = 3543 resource_size(&res) - 4; 3544 rockchip_regmap_config.name = 3545 "rockchip,rk3188-gpio-bank0-pull"; 3546 bank->regmap_pull = devm_regmap_init_mmio(info->dev, 3547 base, 3548 &rockchip_regmap_config); 3549 } 3550 of_node_put(node); 3551 } 3552 3553 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 3554 3555 bank->clk = of_clk_get(bank->of_node, 0); 3556 if (IS_ERR(bank->clk)) 3557 return PTR_ERR(bank->clk); 3558 3559 return clk_prepare(bank->clk); 3560 } 3561 3562 static const struct of_device_id rockchip_pinctrl_dt_match[]; 3563 3564 /* retrieve the soc specific data */ 3565 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 3566 struct rockchip_pinctrl *d, 3567 struct platform_device *pdev) 3568 { 3569 const struct of_device_id *match; 3570 struct device_node *node = pdev->dev.of_node; 3571 struct device_node *np; 3572 struct rockchip_pin_ctrl *ctrl; 3573 struct rockchip_pin_bank *bank; 3574 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 3575 3576 match = of_match_node(rockchip_pinctrl_dt_match, node); 3577 ctrl = (struct rockchip_pin_ctrl *)match->data; 3578 3579 for_each_child_of_node(node, np) { 3580 if (!of_find_property(np, "gpio-controller", NULL)) 3581 continue; 3582 3583 bank = ctrl->pin_banks; 3584 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3585 if (!strcmp(bank->name, np->name)) { 3586 bank->of_node = np; 3587 3588 if (!rockchip_get_bank_data(bank, d)) 3589 bank->valid = true; 3590 3591 break; 3592 } 3593 } 3594 } 3595 3596 grf_offs = ctrl->grf_mux_offset; 3597 pmu_offs = ctrl->pmu_mux_offset; 3598 drv_pmu_offs = ctrl->pmu_drv_offset; 3599 drv_grf_offs = ctrl->grf_drv_offset; 3600 bank = ctrl->pin_banks; 3601 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 3602 int bank_pins = 0; 3603 3604 raw_spin_lock_init(&bank->slock); 3605 bank->drvdata = d; 3606 bank->pin_base = ctrl->nr_pins; 3607 ctrl->nr_pins += bank->nr_pins; 3608 3609 /* calculate iomux and drv offsets */ 3610 for (j = 0; j < 4; j++) { 3611 struct rockchip_iomux *iom = &bank->iomux[j]; 3612 struct rockchip_drv *drv = &bank->drv[j]; 3613 int inc; 3614 3615 if (bank_pins >= bank->nr_pins) 3616 break; 3617 3618 /* preset iomux offset value, set new start value */ 3619 if (iom->offset >= 0) { 3620 if (iom->type & IOMUX_SOURCE_PMU) 3621 pmu_offs = iom->offset; 3622 else 3623 grf_offs = iom->offset; 3624 } else { /* set current iomux offset */ 3625 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3626 pmu_offs : grf_offs; 3627 } 3628 3629 /* preset drv offset value, set new start value */ 3630 if (drv->offset >= 0) { 3631 if (iom->type & IOMUX_SOURCE_PMU) 3632 drv_pmu_offs = drv->offset; 3633 else 3634 drv_grf_offs = drv->offset; 3635 } else { /* set current drv offset */ 3636 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 3637 drv_pmu_offs : drv_grf_offs; 3638 } 3639 3640 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 3641 i, j, iom->offset, drv->offset); 3642 3643 /* 3644 * Increase offset according to iomux width. 3645 * 4bit iomux'es are spread over two registers. 3646 */ 3647 inc = (iom->type & (IOMUX_WIDTH_4BIT | 3648 IOMUX_WIDTH_3BIT | 3649 IOMUX_WIDTH_2BIT)) ? 8 : 4; 3650 if (iom->type & IOMUX_SOURCE_PMU) 3651 pmu_offs += inc; 3652 else 3653 grf_offs += inc; 3654 3655 /* 3656 * Increase offset according to drv width. 3657 * 3bit drive-strenth'es are spread over two registers. 3658 */ 3659 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 3660 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 3661 inc = 8; 3662 else 3663 inc = 4; 3664 3665 if (iom->type & IOMUX_SOURCE_PMU) 3666 drv_pmu_offs += inc; 3667 else 3668 drv_grf_offs += inc; 3669 3670 bank_pins += 8; 3671 } 3672 3673 /* calculate the per-bank recalced_mask */ 3674 for (j = 0; j < ctrl->niomux_recalced; j++) { 3675 int pin = 0; 3676 3677 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 3678 pin = ctrl->iomux_recalced[j].pin; 3679 bank->recalced_mask |= BIT(pin); 3680 } 3681 } 3682 3683 /* calculate the per-bank route_mask */ 3684 for (j = 0; j < ctrl->niomux_routes; j++) { 3685 int pin = 0; 3686 3687 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 3688 pin = ctrl->iomux_routes[j].pin; 3689 bank->route_mask |= BIT(pin); 3690 } 3691 } 3692 } 3693 3694 return ctrl; 3695 } 3696 3697 #define RK3288_GRF_GPIO6C_IOMUX 0x64 3698 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) 3699 3700 static u32 rk3288_grf_gpio6c_iomux; 3701 3702 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) 3703 { 3704 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3705 int ret = pinctrl_force_sleep(info->pctl_dev); 3706 3707 if (ret) 3708 return ret; 3709 3710 /* 3711 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save 3712 * the setting here, and restore it at resume. 3713 */ 3714 if (info->ctrl->type == RK3288) { 3715 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3716 &rk3288_grf_gpio6c_iomux); 3717 if (ret) { 3718 pinctrl_force_default(info->pctl_dev); 3719 return ret; 3720 } 3721 } 3722 3723 return 0; 3724 } 3725 3726 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) 3727 { 3728 struct rockchip_pinctrl *info = dev_get_drvdata(dev); 3729 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, 3730 rk3288_grf_gpio6c_iomux | 3731 GPIO6C6_SEL_WRITE_ENABLE); 3732 3733 if (ret) 3734 return ret; 3735 3736 return pinctrl_force_default(info->pctl_dev); 3737 } 3738 3739 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, 3740 rockchip_pinctrl_resume); 3741 3742 static int rockchip_pinctrl_probe(struct platform_device *pdev) 3743 { 3744 struct rockchip_pinctrl *info; 3745 struct device *dev = &pdev->dev; 3746 struct rockchip_pin_ctrl *ctrl; 3747 struct device_node *np = pdev->dev.of_node, *node; 3748 struct resource *res; 3749 void __iomem *base; 3750 int ret; 3751 3752 if (!dev->of_node) { 3753 dev_err(dev, "device tree node not found\n"); 3754 return -ENODEV; 3755 } 3756 3757 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 3758 if (!info) 3759 return -ENOMEM; 3760 3761 info->dev = dev; 3762 3763 ctrl = rockchip_pinctrl_get_soc_data(info, pdev); 3764 if (!ctrl) { 3765 dev_err(dev, "driver data not available\n"); 3766 return -EINVAL; 3767 } 3768 info->ctrl = ctrl; 3769 3770 node = of_parse_phandle(np, "rockchip,grf", 0); 3771 if (node) { 3772 info->regmap_base = syscon_node_to_regmap(node); 3773 if (IS_ERR(info->regmap_base)) 3774 return PTR_ERR(info->regmap_base); 3775 } else { 3776 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3777 base = devm_ioremap_resource(&pdev->dev, res); 3778 if (IS_ERR(base)) 3779 return PTR_ERR(base); 3780 3781 rockchip_regmap_config.max_register = resource_size(res) - 4; 3782 rockchip_regmap_config.name = "rockchip,pinctrl"; 3783 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, 3784 &rockchip_regmap_config); 3785 3786 /* to check for the old dt-bindings */ 3787 info->reg_size = resource_size(res); 3788 3789 /* Honor the old binding, with pull registers as 2nd resource */ 3790 if (ctrl->type == RK3188 && info->reg_size < 0x200) { 3791 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3792 base = devm_ioremap_resource(&pdev->dev, res); 3793 if (IS_ERR(base)) 3794 return PTR_ERR(base); 3795 3796 rockchip_regmap_config.max_register = 3797 resource_size(res) - 4; 3798 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; 3799 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, 3800 base, 3801 &rockchip_regmap_config); 3802 } 3803 } 3804 3805 /* try to find the optional reference to the pmu syscon */ 3806 node = of_parse_phandle(np, "rockchip,pmu", 0); 3807 if (node) { 3808 info->regmap_pmu = syscon_node_to_regmap(node); 3809 if (IS_ERR(info->regmap_pmu)) 3810 return PTR_ERR(info->regmap_pmu); 3811 } 3812 3813 ret = rockchip_gpiolib_register(pdev, info); 3814 if (ret) 3815 return ret; 3816 3817 ret = rockchip_pinctrl_register(pdev, info); 3818 if (ret) { 3819 rockchip_gpiolib_unregister(pdev, info); 3820 return ret; 3821 } 3822 3823 platform_set_drvdata(pdev, info); 3824 3825 return 0; 3826 } 3827 3828 static struct rockchip_pin_bank px30_pin_banks[] = { 3829 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3830 IOMUX_SOURCE_PMU, 3831 IOMUX_SOURCE_PMU, 3832 IOMUX_SOURCE_PMU 3833 ), 3834 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 3835 IOMUX_WIDTH_4BIT, 3836 IOMUX_WIDTH_4BIT, 3837 IOMUX_WIDTH_4BIT 3838 ), 3839 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 3840 IOMUX_WIDTH_4BIT, 3841 IOMUX_WIDTH_4BIT, 3842 IOMUX_WIDTH_4BIT 3843 ), 3844 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 3845 IOMUX_WIDTH_4BIT, 3846 IOMUX_WIDTH_4BIT, 3847 IOMUX_WIDTH_4BIT 3848 ), 3849 }; 3850 3851 static struct rockchip_pin_ctrl px30_pin_ctrl = { 3852 .pin_banks = px30_pin_banks, 3853 .nr_banks = ARRAY_SIZE(px30_pin_banks), 3854 .label = "PX30-GPIO", 3855 .type = PX30, 3856 .grf_mux_offset = 0x0, 3857 .pmu_mux_offset = 0x0, 3858 .iomux_routes = px30_mux_route_data, 3859 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 3860 .pull_calc_reg = px30_calc_pull_reg_and_bit, 3861 .drv_calc_reg = px30_calc_drv_reg_and_bit, 3862 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 3863 }; 3864 3865 static struct rockchip_pin_bank rv1108_pin_banks[] = { 3866 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 3867 IOMUX_SOURCE_PMU, 3868 IOMUX_SOURCE_PMU, 3869 IOMUX_SOURCE_PMU), 3870 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 3871 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 3872 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 3873 }; 3874 3875 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 3876 .pin_banks = rv1108_pin_banks, 3877 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 3878 .label = "RV1108-GPIO", 3879 .type = RV1108, 3880 .grf_mux_offset = 0x10, 3881 .pmu_mux_offset = 0x0, 3882 .iomux_recalced = rv1108_mux_recalced_data, 3883 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 3884 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 3885 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 3886 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 3887 }; 3888 3889 static struct rockchip_pin_bank rk2928_pin_banks[] = { 3890 PIN_BANK(0, 32, "gpio0"), 3891 PIN_BANK(1, 32, "gpio1"), 3892 PIN_BANK(2, 32, "gpio2"), 3893 PIN_BANK(3, 32, "gpio3"), 3894 }; 3895 3896 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 3897 .pin_banks = rk2928_pin_banks, 3898 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 3899 .label = "RK2928-GPIO", 3900 .type = RK2928, 3901 .grf_mux_offset = 0xa8, 3902 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3903 }; 3904 3905 static struct rockchip_pin_bank rk3036_pin_banks[] = { 3906 PIN_BANK(0, 32, "gpio0"), 3907 PIN_BANK(1, 32, "gpio1"), 3908 PIN_BANK(2, 32, "gpio2"), 3909 }; 3910 3911 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 3912 .pin_banks = rk3036_pin_banks, 3913 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 3914 .label = "RK3036-GPIO", 3915 .type = RK2928, 3916 .grf_mux_offset = 0xa8, 3917 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3918 }; 3919 3920 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 3921 PIN_BANK(0, 32, "gpio0"), 3922 PIN_BANK(1, 32, "gpio1"), 3923 PIN_BANK(2, 32, "gpio2"), 3924 PIN_BANK(3, 32, "gpio3"), 3925 PIN_BANK(4, 32, "gpio4"), 3926 PIN_BANK(6, 16, "gpio6"), 3927 }; 3928 3929 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 3930 .pin_banks = rk3066a_pin_banks, 3931 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 3932 .label = "RK3066a-GPIO", 3933 .type = RK2928, 3934 .grf_mux_offset = 0xa8, 3935 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 3936 }; 3937 3938 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 3939 PIN_BANK(0, 32, "gpio0"), 3940 PIN_BANK(1, 32, "gpio1"), 3941 PIN_BANK(2, 32, "gpio2"), 3942 PIN_BANK(3, 32, "gpio3"), 3943 }; 3944 3945 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 3946 .pin_banks = rk3066b_pin_banks, 3947 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 3948 .label = "RK3066b-GPIO", 3949 .type = RK3066B, 3950 .grf_mux_offset = 0x60, 3951 }; 3952 3953 static struct rockchip_pin_bank rk3128_pin_banks[] = { 3954 PIN_BANK(0, 32, "gpio0"), 3955 PIN_BANK(1, 32, "gpio1"), 3956 PIN_BANK(2, 32, "gpio2"), 3957 PIN_BANK(3, 32, "gpio3"), 3958 }; 3959 3960 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 3961 .pin_banks = rk3128_pin_banks, 3962 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 3963 .label = "RK3128-GPIO", 3964 .type = RK3128, 3965 .grf_mux_offset = 0xa8, 3966 .iomux_recalced = rk3128_mux_recalced_data, 3967 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 3968 .iomux_routes = rk3128_mux_route_data, 3969 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 3970 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 3971 }; 3972 3973 static struct rockchip_pin_bank rk3188_pin_banks[] = { 3974 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 3975 PIN_BANK(1, 32, "gpio1"), 3976 PIN_BANK(2, 32, "gpio2"), 3977 PIN_BANK(3, 32, "gpio3"), 3978 }; 3979 3980 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 3981 .pin_banks = rk3188_pin_banks, 3982 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 3983 .label = "RK3188-GPIO", 3984 .type = RK3188, 3985 .grf_mux_offset = 0x60, 3986 .iomux_routes = rk3188_mux_route_data, 3987 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), 3988 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 3989 }; 3990 3991 static struct rockchip_pin_bank rk3228_pin_banks[] = { 3992 PIN_BANK(0, 32, "gpio0"), 3993 PIN_BANK(1, 32, "gpio1"), 3994 PIN_BANK(2, 32, "gpio2"), 3995 PIN_BANK(3, 32, "gpio3"), 3996 }; 3997 3998 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 3999 .pin_banks = rk3228_pin_banks, 4000 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 4001 .label = "RK3228-GPIO", 4002 .type = RK3288, 4003 .grf_mux_offset = 0x0, 4004 .iomux_routes = rk3228_mux_route_data, 4005 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 4006 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4007 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4008 }; 4009 4010 static struct rockchip_pin_bank rk3288_pin_banks[] = { 4011 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 4012 IOMUX_SOURCE_PMU, 4013 IOMUX_SOURCE_PMU, 4014 IOMUX_UNROUTED 4015 ), 4016 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 4017 IOMUX_UNROUTED, 4018 IOMUX_UNROUTED, 4019 0 4020 ), 4021 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 4022 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 4023 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 4024 IOMUX_WIDTH_4BIT, 4025 0, 4026 0 4027 ), 4028 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 4029 0, 4030 0, 4031 IOMUX_UNROUTED 4032 ), 4033 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 4034 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 4035 0, 4036 IOMUX_WIDTH_4BIT, 4037 IOMUX_UNROUTED 4038 ), 4039 PIN_BANK(8, 16, "gpio8"), 4040 }; 4041 4042 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 4043 .pin_banks = rk3288_pin_banks, 4044 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 4045 .label = "RK3288-GPIO", 4046 .type = RK3288, 4047 .grf_mux_offset = 0x0, 4048 .pmu_mux_offset = 0x84, 4049 .iomux_routes = rk3288_mux_route_data, 4050 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 4051 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 4052 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 4053 }; 4054 4055 static struct rockchip_pin_bank rk3308_pin_banks[] = { 4056 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, 4057 IOMUX_WIDTH_2BIT, 4058 IOMUX_WIDTH_2BIT, 4059 IOMUX_WIDTH_2BIT), 4060 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, 4061 IOMUX_WIDTH_2BIT, 4062 IOMUX_WIDTH_2BIT, 4063 IOMUX_WIDTH_2BIT), 4064 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, 4065 IOMUX_WIDTH_2BIT, 4066 IOMUX_WIDTH_2BIT, 4067 IOMUX_WIDTH_2BIT), 4068 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, 4069 IOMUX_WIDTH_2BIT, 4070 IOMUX_WIDTH_2BIT, 4071 IOMUX_WIDTH_2BIT), 4072 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, 4073 IOMUX_WIDTH_2BIT, 4074 IOMUX_WIDTH_2BIT, 4075 IOMUX_WIDTH_2BIT), 4076 }; 4077 4078 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 4079 .pin_banks = rk3308_pin_banks, 4080 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 4081 .label = "RK3308-GPIO", 4082 .type = RK3308, 4083 .grf_mux_offset = 0x0, 4084 .iomux_recalced = rk3308_mux_recalced_data, 4085 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 4086 .iomux_routes = rk3308_mux_route_data, 4087 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 4088 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 4089 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 4090 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 4091 }; 4092 4093 static struct rockchip_pin_bank rk3328_pin_banks[] = { 4094 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 4095 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 4096 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 4097 IOMUX_WIDTH_3BIT, 4098 IOMUX_WIDTH_3BIT, 4099 0), 4100 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 4101 IOMUX_WIDTH_3BIT, 4102 IOMUX_WIDTH_3BIT, 4103 0, 4104 0), 4105 }; 4106 4107 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 4108 .pin_banks = rk3328_pin_banks, 4109 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 4110 .label = "RK3328-GPIO", 4111 .type = RK3288, 4112 .grf_mux_offset = 0x0, 4113 .iomux_recalced = rk3328_mux_recalced_data, 4114 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 4115 .iomux_routes = rk3328_mux_route_data, 4116 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 4117 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 4118 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 4119 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 4120 }; 4121 4122 static struct rockchip_pin_bank rk3368_pin_banks[] = { 4123 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 4124 IOMUX_SOURCE_PMU, 4125 IOMUX_SOURCE_PMU, 4126 IOMUX_SOURCE_PMU 4127 ), 4128 PIN_BANK(1, 32, "gpio1"), 4129 PIN_BANK(2, 32, "gpio2"), 4130 PIN_BANK(3, 32, "gpio3"), 4131 }; 4132 4133 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 4134 .pin_banks = rk3368_pin_banks, 4135 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 4136 .label = "RK3368-GPIO", 4137 .type = RK3368, 4138 .grf_mux_offset = 0x0, 4139 .pmu_mux_offset = 0x0, 4140 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 4141 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 4142 }; 4143 4144 static struct rockchip_pin_bank rk3399_pin_banks[] = { 4145 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 4146 IOMUX_SOURCE_PMU, 4147 IOMUX_SOURCE_PMU, 4148 IOMUX_SOURCE_PMU, 4149 IOMUX_SOURCE_PMU, 4150 DRV_TYPE_IO_1V8_ONLY, 4151 DRV_TYPE_IO_1V8_ONLY, 4152 DRV_TYPE_IO_DEFAULT, 4153 DRV_TYPE_IO_DEFAULT, 4154 0x80, 4155 0x88, 4156 -1, 4157 -1, 4158 PULL_TYPE_IO_1V8_ONLY, 4159 PULL_TYPE_IO_1V8_ONLY, 4160 PULL_TYPE_IO_DEFAULT, 4161 PULL_TYPE_IO_DEFAULT 4162 ), 4163 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 4164 IOMUX_SOURCE_PMU, 4165 IOMUX_SOURCE_PMU, 4166 IOMUX_SOURCE_PMU, 4167 DRV_TYPE_IO_1V8_OR_3V0, 4168 DRV_TYPE_IO_1V8_OR_3V0, 4169 DRV_TYPE_IO_1V8_OR_3V0, 4170 DRV_TYPE_IO_1V8_OR_3V0, 4171 0xa0, 4172 0xa8, 4173 0xb0, 4174 0xb8 4175 ), 4176 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 4177 DRV_TYPE_IO_1V8_OR_3V0, 4178 DRV_TYPE_IO_1V8_ONLY, 4179 DRV_TYPE_IO_1V8_ONLY, 4180 PULL_TYPE_IO_DEFAULT, 4181 PULL_TYPE_IO_DEFAULT, 4182 PULL_TYPE_IO_1V8_ONLY, 4183 PULL_TYPE_IO_1V8_ONLY 4184 ), 4185 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 4186 DRV_TYPE_IO_3V3_ONLY, 4187 DRV_TYPE_IO_3V3_ONLY, 4188 DRV_TYPE_IO_1V8_OR_3V0 4189 ), 4190 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 4191 DRV_TYPE_IO_1V8_3V0_AUTO, 4192 DRV_TYPE_IO_1V8_OR_3V0, 4193 DRV_TYPE_IO_1V8_OR_3V0 4194 ), 4195 }; 4196 4197 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 4198 .pin_banks = rk3399_pin_banks, 4199 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 4200 .label = "RK3399-GPIO", 4201 .type = RK3399, 4202 .grf_mux_offset = 0xe000, 4203 .pmu_mux_offset = 0x0, 4204 .grf_drv_offset = 0xe100, 4205 .pmu_drv_offset = 0x80, 4206 .iomux_routes = rk3399_mux_route_data, 4207 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 4208 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 4209 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 4210 }; 4211 4212 static const struct of_device_id rockchip_pinctrl_dt_match[] = { 4213 { .compatible = "rockchip,px30-pinctrl", 4214 .data = &px30_pin_ctrl }, 4215 { .compatible = "rockchip,rv1108-pinctrl", 4216 .data = &rv1108_pin_ctrl }, 4217 { .compatible = "rockchip,rk2928-pinctrl", 4218 .data = &rk2928_pin_ctrl }, 4219 { .compatible = "rockchip,rk3036-pinctrl", 4220 .data = &rk3036_pin_ctrl }, 4221 { .compatible = "rockchip,rk3066a-pinctrl", 4222 .data = &rk3066a_pin_ctrl }, 4223 { .compatible = "rockchip,rk3066b-pinctrl", 4224 .data = &rk3066b_pin_ctrl }, 4225 { .compatible = "rockchip,rk3128-pinctrl", 4226 .data = (void *)&rk3128_pin_ctrl }, 4227 { .compatible = "rockchip,rk3188-pinctrl", 4228 .data = &rk3188_pin_ctrl }, 4229 { .compatible = "rockchip,rk3228-pinctrl", 4230 .data = &rk3228_pin_ctrl }, 4231 { .compatible = "rockchip,rk3288-pinctrl", 4232 .data = &rk3288_pin_ctrl }, 4233 { .compatible = "rockchip,rk3308-pinctrl", 4234 .data = &rk3308_pin_ctrl }, 4235 { .compatible = "rockchip,rk3328-pinctrl", 4236 .data = &rk3328_pin_ctrl }, 4237 { .compatible = "rockchip,rk3368-pinctrl", 4238 .data = &rk3368_pin_ctrl }, 4239 { .compatible = "rockchip,rk3399-pinctrl", 4240 .data = &rk3399_pin_ctrl }, 4241 {}, 4242 }; 4243 4244 static struct platform_driver rockchip_pinctrl_driver = { 4245 .probe = rockchip_pinctrl_probe, 4246 .driver = { 4247 .name = "rockchip-pinctrl", 4248 .pm = &rockchip_pinctrl_dev_pm_ops, 4249 .of_match_table = rockchip_pinctrl_dt_match, 4250 }, 4251 }; 4252 4253 static int __init rockchip_pinctrl_drv_register(void) 4254 { 4255 return platform_driver_register(&rockchip_pinctrl_driver); 4256 } 4257 postcore_initcall(rockchip_pinctrl_drv_register); 4258