1 /* 2 * Driver for the Gemini pin controller 3 * 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * This is a group-only pin controller. 7 */ 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/pinctrl/machine.h> 14 #include <linux/pinctrl/pinctrl.h> 15 #include <linux/pinctrl/pinmux.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/regmap.h> 19 20 #include "pinctrl-utils.h" 21 22 #define DRIVER_NAME "pinctrl-gemini" 23 24 /** 25 * @dev: a pointer back to containing device 26 * @virtbase: the offset to the controller in virtual memory 27 * @map: regmap to access registers 28 * @is_3512: whether the SoC/package is the 3512 variant 29 * @is_3516: whether the SoC/package is the 3516 variant 30 * @flash_pin: whether the flash pin (extended pins for parallel 31 * flash) is set 32 */ 33 struct gemini_pmx { 34 struct device *dev; 35 struct pinctrl_dev *pctl; 36 struct regmap *map; 37 bool is_3512; 38 bool is_3516; 39 bool flash_pin; 40 }; 41 42 /** 43 * struct gemini_pin_group - describes a Gemini pin group 44 * @name: the name of this specific pin group 45 * @pins: an array of discrete physical pins used in this group, taken 46 * from the driver-local pin enumeration space 47 * @num_pins: the number of pins in this group array, i.e. the number of 48 * elements in .pins so we can iterate over that array 49 * @mask: bits to clear to enable this when doing pin muxing 50 * @value: bits to set to enable this when doing pin muxing 51 */ 52 struct gemini_pin_group { 53 const char *name; 54 const unsigned int *pins; 55 const unsigned int num_pins; 56 u32 mask; 57 u32 value; 58 }; 59 60 /* 61 * Global Miscellaneous Control Register 62 * This register controls all Gemini pad/pin multiplexing 63 * 64 * It is a tricky register though: 65 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot 66 * be brought back online, so it means permanent disablement of the 67 * corresponding pads. 68 * - For the bits named *_DISABLE, once you enable something, it cannot be 69 * DISABLED again. So you select a flash configuration once, and then 70 * you are stuck with it. 71 */ 72 #define GLOBAL_WORD_ID 0x00 73 #define GLOBAL_STATUS 0x04 74 #define GLOBAL_STATUS_FLPIN BIT(20) 75 #define GLOBAL_MISC_CTRL 0x30 76 #define TVC_CLK_PAD_ENABLE BIT(20) 77 #define PCI_CLK_PAD_ENABLE BIT(17) 78 #define LPC_CLK_PAD_ENABLE BIT(16) 79 #define TVC_PADS_ENABLE BIT(9) 80 #define SSP_PADS_ENABLE BIT(8) 81 #define LCD_PADS_ENABLE BIT(7) 82 #define LPC_PADS_ENABLE BIT(6) 83 #define PCI_PADS_ENABLE BIT(5) 84 #define IDE_PADS_ENABLE BIT(4) 85 #define DRAM_PADS_POWERDOWN BIT(3) 86 #define NAND_PADS_DISABLE BIT(2) 87 #define PFLASH_PADS_DISABLE BIT(1) 88 #define SFLASH_PADS_DISABLE BIT(0) 89 #define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) 90 #define PADS_MAXBIT 20 91 92 /* Ordered by bit index */ 93 static const char * const gemini_padgroups[] = { 94 "serial flash", 95 "parallel flash", 96 "NAND flash", 97 "DRAM", 98 "IDE", 99 "PCI", 100 "LPC", 101 "LCD", 102 "SSP", 103 "TVC", 104 NULL, NULL, NULL, NULL, NULL, NULL, 105 "LPC CLK", 106 "PCI CLK", 107 NULL, NULL, 108 "TVC CLK", 109 }; 110 111 static const struct pinctrl_pin_desc gemini_3512_pins[] = { 112 /* Row A */ 113 PINCTRL_PIN(0, "A1 VREF CTRL"), 114 PINCTRL_PIN(1, "A2 VCC2IO CTRL"), 115 PINCTRL_PIN(2, "A3 DRAM CK"), 116 PINCTRL_PIN(3, "A4 DRAM CK N"), 117 PINCTRL_PIN(4, "A5 DRAM A5"), 118 PINCTRL_PIN(5, "A6 DRAM CKE"), 119 PINCTRL_PIN(6, "A7 DRAM DQ11"), 120 PINCTRL_PIN(7, "A8 DRAM DQ0"), 121 PINCTRL_PIN(8, "A9 DRAM DQ5"), 122 PINCTRL_PIN(9, "A10 DRAM DQ6"), 123 PINCTRL_PIN(10, "A11 DRAM DRAM VREF"), 124 PINCTRL_PIN(11, "A12 DRAM BA1"), 125 PINCTRL_PIN(12, "A13 DRAM A2"), 126 PINCTRL_PIN(13, "A14 PCI GNT1 N"), 127 PINCTRL_PIN(14, "A15 PCI REQ9 N"), 128 PINCTRL_PIN(15, "A16 PCI REQ2 N"), 129 PINCTRL_PIN(16, "A17 PCI REQ3 N"), 130 PINCTRL_PIN(17, "A18 PCI AD31"), 131 /* Row B */ 132 PINCTRL_PIN(18, "B1 VCCK CTRL"), 133 PINCTRL_PIN(19, "B2 PWR EN"), 134 PINCTRL_PIN(20, "B3 RTC CLKI"), 135 PINCTRL_PIN(21, "B4 DRAM A4"), 136 PINCTRL_PIN(22, "B5 DRAM A6"), 137 PINCTRL_PIN(23, "B6 DRAM A12"), 138 PINCTRL_PIN(24, "B7 DRAM DQS1"), 139 PINCTRL_PIN(25, "B8 DRAM DQ15"), 140 PINCTRL_PIN(26, "B9 DRAM DQ4"), 141 PINCTRL_PIN(27, "B10 DRAM DQS0"), 142 PINCTRL_PIN(28, "B11 DRAM WE N"), 143 PINCTRL_PIN(29, "B12 DRAM A10"), 144 PINCTRL_PIN(30, "B13 DRAM A3"), 145 PINCTRL_PIN(31, "B14 PCI GNT0 N"), 146 PINCTRL_PIN(32, "B15 PCI GNT3 N"), 147 PINCTRL_PIN(33, "B16 PCI REQ1 N"), 148 PINCTRL_PIN(34, "B17 PCI AD30"), 149 PINCTRL_PIN(35, "B18 PCI AD29"), 150 /* Row C */ 151 PINCTRL_PIN(36, "C1 CIR RST N"), /* REALLY? CIR is not in 3512... */ 152 PINCTRL_PIN(37, "C2 XTALI"), 153 PINCTRL_PIN(38, "C3 PWR BTN"), 154 PINCTRL_PIN(39, "C4 RTC CLKO"), 155 PINCTRL_PIN(40, "C5 DRAM A7"), 156 PINCTRL_PIN(41, "C6 DRAM A11"), 157 PINCTRL_PIN(42, "C7 DRAM DQ10"), 158 PINCTRL_PIN(43, "C8 DRAM DQ14"), 159 PINCTRL_PIN(44, "C9 DRAM DQ3"), 160 PINCTRL_PIN(45, "C10 DRAM DQ7"), 161 PINCTRL_PIN(46, "C11 DRAM CAS N"), 162 PINCTRL_PIN(47, "C12 DRAM A0"), 163 PINCTRL_PIN(48, "C13 PCI INT0 N"), 164 PINCTRL_PIN(49, "C14 EXT RESET N"), 165 PINCTRL_PIN(50, "C15 PCI GNT2 N"), 166 PINCTRL_PIN(51, "C16 PCI AD28"), 167 PINCTRL_PIN(52, "C17 PCI AD27"), 168 PINCTRL_PIN(53, "C18 PCI AD26"), 169 /* Row D */ 170 PINCTRL_PIN(54, "D1 AVCCKHA"), 171 PINCTRL_PIN(55, "D2 AGNDIOHA"), 172 PINCTRL_PIN(56, "D3 XTALO"), 173 PINCTRL_PIN(57, "D4 AVCC3IOHA"), 174 PINCTRL_PIN(58, "D5 DRAM A8"), 175 PINCTRL_PIN(59, "D6 DRAM A9"), 176 PINCTRL_PIN(60, "D7 DRAM DQ9"), 177 PINCTRL_PIN(61, "D8 DRAM DQ13"), 178 PINCTRL_PIN(62, "D9 DRAM DQ2"), 179 PINCTRL_PIN(63, "D10 DRAM A13"), 180 PINCTRL_PIN(64, "D11 DRAM RAS N"), 181 PINCTRL_PIN(65, "D12 DRAM A1"), 182 PINCTRL_PIN(66, "D13 PCI INTC N"), 183 PINCTRL_PIN(67, "D14 PCI CLK"), 184 PINCTRL_PIN(68, "D15 PCI AD25"), 185 PINCTRL_PIN(69, "D16 PCI AD24"), 186 PINCTRL_PIN(70, "D17 PCI CBE3 N"), 187 PINCTRL_PIN(71, "D18 PCI AD23"), 188 /* Row E */ 189 PINCTRL_PIN(72, "E1 AVCC3IOHA"), 190 PINCTRL_PIN(73, "E2 EBG"), 191 PINCTRL_PIN(74, "E3 AVCC3IOHB"), 192 PINCTRL_PIN(75, "E4 REXT"), 193 PINCTRL_PIN(76, "E5 GND"), 194 PINCTRL_PIN(77, "E6 DRAM DQM1"), 195 PINCTRL_PIN(78, "E7 DRAM DQ8"), 196 PINCTRL_PIN(79, "E8 DRAM DQ12"), 197 PINCTRL_PIN(80, "E9 DRAM DQ1"), 198 PINCTRL_PIN(81, "E10 DRAM DQM0"), 199 PINCTRL_PIN(82, "E11 DRAM BA0"), 200 PINCTRL_PIN(83, "E12 PCI INTA N"), 201 PINCTRL_PIN(84, "E13 PCI INTB N"), 202 PINCTRL_PIN(85, "E14 GND"), 203 PINCTRL_PIN(86, "E15 PCI AD22"), 204 PINCTRL_PIN(87, "E16 PCI AD21"), 205 PINCTRL_PIN(88, "E17 PCI AD20"), 206 PINCTRL_PIN(89, "E18 PCI AD19"), 207 /* Row F */ 208 PINCTRL_PIN(90, "F1 SATA0 RXDP"), 209 PINCTRL_PIN(91, "F2 SATA0 RXDN"), 210 PINCTRL_PIN(92, "F3 AGNDK 0"), 211 PINCTRL_PIN(93, "F4 AVCC3 S"), 212 PINCTRL_PIN(94, "F5 AVCCK P"), 213 PINCTRL_PIN(95, "F6 GND"), 214 PINCTRL_PIN(96, "F7 VCC2IOHA 2"), 215 PINCTRL_PIN(97, "F8 VCC2IOHA 2"), 216 PINCTRL_PIN(98, "F9 V1"), 217 PINCTRL_PIN(99, "F10 V1"), 218 PINCTRL_PIN(100, "F11 VCC2IOHA 2"), 219 PINCTRL_PIN(101, "F12 VCC2IOHA 2"), 220 PINCTRL_PIN(102, "F13 GND"), 221 PINCTRL_PIN(103, "F14 PCI AD18"), 222 PINCTRL_PIN(104, "F15 PCI AD17"), 223 PINCTRL_PIN(105, "F16 PCI AD16"), 224 PINCTRL_PIN(106, "F17 PCI CBE2 N"), 225 PINCTRL_PIN(107, "F18 PCI FRAME N"), 226 /* Row G */ 227 PINCTRL_PIN(108, "G1 SATA0 TXDP"), 228 PINCTRL_PIN(109, "G2 SATA0 TXDN"), 229 PINCTRL_PIN(110, "G3 AGNDK 1"), 230 PINCTRL_PIN(111, "G4 AVCCK 0"), 231 PINCTRL_PIN(112, "G5 TEST CLKOUT"), 232 PINCTRL_PIN(113, "G6 AGND"), 233 PINCTRL_PIN(114, "G7 GND"), 234 PINCTRL_PIN(115, "G8 VCC2IOHA 2"), 235 PINCTRL_PIN(116, "G9 V1"), 236 PINCTRL_PIN(117, "G10 V1"), 237 PINCTRL_PIN(118, "G11 VCC2IOHA 2"), 238 PINCTRL_PIN(119, "G12 GND"), 239 PINCTRL_PIN(120, "G13 VCC3IOHA"), 240 PINCTRL_PIN(121, "G14 PCI IRDY N"), 241 PINCTRL_PIN(122, "G15 PCI TRDY N"), 242 PINCTRL_PIN(123, "G16 PCI DEVSEL N"), 243 PINCTRL_PIN(124, "G17 PCI STOP N"), 244 PINCTRL_PIN(125, "G18 PCI PAR"), 245 /* Row H */ 246 PINCTRL_PIN(126, "H1 SATA1 TXDP"), 247 PINCTRL_PIN(127, "H2 SATA1 TXDN"), 248 PINCTRL_PIN(128, "H3 AGNDK 2"), 249 PINCTRL_PIN(129, "H4 AVCCK 1"), 250 PINCTRL_PIN(130, "H5 AVCCK S"), 251 PINCTRL_PIN(131, "H6 AVCCKHB"), 252 PINCTRL_PIN(132, "H7 AGND"), 253 PINCTRL_PIN(133, "H8 GND"), 254 PINCTRL_PIN(134, "H9 GND"), 255 PINCTRL_PIN(135, "H10 GND"), 256 PINCTRL_PIN(136, "H11 GND"), 257 PINCTRL_PIN(137, "H12 VCC3IOHA"), 258 PINCTRL_PIN(138, "H13 VCC3IOHA"), 259 PINCTRL_PIN(139, "H14 PCI CBE1 N"), 260 PINCTRL_PIN(140, "H15 PCI AD15"), 261 PINCTRL_PIN(141, "H16 PCI AD14"), 262 PINCTRL_PIN(142, "H17 PCI AD13"), 263 PINCTRL_PIN(143, "H18 PCI AD12"), 264 /* Row J (for some reason I is skipped) */ 265 PINCTRL_PIN(144, "J1 SATA1 RXDP"), 266 PINCTRL_PIN(145, "J2 SATA1 RXDN"), 267 PINCTRL_PIN(146, "J3 AGNDK 3"), 268 PINCTRL_PIN(147, "J4 AVCCK 2"), 269 PINCTRL_PIN(148, "J5 IDE DA1"), 270 PINCTRL_PIN(149, "J6 V1"), 271 PINCTRL_PIN(150, "J7 V1"), 272 PINCTRL_PIN(151, "J8 GND"), 273 PINCTRL_PIN(152, "J9 GND"), 274 PINCTRL_PIN(153, "J10 GND"), 275 PINCTRL_PIN(154, "J11 GND"), 276 PINCTRL_PIN(155, "J12 V1"), 277 PINCTRL_PIN(156, "J13 V1"), 278 PINCTRL_PIN(157, "J14 PCI AD11"), 279 PINCTRL_PIN(158, "J15 PCI AD10"), 280 PINCTRL_PIN(159, "J16 PCI AD9"), 281 PINCTRL_PIN(160, "J17 PCI AD8"), 282 PINCTRL_PIN(161, "J18 PCI CBE0 N"), 283 /* Row K */ 284 PINCTRL_PIN(162, "K1 IDE CS1 N"), 285 PINCTRL_PIN(163, "K2 IDE CS0 N"), 286 PINCTRL_PIN(164, "K3 AVCCK 3"), 287 PINCTRL_PIN(165, "K4 IDE DA2"), 288 PINCTRL_PIN(166, "K5 IDE DA0"), 289 PINCTRL_PIN(167, "K6 V1"), 290 PINCTRL_PIN(168, "K7 V1"), 291 PINCTRL_PIN(169, "K8 GND"), 292 PINCTRL_PIN(170, "K9 GND"), 293 PINCTRL_PIN(171, "K10 GND"), 294 PINCTRL_PIN(172, "K11 GND"), 295 PINCTRL_PIN(173, "K12 V1"), 296 PINCTRL_PIN(174, "K13 V1"), 297 PINCTRL_PIN(175, "K14 PCI AD3"), 298 PINCTRL_PIN(176, "K15 PCI AD4"), 299 PINCTRL_PIN(177, "K16 PCI AD5"), 300 PINCTRL_PIN(178, "K17 PCI AD6"), 301 PINCTRL_PIN(179, "K18 PCI AD7"), 302 /* Row L */ 303 PINCTRL_PIN(180, "L1 IDE INTRQ"), 304 PINCTRL_PIN(181, "L2 IDE DMACK N"), 305 PINCTRL_PIN(182, "L3 IDE IORDY"), 306 PINCTRL_PIN(183, "L4 IDE DIOR N"), 307 PINCTRL_PIN(184, "L5 IDE DIOW N"), 308 PINCTRL_PIN(185, "L6 VCC3IOHA"), 309 PINCTRL_PIN(186, "L7 VCC3IOHA"), 310 PINCTRL_PIN(187, "L8 GND"), 311 PINCTRL_PIN(188, "L9 GND"), 312 PINCTRL_PIN(189, "L10 GND"), 313 PINCTRL_PIN(190, "L11 GND"), 314 PINCTRL_PIN(191, "L12 VCC3IOHA"), 315 PINCTRL_PIN(192, "L13 VCC3IOHA"), 316 PINCTRL_PIN(193, "L14 GPIO0 30"), 317 PINCTRL_PIN(194, "L15 GPIO0 31"), 318 PINCTRL_PIN(195, "L16 PCI AD0"), 319 PINCTRL_PIN(196, "L17 PCI AD1"), 320 PINCTRL_PIN(197, "L18 PCI AD2"), 321 /* Row M */ 322 PINCTRL_PIN(198, "M1 IDE DMARQ"), 323 PINCTRL_PIN(199, "M2 IDE DD15"), 324 PINCTRL_PIN(200, "M3 IDE DD0"), 325 PINCTRL_PIN(201, "M4 IDE DD14"), 326 PINCTRL_PIN(202, "M5 IDE DD1"), 327 PINCTRL_PIN(203, "M6 VCC3IOHA"), 328 PINCTRL_PIN(204, "M7 GND"), 329 PINCTRL_PIN(205, "M8 VCC2IOHA 1"), 330 PINCTRL_PIN(206, "M9 V1"), 331 PINCTRL_PIN(207, "M10 V1"), 332 PINCTRL_PIN(208, "M11 VCC3IOHA"), 333 PINCTRL_PIN(209, "M12 GND"), 334 PINCTRL_PIN(210, "M13 VCC3IOHA"), 335 PINCTRL_PIN(211, "M14 GPIO0 25"), 336 PINCTRL_PIN(212, "M15 GPIO0 26"), 337 PINCTRL_PIN(213, "M16 GPIO0 27"), 338 PINCTRL_PIN(214, "M17 GPIO0 28"), 339 PINCTRL_PIN(215, "M18 GPIO0 29"), 340 /* Row N */ 341 PINCTRL_PIN(216, "N1 IDE DD13"), 342 PINCTRL_PIN(217, "N2 IDE DD2"), 343 PINCTRL_PIN(218, "N3 IDE DD12"), 344 PINCTRL_PIN(219, "N4 IDE DD3"), 345 PINCTRL_PIN(220, "N5 IDE DD11"), 346 PINCTRL_PIN(221, "N6 GND"), 347 PINCTRL_PIN(222, "N7 VCC2IOHA 1"), 348 PINCTRL_PIN(223, "N8 VCC2IOHA 1"), 349 PINCTRL_PIN(224, "N9 V1"), 350 PINCTRL_PIN(225, "N10 V1"), 351 PINCTRL_PIN(226, "N11 VCC3IOHA"), 352 PINCTRL_PIN(227, "N12 VCC3IOHA"), 353 PINCTRL_PIN(228, "N13 GND"), 354 PINCTRL_PIN(229, "N14 GPIO0 20"), 355 PINCTRL_PIN(230, "N15 GPIO0 21"), 356 PINCTRL_PIN(231, "N16 GPIO0 22"), 357 PINCTRL_PIN(232, "N17 GPIO0 23"), 358 PINCTRL_PIN(233, "N18 GPIO0 24"), 359 /* Row P (for some reason O is skipped) */ 360 PINCTRL_PIN(234, "P1 IDE DD4"), 361 PINCTRL_PIN(235, "P2 IDE DD10"), 362 PINCTRL_PIN(236, "P3 IDE DD5"), 363 PINCTRL_PIN(237, "P4 IDE DD9"), 364 PINCTRL_PIN(238, "P5 GND"), 365 PINCTRL_PIN(239, "P6 USB XSCO"), 366 PINCTRL_PIN(240, "P7 GMAC0 TXD3"), 367 PINCTRL_PIN(241, "P8 GMAC0 TXEN"), 368 PINCTRL_PIN(242, "P9 GMAC0 RXD2"), 369 PINCTRL_PIN(243, "P10 GMAC1 TXC"), 370 PINCTRL_PIN(244, "P11 GMAC1 RXD1"), 371 PINCTRL_PIN(245, "P12 MODE SEL 1"), 372 PINCTRL_PIN(246, "P13 GPIO1 28"), 373 PINCTRL_PIN(247, "P14 GND"), 374 PINCTRL_PIN(248, "P15 GPIO0 5"), 375 PINCTRL_PIN(249, "P16 GPIO0 17"), 376 PINCTRL_PIN(250, "P17 GPIO0 18"), 377 PINCTRL_PIN(251, "P18 GPIO0 19"), 378 /* Row R (for some reason Q us skipped) */ 379 PINCTRL_PIN(252, "R1 IDE DD6"), 380 PINCTRL_PIN(253, "R2 IDE DD8"), 381 PINCTRL_PIN(254, "R3 IDE DD7"), 382 PINCTRL_PIN(255, "R4 IDE RESET N"), 383 PINCTRL_PIN(256, "R5 ICE0 DBGACK"), 384 PINCTRL_PIN(257, "R6 USB XSCI"), 385 PINCTRL_PIN(258, "R7 GMAC0 TXD2"), 386 PINCTRL_PIN(259, "R8 GMAC0 RXDV"), 387 PINCTRL_PIN(260, "R9 GMAC0 RXD3"), 388 PINCTRL_PIN(261, "R10 GMAC1 TXD0"), 389 PINCTRL_PIN(262, "R11 GMAC1 RXD0"), 390 PINCTRL_PIN(263, "R12 MODE SEL 0"), 391 PINCTRL_PIN(264, "R13 MODE SEL 3"), 392 PINCTRL_PIN(265, "R14 GPIO0 0"), 393 PINCTRL_PIN(266, "R15 GPIO0 4"), 394 PINCTRL_PIN(267, "R16 GPIO0 9"), 395 PINCTRL_PIN(268, "R17 GPIO0 15"), 396 PINCTRL_PIN(269, "R18 GPIO0 16"), 397 /* Row T (for some reason S is skipped) */ 398 PINCTRL_PIN(270, "T1 ICE0 DBGRQ"), 399 PINCTRL_PIN(271, "T2 ICE0 IDO"), 400 PINCTRL_PIN(272, "T3 ICE0 ICK"), 401 PINCTRL_PIN(273, "T4 ICE0 IMS"), 402 PINCTRL_PIN(274, "T5 ICE0 IDI"), 403 PINCTRL_PIN(275, "T6 USB RREF"), 404 PINCTRL_PIN(276, "T7 GMAC0 TXD1"), 405 PINCTRL_PIN(277, "T8 GMAC0 RXC"), 406 PINCTRL_PIN(278, "T9 GMAC0 CRS"), 407 PINCTRL_PIN(279, "T10 GMAC1 TXD1"), 408 PINCTRL_PIN(280, "T11 GMAC1 RXC"), 409 PINCTRL_PIN(281, "T12 GMAC1 CRS"), 410 PINCTRL_PIN(282, "T13 EXT CLK"), 411 PINCTRL_PIN(283, "T14 GPIO1 31"), 412 PINCTRL_PIN(284, "T15 GPIO0 3"), 413 PINCTRL_PIN(285, "T16 GPIO0 8"), 414 PINCTRL_PIN(286, "T17 GPIO0 12"), 415 PINCTRL_PIN(287, "T18 GPIO0 14"), 416 /* Row U */ 417 PINCTRL_PIN(288, "U1 ICE0 IRST N"), 418 PINCTRL_PIN(289, "U2 USB0 VCCHSRT"), 419 PINCTRL_PIN(290, "U3 USB0 DP"), 420 PINCTRL_PIN(291, "U4 USB VCCA U20"), 421 PINCTRL_PIN(292, "U5 USB1 DP"), 422 PINCTRL_PIN(293, "U6 USB1 GNDHSRT 1"), 423 PINCTRL_PIN(294, "U7 GMAC0 TXD0"), 424 PINCTRL_PIN(295, "U8 GMAC0 RXD0"), 425 PINCTRL_PIN(296, "U9 GMAC1 COL"), 426 PINCTRL_PIN(297, "U10 GMAC1 TXD2"), 427 PINCTRL_PIN(298, "U11 GMAC1 RXDV"), 428 PINCTRL_PIN(299, "U12 GMAC1 RXD3"), 429 PINCTRL_PIN(300, "U13 MODE SEL 2"), 430 PINCTRL_PIN(301, "U14 GPIO1 30"), 431 PINCTRL_PIN(302, "U15 GPIO0 2"), 432 PINCTRL_PIN(303, "U16 GPIO0 7"), 433 PINCTRL_PIN(304, "U17 GPIO0 11"), 434 PINCTRL_PIN(305, "U18 GPIO0 13"), 435 /* Row V */ 436 PINCTRL_PIN(306, "V1 USB0 GNDHSRT"), 437 PINCTRL_PIN(307, "V2 USB0 DM"), 438 PINCTRL_PIN(308, "V3 USB GNDA U20"), 439 PINCTRL_PIN(309, "V4 USB1 DM"), 440 PINCTRL_PIN(310, "V5 USB1 VCCHSRT1"), 441 PINCTRL_PIN(311, "V6 GMAC0 COL"), 442 PINCTRL_PIN(312, "V7 GMAC0 TXC"), 443 PINCTRL_PIN(313, "V8 GMAC0 RXD1"), 444 PINCTRL_PIN(314, "V9 REF CLK"), 445 PINCTRL_PIN(315, "V10 GMAC1 TXD3"), 446 PINCTRL_PIN(316, "V11 GMAC1 TXEN"), 447 PINCTRL_PIN(317, "V12 GMAC1 RXD2"), 448 PINCTRL_PIN(318, "V13 M30 CLK"), 449 PINCTRL_PIN(319, "V14 GPIO1 29"), 450 PINCTRL_PIN(320, "V15 GPIO0 1"), 451 PINCTRL_PIN(321, "V16 GPIO0 6"), 452 PINCTRL_PIN(322, "V17 GPIO0 10"), 453 PINCTRL_PIN(323, "V18 SYS RESET N"), 454 }; 455 456 457 /* Digital ground */ 458 static const unsigned int gnd_3512_pins[] = { 459 76, 85, 95, 102, 114, 119, 133, 134, 135, 136, 151, 152, 153, 154, 169, 460 170, 171, 172, 187, 188, 189, 190, 204, 209, 221, 228, 238, 247 461 }; 462 463 static const unsigned int dram_3512_pins[] = { 464 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 22, 23, 24, 25, 26, 27, 28, 29, 465 30, 40, 41, 42, 43, 44, 45, 46, 47, 58, 59, 60, 61, 62, 63, 64, 65, 77, 466 78, 79, 80, 81, 82 467 }; 468 469 static const unsigned int rtc_3512_pins[] = { 57, 20, 39 }; 470 471 static const unsigned int power_3512_pins[] = { 19, 38, 36, 55, 37, 56, 54, 72 }; 472 473 static const unsigned int system_3512_pins[] = { 474 318, 264, 300, 245, 263, 282, 314, 323, 49, 475 }; 476 477 static const unsigned int vcontrol_3512_pins[] = { 18, 0, 1 }; 478 479 static const unsigned int ice_3512_pins[] = { 256, 270, 271, 272, 273, 274, 288 }; 480 481 static const unsigned int ide_3512_pins[] = { 482 162, 163, 165, 166, 148, 180, 181, 182, 183, 184, 198, 199, 200, 201, 202, 483 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 253, 254, 255 484 }; 485 486 static const unsigned int sata_3512_pins[] = { 487 75, 74, 73, 93, 94, 131, 112, 130, 92, 91, 90, 111, 110, 109, 108, 129, 488 128, 127, 126, 147, 146, 145, 144, 164 489 }; 490 491 static const unsigned int usb_3512_pins[] = { 492 306, 289, 307, 290, 239, 257, 275, 308, 291, 309, 292, 310, 293 493 }; 494 495 /* GMII, ethernet pins */ 496 static const unsigned int gmii_3512_pins[] = { 497 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, 498 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 499 }; 500 501 static const unsigned int pci_3512_pins[] = { 502 13, 14, 15, 16, 17, 31, 32, 33, 34, 35, 48, 50, 51, 52, 53, 66, 67, 68, 69, 503 70, 71, 83, 84, 86, 87, 88, 89, 103, 104, 105, 106, 107, 121, 122, 123, 504 124, 125, 139, 140, 141, 142, 143, 157, 158, 159, 160, 161, 175, 176, 177, 505 178, 179, 195, 196, 197 506 }; 507 508 /* 509 * Apparently the LPC interface is using the PCICLK for the clocking so 510 * PCI needs to be active at the same time. 511 */ 512 static const unsigned int lpc_3512_pins[] = { 513 285, /* LPC_LAD[0] */ 514 304, /* LPC_SERIRQ */ 515 286, /* LPC_LAD[2] */ 516 305, /* LPC_LFRAME# */ 517 287, /* LPC_LAD[3] */ 518 268, /* LPC_LAD[1] */ 519 }; 520 521 /* Character LCD */ 522 static const unsigned int lcd_3512_pins[] = { 523 262, 244, 317, 299, 246, 319, 301, 283, 269, 233, 211 524 }; 525 526 static const unsigned int ssp_3512_pins[] = { 527 285, /* SSP_97RST# SSP AC97 Reset, active low */ 528 304, /* SSP_FSC */ 529 286, /* SSP_ECLK */ 530 305, /* SSP_TXD */ 531 287, /* SSP_RXD */ 532 268, /* SSP_SCLK */ 533 }; 534 535 static const unsigned int uart_rxtx_3512_pins[] = { 536 267, /* UART_SIN serial input, RX */ 537 322, /* UART_SOUT serial output, TX */ 538 }; 539 540 static const unsigned int uart_modem_3512_pins[] = { 541 285, /* UART_NDCD DCD carrier detect */ 542 304, /* UART_NDTR DTR data terminal ready */ 543 286, /* UART_NDSR DSR data set ready */ 544 305, /* UART_NRTS RTS request to send */ 545 287, /* UART_NCTS CTS clear to send */ 546 268, /* UART_NRI RI ring indicator */ 547 }; 548 549 static const unsigned int tvc_3512_pins[] = { 550 246, /* TVC_DATA[0] */ 551 319, /* TVC_DATA[1] */ 552 301, /* TVC_DATA[2] */ 553 283, /* TVC_DATA[3] */ 554 265, /* TVC_CLK */ 555 320, /* TVC_DATA[4] */ 556 302, /* TVC_DATA[5] */ 557 284, /* TVC_DATA[6] */ 558 266, /* TVC_DATA[7] */ 559 }; 560 561 /* NAND flash pins */ 562 static const unsigned int nflash_3512_pins[] = { 563 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 252, 564 253, 254, 249, 250, 232, 233, 211, 193, 194 565 }; 566 567 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 568 static const unsigned int pflash_3512_pins[] = { 569 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 570 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 571 214, 215, 193, 194 572 }; 573 574 /* 575 * The parallel flash can be set up in a 26-bit address bus mode exposing 576 * A[0-15] (A[15] takes the place of ALE), but it has the 577 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 578 * used at the same time. 579 */ 580 static const unsigned int pflash_3512_pins_extended[] = { 581 162, 163, 165, 166, 148, 199, 200, 201, 202, 216, 217, 218, 219, 220, 582 234, 235, 236, 237, 252, 253, 254, 251, 229, 232, 233, 211, 212, 213, 583 214, 215, 193, 194, 584 /* The extra pins */ 585 296, 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281, 586 265, 587 }; 588 589 /* Serial flash pins CE0, CE1, DI, DO, CK */ 590 static const unsigned int sflash_3512_pins[] = { 230, 231, 232, 233, 211 }; 591 592 /* The GPIO0A (0) pin overlap with TVC and extended parallel flash */ 593 static const unsigned int gpio0a_3512_pins[] = { 265 }; 594 595 /* The GPIO0B (1-4) pins overlap with TVC and ICE */ 596 static const unsigned int gpio0b_3512_pins[] = { 320, 302, 284, 266 }; 597 598 /* The GPIO0C (5-7) pins overlap with ICE */ 599 static const unsigned int gpio0c_3512_pins[] = { 248, 321, 303 }; 600 601 /* The GPIO0D (9,10) pins overlap with UART RX/TX */ 602 static const unsigned int gpio0d_3512_pins[] = { 267, 322 }; 603 604 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ 605 static const unsigned int gpio0e_3512_pins[] = { 285, 304, 286, 305, 287, 268 }; 606 607 /* The GPIO0F (16) pins overlap with LCD */ 608 static const unsigned int gpio0f_3512_pins[] = { 269 }; 609 610 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ 611 static const unsigned int gpio0g_3512_pins[] = { 249, 250 }; 612 613 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ 614 static const unsigned int gpio0h_3512_pins[] = { 251, 229 }; 615 616 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ 617 static const unsigned int gpio0i_3512_pins[] = { 230, 231 }; 618 619 /* The GPIO0J (23) pins overlap with all flash */ 620 static const unsigned int gpio0j_3512_pins[] = { 232 }; 621 622 /* The GPIO0K (24,25) pins overlap with all flash and LCD */ 623 static const unsigned int gpio0k_3512_pins[] = { 233, 211 }; 624 625 /* The GPIO0L (26-29) pins overlap with parallel flash */ 626 static const unsigned int gpio0l_3512_pins[] = { 212, 213, 214, 215 }; 627 628 /* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ 629 static const unsigned int gpio0m_3512_pins[] = { 193, 194 }; 630 631 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 632 static const unsigned int gpio1a_3512_pins[] = { 162, 163, 165, 166, 148 }; 633 634 /* The GPIO1B (5-10, 27) pins overlap with just IDE */ 635 static const unsigned int gpio1b_3512_pins[] = { 636 180, 181, 182, 183, 184, 198, 255 637 }; 638 639 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 640 static const unsigned int gpio1c_3512_pins[] = { 641 199, 200, 201, 202, 216, 217, 218, 219, 220, 234, 235, 236, 237, 642 252, 253, 254 643 }; 644 645 /* The GPIO1D (28-31) pins overlap with LCD and TVC */ 646 static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; 647 648 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 649 static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; 650 651 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 652 static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; 653 654 /* The GPIO2C (8-31) pins overlap with PCI */ 655 static const unsigned int gpio2c_3512_pins[] = { 656 17, 34, 35, 51, 52, 53, 68, 69, 71, 86, 87, 88, 89, 103, 104, 105, 657 140, 141, 142, 143, 157, 158, 159, 160 658 }; 659 660 /* Groups for the 3512 SoC/package */ 661 static const struct gemini_pin_group gemini_3512_pin_groups[] = { 662 { 663 .name = "gndgrp", 664 .pins = gnd_3512_pins, 665 .num_pins = ARRAY_SIZE(gnd_3512_pins), 666 }, 667 { 668 .name = "dramgrp", 669 .pins = dram_3512_pins, 670 .num_pins = ARRAY_SIZE(dram_3512_pins), 671 .mask = DRAM_PADS_POWERDOWN, 672 }, 673 { 674 .name = "rtcgrp", 675 .pins = rtc_3512_pins, 676 .num_pins = ARRAY_SIZE(rtc_3512_pins), 677 }, 678 { 679 .name = "powergrp", 680 .pins = power_3512_pins, 681 .num_pins = ARRAY_SIZE(power_3512_pins), 682 }, 683 { 684 .name = "systemgrp", 685 .pins = system_3512_pins, 686 .num_pins = ARRAY_SIZE(system_3512_pins), 687 }, 688 { 689 .name = "vcontrolgrp", 690 .pins = vcontrol_3512_pins, 691 .num_pins = ARRAY_SIZE(vcontrol_3512_pins), 692 }, 693 { 694 .name = "icegrp", 695 .pins = ice_3512_pins, 696 .num_pins = ARRAY_SIZE(ice_3512_pins), 697 /* Conflict with some GPIO groups */ 698 }, 699 { 700 .name = "idegrp", 701 .pins = ide_3512_pins, 702 .num_pins = ARRAY_SIZE(ide_3512_pins), 703 /* Conflict with all flash usage */ 704 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 705 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 706 }, 707 { 708 .name = "satagrp", 709 .pins = sata_3512_pins, 710 .num_pins = ARRAY_SIZE(sata_3512_pins), 711 }, 712 { 713 .name = "usbgrp", 714 .pins = usb_3512_pins, 715 .num_pins = ARRAY_SIZE(usb_3512_pins), 716 }, 717 { 718 .name = "gmiigrp", 719 .pins = gmii_3512_pins, 720 .num_pins = ARRAY_SIZE(gmii_3512_pins), 721 }, 722 { 723 .name = "pcigrp", 724 .pins = pci_3512_pins, 725 .num_pins = ARRAY_SIZE(pci_3512_pins), 726 /* Conflict only with GPIO2 */ 727 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 728 }, 729 { 730 .name = "lpcgrp", 731 .pins = lpc_3512_pins, 732 .num_pins = ARRAY_SIZE(lpc_3512_pins), 733 /* Conflict with SSP and UART modem pins */ 734 .mask = SSP_PADS_ENABLE, 735 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 736 }, 737 { 738 .name = "lcdgrp", 739 .pins = lcd_3512_pins, 740 .num_pins = ARRAY_SIZE(lcd_3512_pins), 741 /* Conflict with TVC and ICE */ 742 .mask = TVC_PADS_ENABLE, 743 .value = LCD_PADS_ENABLE, 744 }, 745 { 746 .name = "sspgrp", 747 .pins = ssp_3512_pins, 748 .num_pins = ARRAY_SIZE(ssp_3512_pins), 749 /* Conflict with LPC and UART modem pins */ 750 .mask = LPC_PADS_ENABLE, 751 .value = SSP_PADS_ENABLE, 752 }, 753 { 754 .name = "uartrxtxgrp", 755 .pins = uart_rxtx_3512_pins, 756 .num_pins = ARRAY_SIZE(uart_rxtx_3512_pins), 757 /* No conflicts except GPIO */ 758 }, 759 { 760 .name = "uartmodemgrp", 761 .pins = uart_modem_3512_pins, 762 .num_pins = ARRAY_SIZE(uart_modem_3512_pins), 763 /* 764 * Conflict with LPC and SSP, 765 * so when those are both disabled, modem UART can thrive. 766 */ 767 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 768 }, 769 { 770 .name = "tvcgrp", 771 .pins = tvc_3512_pins, 772 .num_pins = ARRAY_SIZE(tvc_3512_pins), 773 /* Conflict with character LCD and ICE */ 774 .mask = LCD_PADS_ENABLE, 775 .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, 776 }, 777 /* 778 * The construction is done such that it is possible to use a serial 779 * flash together with a NAND or parallel (NOR) flash, but it is not 780 * possible to use NAND and parallel flash together. To use serial 781 * flash with one of the two others, the muxbits need to be flipped 782 * around before any access. 783 */ 784 { 785 .name = "nflashgrp", 786 .pins = nflash_3512_pins, 787 .num_pins = ARRAY_SIZE(nflash_3512_pins), 788 /* Conflict with IDE, parallel and serial flash */ 789 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 790 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 791 }, 792 { 793 .name = "pflashgrp", 794 .pins = pflash_3512_pins, 795 .num_pins = ARRAY_SIZE(pflash_3512_pins), 796 /* Conflict with IDE, NAND and serial flash */ 797 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 798 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 799 }, 800 { 801 .name = "sflashgrp", 802 .pins = sflash_3512_pins, 803 .num_pins = ARRAY_SIZE(sflash_3512_pins), 804 /* Conflict with IDE, NAND and parallel flash */ 805 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 806 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 807 }, 808 { 809 .name = "gpio0agrp", 810 .pins = gpio0a_3512_pins, 811 .num_pins = ARRAY_SIZE(gpio0a_3512_pins), 812 /* Conflict with TVC */ 813 .mask = TVC_PADS_ENABLE, 814 }, 815 { 816 .name = "gpio0bgrp", 817 .pins = gpio0b_3512_pins, 818 .num_pins = ARRAY_SIZE(gpio0b_3512_pins), 819 /* Conflict with TVC and ICE */ 820 .mask = TVC_PADS_ENABLE, 821 }, 822 { 823 .name = "gpio0cgrp", 824 .pins = gpio0c_3512_pins, 825 .num_pins = ARRAY_SIZE(gpio0c_3512_pins), 826 /* Conflict with ICE */ 827 }, 828 { 829 .name = "gpio0dgrp", 830 .pins = gpio0d_3512_pins, 831 .num_pins = ARRAY_SIZE(gpio0d_3512_pins), 832 /* Conflict with UART RX/TX */ 833 }, 834 { 835 .name = "gpio0egrp", 836 .pins = gpio0e_3512_pins, 837 .num_pins = ARRAY_SIZE(gpio0e_3512_pins), 838 /* Conflict with LPC, UART modem pins, SSP */ 839 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 840 }, 841 { 842 .name = "gpio0fgrp", 843 .pins = gpio0f_3512_pins, 844 .num_pins = ARRAY_SIZE(gpio0f_3512_pins), 845 /* Conflict with LCD */ 846 .mask = LCD_PADS_ENABLE, 847 }, 848 { 849 .name = "gpio0ggrp", 850 .pins = gpio0g_3512_pins, 851 .num_pins = ARRAY_SIZE(gpio0g_3512_pins), 852 /* Conflict with NAND flash */ 853 .value = NAND_PADS_DISABLE, 854 }, 855 { 856 .name = "gpio0hgrp", 857 .pins = gpio0h_3512_pins, 858 .num_pins = ARRAY_SIZE(gpio0h_3512_pins), 859 /* Conflict with parallel flash */ 860 .value = PFLASH_PADS_DISABLE, 861 }, 862 { 863 .name = "gpio0igrp", 864 .pins = gpio0i_3512_pins, 865 .num_pins = ARRAY_SIZE(gpio0i_3512_pins), 866 /* Conflict with serial flash */ 867 .value = SFLASH_PADS_DISABLE, 868 }, 869 { 870 .name = "gpio0jgrp", 871 .pins = gpio0j_3512_pins, 872 .num_pins = ARRAY_SIZE(gpio0j_3512_pins), 873 /* Conflict with all flash */ 874 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 875 SFLASH_PADS_DISABLE, 876 }, 877 { 878 .name = "gpio0kgrp", 879 .pins = gpio0k_3512_pins, 880 .num_pins = ARRAY_SIZE(gpio0k_3512_pins), 881 /* Conflict with all flash and LCD */ 882 .mask = LCD_PADS_ENABLE, 883 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 884 SFLASH_PADS_DISABLE, 885 }, 886 { 887 .name = "gpio0lgrp", 888 .pins = gpio0l_3512_pins, 889 .num_pins = ARRAY_SIZE(gpio0l_3512_pins), 890 /* Conflict with parallel flash */ 891 .value = PFLASH_PADS_DISABLE, 892 }, 893 { 894 .name = "gpio0mgrp", 895 .pins = gpio0m_3512_pins, 896 .num_pins = ARRAY_SIZE(gpio0m_3512_pins), 897 /* Conflict with parallel and NAND flash */ 898 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 899 }, 900 { 901 .name = "gpio1agrp", 902 .pins = gpio1a_3512_pins, 903 .num_pins = ARRAY_SIZE(gpio1a_3512_pins), 904 /* Conflict with IDE and parallel flash */ 905 .mask = IDE_PADS_ENABLE, 906 .value = PFLASH_PADS_DISABLE, 907 }, 908 { 909 .name = "gpio1bgrp", 910 .pins = gpio1b_3512_pins, 911 .num_pins = ARRAY_SIZE(gpio1b_3512_pins), 912 /* Conflict with IDE only */ 913 .mask = IDE_PADS_ENABLE, 914 }, 915 { 916 .name = "gpio1cgrp", 917 .pins = gpio1c_3512_pins, 918 .num_pins = ARRAY_SIZE(gpio1c_3512_pins), 919 /* Conflict with IDE, parallel and NAND flash */ 920 .mask = IDE_PADS_ENABLE, 921 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 922 }, 923 { 924 .name = "gpio1dgrp", 925 .pins = gpio1d_3512_pins, 926 .num_pins = ARRAY_SIZE(gpio1d_3512_pins), 927 /* Conflict with LCD and TVC */ 928 .mask = LCD_PADS_ENABLE | TVC_PADS_ENABLE, 929 }, 930 { 931 .name = "gpio2agrp", 932 .pins = gpio2a_3512_pins, 933 .num_pins = ARRAY_SIZE(gpio2a_3512_pins), 934 /* Conflict with GMII and extended parallel flash */ 935 }, 936 { 937 .name = "gpio2bgrp", 938 .pins = gpio2b_3512_pins, 939 .num_pins = ARRAY_SIZE(gpio2b_3512_pins), 940 /* Conflict with GMII, extended parallel flash and LCD */ 941 .mask = LCD_PADS_ENABLE, 942 }, 943 { 944 .name = "gpio2cgrp", 945 .pins = gpio2c_3512_pins, 946 .num_pins = ARRAY_SIZE(gpio2c_3512_pins), 947 /* Conflict with PCI */ 948 .mask = PCI_PADS_ENABLE, 949 }, 950 }; 951 952 /* Pin names for the pinmux subsystem, 3516 variant */ 953 static const struct pinctrl_pin_desc gemini_3516_pins[] = { 954 /* Row A */ 955 PINCTRL_PIN(0, "A1 AVCC3IOHA"), 956 PINCTRL_PIN(1, "A2 DRAM CK N"), 957 PINCTRL_PIN(2, "A3 DRAM CK"), 958 PINCTRL_PIN(3, "A4 DRAM DQM1"), 959 PINCTRL_PIN(4, "A5 DRAM DQ9"), 960 PINCTRL_PIN(5, "A6 DRAM DQ13"), 961 PINCTRL_PIN(6, "A7 DRAM DQ1"), 962 PINCTRL_PIN(7, "A8 DRAM DQ2"), 963 PINCTRL_PIN(8, "A9 DRAM DQ4"), 964 PINCTRL_PIN(9, "A10 DRAM VREF"), 965 PINCTRL_PIN(10, "A11 DRAM DQ24"), 966 PINCTRL_PIN(11, "A12 DRAM DQ28"), 967 PINCTRL_PIN(12, "A13 DRAM DQ30"), 968 PINCTRL_PIN(13, "A14 DRAM DQ18"), 969 PINCTRL_PIN(14, "A15 DRAM DQ21"), 970 PINCTRL_PIN(15, "A16 DRAM CAS_N"), 971 PINCTRL_PIN(16, "A17 DRAM BA1"), 972 PINCTRL_PIN(17, "A18 PCI INTA N"), 973 PINCTRL_PIN(18, "A19 PCI INTB N"), 974 PINCTRL_PIN(19, "A20 PCI INTC N"), 975 /* Row B */ 976 PINCTRL_PIN(20, "B1 PWR EN"), 977 PINCTRL_PIN(21, "B2 GND"), 978 PINCTRL_PIN(22, "B3 RTC CLKO"), 979 PINCTRL_PIN(23, "B4 DRAM A5"), 980 PINCTRL_PIN(24, "B5 DRAM A6"), 981 PINCTRL_PIN(25, "B6 DRAM DQS1"), 982 PINCTRL_PIN(26, "B7 DRAM DQ11"), 983 PINCTRL_PIN(27, "B8 DRAM DQ0"), 984 PINCTRL_PIN(28, "B9 DRAM DQS0"), 985 PINCTRL_PIN(29, "B10 DRAM DQ7"), 986 PINCTRL_PIN(30, "B11 DRAM DQS3"), 987 PINCTRL_PIN(31, "B12 DRAM DQ27"), 988 PINCTRL_PIN(32, "B13 DRAM DQ31"), 989 PINCTRL_PIN(33, "B14 DRAM DQ20"), 990 PINCTRL_PIN(34, "B15 DRAM DQS2"), 991 PINCTRL_PIN(35, "B16 DRAM WE N"), 992 PINCTRL_PIN(36, "B17 DRAM A10"), 993 PINCTRL_PIN(37, "B18 DRAM A2"), 994 PINCTRL_PIN(38, "B19 GND"), 995 PINCTRL_PIN(39, "B20 PCI GNT0 N"), 996 /* Row C */ 997 PINCTRL_PIN(40, "C1 AGNDIOHA"), 998 PINCTRL_PIN(41, "C2 XTALI"), 999 PINCTRL_PIN(42, "C3 GND"), 1000 PINCTRL_PIN(43, "C4 RTC CLKI"), 1001 PINCTRL_PIN(44, "C5 DRAM A12"), 1002 PINCTRL_PIN(45, "C6 DRAM A11"), 1003 PINCTRL_PIN(46, "C7 DRAM DQ8"), 1004 PINCTRL_PIN(47, "C8 DRAM DQ10"), 1005 PINCTRL_PIN(48, "C9 DRAM DQ3"), 1006 PINCTRL_PIN(49, "C10 DRAM DQ6"), 1007 PINCTRL_PIN(50, "C11 DRAM DQM0"), 1008 PINCTRL_PIN(51, "C12 DRAM DQ26"), 1009 PINCTRL_PIN(52, "C13 DRAM DQ16"), 1010 PINCTRL_PIN(53, "C14 DRAM DQ22"), 1011 PINCTRL_PIN(54, "C15 DRAM DQM2"), 1012 PINCTRL_PIN(55, "C16 DRAM BA0"), 1013 PINCTRL_PIN(56, "C17 DRAM A3"), 1014 PINCTRL_PIN(57, "C18 GND"), 1015 PINCTRL_PIN(58, "C19 PCI GNT1 N"), 1016 PINCTRL_PIN(59, "C20 PCI REQ2 N"), 1017 /* Row D */ 1018 PINCTRL_PIN(60, "D1 AVCC3IOAHA"), 1019 PINCTRL_PIN(61, "D2 AVCCKHA"), 1020 PINCTRL_PIN(62, "D3 XTALO"), 1021 PINCTRL_PIN(63, "D4 GND"), 1022 PINCTRL_PIN(64, "D5 CIR RXD"), 1023 PINCTRL_PIN(65, "D6 DRAM A7"), 1024 PINCTRL_PIN(66, "D7 DRAM A4"), 1025 PINCTRL_PIN(67, "D8 DRAM A8"), 1026 PINCTRL_PIN(68, "D9 DRAM CKE"), 1027 PINCTRL_PIN(69, "D10 DRAM DQ14"), 1028 PINCTRL_PIN(70, "D11 DRAM DQ5"), 1029 PINCTRL_PIN(71, "D12 DRAM DQ25"), 1030 PINCTRL_PIN(72, "D13 DRAM DQ17"), 1031 PINCTRL_PIN(73, "D14 DRAM DQ23"), 1032 PINCTRL_PIN(74, "D15 DRAM RAS N"), 1033 PINCTRL_PIN(75, "D16 DRAM A1"), 1034 PINCTRL_PIN(76, "D17 GND"), 1035 PINCTRL_PIN(77, "D18 EXT RESET N"), 1036 PINCTRL_PIN(78, "D19 PCI REQ1 N"), 1037 PINCTRL_PIN(79, "D20 PCI REQ3 N"), 1038 /* Row E */ 1039 PINCTRL_PIN(80, "E1 VCC2IO CTRL"), 1040 PINCTRL_PIN(81, "E2 VREF CTRL"), 1041 PINCTRL_PIN(82, "E3 CIR RST N"), 1042 PINCTRL_PIN(83, "E4 PWR BTN"), 1043 PINCTRL_PIN(84, "E5 GND"), 1044 PINCTRL_PIN(85, "E6 CIR TXD"), 1045 PINCTRL_PIN(86, "E7 VCCK CTRL"), 1046 PINCTRL_PIN(87, "E8 DRAM A9"), 1047 PINCTRL_PIN(88, "E9 DRAM DQ12"), 1048 PINCTRL_PIN(89, "E10 DRAM DQ15"), 1049 PINCTRL_PIN(90, "E11 DRAM DQM3"), 1050 PINCTRL_PIN(91, "E12 DRAM DQ29"), 1051 PINCTRL_PIN(92, "E13 DRAM DQ19"), 1052 PINCTRL_PIN(93, "E14 DRAM A13"), 1053 PINCTRL_PIN(94, "E15 DRAM A0"), 1054 PINCTRL_PIN(95, "E16 GND"), 1055 PINCTRL_PIN(96, "E17 PCI INTD N"), 1056 PINCTRL_PIN(97, "E18 PCI GNT3 N"), 1057 PINCTRL_PIN(98, "E19 PCI AD29"), 1058 PINCTRL_PIN(99, "E20 PCI AD28"), 1059 /* Row F */ 1060 PINCTRL_PIN(100, "F1 AVCCKHB"), 1061 PINCTRL_PIN(101, "F2 AVCCK P"), 1062 PINCTRL_PIN(102, "F3 EBG"), 1063 PINCTRL_PIN(103, "F4 REXT"), 1064 PINCTRL_PIN(104, "F5 AVCC3IOHB"), 1065 PINCTRL_PIN(105, "F6 GND"), 1066 PINCTRL_PIN(106, "F7 VCC2IOHA 2"), 1067 PINCTRL_PIN(107, "F8 VCC2IOHA 2"), 1068 PINCTRL_PIN(108, "F9 VCC2IOHA 2"), 1069 PINCTRL_PIN(109, "F10 V1"), 1070 PINCTRL_PIN(110, "F11 V1"), 1071 PINCTRL_PIN(111, "F12 VCC2IOHA 2"), 1072 PINCTRL_PIN(112, "F13 VCC2IOHA 2"), 1073 PINCTRL_PIN(113, "F14 VCC2IOHA 2"), 1074 PINCTRL_PIN(114, "F15 GND"), 1075 PINCTRL_PIN(115, "F16 PCI CLK"), 1076 PINCTRL_PIN(116, "F17 PCI GNT2 N"), 1077 PINCTRL_PIN(117, "F18 PCI AD31"), 1078 PINCTRL_PIN(118, "F19 PCI AD26"), 1079 PINCTRL_PIN(119, "F20 PCI CBE3 N"), 1080 /* Row G */ 1081 PINCTRL_PIN(120, "G1 SATA0 RXDP"), 1082 PINCTRL_PIN(121, "G2 SATA0 RXDN"), 1083 PINCTRL_PIN(122, "G3 AGNDK 0"), 1084 PINCTRL_PIN(123, "G4 AVCCK S"), 1085 PINCTRL_PIN(124, "G5 AVCC3 S"), 1086 PINCTRL_PIN(125, "G6 VCC2IOHA 2"), 1087 PINCTRL_PIN(126, "G7 GND"), 1088 PINCTRL_PIN(127, "G8 VCC2IOHA 2"), 1089 PINCTRL_PIN(128, "G9 V1"), 1090 PINCTRL_PIN(129, "G10 V1"), 1091 PINCTRL_PIN(130, "G11 V1"), 1092 PINCTRL_PIN(131, "G12 V1"), 1093 PINCTRL_PIN(132, "G13 VCC2IOHA 2"), 1094 PINCTRL_PIN(133, "G14 GND"), 1095 PINCTRL_PIN(134, "G15 VCC3IOHA"), 1096 PINCTRL_PIN(135, "G16 PCI REQ0 N"), 1097 PINCTRL_PIN(136, "G17 PCI AD30"), 1098 PINCTRL_PIN(137, "G18 PCI AD24"), 1099 PINCTRL_PIN(138, "G19 PCI AD23"), 1100 PINCTRL_PIN(139, "G20 PCI AD21"), 1101 /* Row H */ 1102 PINCTRL_PIN(140, "H1 SATA0 TXDP"), 1103 PINCTRL_PIN(141, "H2 SATA0 TXDN"), 1104 PINCTRL_PIN(142, "H3 AGNDK 1"), 1105 PINCTRL_PIN(143, "H4 AVCCK 0"), 1106 PINCTRL_PIN(144, "H5 TEST CLKOUT"), 1107 PINCTRL_PIN(145, "H6 AGND"), 1108 PINCTRL_PIN(146, "H7 VCC2IOHA 2"), 1109 PINCTRL_PIN(147, "H8 GND"), 1110 PINCTRL_PIN(148, "H9 GND"), 1111 PINCTRL_PIN(149, "H10 GDN"), 1112 PINCTRL_PIN(150, "H11 GND"), 1113 PINCTRL_PIN(151, "H12 GND"), 1114 PINCTRL_PIN(152, "H13 GND"), 1115 PINCTRL_PIN(153, "H14 VCC3IOHA"), 1116 PINCTRL_PIN(154, "H15 VCC3IOHA"), 1117 PINCTRL_PIN(155, "H16 PCI AD27"), 1118 PINCTRL_PIN(156, "H17 PCI AD25"), 1119 PINCTRL_PIN(157, "H18 PCI AD22"), 1120 PINCTRL_PIN(158, "H19 PCI AD18"), 1121 PINCTRL_PIN(159, "H20 PCI AD17"), 1122 /* Row J (for some reason I is skipped) */ 1123 PINCTRL_PIN(160, "J1 SATA1 TXDP"), 1124 PINCTRL_PIN(161, "J2 SATA1 TXDN"), 1125 PINCTRL_PIN(162, "J3 AGNDK 2"), 1126 PINCTRL_PIN(163, "J4 AVCCK 1"), 1127 PINCTRL_PIN(164, "J5 AGND"), 1128 PINCTRL_PIN(165, "J6 AGND"), 1129 PINCTRL_PIN(166, "J7 V1"), 1130 PINCTRL_PIN(167, "J8 GND"), 1131 PINCTRL_PIN(168, "J9 GND"), 1132 PINCTRL_PIN(169, "J10 GND"), 1133 PINCTRL_PIN(170, "J11 GND"), 1134 PINCTRL_PIN(171, "J12 GND"), 1135 PINCTRL_PIN(172, "J13 GND"), 1136 PINCTRL_PIN(173, "J14 V1"), 1137 PINCTRL_PIN(174, "J15 VCC3IOHA"), 1138 PINCTRL_PIN(175, "J16 PCI AD19"), 1139 PINCTRL_PIN(176, "J17 PCI AD20"), 1140 PINCTRL_PIN(177, "J18 PCI AD16"), 1141 PINCTRL_PIN(178, "J19 PCI CBE2 N"), 1142 PINCTRL_PIN(179, "J20 PCI FRAME N"), 1143 /* Row K */ 1144 PINCTRL_PIN(180, "K1 SATA1 RXDP"), 1145 PINCTRL_PIN(181, "K2 SATA1 RXDN"), 1146 PINCTRL_PIN(182, "K3 AGNDK 3"), 1147 PINCTRL_PIN(183, "K4 AVCCK 2"), 1148 PINCTRL_PIN(184, "K5 AGND"), 1149 PINCTRL_PIN(185, "K6 V1"), 1150 PINCTRL_PIN(186, "K7 V1"), 1151 PINCTRL_PIN(187, "K8 GND"), 1152 PINCTRL_PIN(188, "K9 GND"), 1153 PINCTRL_PIN(189, "K10 GND"), 1154 PINCTRL_PIN(190, "K11 GND"), 1155 PINCTRL_PIN(191, "K12 GND"), 1156 PINCTRL_PIN(192, "K13 GND"), 1157 PINCTRL_PIN(193, "K14 V1"), 1158 PINCTRL_PIN(194, "K15 V1"), 1159 PINCTRL_PIN(195, "K16 PCI TRDY N"), 1160 PINCTRL_PIN(196, "K17 PCI IRDY N"), 1161 PINCTRL_PIN(197, "K18 PCI DEVSEL N"), 1162 PINCTRL_PIN(198, "K19 PCI STOP N"), 1163 PINCTRL_PIN(199, "K20 PCI PAR"), 1164 /* Row L */ 1165 PINCTRL_PIN(200, "L1 IDE CS0 N"), 1166 PINCTRL_PIN(201, "L2 IDE DA0"), 1167 PINCTRL_PIN(202, "L3 AVCCK 3"), 1168 PINCTRL_PIN(203, "L4 AGND"), 1169 PINCTRL_PIN(204, "L5 IDE DIOR N"), 1170 PINCTRL_PIN(205, "L6 V1"), 1171 PINCTRL_PIN(206, "L7 V1"), 1172 PINCTRL_PIN(207, "L8 GND"), 1173 PINCTRL_PIN(208, "L9 GND"), 1174 PINCTRL_PIN(209, "L10 GND"), 1175 PINCTRL_PIN(210, "L11 GND"), 1176 PINCTRL_PIN(211, "L12 GND"), 1177 PINCTRL_PIN(212, "L13 GND"), 1178 PINCTRL_PIN(213, "L14 V1"), 1179 PINCTRL_PIN(214, "L15 V1"), 1180 PINCTRL_PIN(215, "L16 PCI AD12"), 1181 PINCTRL_PIN(216, "L17 PCI AD13"), 1182 PINCTRL_PIN(217, "L18 PCI AD14"), 1183 PINCTRL_PIN(218, "L19 PCI AD15"), 1184 PINCTRL_PIN(219, "L20 PCI CBE1 N"), 1185 /* Row M */ 1186 PINCTRL_PIN(220, "M1 IDE DA1"), 1187 PINCTRL_PIN(221, "M2 IDE CS1 N"), 1188 PINCTRL_PIN(222, "M3 IDE DA2"), 1189 PINCTRL_PIN(223, "M4 IDE DMACK N"), 1190 PINCTRL_PIN(224, "M5 IDE DD1"), 1191 PINCTRL_PIN(225, "M6 VCC3IOHA"), 1192 PINCTRL_PIN(226, "M7 V1"), 1193 PINCTRL_PIN(227, "M8 GND"), 1194 PINCTRL_PIN(228, "M9 GND"), 1195 PINCTRL_PIN(229, "M10 GND"), 1196 PINCTRL_PIN(230, "M11 GND"), 1197 PINCTRL_PIN(231, "M12 GND"), 1198 PINCTRL_PIN(232, "M13 GND"), 1199 PINCTRL_PIN(233, "M14 V1"), 1200 PINCTRL_PIN(234, "M15 VCC3IOHA"), 1201 PINCTRL_PIN(235, "M16 PCI AD7"), 1202 PINCTRL_PIN(236, "M17 PCI AD6"), 1203 PINCTRL_PIN(237, "M18 PCI AD9"), 1204 PINCTRL_PIN(238, "M19 PCI AD10"), 1205 PINCTRL_PIN(239, "M20 PCI AD11"), 1206 /* Row N */ 1207 PINCTRL_PIN(240, "N1 IDE IORDY"), 1208 PINCTRL_PIN(241, "N2 IDE INTRQ"), 1209 PINCTRL_PIN(242, "N3 IDE DIOW N"), 1210 PINCTRL_PIN(243, "N4 IDE DD15"), 1211 PINCTRL_PIN(244, "N5 IDE DMARQ"), 1212 PINCTRL_PIN(245, "N6 VCC3IOHA"), 1213 PINCTRL_PIN(246, "N7 VCC3IOHA"), 1214 PINCTRL_PIN(247, "N8 GND"), 1215 PINCTRL_PIN(248, "N9 GND"), 1216 PINCTRL_PIN(249, "N10 GND"), 1217 PINCTRL_PIN(250, "N11 GND"), 1218 PINCTRL_PIN(251, "N12 GND"), 1219 PINCTRL_PIN(252, "N13 GND"), 1220 PINCTRL_PIN(253, "N14 VCC3IOHA"), 1221 PINCTRL_PIN(254, "N15 VCC3IOHA"), 1222 PINCTRL_PIN(255, "N16 PCI CLKRUN N"), 1223 PINCTRL_PIN(256, "N17 PCI AD0"), 1224 PINCTRL_PIN(257, "N18 PCI AD4"), 1225 PINCTRL_PIN(258, "N19 PCI CBE0 N"), 1226 PINCTRL_PIN(259, "N20 PCI AD8"), 1227 /* Row P (for some reason O is skipped) */ 1228 PINCTRL_PIN(260, "P1 IDE DD0"), 1229 PINCTRL_PIN(261, "P2 IDE DD14"), 1230 PINCTRL_PIN(262, "P3 IDE DD2"), 1231 PINCTRL_PIN(263, "P4 IDE DD4"), 1232 PINCTRL_PIN(264, "P5 IDE DD3"), 1233 PINCTRL_PIN(265, "P6 VCC3IOHA"), 1234 PINCTRL_PIN(266, "P7 GND"), 1235 PINCTRL_PIN(267, "P8 VCC2IOHA 1"), 1236 PINCTRL_PIN(268, "P9 V1"), 1237 PINCTRL_PIN(269, "P10 V1"), 1238 PINCTRL_PIN(270, "P11 V1"), 1239 PINCTRL_PIN(271, "P12 V1"), 1240 PINCTRL_PIN(272, "P13 VCC3IOHA"), 1241 PINCTRL_PIN(273, "P14 GND"), 1242 PINCTRL_PIN(274, "P15 VCC3IOHA"), 1243 PINCTRL_PIN(275, "P16 GPIO0 30"), 1244 PINCTRL_PIN(276, "P17 GPIO0 28"), 1245 PINCTRL_PIN(277, "P18 PCI AD1"), 1246 PINCTRL_PIN(278, "P19 PCI AD3"), 1247 PINCTRL_PIN(279, "P20 PCI AD5"), 1248 /* Row R (for some reason Q us skipped) */ 1249 PINCTRL_PIN(280, "R1 IDE DD13"), 1250 PINCTRL_PIN(281, "R2 IDE DD12"), 1251 PINCTRL_PIN(282, "R3 IDE DD10"), 1252 PINCTRL_PIN(283, "R4 IDE DD6"), 1253 PINCTRL_PIN(284, "R5 ICE0 IDI"), 1254 PINCTRL_PIN(285, "R6 GND"), 1255 PINCTRL_PIN(286, "R7 VCC2IOHA 1"), 1256 PINCTRL_PIN(287, "R8 VCC2IOHA 1"), 1257 PINCTRL_PIN(288, "R9 VCC2IOHA 1"), 1258 PINCTRL_PIN(289, "R10 V1"), 1259 PINCTRL_PIN(290, "R11 V1"), 1260 PINCTRL_PIN(291, "R12 VCC3IOHA"), 1261 PINCTRL_PIN(292, "R13 VCC3IOHA"), 1262 PINCTRL_PIN(293, "R14 VCC3IOHA"), 1263 PINCTRL_PIN(294, "R15 GND"), 1264 PINCTRL_PIN(295, "R16 GPIO0 23"), 1265 PINCTRL_PIN(296, "R17 GPIO0 21"), 1266 PINCTRL_PIN(297, "R18 GPIO0 26"), 1267 PINCTRL_PIN(298, "R19 GPIO0 31"), 1268 PINCTRL_PIN(299, "R20 PCI AD2"), 1269 /* Row T (for some reason S is skipped) */ 1270 PINCTRL_PIN(300, "T1 IDE DD11"), 1271 PINCTRL_PIN(301, "T2 IDE DD5"), 1272 PINCTRL_PIN(302, "T3 IDE DD8"), 1273 PINCTRL_PIN(303, "T4 ICE0 IDO"), 1274 PINCTRL_PIN(304, "T5 GND"), 1275 PINCTRL_PIN(305, "T6 USB GNDA U20"), 1276 PINCTRL_PIN(306, "T7 GMAC0 TXD0"), 1277 PINCTRL_PIN(307, "T8 GMAC0 TXEN"), 1278 PINCTRL_PIN(308, "T9 GMAC1 TXD3"), 1279 PINCTRL_PIN(309, "T10 GMAC1 RXDV"), 1280 PINCTRL_PIN(310, "T11 GMAC1 RXD2"), 1281 PINCTRL_PIN(311, "T12 GPIO1 29"), 1282 PINCTRL_PIN(312, "T13 GPIO0 3"), 1283 PINCTRL_PIN(313, "T14 GPIO0 9"), 1284 PINCTRL_PIN(314, "T15 GPIO0 16"), 1285 PINCTRL_PIN(315, "T16 GND"), 1286 PINCTRL_PIN(316, "T17 GPIO0 14"), 1287 PINCTRL_PIN(317, "T18 GPIO0 19"), 1288 PINCTRL_PIN(318, "T19 GPIO0 27"), 1289 PINCTRL_PIN(319, "T20 GPIO0 29"), 1290 /* Row U */ 1291 PINCTRL_PIN(320, "U1 IDE DD9"), 1292 PINCTRL_PIN(321, "U2 IDE DD7"), 1293 PINCTRL_PIN(322, "U3 ICE0 ICK"), 1294 PINCTRL_PIN(323, "U4 GND"), 1295 PINCTRL_PIN(324, "U5 USB XSCO"), 1296 PINCTRL_PIN(325, "U6 GMAC0 TXD1"), 1297 PINCTRL_PIN(326, "U7 GMAC0 TXD3"), 1298 PINCTRL_PIN(327, "U8 GMAC0 TXC"), 1299 PINCTRL_PIN(328, "U9 GMAC0 RXD3"), 1300 PINCTRL_PIN(329, "U10 GMAC1 TXD0"), 1301 PINCTRL_PIN(330, "U11 GMAC1 CRS"), 1302 PINCTRL_PIN(331, "U12 EXT CLK"), 1303 PINCTRL_PIN(332, "U13 DEV DEF"), 1304 PINCTRL_PIN(333, "U14 GPIO0 0"), 1305 PINCTRL_PIN(334, "U15 GPIO0 4"), 1306 PINCTRL_PIN(335, "U16 GPIO0 10"), 1307 PINCTRL_PIN(336, "U17 GND"), 1308 PINCTRL_PIN(337, "U18 GPIO0 17"), 1309 PINCTRL_PIN(338, "U19 GPIO0 22"), 1310 PINCTRL_PIN(339, "U20 GPIO0 25"), 1311 /* Row V */ 1312 PINCTRL_PIN(340, "V1 ICE0 DBGACK"), 1313 PINCTRL_PIN(341, "V2 ICE0 DBGRQ"), 1314 PINCTRL_PIN(342, "V3 GND"), 1315 PINCTRL_PIN(343, "V4 ICE0 IRST N"), 1316 PINCTRL_PIN(344, "V5 USB XSCI"), 1317 PINCTRL_PIN(345, "V6 GMAC0 COL"), 1318 PINCTRL_PIN(346, "V7 GMAC0 TXD2"), 1319 PINCTRL_PIN(347, "V8 GMAC0 RXDV"), 1320 PINCTRL_PIN(348, "V9 GMAC0 RXD1"), 1321 PINCTRL_PIN(349, "V10 GMAC1 COL"), 1322 PINCTRL_PIN(350, "V11 GMAC1 TXC"), 1323 PINCTRL_PIN(351, "V12 GMAC1 RXD1"), 1324 PINCTRL_PIN(352, "V13 MODE SEL1"), 1325 PINCTRL_PIN(353, "V14 GPIO1 28"), 1326 PINCTRL_PIN(354, "V15 GPIO0 1"), 1327 PINCTRL_PIN(355, "V16 GPIO0 8"), 1328 PINCTRL_PIN(356, "V17 GPIO0 11"), 1329 PINCTRL_PIN(357, "V18 GND"), 1330 PINCTRL_PIN(358, "V19 GPIO0 18"), 1331 PINCTRL_PIN(359, "V20 GPIO0 24"), 1332 /* Row W */ 1333 PINCTRL_PIN(360, "W1 IDE RESET N"), 1334 PINCTRL_PIN(361, "W2 GND"), 1335 PINCTRL_PIN(362, "W3 USB0 VCCHSRT"), 1336 PINCTRL_PIN(363, "W4 USB0 DP"), 1337 PINCTRL_PIN(364, "W5 USB VCCA U20"), 1338 PINCTRL_PIN(365, "W6 USB1 DP"), 1339 PINCTRL_PIN(366, "W7 USB1 GNDHSRT"), 1340 PINCTRL_PIN(367, "W8 GMAC0 RXD0"), 1341 PINCTRL_PIN(368, "W9 GMAC0 CRS"), 1342 PINCTRL_PIN(369, "W10 GMAC1 TXD2"), 1343 PINCTRL_PIN(370, "W11 GMAC1 TXEN"), 1344 PINCTRL_PIN(371, "W12 GMAC1 RXD3"), 1345 PINCTRL_PIN(372, "W13 MODE SEL0"), 1346 PINCTRL_PIN(373, "W14 MODE SEL3"), 1347 PINCTRL_PIN(374, "W15 GPIO1 31"), 1348 PINCTRL_PIN(375, "W16 GPIO0 5"), 1349 PINCTRL_PIN(376, "W17 GPIO0 7"), 1350 PINCTRL_PIN(377, "W18 GPIO0 12"), 1351 PINCTRL_PIN(378, "W19 GND"), 1352 PINCTRL_PIN(379, "W20 GPIO0 20"), 1353 /* Row Y */ 1354 PINCTRL_PIN(380, "Y1 ICE0 IMS"), 1355 PINCTRL_PIN(381, "Y2 USB0 GNDHSRT"), 1356 PINCTRL_PIN(382, "Y3 USB0 DM"), 1357 PINCTRL_PIN(383, "Y4 USB RREF"), 1358 PINCTRL_PIN(384, "Y5 USB1 DM"), 1359 PINCTRL_PIN(385, "Y6 USB1 VCCHSRT"), 1360 PINCTRL_PIN(386, "Y7 GMAC0 RXC"), 1361 PINCTRL_PIN(387, "Y8 GMAC0 RXD2"), 1362 PINCTRL_PIN(388, "Y9 REF CLK"), 1363 PINCTRL_PIN(389, "Y10 GMAC1 TXD1"), 1364 PINCTRL_PIN(390, "Y11 GMAC1 RXC"), 1365 PINCTRL_PIN(391, "Y12 GMAC1 RXD0"), 1366 PINCTRL_PIN(392, "Y13 M30 CLK"), 1367 PINCTRL_PIN(393, "Y14 MODE SEL2"), 1368 PINCTRL_PIN(394, "Y15 GPIO1 30"), 1369 PINCTRL_PIN(395, "Y16 GPIO0 2"), 1370 PINCTRL_PIN(396, "Y17 GPIO0 6"), 1371 PINCTRL_PIN(397, "Y18 SYS RESET N"), 1372 PINCTRL_PIN(398, "Y19 GPIO0 13"), 1373 PINCTRL_PIN(399, "Y20 GPIO0 15"), 1374 }; 1375 1376 /* Digital ground */ 1377 static const unsigned int gnd_3516_pins[] = { 1378 21, 38, 42, 57, 63, 76, 84, 95, 105, 114, 126, 133, 147, 148, 149, 150, 1379 151, 152, 167, 168, 169, 170, 171, 172, 187, 188, 189, 190, 191, 192, 1380 207, 208, 209, 210, 211, 212, 227, 228, 229, 230, 231, 232, 247, 248, 1381 249, 250, 251, 252, 266, 273, 285, 294, 304, 315, 323, 336, 342, 357, 1382 361, 378 1383 }; 1384 1385 static const unsigned int dram_3516_pins[] = { 1386 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 26, 1387 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 44, 45, 46, 47, 48, 49, 50, 1388 51, 52, 53, 54, 55, 56, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 1389 87, 88, 89, 90, 91, 92, 93, 94 1390 }; 1391 1392 static const unsigned int rtc_3516_pins[] = { 0, 43, 22 }; 1393 1394 static const unsigned int power_3516_pins[] = { 20, 83, 40, 41, 60, 61, 62 }; 1395 1396 static const unsigned int cir_3516_pins[] = { 85, 64, 82 }; 1397 1398 static const unsigned int system_3516_pins[] = { 1399 332, 392, 372, 373, 393, 352, 331, 388, 397, 77 1400 }; 1401 1402 static const unsigned int vcontrol_3516_pins[] = { 86, 81, 80 }; 1403 1404 static const unsigned int ice_3516_pins[] = { 340, 341, 303, 322, 380, 284, 343 }; 1405 1406 static const unsigned int ide_3516_pins[] = { 1407 200, 201, 204, 220, 221, 222, 223, 224, 240, 241, 242, 243, 244, 260, 1408 261, 262, 263, 264, 280, 281, 282, 283, 300, 301, 302, 320, 321, 360 1409 }; 1410 1411 static const unsigned int sata_3516_pins[] = { 1412 100, 101, 102, 103, 104, 120, 121, 122, 123, 124, 140, 141, 142, 143, 1413 144, 160, 161, 162, 163, 180, 181, 182, 183, 202 1414 }; 1415 1416 static const unsigned int usb_3516_pins[] = { 1417 305, 324, 344, 362, 363, 364, 365, 366, 381, 382, 383, 384, 385 1418 }; 1419 1420 /* GMII, ethernet pins */ 1421 static const unsigned int gmii_3516_pins[] = { 1422 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, 1423 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 1424 }; 1425 1426 static const unsigned int pci_3516_pins[] = { 1427 17, 18, 19, 39, 58, 59, 78, 79, 96, 97, 98, 99, 115, 116, 117, 118, 1428 119, 135, 136, 137, 138, 139, 155, 156, 157, 158, 159, 175, 176, 177, 1429 178, 179, 195, 196, 197, 198, 199, 215, 216, 217, 218, 219, 235, 236, 1430 237, 238, 239, 255, 256, 257, 258, 259, 277, 278, 279, 299 1431 }; 1432 1433 /* 1434 * Apparently the LPC interface is using the PCICLK for the clocking so 1435 * PCI needs to be active at the same time. 1436 */ 1437 static const unsigned int lpc_3516_pins[] = { 1438 355, /* LPC_LAD[0] */ 1439 356, /* LPC_SERIRQ */ 1440 377, /* LPC_LAD[2] */ 1441 398, /* LPC_LFRAME# */ 1442 316, /* LPC_LAD[3] */ 1443 399, /* LPC_LAD[1] */ 1444 }; 1445 1446 /* Character LCD */ 1447 static const unsigned int lcd_3516_pins[] = { 1448 391, 351, 310, 371, 353, 311, 394, 374, 314, 359, 339 1449 }; 1450 1451 static const unsigned int ssp_3516_pins[] = { 1452 355, /* SSP_97RST# SSP AC97 Reset, active low */ 1453 356, /* SSP_FSC */ 1454 377, /* SSP_ECLK */ 1455 398, /* SSP_TXD */ 1456 316, /* SSP_RXD */ 1457 399, /* SSP_SCLK */ 1458 }; 1459 1460 static const unsigned int uart_rxtx_3516_pins[] = { 1461 313, /* UART_SIN serial input, RX */ 1462 335, /* UART_SOUT serial output, TX */ 1463 }; 1464 1465 static const unsigned int uart_modem_3516_pins[] = { 1466 355, /* UART_NDCD DCD carrier detect */ 1467 356, /* UART_NDTR DTR data terminal ready */ 1468 377, /* UART_NDSR DSR data set ready */ 1469 398, /* UART_NRTS RTS request to send */ 1470 316, /* UART_NCTS CTS clear to send */ 1471 399, /* UART_NRI RI ring indicator */ 1472 }; 1473 1474 static const unsigned int tvc_3516_pins[] = { 1475 353, /* TVC_DATA[0] */ 1476 311, /* TVC_DATA[1] */ 1477 394, /* TVC_DATA[2] */ 1478 374, /* TVC_DATA[3] */ 1479 333, /* TVC_CLK */ 1480 354, /* TVC_DATA[4] */ 1481 395, /* TVC_DATA[5] */ 1482 312, /* TVC_DATA[6] */ 1483 334, /* TVC_DATA[7] */ 1484 }; 1485 1486 /* NAND flash pins */ 1487 static const unsigned int nflash_3516_pins[] = { 1488 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1489 302, 321, 337, 358, 295, 359, 339, 275, 298 1490 }; 1491 1492 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ 1493 static const unsigned int pflash_3516_pins[] = { 1494 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1495 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1496 276, 319, 275, 298 1497 }; 1498 1499 /* 1500 * The parallel flash can be set up in a 26-bit address bus mode exposing 1501 * A[0-15] (A[15] takes the place of ALE), but it has the 1502 * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be 1503 * used at the same time. 1504 */ 1505 static const unsigned int pflash_3516_pins_extended[] = { 1506 221, 200, 222, 201, 220, 243, 260, 261, 224, 280, 262, 281, 264, 300, 1507 263, 282, 301, 320, 283, 302, 321, 317, 379, 295, 359, 339, 297, 318, 1508 276, 319, 275, 298, 1509 /* The extra pins */ 1510 349, 308, 369, 389, 329, 350, 370, 309, 390, 391, 351, 310, 371, 330, 1511 333 1512 }; 1513 1514 /* Serial flash pins CE0, CE1, DI, DO, CK */ 1515 static const unsigned int sflash_3516_pins[] = { 296, 338, 295, 359, 339 }; 1516 1517 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ 1518 static const unsigned int gpio0a_3516_pins[] = { 333, 354, 395, 312, 334 }; 1519 1520 /* The GPIO0B (5-7) pins overlap with ICE */ 1521 static const unsigned int gpio0b_3516_pins[] = { 375, 396, 376 }; 1522 1523 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ 1524 static const unsigned int gpio0c_3516_pins[] = { 355, 356, 377, 398, 316, 399 }; 1525 1526 /* The GPIO0D (9,10) pins overlap with UART RX/TX */ 1527 static const unsigned int gpio0d_3516_pins[] = { 313, 335 }; 1528 1529 /* The GPIO0E (16) pins overlap with LCD */ 1530 static const unsigned int gpio0e_3516_pins[] = { 314 }; 1531 1532 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ 1533 static const unsigned int gpio0f_3516_pins[] = { 337, 358 }; 1534 1535 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ 1536 static const unsigned int gpio0g_3516_pins[] = { 317, 379, 297, 318, 276, 319 }; 1537 1538 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ 1539 static const unsigned int gpio0h_3516_pins[] = { 296, 338 }; 1540 1541 /* The GPIO0I (23) pins overlap with all flash */ 1542 static const unsigned int gpio0i_3516_pins[] = { 295 }; 1543 1544 /* The GPIO0J (24,25) pins overlap with all flash and LCD */ 1545 static const unsigned int gpio0j_3516_pins[] = { 359, 339 }; 1546 1547 /* The GPIO0K (30,31) pins overlap with NAND flash */ 1548 static const unsigned int gpio0k_3516_pins[] = { 275, 298 }; 1549 1550 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ 1551 static const unsigned int gpio1a_3516_pins[] = { 221, 200, 222, 201, 220 }; 1552 1553 /* The GPIO1B (5-10,27) pins overlap with just IDE */ 1554 static const unsigned int gpio1b_3516_pins[] = { 241, 223, 240, 204, 242, 244, 360 }; 1555 1556 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ 1557 static const unsigned int gpio1c_3516_pins[] = { 1558 243, 260, 261, 224, 280, 262, 281, 264, 300, 263, 282, 301, 320, 283, 1559 302, 321 1560 }; 1561 1562 /* The GPIO1D (28-31) pins overlap with TVC */ 1563 static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; 1564 1565 /* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 1566 static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; 1567 1568 /* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 1569 static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; 1570 1571 /* The GPIO2C (8-31) pins overlap with PCI */ 1572 static const unsigned int gpio2c_3516_pins[] = { 1573 259, 237, 238, 239, 215, 216, 217, 218, 177, 159, 158, 175, 176, 139, 1574 157, 138, 137, 156, 118, 155, 99, 98, 136, 117 1575 }; 1576 1577 /* Groups for the 3516 SoC/package */ 1578 static const struct gemini_pin_group gemini_3516_pin_groups[] = { 1579 { 1580 .name = "gndgrp", 1581 .pins = gnd_3516_pins, 1582 .num_pins = ARRAY_SIZE(gnd_3516_pins), 1583 }, 1584 { 1585 .name = "dramgrp", 1586 .pins = dram_3516_pins, 1587 .num_pins = ARRAY_SIZE(dram_3516_pins), 1588 .mask = DRAM_PADS_POWERDOWN, 1589 }, 1590 { 1591 .name = "rtcgrp", 1592 .pins = rtc_3516_pins, 1593 .num_pins = ARRAY_SIZE(rtc_3516_pins), 1594 }, 1595 { 1596 .name = "powergrp", 1597 .pins = power_3516_pins, 1598 .num_pins = ARRAY_SIZE(power_3516_pins), 1599 }, 1600 { 1601 .name = "cirgrp", 1602 .pins = cir_3516_pins, 1603 .num_pins = ARRAY_SIZE(cir_3516_pins), 1604 }, 1605 { 1606 .name = "systemgrp", 1607 .pins = system_3516_pins, 1608 .num_pins = ARRAY_SIZE(system_3516_pins), 1609 }, 1610 { 1611 .name = "vcontrolgrp", 1612 .pins = vcontrol_3516_pins, 1613 .num_pins = ARRAY_SIZE(vcontrol_3516_pins), 1614 }, 1615 { 1616 .name = "icegrp", 1617 .pins = ice_3516_pins, 1618 .num_pins = ARRAY_SIZE(ice_3516_pins), 1619 /* Conflict with some GPIO groups */ 1620 }, 1621 { 1622 .name = "idegrp", 1623 .pins = ide_3516_pins, 1624 .num_pins = ARRAY_SIZE(ide_3516_pins), 1625 /* Conflict with all flash usage */ 1626 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | 1627 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1628 }, 1629 { 1630 .name = "satagrp", 1631 .pins = sata_3516_pins, 1632 .num_pins = ARRAY_SIZE(sata_3516_pins), 1633 }, 1634 { 1635 .name = "usbgrp", 1636 .pins = usb_3516_pins, 1637 .num_pins = ARRAY_SIZE(usb_3516_pins), 1638 }, 1639 { 1640 .name = "gmiigrp", 1641 .pins = gmii_3516_pins, 1642 .num_pins = ARRAY_SIZE(gmii_3516_pins), 1643 }, 1644 { 1645 .name = "pcigrp", 1646 .pins = pci_3516_pins, 1647 .num_pins = ARRAY_SIZE(pci_3516_pins), 1648 /* Conflict only with GPIO2 */ 1649 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, 1650 }, 1651 { 1652 .name = "lpcgrp", 1653 .pins = lpc_3516_pins, 1654 .num_pins = ARRAY_SIZE(lpc_3516_pins), 1655 /* Conflict with SSP */ 1656 .mask = SSP_PADS_ENABLE, 1657 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE, 1658 }, 1659 { 1660 .name = "lcdgrp", 1661 .pins = lcd_3516_pins, 1662 .num_pins = ARRAY_SIZE(lcd_3516_pins), 1663 .mask = TVC_PADS_ENABLE, 1664 .value = LCD_PADS_ENABLE, 1665 }, 1666 { 1667 .name = "sspgrp", 1668 .pins = ssp_3516_pins, 1669 .num_pins = ARRAY_SIZE(ssp_3516_pins), 1670 /* Conflict with LPC */ 1671 .mask = LPC_PADS_ENABLE, 1672 .value = SSP_PADS_ENABLE, 1673 }, 1674 { 1675 .name = "uartrxtxgrp", 1676 .pins = uart_rxtx_3516_pins, 1677 .num_pins = ARRAY_SIZE(uart_rxtx_3516_pins), 1678 /* No conflicts except GPIO */ 1679 }, 1680 { 1681 .name = "uartmodemgrp", 1682 .pins = uart_modem_3516_pins, 1683 .num_pins = ARRAY_SIZE(uart_modem_3516_pins), 1684 /* 1685 * Conflict with LPC and SSP, 1686 * so when those are both disabled, modem UART can thrive. 1687 */ 1688 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1689 }, 1690 { 1691 .name = "tvcgrp", 1692 .pins = tvc_3516_pins, 1693 .num_pins = ARRAY_SIZE(tvc_3516_pins), 1694 /* Conflict with character LCD */ 1695 .mask = LCD_PADS_ENABLE, 1696 .value = TVC_PADS_ENABLE | TVC_CLK_PAD_ENABLE, 1697 }, 1698 /* 1699 * The construction is done such that it is possible to use a serial 1700 * flash together with a NAND or parallel (NOR) flash, but it is not 1701 * possible to use NAND and parallel flash together. To use serial 1702 * flash with one of the two others, the muxbits need to be flipped 1703 * around before any access. 1704 */ 1705 { 1706 .name = "nflashgrp", 1707 .pins = nflash_3516_pins, 1708 .num_pins = ARRAY_SIZE(nflash_3516_pins), 1709 /* Conflict with IDE, parallel and serial flash */ 1710 .mask = NAND_PADS_DISABLE | IDE_PADS_ENABLE, 1711 .value = PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, 1712 }, 1713 { 1714 .name = "pflashgrp", 1715 .pins = pflash_3516_pins, 1716 .num_pins = ARRAY_SIZE(pflash_3516_pins), 1717 /* Conflict with IDE, NAND and serial flash */ 1718 .mask = PFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1719 .value = NAND_PADS_DISABLE | SFLASH_PADS_DISABLE, 1720 }, 1721 { 1722 .name = "sflashgrp", 1723 .pins = sflash_3516_pins, 1724 .num_pins = ARRAY_SIZE(sflash_3516_pins), 1725 /* Conflict with IDE, NAND and parallel flash */ 1726 .mask = SFLASH_PADS_DISABLE | IDE_PADS_ENABLE, 1727 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1728 }, 1729 { 1730 .name = "gpio0agrp", 1731 .pins = gpio0a_3516_pins, 1732 .num_pins = ARRAY_SIZE(gpio0a_3516_pins), 1733 /* Conflict with TVC and ICE */ 1734 .mask = TVC_PADS_ENABLE, 1735 }, 1736 { 1737 .name = "gpio0bgrp", 1738 .pins = gpio0b_3516_pins, 1739 .num_pins = ARRAY_SIZE(gpio0b_3516_pins), 1740 /* Conflict with ICE */ 1741 }, 1742 { 1743 .name = "gpio0cgrp", 1744 .pins = gpio0c_3516_pins, 1745 .num_pins = ARRAY_SIZE(gpio0c_3516_pins), 1746 /* Conflict with LPC, UART and SSP */ 1747 .mask = LPC_PADS_ENABLE | SSP_PADS_ENABLE, 1748 }, 1749 { 1750 .name = "gpio0dgrp", 1751 .pins = gpio0d_3516_pins, 1752 .num_pins = ARRAY_SIZE(gpio0d_3516_pins), 1753 /* Conflict with UART */ 1754 }, 1755 { 1756 .name = "gpio0egrp", 1757 .pins = gpio0e_3516_pins, 1758 .num_pins = ARRAY_SIZE(gpio0e_3516_pins), 1759 /* Conflict with LCD */ 1760 .mask = LCD_PADS_ENABLE, 1761 }, 1762 { 1763 .name = "gpio0fgrp", 1764 .pins = gpio0f_3516_pins, 1765 .num_pins = ARRAY_SIZE(gpio0f_3516_pins), 1766 /* Conflict with NAND flash */ 1767 .value = NAND_PADS_DISABLE, 1768 }, 1769 { 1770 .name = "gpio0ggrp", 1771 .pins = gpio0g_3516_pins, 1772 .num_pins = ARRAY_SIZE(gpio0g_3516_pins), 1773 /* Conflict with parallel flash */ 1774 .value = PFLASH_PADS_DISABLE, 1775 }, 1776 { 1777 .name = "gpio0hgrp", 1778 .pins = gpio0h_3516_pins, 1779 .num_pins = ARRAY_SIZE(gpio0h_3516_pins), 1780 /* Conflict with serial flash */ 1781 .value = SFLASH_PADS_DISABLE, 1782 }, 1783 { 1784 .name = "gpio0igrp", 1785 .pins = gpio0i_3516_pins, 1786 .num_pins = ARRAY_SIZE(gpio0i_3516_pins), 1787 /* Conflict with all flash */ 1788 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1789 SFLASH_PADS_DISABLE, 1790 }, 1791 { 1792 .name = "gpio0jgrp", 1793 .pins = gpio0j_3516_pins, 1794 .num_pins = ARRAY_SIZE(gpio0j_3516_pins), 1795 /* Conflict with all flash and LCD */ 1796 .mask = LCD_PADS_ENABLE, 1797 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE | 1798 SFLASH_PADS_DISABLE, 1799 }, 1800 { 1801 .name = "gpio0kgrp", 1802 .pins = gpio0k_3516_pins, 1803 .num_pins = ARRAY_SIZE(gpio0k_3516_pins), 1804 /* Conflict with parallel and NAND flash */ 1805 .value = PFLASH_PADS_DISABLE | NAND_PADS_DISABLE, 1806 }, 1807 { 1808 .name = "gpio1agrp", 1809 .pins = gpio1a_3516_pins, 1810 .num_pins = ARRAY_SIZE(gpio1a_3516_pins), 1811 /* Conflict with IDE and parallel flash */ 1812 .mask = IDE_PADS_ENABLE, 1813 .value = PFLASH_PADS_DISABLE, 1814 }, 1815 { 1816 .name = "gpio1bgrp", 1817 .pins = gpio1b_3516_pins, 1818 .num_pins = ARRAY_SIZE(gpio1b_3516_pins), 1819 /* Conflict with IDE only */ 1820 .mask = IDE_PADS_ENABLE, 1821 }, 1822 { 1823 .name = "gpio1cgrp", 1824 .pins = gpio1c_3516_pins, 1825 .num_pins = ARRAY_SIZE(gpio1c_3516_pins), 1826 /* Conflict with IDE, parallel and NAND flash */ 1827 .mask = IDE_PADS_ENABLE, 1828 .value = NAND_PADS_DISABLE | PFLASH_PADS_DISABLE, 1829 }, 1830 { 1831 .name = "gpio1dgrp", 1832 .pins = gpio1d_3516_pins, 1833 .num_pins = ARRAY_SIZE(gpio1d_3516_pins), 1834 /* Conflict with TVC */ 1835 .mask = TVC_PADS_ENABLE, 1836 }, 1837 { 1838 .name = "gpio2agrp", 1839 .pins = gpio2a_3516_pins, 1840 .num_pins = ARRAY_SIZE(gpio2a_3516_pins), 1841 /* Conflict with GMII and extended parallel flash */ 1842 }, 1843 { 1844 .name = "gpio2bgrp", 1845 .pins = gpio2b_3516_pins, 1846 .num_pins = ARRAY_SIZE(gpio2b_3516_pins), 1847 /* Conflict with GMII, extended parallel flash and LCD */ 1848 .mask = LCD_PADS_ENABLE, 1849 }, 1850 { 1851 .name = "gpio2cgrp", 1852 .pins = gpio2c_3516_pins, 1853 .num_pins = ARRAY_SIZE(gpio2c_3516_pins), 1854 /* Conflict with PCI */ 1855 .mask = PCI_PADS_ENABLE, 1856 }, 1857 }; 1858 1859 static int gemini_get_groups_count(struct pinctrl_dev *pctldev) 1860 { 1861 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1862 1863 if (pmx->is_3512) 1864 return ARRAY_SIZE(gemini_3512_pin_groups); 1865 if (pmx->is_3516) 1866 return ARRAY_SIZE(gemini_3516_pin_groups); 1867 return 0; 1868 } 1869 1870 static const char *gemini_get_group_name(struct pinctrl_dev *pctldev, 1871 unsigned int selector) 1872 { 1873 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1874 1875 if (pmx->is_3512) 1876 return gemini_3512_pin_groups[selector].name; 1877 if (pmx->is_3516) 1878 return gemini_3516_pin_groups[selector].name; 1879 return NULL; 1880 } 1881 1882 static int gemini_get_group_pins(struct pinctrl_dev *pctldev, 1883 unsigned int selector, 1884 const unsigned int **pins, 1885 unsigned int *num_pins) 1886 { 1887 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1888 1889 /* The special case with the 3516 flash pin */ 1890 if (pmx->flash_pin && 1891 pmx->is_3512 && 1892 !strcmp(gemini_3512_pin_groups[selector].name, "pflashgrp")) { 1893 *pins = pflash_3512_pins_extended; 1894 *num_pins = ARRAY_SIZE(pflash_3512_pins_extended); 1895 return 0; 1896 } 1897 if (pmx->flash_pin && 1898 pmx->is_3516 && 1899 !strcmp(gemini_3516_pin_groups[selector].name, "pflashgrp")) { 1900 *pins = pflash_3516_pins_extended; 1901 *num_pins = ARRAY_SIZE(pflash_3516_pins_extended); 1902 return 0; 1903 } 1904 if (pmx->is_3512) { 1905 *pins = gemini_3512_pin_groups[selector].pins; 1906 *num_pins = gemini_3512_pin_groups[selector].num_pins; 1907 } 1908 if (pmx->is_3516) { 1909 *pins = gemini_3516_pin_groups[selector].pins; 1910 *num_pins = gemini_3516_pin_groups[selector].num_pins; 1911 } 1912 return 0; 1913 } 1914 1915 static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1916 unsigned int offset) 1917 { 1918 seq_printf(s, " " DRIVER_NAME); 1919 } 1920 1921 static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 1922 struct device_node *np, 1923 struct pinctrl_map **map, 1924 unsigned int *reserved_maps, 1925 unsigned int *num_maps) 1926 { 1927 int ret; 1928 const char *function = NULL; 1929 const char *group; 1930 struct property *prop; 1931 1932 ret = of_property_read_string(np, "function", &function); 1933 if (ret < 0) 1934 return ret; 1935 1936 ret = of_property_count_strings(np, "groups"); 1937 if (ret < 0) 1938 return ret; 1939 1940 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 1941 num_maps, ret); 1942 if (ret < 0) 1943 return ret; 1944 1945 of_property_for_each_string(np, "groups", prop, group) { 1946 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, 1947 num_maps, group, function); 1948 if (ret < 0) 1949 return ret; 1950 pr_debug("ADDED FUNCTION %s <-> GROUP %s\n", 1951 function, group); 1952 } 1953 1954 return 0; 1955 } 1956 1957 static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 1958 struct device_node *np_config, 1959 struct pinctrl_map **map, 1960 unsigned int *num_maps) 1961 { 1962 unsigned int reserved_maps = 0; 1963 struct device_node *np; 1964 int ret; 1965 1966 *map = NULL; 1967 *num_maps = 0; 1968 1969 for_each_child_of_node(np_config, np) { 1970 ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map, 1971 &reserved_maps, num_maps); 1972 if (ret < 0) { 1973 pinctrl_utils_free_map(pctldev, *map, *num_maps); 1974 return ret; 1975 } 1976 } 1977 1978 return 0; 1979 }; 1980 1981 static const struct pinctrl_ops gemini_pctrl_ops = { 1982 .get_groups_count = gemini_get_groups_count, 1983 .get_group_name = gemini_get_group_name, 1984 .get_group_pins = gemini_get_group_pins, 1985 .pin_dbg_show = gemini_pin_dbg_show, 1986 .dt_node_to_map = gemini_pinctrl_dt_node_to_map, 1987 .dt_free_map = pinctrl_utils_free_map, 1988 }; 1989 1990 /** 1991 * struct gemini_pmx_func - describes Gemini pinmux functions 1992 * @name: the name of this specific function 1993 * @groups: corresponding pin groups 1994 */ 1995 struct gemini_pmx_func { 1996 const char *name; 1997 const char * const *groups; 1998 const unsigned int num_groups; 1999 }; 2000 2001 static const char * const dramgrps[] = { "dramgrp" }; 2002 static const char * const rtcgrps[] = { "rtcgrp" }; 2003 static const char * const powergrps[] = { "powergrp" }; 2004 static const char * const cirgrps[] = { "cirgrp" }; 2005 static const char * const systemgrps[] = { "systemgrp" }; 2006 static const char * const vcontrolgrps[] = { "vcontrolgrp" }; 2007 static const char * const icegrps[] = { "icegrp" }; 2008 static const char * const idegrps[] = { "idegrp" }; 2009 static const char * const satagrps[] = { "satagrp" }; 2010 static const char * const usbgrps[] = { "usbgrp" }; 2011 static const char * const gmiigrps[] = { "gmiigrp" }; 2012 static const char * const pcigrps[] = { "pcigrp" }; 2013 static const char * const lpcgrps[] = { "lpcgrp" }; 2014 static const char * const lcdgrps[] = { "lcdgrp" }; 2015 static const char * const sspgrps[] = { "sspgrp" }; 2016 static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" }; 2017 static const char * const tvcgrps[] = { "tvcgrp" }; 2018 static const char * const nflashgrps[] = { "nflashgrp" }; 2019 static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" }; 2020 static const char * const sflashgrps[] = { "sflashgrp" }; 2021 static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp", 2022 "gpio0dgrp", "gpio0egrp", "gpio0fgrp", 2023 "gpio0ggrp", "gpio0hgrp", "gpio0igrp", 2024 "gpio0jgrp", "gpio0kgrp" }; 2025 static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp", 2026 "gpio1dgrp" }; 2027 static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" }; 2028 2029 static const struct gemini_pmx_func gemini_pmx_functions[] = { 2030 { 2031 .name = "dram", 2032 .groups = dramgrps, 2033 .num_groups = ARRAY_SIZE(idegrps), 2034 }, 2035 { 2036 .name = "rtc", 2037 .groups = rtcgrps, 2038 .num_groups = ARRAY_SIZE(rtcgrps), 2039 }, 2040 { 2041 .name = "power", 2042 .groups = powergrps, 2043 .num_groups = ARRAY_SIZE(powergrps), 2044 }, 2045 { 2046 /* This function is strictly unavailable on 3512 */ 2047 .name = "cir", 2048 .groups = cirgrps, 2049 .num_groups = ARRAY_SIZE(cirgrps), 2050 }, 2051 { 2052 .name = "system", 2053 .groups = systemgrps, 2054 .num_groups = ARRAY_SIZE(systemgrps), 2055 }, 2056 { 2057 .name = "vcontrol", 2058 .groups = vcontrolgrps, 2059 .num_groups = ARRAY_SIZE(vcontrolgrps), 2060 }, 2061 { 2062 .name = "ice", 2063 .groups = icegrps, 2064 .num_groups = ARRAY_SIZE(icegrps), 2065 }, 2066 { 2067 .name = "ide", 2068 .groups = idegrps, 2069 .num_groups = ARRAY_SIZE(idegrps), 2070 }, 2071 { 2072 .name = "sata", 2073 .groups = satagrps, 2074 .num_groups = ARRAY_SIZE(satagrps), 2075 }, 2076 { 2077 .name = "pci", 2078 .groups = pcigrps, 2079 .num_groups = ARRAY_SIZE(pcigrps), 2080 }, 2081 { 2082 .name = "lpc", 2083 .groups = lpcgrps, 2084 .num_groups = ARRAY_SIZE(lpcgrps), 2085 }, 2086 { 2087 .name = "lcd", 2088 .groups = lcdgrps, 2089 .num_groups = ARRAY_SIZE(lcdgrps), 2090 }, 2091 { 2092 .name = "ssp", 2093 .groups = sspgrps, 2094 .num_groups = ARRAY_SIZE(sspgrps), 2095 }, 2096 { 2097 .name = "uart", 2098 .groups = uartgrps, 2099 .num_groups = ARRAY_SIZE(uartgrps), 2100 }, 2101 { 2102 .name = "tvc", 2103 .groups = tvcgrps, 2104 .num_groups = ARRAY_SIZE(tvcgrps), 2105 }, 2106 { 2107 .name = "nflash", 2108 .groups = nflashgrps, 2109 .num_groups = ARRAY_SIZE(nflashgrps), 2110 }, 2111 { 2112 .name = "pflash", 2113 .groups = pflashgrps, 2114 .num_groups = ARRAY_SIZE(pflashgrps), 2115 }, 2116 { 2117 .name = "sflash", 2118 .groups = sflashgrps, 2119 .num_groups = ARRAY_SIZE(sflashgrps), 2120 }, 2121 { 2122 .name = "gpio0", 2123 .groups = gpio0grps, 2124 .num_groups = ARRAY_SIZE(gpio0grps), 2125 }, 2126 { 2127 .name = "gpio1", 2128 .groups = gpio1grps, 2129 .num_groups = ARRAY_SIZE(gpio1grps), 2130 }, 2131 { 2132 .name = "gpio2", 2133 .groups = gpio2grps, 2134 .num_groups = ARRAY_SIZE(gpio2grps), 2135 }, 2136 }; 2137 2138 2139 static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev, 2140 unsigned int selector, 2141 unsigned int group) 2142 { 2143 struct gemini_pmx *pmx; 2144 const struct gemini_pmx_func *func; 2145 const struct gemini_pin_group *grp; 2146 u32 before, after, expected; 2147 unsigned long tmp; 2148 int i; 2149 2150 pmx = pinctrl_dev_get_drvdata(pctldev); 2151 2152 func = &gemini_pmx_functions[selector]; 2153 if (pmx->is_3512) 2154 grp = &gemini_3512_pin_groups[group]; 2155 else if (pmx->is_3516) 2156 grp = &gemini_3516_pin_groups[group]; 2157 else { 2158 dev_err(pmx->dev, "invalid SoC type\n"); 2159 return -ENODEV; 2160 } 2161 2162 dev_info(pmx->dev, 2163 "ACTIVATE function \"%s\" with group \"%s\"\n", 2164 func->name, grp->name); 2165 2166 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before); 2167 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL, grp->mask, 2168 grp->value); 2169 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after); 2170 2171 /* Which bits changed */ 2172 before &= PADS_MASK; 2173 after &= PADS_MASK; 2174 expected = before &= ~grp->mask; 2175 expected |= grp->value; 2176 expected &= PADS_MASK; 2177 2178 /* Print changed states */ 2179 tmp = grp->mask; 2180 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2181 bool enabled = !(i > 3); 2182 2183 /* Did not go low though it should */ 2184 if (after & BIT(i)) { 2185 dev_err(pmx->dev, 2186 "pin group %s could not be %s: " 2187 "probably a hardware limitation\n", 2188 gemini_padgroups[i], 2189 enabled ? "enabled" : "disabled"); 2190 dev_err(pmx->dev, 2191 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2192 before, after, expected); 2193 } else { 2194 dev_info(pmx->dev, 2195 "padgroup %s %s\n", 2196 gemini_padgroups[i], 2197 enabled ? "enabled" : "disabled"); 2198 } 2199 } 2200 2201 tmp = grp->value; 2202 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2203 bool enabled = (i > 3); 2204 2205 /* Did not go high though it should */ 2206 if (!(after & BIT(i))) { 2207 dev_err(pmx->dev, 2208 "pin group %s could not be %s: " 2209 "probably a hardware limitation\n", 2210 gemini_padgroups[i], 2211 enabled ? "enabled" : "disabled"); 2212 dev_err(pmx->dev, 2213 "GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n", 2214 before, after, expected); 2215 } else { 2216 dev_info(pmx->dev, 2217 "padgroup %s %s\n", 2218 gemini_padgroups[i], 2219 enabled ? "enabled" : "disabled"); 2220 } 2221 } 2222 2223 return 0; 2224 } 2225 2226 static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 2227 { 2228 return ARRAY_SIZE(gemini_pmx_functions); 2229 } 2230 2231 static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev, 2232 unsigned int selector) 2233 { 2234 return gemini_pmx_functions[selector].name; 2235 } 2236 2237 static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev, 2238 unsigned int selector, 2239 const char * const **groups, 2240 unsigned int * const num_groups) 2241 { 2242 *groups = gemini_pmx_functions[selector].groups; 2243 *num_groups = gemini_pmx_functions[selector].num_groups; 2244 return 0; 2245 } 2246 2247 static const struct pinmux_ops gemini_pmx_ops = { 2248 .get_functions_count = gemini_pmx_get_funcs_count, 2249 .get_function_name = gemini_pmx_get_func_name, 2250 .get_function_groups = gemini_pmx_get_groups, 2251 .set_mux = gemini_pmx_set_mux, 2252 }; 2253 2254 static struct pinctrl_desc gemini_pmx_desc = { 2255 .name = DRIVER_NAME, 2256 .pctlops = &gemini_pctrl_ops, 2257 .pmxops = &gemini_pmx_ops, 2258 .owner = THIS_MODULE, 2259 }; 2260 2261 static int gemini_pmx_probe(struct platform_device *pdev) 2262 { 2263 struct gemini_pmx *pmx; 2264 struct regmap *map; 2265 struct device *dev = &pdev->dev; 2266 struct device *parent; 2267 unsigned long tmp; 2268 u32 val; 2269 int ret; 2270 int i; 2271 2272 /* Create state holders etc for this driver */ 2273 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 2274 if (!pmx) 2275 return -ENOMEM; 2276 2277 pmx->dev = &pdev->dev; 2278 parent = dev->parent; 2279 if (!parent) { 2280 dev_err(dev, "no parent to pin controller\n"); 2281 return -ENODEV; 2282 } 2283 map = syscon_node_to_regmap(parent->of_node); 2284 if (IS_ERR(map)) { 2285 dev_err(dev, "no syscon regmap\n"); 2286 return PTR_ERR(map); 2287 } 2288 pmx->map = map; 2289 2290 /* Check that regmap works at first call, then no more */ 2291 ret = regmap_read(map, GLOBAL_WORD_ID, &val); 2292 if (ret) { 2293 dev_err(dev, "cannot access regmap\n"); 2294 return ret; 2295 } 2296 val >>= 8; 2297 val &= 0xffff; 2298 if (val == 0x3512) { 2299 pmx->is_3512 = true; 2300 gemini_pmx_desc.pins = gemini_3512_pins; 2301 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); 2302 dev_info(dev, "detected 3512 chip variant\n"); 2303 } else if (val == 0x3516) { 2304 pmx->is_3516 = true; 2305 gemini_pmx_desc.pins = gemini_3516_pins; 2306 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); 2307 dev_info(dev, "detected 3516 chip variant\n"); 2308 } else { 2309 dev_err(dev, "unknown chip ID: %04x\n", val); 2310 return -ENODEV; 2311 } 2312 2313 ret = regmap_read(map, GLOBAL_MISC_CTRL, &val); 2314 dev_info(dev, "GLOBAL MISC CTRL at boot: 0x%08x\n", val); 2315 /* Mask off relevant pads */ 2316 val &= PADS_MASK; 2317 /* Invert the meaning of the DRAM+flash pads */ 2318 val ^= 0x0f; 2319 /* Print initial state */ 2320 tmp = val; 2321 for_each_set_bit(i, &tmp, PADS_MAXBIT) { 2322 dev_info(dev, "pad group %s %s\n", gemini_padgroups[i], 2323 (val & BIT(i)) ? "enabled" : "disabled"); 2324 } 2325 2326 /* Check if flash pin is set */ 2327 regmap_read(map, GLOBAL_STATUS, &val); 2328 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN); 2329 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set"); 2330 2331 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx); 2332 if (IS_ERR(pmx->pctl)) { 2333 dev_err(dev, "could not register pinmux driver\n"); 2334 return PTR_ERR(pmx->pctl); 2335 } 2336 2337 dev_info(dev, "initialized Gemini pin control driver\n"); 2338 2339 return 0; 2340 } 2341 2342 static const struct of_device_id gemini_pinctrl_match[] = { 2343 { .compatible = "cortina,gemini-pinctrl" }, 2344 {}, 2345 }; 2346 2347 static struct platform_driver gemini_pmx_driver = { 2348 .driver = { 2349 .name = DRIVER_NAME, 2350 .of_match_table = gemini_pinctrl_match, 2351 }, 2352 .probe = gemini_pmx_probe, 2353 }; 2354 2355 static int __init gemini_pmx_init(void) 2356 { 2357 return platform_driver_register(&gemini_pmx_driver); 2358 } 2359 arch_initcall(gemini_pmx_init); 2360