1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Cedar Fork PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2017, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #include <linux/pinctrl/pinctrl.h> 14 15 #include "pinctrl-intel.h" 16 17 #define CDF_PAD_OWN 0x020 18 #define CDF_PADCFGLOCK 0x0c0 19 #define CDF_HOSTSW_OWN 0x120 20 #define CDF_GPI_IS 0x200 21 #define CDF_GPI_IE 0x230 22 23 #define CDF_GPP(r, s, e) \ 24 { \ 25 .reg_num = (r), \ 26 .base = (s), \ 27 .size = ((e) - (s) + 1), \ 28 } 29 30 #define CDF_COMMUNITY(b, s, e, g) \ 31 { \ 32 .barno = (b), \ 33 .padown_offset = CDF_PAD_OWN, \ 34 .padcfglock_offset = CDF_PADCFGLOCK, \ 35 .hostown_offset = CDF_HOSTSW_OWN, \ 36 .is_offset = CDF_GPI_IS, \ 37 .ie_offset = CDF_GPI_IE, \ 38 .pin_base = (s), \ 39 .npins = ((e) - (s) + 1), \ 40 .gpps = (g), \ 41 .ngpps = ARRAY_SIZE(g), \ 42 } 43 44 /* Cedar Fork PCH */ 45 static const struct pinctrl_pin_desc cdf_pins[] = { 46 /* WEST2 */ 47 PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"), 48 PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"), 49 PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"), 50 PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"), 51 PINCTRL_PIN(4, "GBE0_I2C_CLK"), 52 PINCTRL_PIN(5, "GBE0_I2C_DATA"), 53 PINCTRL_PIN(6, "GBE1_I2C_CLK"), 54 PINCTRL_PIN(7, "GBE1_I2C_DATA"), 55 PINCTRL_PIN(8, "GBE2_I2C_CLK"), 56 PINCTRL_PIN(9, "GBE2_I2C_DATA"), 57 PINCTRL_PIN(10, "GBE3_I2C_CLK"), 58 PINCTRL_PIN(11, "GBE3_I2C_DATA"), 59 PINCTRL_PIN(12, "GBE0_LED0"), 60 PINCTRL_PIN(13, "GBE0_LED1"), 61 PINCTRL_PIN(14, "GBE0_LED2"), 62 PINCTRL_PIN(15, "GBE1_LED0"), 63 PINCTRL_PIN(16, "GBE1_LED1"), 64 PINCTRL_PIN(17, "GBE1_LED2"), 65 PINCTRL_PIN(18, "GBE2_LED0"), 66 PINCTRL_PIN(19, "GBE2_LED1"), 67 PINCTRL_PIN(20, "GBE2_LED2"), 68 PINCTRL_PIN(21, "GBE3_LED0"), 69 PINCTRL_PIN(22, "GBE3_LED1"), 70 PINCTRL_PIN(23, "GBE3_LED2"), 71 /* WEST3 */ 72 PINCTRL_PIN(24, "NCSI_RXD0"), 73 PINCTRL_PIN(25, "NCSI_CLK_IN"), 74 PINCTRL_PIN(26, "NCSI_RXD1"), 75 PINCTRL_PIN(27, "NCSI_CRS_DV"), 76 PINCTRL_PIN(28, "NCSI_ARB_IN"), 77 PINCTRL_PIN(29, "NCSI_TX_EN"), 78 PINCTRL_PIN(30, "NCSI_TXD0"), 79 PINCTRL_PIN(31, "NCSI_TXD1"), 80 PINCTRL_PIN(32, "NCSI_ARB_OUT"), 81 PINCTRL_PIN(33, "GBE_SMB_CLK"), 82 PINCTRL_PIN(34, "GBE_SMB_DATA"), 83 PINCTRL_PIN(35, "GBE_SMB_ALRT_N"), 84 PINCTRL_PIN(36, "THERMTRIP_N"), 85 PINCTRL_PIN(37, "PCHHOT_N"), 86 PINCTRL_PIN(38, "ERROR0_N"), 87 PINCTRL_PIN(39, "ERROR1_N"), 88 PINCTRL_PIN(40, "ERROR2_N"), 89 PINCTRL_PIN(41, "MSMI_N"), 90 PINCTRL_PIN(42, "CATERR_N"), 91 PINCTRL_PIN(43, "MEMTRIP_N"), 92 PINCTRL_PIN(44, "UART0_RXD"), 93 PINCTRL_PIN(45, "UART0_TXD"), 94 PINCTRL_PIN(46, "GBE_UART_RXD"), 95 PINCTRL_PIN(47, "GBE_UART_TXD"), 96 /* WEST01 */ 97 PINCTRL_PIN(48, "GBE_GPIO13"), 98 PINCTRL_PIN(49, "AUX_PWR"), 99 PINCTRL_PIN(50, "UART0_RTS"), 100 PINCTRL_PIN(51, "UART0_CTS"), 101 PINCTRL_PIN(52, "FAN_PWM_0"), 102 PINCTRL_PIN(53, "FAN_PWM_1"), 103 PINCTRL_PIN(54, "FAN_PWM_2"), 104 PINCTRL_PIN(55, "FAN_PWM_3"), 105 PINCTRL_PIN(56, "FAN_TACH_0"), 106 PINCTRL_PIN(57, "FAN_TACH_1"), 107 PINCTRL_PIN(58, "FAN_TACH_2"), 108 PINCTRL_PIN(59, "FAN_TACH_3"), 109 PINCTRL_PIN(60, "ME_SMB0_CLK"), 110 PINCTRL_PIN(61, "ME_SMB0_DATA"), 111 PINCTRL_PIN(62, "ME_SMB0_ALRT_N"), 112 PINCTRL_PIN(63, "ME_SMB1_CLK"), 113 PINCTRL_PIN(64, "ME_SMB1_DATA"), 114 PINCTRL_PIN(65, "ME_SMB1_ALRT_N"), 115 PINCTRL_PIN(66, "ME_SMB2_CLK"), 116 PINCTRL_PIN(67, "ME_SMB2_DATA"), 117 PINCTRL_PIN(68, "ME_SMB2_ALRT_N"), 118 PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"), 119 PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"), 120 /* WEST5 */ 121 PINCTRL_PIN(71, "IE_UART_RXD"), 122 PINCTRL_PIN(72, "IE_UART_TXD"), 123 PINCTRL_PIN(73, "VPP_SMB_CLK"), 124 PINCTRL_PIN(74, "VPP_SMB_DATA"), 125 PINCTRL_PIN(75, "VPP_SMB_ALRT_N"), 126 PINCTRL_PIN(76, "PCIE_CLKREQ0_N"), 127 PINCTRL_PIN(77, "PCIE_CLKREQ1_N"), 128 PINCTRL_PIN(78, "PCIE_CLKREQ2_N"), 129 PINCTRL_PIN(79, "PCIE_CLKREQ3_N"), 130 PINCTRL_PIN(80, "PCIE_CLKREQ4_N"), 131 PINCTRL_PIN(81, "PCIE_CLKREQ5_N"), 132 PINCTRL_PIN(82, "PCIE_CLKREQ6_N"), 133 PINCTRL_PIN(83, "PCIE_CLKREQ7_N"), 134 PINCTRL_PIN(84, "PCIE_CLKREQ8_N"), 135 PINCTRL_PIN(85, "PCIE_CLKREQ9_N"), 136 PINCTRL_PIN(86, "FLEX_CLK_SE0"), 137 PINCTRL_PIN(87, "FLEX_CLK_SE1"), 138 PINCTRL_PIN(88, "FLEX_CLK1_50"), 139 PINCTRL_PIN(89, "FLEX_CLK2_50"), 140 PINCTRL_PIN(90, "FLEX_CLK_125"), 141 /* WESTC */ 142 PINCTRL_PIN(91, "TCK_PCH"), 143 PINCTRL_PIN(92, "JTAGX_PCH"), 144 PINCTRL_PIN(93, "TRST_N_PCH"), 145 PINCTRL_PIN(94, "TMS_PCH"), 146 PINCTRL_PIN(95, "TDI_PCH"), 147 PINCTRL_PIN(96, "TDO_PCH"), 148 /* WESTC_DFX */ 149 PINCTRL_PIN(97, "CX_PRDY_N"), 150 PINCTRL_PIN(98, "CX_PREQ_N"), 151 PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"), 152 PINCTRL_PIN(100, "TRIGGER0_N"), 153 PINCTRL_PIN(101, "TRIGGER1_N"), 154 /* WESTA */ 155 PINCTRL_PIN(102, "DBG_PTI_CLK0"), 156 PINCTRL_PIN(103, "DBG_PTI_CLK3"), 157 PINCTRL_PIN(104, "DBG_PTI_DATA0"), 158 PINCTRL_PIN(105, "DBG_PTI_DATA1"), 159 PINCTRL_PIN(106, "DBG_PTI_DATA2"), 160 PINCTRL_PIN(107, "DBG_PTI_DATA3"), 161 PINCTRL_PIN(108, "DBG_PTI_DATA4"), 162 PINCTRL_PIN(109, "DBG_PTI_DATA5"), 163 PINCTRL_PIN(110, "DBG_PTI_DATA6"), 164 PINCTRL_PIN(111, "DBG_PTI_DATA7"), 165 /* WESTB */ 166 PINCTRL_PIN(112, "DBG_PTI_DATA8"), 167 PINCTRL_PIN(113, "DBG_PTI_DATA9"), 168 PINCTRL_PIN(114, "DBG_PTI_DATA10"), 169 PINCTRL_PIN(115, "DBG_PTI_DATA11"), 170 PINCTRL_PIN(116, "DBG_PTI_DATA12"), 171 PINCTRL_PIN(117, "DBG_PTI_DATA13"), 172 PINCTRL_PIN(118, "DBG_PTI_DATA14"), 173 PINCTRL_PIN(119, "DBG_PTI_DATA15"), 174 PINCTRL_PIN(120, "DBG_SPARE0"), 175 PINCTRL_PIN(121, "DBG_SPARE1"), 176 PINCTRL_PIN(122, "DBG_SPARE2"), 177 PINCTRL_PIN(123, "DBG_SPARE3"), 178 /* WESTD */ 179 PINCTRL_PIN(124, "CPU_PWR_GOOD"), 180 PINCTRL_PIN(125, "PLTRST_CPU_N"), 181 PINCTRL_PIN(126, "NAC_RESET_NAC_N"), 182 PINCTRL_PIN(127, "PCH_SBLINK_RX"), 183 PINCTRL_PIN(128, "PCH_SBLINK_TX"), 184 PINCTRL_PIN(129, "PMSYNC_CLK"), 185 PINCTRL_PIN(130, "CPU_ERR0_N"), 186 PINCTRL_PIN(131, "CPU_ERR1_N"), 187 PINCTRL_PIN(132, "CPU_ERR2_N"), 188 PINCTRL_PIN(133, "CPU_THERMTRIP_N"), 189 PINCTRL_PIN(134, "CPU_MSMI_N"), 190 PINCTRL_PIN(135, "CPU_CATERR_N"), 191 PINCTRL_PIN(136, "CPU_MEMTRIP_N"), 192 PINCTRL_PIN(137, "NAC_GR_N"), 193 PINCTRL_PIN(138, "NAC_XTAL_VALID"), 194 PINCTRL_PIN(139, "NAC_WAKE_N"), 195 PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"), 196 PINCTRL_PIN(141, "NAC_SBLINK_N2S"), 197 PINCTRL_PIN(142, "NAC_SBLINK_S2N"), 198 PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"), 199 /* WESTD_PECI */ 200 PINCTRL_PIN(144, "ME_PECI"), 201 /* WESTF */ 202 PINCTRL_PIN(145, "NAC_RMII_CLK"), 203 PINCTRL_PIN(146, "NAC_RGMII_CLK"), 204 PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"), 205 PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"), 206 PINCTRL_PIN(149, "NAC_SPARE2"), 207 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"), 208 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"), 209 PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"), 210 PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"), 211 PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"), 212 PINCTRL_PIN(155, "NAC_NCSI_RXD0"), 213 PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"), 214 PINCTRL_PIN(157, "NAC_NCSI_RXD1"), 215 PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"), 216 PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"), 217 PINCTRL_PIN(160, "NAC_NCSI_TX_EN"), 218 PINCTRL_PIN(161, "NAC_NCSI_TXD0"), 219 PINCTRL_PIN(162, "NAC_NCSI_TXD1"), 220 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"), 221 PINCTRL_PIN(164, "NAC_NCSI_OE_N"), 222 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"), 223 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"), 224 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"), 225 /* EAST2 */ 226 PINCTRL_PIN(168, "USB_OC0_N"), 227 PINCTRL_PIN(169, "GBE_GPIO0"), 228 PINCTRL_PIN(170, "GBE_GPIO1"), 229 PINCTRL_PIN(171, "GBE_GPIO2"), 230 PINCTRL_PIN(172, "GBE_GPIO3"), 231 PINCTRL_PIN(173, "GBE_GPIO4"), 232 PINCTRL_PIN(174, "GBE_GPIO5"), 233 PINCTRL_PIN(175, "GBE_GPIO6"), 234 PINCTRL_PIN(176, "GBE_GPIO7"), 235 PINCTRL_PIN(177, "SPI_TPM_CS_N"), 236 PINCTRL_PIN(178, "GBE_GPIO9"), 237 PINCTRL_PIN(179, "GBE_GPIO10"), 238 PINCTRL_PIN(180, "GBE_GPIO11"), 239 PINCTRL_PIN(181, "GBE_GPIO12"), 240 PINCTRL_PIN(182, "PECI_SMB_DATA"), 241 PINCTRL_PIN(183, "SATA0_LED_N"), 242 PINCTRL_PIN(184, "SATA1_LED_N"), 243 PINCTRL_PIN(185, "SATA_PDETECT0"), 244 PINCTRL_PIN(186, "SATA_PDETECT1"), 245 PINCTRL_PIN(187, "SATA0_SDOUT"), 246 PINCTRL_PIN(188, "SATA1_SDOUT"), 247 PINCTRL_PIN(189, "SATA2_LED_N"), 248 PINCTRL_PIN(190, "SATA_PDETECT2"), 249 PINCTRL_PIN(191, "SATA2_SDOUT"), 250 /* EAST3 */ 251 PINCTRL_PIN(192, "ESPI_IO0"), 252 PINCTRL_PIN(193, "ESPI_IO1"), 253 PINCTRL_PIN(194, "ESPI_IO2"), 254 PINCTRL_PIN(195, "ESPI_IO3"), 255 PINCTRL_PIN(196, "ESPI_CLK"), 256 PINCTRL_PIN(197, "ESPI_RST_N"), 257 PINCTRL_PIN(198, "ESPI_CS0_N"), 258 PINCTRL_PIN(199, "ESPI_ALRT0_N"), 259 PINCTRL_PIN(200, "ESPI_CS1_N"), 260 PINCTRL_PIN(201, "ESPI_ALRT1_N"), 261 PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"), 262 /* EAST0 */ 263 PINCTRL_PIN(203, "SPI_CS0_N"), 264 PINCTRL_PIN(204, "SPI_CS1_N"), 265 PINCTRL_PIN(205, "SPI_MOSI_IO0"), 266 PINCTRL_PIN(206, "SPI_MISO_IO1"), 267 PINCTRL_PIN(207, "SPI_IO2"), 268 PINCTRL_PIN(208, "SPI_IO3"), 269 PINCTRL_PIN(209, "SPI_CLK"), 270 PINCTRL_PIN(210, "SPI_CLK_LOOPBK"), 271 PINCTRL_PIN(211, "SUSPWRDNACK"), 272 PINCTRL_PIN(212, "PMU_SUSCLK"), 273 PINCTRL_PIN(213, "ADR_COMPLETE"), 274 PINCTRL_PIN(214, "ADR_TRIGGER_N"), 275 PINCTRL_PIN(215, "PMU_SLP_S45_N"), 276 PINCTRL_PIN(216, "PMU_SLP_S3_N"), 277 PINCTRL_PIN(217, "PMU_WAKE_N"), 278 PINCTRL_PIN(218, "PMU_PWRBTN_N"), 279 PINCTRL_PIN(219, "PMU_RESETBUTTON_N"), 280 PINCTRL_PIN(220, "PMU_PLTRST_N"), 281 PINCTRL_PIN(221, "SUS_STAT_N"), 282 PINCTRL_PIN(222, "PMU_I2C_CLK"), 283 PINCTRL_PIN(223, "PMU_I2C_DATA"), 284 PINCTRL_PIN(224, "PECI_SMB_CLK"), 285 PINCTRL_PIN(225, "PECI_SMB_ALRT_N"), 286 /* EMMC */ 287 PINCTRL_PIN(226, "EMMC_CMD"), 288 PINCTRL_PIN(227, "EMMC_STROBE"), 289 PINCTRL_PIN(228, "EMMC_CLK"), 290 PINCTRL_PIN(229, "EMMC_D0"), 291 PINCTRL_PIN(230, "EMMC_D1"), 292 PINCTRL_PIN(231, "EMMC_D2"), 293 PINCTRL_PIN(232, "EMMC_D3"), 294 PINCTRL_PIN(233, "EMMC_D4"), 295 PINCTRL_PIN(234, "EMMC_D5"), 296 PINCTRL_PIN(235, "EMMC_D6"), 297 PINCTRL_PIN(236, "EMMC_D7"), 298 }; 299 300 static const struct intel_padgroup cdf_community0_gpps[] = { 301 CDF_GPP(0, 0, 23), /* WEST2 */ 302 CDF_GPP(1, 24, 47), /* WEST3 */ 303 CDF_GPP(2, 48, 70), /* WEST01 */ 304 CDF_GPP(3, 71, 90), /* WEST5 */ 305 CDF_GPP(4, 91, 96), /* WESTC */ 306 CDF_GPP(5, 97, 101), /* WESTC_DFX */ 307 CDF_GPP(6, 102, 111), /* WESTA */ 308 CDF_GPP(7, 112, 123), /* WESTB */ 309 CDF_GPP(8, 124, 143), /* WESTD */ 310 CDF_GPP(9, 144, 144), /* WESTD_PECI */ 311 CDF_GPP(10, 145, 167), /* WESTF */ 312 }; 313 314 static const struct intel_padgroup cdf_community1_gpps[] = { 315 CDF_GPP(0, 168, 191), /* EAST2 */ 316 CDF_GPP(1, 192, 202), /* EAST3 */ 317 CDF_GPP(2, 203, 225), /* EAST0 */ 318 CDF_GPP(3, 226, 236), /* EMMC */ 319 }; 320 321 static const struct intel_community cdf_communities[] = { 322 CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */ 323 CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */ 324 }; 325 326 static const struct intel_pinctrl_soc_data cdf_soc_data = { 327 .pins = cdf_pins, 328 .npins = ARRAY_SIZE(cdf_pins), 329 .communities = cdf_communities, 330 .ncommunities = ARRAY_SIZE(cdf_communities), 331 }; 332 333 static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops); 334 335 static const struct acpi_device_id cdf_pinctrl_acpi_match[] = { 336 { "INTC3001", (kernel_ulong_t)&cdf_soc_data }, 337 { } 338 }; 339 MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match); 340 341 static struct platform_driver cdf_pinctrl_driver = { 342 .probe = intel_pinctrl_probe_by_hid, 343 .driver = { 344 .name = "cedarfork-pinctrl", 345 .acpi_match_table = cdf_pinctrl_acpi_match, 346 .pm = &cdf_pinctrl_pm_ops, 347 }, 348 }; 349 350 static int __init cdf_pinctrl_init(void) 351 { 352 return platform_driver_register(&cdf_pinctrl_driver); 353 } 354 subsys_initcall(cdf_pinctrl_init); 355 356 static void __exit cdf_pinctrl_exit(void) 357 { 358 platform_driver_unregister(&cdf_pinctrl_driver); 359 } 360 module_exit(cdf_pinctrl_exit); 361 362 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 363 MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver"); 364 MODULE_LICENSE("GPL v2"); 365