1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lochnagar pin and GPIO control 4 * 5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 * 8 * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9 */ 10 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinconf-generic.h> 22 23 #include <linux/mfd/lochnagar.h> 24 #include <linux/mfd/lochnagar1_regs.h> 25 #include <linux/mfd/lochnagar2_regs.h> 26 27 #include <dt-bindings/pinctrl/lochnagar.h> 28 29 #include "../pinctrl-utils.h" 30 31 #define LN2_NUM_GPIO_CHANNELS 16 32 33 #define LN_CDC_AIF1_STR "codec-aif1" 34 #define LN_CDC_AIF2_STR "codec-aif2" 35 #define LN_CDC_AIF3_STR "codec-aif3" 36 #define LN_DSP_AIF1_STR "dsp-aif1" 37 #define LN_DSP_AIF2_STR "dsp-aif2" 38 #define LN_PSIA1_STR "psia1" 39 #define LN_PSIA2_STR "psia2" 40 #define LN_GF_AIF1_STR "gf-aif1" 41 #define LN_GF_AIF2_STR "gf-aif2" 42 #define LN_GF_AIF3_STR "gf-aif3" 43 #define LN_GF_AIF4_STR "gf-aif4" 44 #define LN_SPDIF_AIF_STR "spdif-aif" 45 #define LN_USB_AIF1_STR "usb-aif1" 46 #define LN_USB_AIF2_STR "usb-aif2" 47 #define LN_ADAT_AIF_STR "adat-aif" 48 #define LN_SOUNDCARD_AIF_STR "soundcard-aif" 49 50 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \ 51 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \ 52 .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \ 53 .shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \ 54 } 55 56 #define LN_PIN_SAIF(REV, ID, NAME) \ 57 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \ 58 { .name = NAME, .type = LN_PTYPE_AIF, } 59 60 #define LN_PIN_AIF(REV, ID) \ 61 LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \ 62 LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \ 63 LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \ 64 LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat") 65 66 #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ 67 LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT) 68 69 #define LN1_PIN_MUX(ID, NAME) \ 70 static const struct lochnagar_pin lochnagar1_##ID##_pin = \ 71 { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, } 72 73 #define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID) 74 75 #define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \ 76 LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT) 77 78 #define LN2_PIN_MUX(ID, NAME) \ 79 static const struct lochnagar_pin lochnagar2_##ID##_pin = \ 80 { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, } 81 82 #define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID) 83 84 #define LN2_PIN_GAI(ID) \ 85 LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \ 86 LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \ 87 LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \ 88 LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat") 89 90 #define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \ 91 .number = LOCHNAGAR##REV##_PIN_##ID, \ 92 .name = lochnagar##REV##_##ID##_pin.name, \ 93 .drv_data = (void *)&lochnagar##REV##_##ID##_pin, \ 94 } 95 96 #define LN1_PIN(ID) LN_PIN(1, ID) 97 #define LN2_PIN(ID) LN_PIN(2, ID) 98 99 #define LN_PINS(REV, ID) \ 100 LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \ 101 LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT) 102 103 #define LN1_PINS(ID) LN_PINS(1, ID) 104 #define LN2_PINS(ID) LN_PINS(2, ID) 105 106 enum { 107 LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS, 108 LOCHNAGAR1_PIN_GF_GPIO3, 109 LOCHNAGAR1_PIN_GF_GPIO7, 110 LOCHNAGAR1_PIN_LED1, 111 LOCHNAGAR1_PIN_LED2, 112 LOCHNAGAR1_PIN_CDC_AIF1_BCLK, 113 LOCHNAGAR1_PIN_CDC_AIF1_LRCLK, 114 LOCHNAGAR1_PIN_CDC_AIF1_RXDAT, 115 LOCHNAGAR1_PIN_CDC_AIF1_TXDAT, 116 LOCHNAGAR1_PIN_CDC_AIF2_BCLK, 117 LOCHNAGAR1_PIN_CDC_AIF2_LRCLK, 118 LOCHNAGAR1_PIN_CDC_AIF2_RXDAT, 119 LOCHNAGAR1_PIN_CDC_AIF2_TXDAT, 120 LOCHNAGAR1_PIN_CDC_AIF3_BCLK, 121 LOCHNAGAR1_PIN_CDC_AIF3_LRCLK, 122 LOCHNAGAR1_PIN_CDC_AIF3_RXDAT, 123 LOCHNAGAR1_PIN_CDC_AIF3_TXDAT, 124 LOCHNAGAR1_PIN_DSP_AIF1_BCLK, 125 LOCHNAGAR1_PIN_DSP_AIF1_LRCLK, 126 LOCHNAGAR1_PIN_DSP_AIF1_RXDAT, 127 LOCHNAGAR1_PIN_DSP_AIF1_TXDAT, 128 LOCHNAGAR1_PIN_DSP_AIF2_BCLK, 129 LOCHNAGAR1_PIN_DSP_AIF2_LRCLK, 130 LOCHNAGAR1_PIN_DSP_AIF2_RXDAT, 131 LOCHNAGAR1_PIN_DSP_AIF2_TXDAT, 132 LOCHNAGAR1_PIN_PSIA1_BCLK, 133 LOCHNAGAR1_PIN_PSIA1_LRCLK, 134 LOCHNAGAR1_PIN_PSIA1_RXDAT, 135 LOCHNAGAR1_PIN_PSIA1_TXDAT, 136 LOCHNAGAR1_PIN_PSIA2_BCLK, 137 LOCHNAGAR1_PIN_PSIA2_LRCLK, 138 LOCHNAGAR1_PIN_PSIA2_RXDAT, 139 LOCHNAGAR1_PIN_PSIA2_TXDAT, 140 LOCHNAGAR1_PIN_SPDIF_AIF_BCLK, 141 LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK, 142 LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT, 143 LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT, 144 LOCHNAGAR1_PIN_GF_AIF3_BCLK, 145 LOCHNAGAR1_PIN_GF_AIF3_RXDAT, 146 LOCHNAGAR1_PIN_GF_AIF3_LRCLK, 147 LOCHNAGAR1_PIN_GF_AIF3_TXDAT, 148 LOCHNAGAR1_PIN_GF_AIF4_BCLK, 149 LOCHNAGAR1_PIN_GF_AIF4_RXDAT, 150 LOCHNAGAR1_PIN_GF_AIF4_LRCLK, 151 LOCHNAGAR1_PIN_GF_AIF4_TXDAT, 152 LOCHNAGAR1_PIN_GF_AIF1_BCLK, 153 LOCHNAGAR1_PIN_GF_AIF1_RXDAT, 154 LOCHNAGAR1_PIN_GF_AIF1_LRCLK, 155 LOCHNAGAR1_PIN_GF_AIF1_TXDAT, 156 LOCHNAGAR1_PIN_GF_AIF2_BCLK, 157 LOCHNAGAR1_PIN_GF_AIF2_RXDAT, 158 LOCHNAGAR1_PIN_GF_AIF2_LRCLK, 159 LOCHNAGAR1_PIN_GF_AIF2_TXDAT, 160 161 LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS, 162 LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK, 163 LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT, 164 LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT, 165 LOCHNAGAR2_PIN_USB_AIF1_BCLK, 166 LOCHNAGAR2_PIN_USB_AIF1_LRCLK, 167 LOCHNAGAR2_PIN_USB_AIF1_RXDAT, 168 LOCHNAGAR2_PIN_USB_AIF1_TXDAT, 169 LOCHNAGAR2_PIN_USB_AIF2_BCLK, 170 LOCHNAGAR2_PIN_USB_AIF2_LRCLK, 171 LOCHNAGAR2_PIN_USB_AIF2_RXDAT, 172 LOCHNAGAR2_PIN_USB_AIF2_TXDAT, 173 LOCHNAGAR2_PIN_ADAT_AIF_BCLK, 174 LOCHNAGAR2_PIN_ADAT_AIF_LRCLK, 175 LOCHNAGAR2_PIN_ADAT_AIF_RXDAT, 176 LOCHNAGAR2_PIN_ADAT_AIF_TXDAT, 177 LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK, 178 LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK, 179 LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT, 180 LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT, 181 }; 182 183 enum lochnagar_pin_type { 184 LN_PTYPE_GPIO, 185 LN_PTYPE_MUX, 186 LN_PTYPE_AIF, 187 LN_PTYPE_COUNT, 188 }; 189 190 struct lochnagar_pin { 191 const char name[20]; 192 193 enum lochnagar_pin_type type; 194 195 unsigned int reg; 196 int shift; 197 bool invert; 198 }; 199 200 LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1); 201 LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1); 202 LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0); 203 LN1_PIN_MUX(GF_GPIO2, "gf-gpio2"); 204 LN1_PIN_MUX(GF_GPIO3, "gf-gpio3"); 205 LN1_PIN_MUX(GF_GPIO7, "gf-gpio7"); 206 LN1_PIN_MUX(LED1, "led1"); 207 LN1_PIN_MUX(LED2, "led2"); 208 LN1_PIN_AIF(CDC_AIF1); 209 LN1_PIN_AIF(CDC_AIF2); 210 LN1_PIN_AIF(CDC_AIF3); 211 LN1_PIN_AIF(DSP_AIF1); 212 LN1_PIN_AIF(DSP_AIF2); 213 LN1_PIN_AIF(PSIA1); 214 LN1_PIN_AIF(PSIA2); 215 LN1_PIN_AIF(SPDIF_AIF); 216 LN1_PIN_AIF(GF_AIF1); 217 LN1_PIN_AIF(GF_AIF2); 218 LN1_PIN_AIF(GF_AIF3); 219 LN1_PIN_AIF(GF_AIF4); 220 221 LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1); 222 LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1); 223 LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0); 224 LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0); 225 LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0); 226 LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1); 227 LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1"); 228 LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2"); 229 LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3"); 230 LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4"); 231 LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5"); 232 LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6"); 233 LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1"); 234 LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2"); 235 LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3"); 236 LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4"); 237 LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5"); 238 LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6"); 239 LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7"); 240 LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8"); 241 LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1"); 242 LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2"); 243 LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3"); 244 LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4"); 245 LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5"); 246 LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6"); 247 LN2_PIN_MUX(GF_GPIO2, "gf-gpio2"); 248 LN2_PIN_MUX(GF_GPIO3, "gf-gpio3"); 249 LN2_PIN_MUX(GF_GPIO7, "gf-gpio7"); 250 LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx"); 251 LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx"); 252 LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx"); 253 LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx"); 254 LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx"); 255 LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx"); 256 LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx"); 257 LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1"); 258 LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1"); 259 LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2"); 260 LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2"); 261 LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1"); 262 LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1"); 263 LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2"); 264 LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2"); 265 LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3"); 266 LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3"); 267 LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4"); 268 LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4"); 269 LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1"); 270 LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1"); 271 LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2"); 272 LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2"); 273 LN2_PIN_MUX(I2C2_SCL, "i2c2-scl"); 274 LN2_PIN_MUX(I2C2_SDA, "i2c2-sda"); 275 LN2_PIN_MUX(I2C3_SCL, "i2c3-scl"); 276 LN2_PIN_MUX(I2C3_SDA, "i2c3-sda"); 277 LN2_PIN_MUX(I2C4_SCL, "i2c4-scl"); 278 LN2_PIN_MUX(I2C4_SDA, "i2c4-sda"); 279 LN2_PIN_MUX(DSP_STANDBY, "dsp-standby"); 280 LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1"); 281 LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2"); 282 LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin"); 283 LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk"); 284 LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk"); 285 LN2_PIN_MUX(GF_GPIO1, "gf-gpio1"); 286 LN2_PIN_MUX(GF_GPIO5, "gf-gpio5"); 287 LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20"); 288 LN2_PIN_GAI(CDC_AIF1); 289 LN2_PIN_GAI(CDC_AIF2); 290 LN2_PIN_GAI(CDC_AIF3); 291 LN2_PIN_GAI(DSP_AIF1); 292 LN2_PIN_GAI(DSP_AIF2); 293 LN2_PIN_GAI(PSIA1); 294 LN2_PIN_GAI(PSIA2); 295 LN2_PIN_GAI(GF_AIF1); 296 LN2_PIN_GAI(GF_AIF2); 297 LN2_PIN_GAI(GF_AIF3); 298 LN2_PIN_GAI(GF_AIF4); 299 LN2_PIN_AIF(SPDIF_AIF); 300 LN2_PIN_AIF(USB_AIF1); 301 LN2_PIN_AIF(USB_AIF2); 302 LN2_PIN_AIF(ADAT_AIF); 303 LN2_PIN_AIF(SOUNDCARD_AIF); 304 305 static const struct pinctrl_pin_desc lochnagar1_pins[] = { 306 LN1_PIN(CDC_RESET), LN1_PIN(DSP_RESET), LN1_PIN(CDC_CIF1MODE), 307 LN1_PIN(GF_GPIO2), LN1_PIN(GF_GPIO3), LN1_PIN(GF_GPIO7), 308 LN1_PIN(LED1), LN1_PIN(LED2), 309 LN1_PINS(CDC_AIF1), LN1_PINS(CDC_AIF2), LN1_PINS(CDC_AIF3), 310 LN1_PINS(DSP_AIF1), LN1_PINS(DSP_AIF2), 311 LN1_PINS(PSIA1), LN1_PINS(PSIA2), 312 LN1_PINS(SPDIF_AIF), 313 LN1_PINS(GF_AIF1), LN1_PINS(GF_AIF2), 314 LN1_PINS(GF_AIF3), LN1_PINS(GF_AIF4), 315 }; 316 317 static const struct pinctrl_pin_desc lochnagar2_pins[] = { 318 LN2_PIN(CDC_RESET), LN2_PIN(DSP_RESET), LN2_PIN(CDC_CIF1MODE), 319 LN2_PIN(CDC_LDOENA), 320 LN2_PIN(SPDIF_HWMODE), LN2_PIN(SPDIF_RESET), 321 LN2_PIN(FPGA_GPIO1), LN2_PIN(FPGA_GPIO2), LN2_PIN(FPGA_GPIO3), 322 LN2_PIN(FPGA_GPIO4), LN2_PIN(FPGA_GPIO5), LN2_PIN(FPGA_GPIO6), 323 LN2_PIN(CDC_GPIO1), LN2_PIN(CDC_GPIO2), LN2_PIN(CDC_GPIO3), 324 LN2_PIN(CDC_GPIO4), LN2_PIN(CDC_GPIO5), LN2_PIN(CDC_GPIO6), 325 LN2_PIN(CDC_GPIO7), LN2_PIN(CDC_GPIO8), 326 LN2_PIN(DSP_GPIO1), LN2_PIN(DSP_GPIO2), LN2_PIN(DSP_GPIO3), 327 LN2_PIN(DSP_GPIO4), LN2_PIN(DSP_GPIO5), LN2_PIN(DSP_GPIO6), 328 LN2_PIN(DSP_GPIO20), 329 LN2_PIN(GF_GPIO1), LN2_PIN(GF_GPIO2), LN2_PIN(GF_GPIO3), 330 LN2_PIN(GF_GPIO5), LN2_PIN(GF_GPIO7), 331 LN2_PINS(CDC_AIF1), LN2_PINS(CDC_AIF2), LN2_PINS(CDC_AIF3), 332 LN2_PINS(DSP_AIF1), LN2_PINS(DSP_AIF2), 333 LN2_PINS(PSIA1), LN2_PINS(PSIA2), 334 LN2_PINS(GF_AIF1), LN2_PINS(GF_AIF2), 335 LN2_PINS(GF_AIF3), LN2_PINS(GF_AIF4), 336 LN2_PIN(DSP_UART1_RX), LN2_PIN(DSP_UART1_TX), 337 LN2_PIN(DSP_UART2_RX), LN2_PIN(DSP_UART2_TX), 338 LN2_PIN(GF_UART2_RX), LN2_PIN(GF_UART2_TX), 339 LN2_PIN(USB_UART_RX), 340 LN2_PIN(CDC_PDMCLK1), LN2_PIN(CDC_PDMDAT1), 341 LN2_PIN(CDC_PDMCLK2), LN2_PIN(CDC_PDMDAT2), 342 LN2_PIN(CDC_DMICCLK1), LN2_PIN(CDC_DMICDAT1), 343 LN2_PIN(CDC_DMICCLK2), LN2_PIN(CDC_DMICDAT2), 344 LN2_PIN(CDC_DMICCLK3), LN2_PIN(CDC_DMICDAT3), 345 LN2_PIN(CDC_DMICCLK4), LN2_PIN(CDC_DMICDAT4), 346 LN2_PIN(DSP_DMICCLK1), LN2_PIN(DSP_DMICDAT1), 347 LN2_PIN(DSP_DMICCLK2), LN2_PIN(DSP_DMICDAT2), 348 LN2_PIN(I2C2_SCL), LN2_PIN(I2C2_SDA), 349 LN2_PIN(I2C3_SCL), LN2_PIN(I2C3_SDA), 350 LN2_PIN(I2C4_SCL), LN2_PIN(I2C4_SDA), 351 LN2_PIN(DSP_STANDBY), 352 LN2_PIN(CDC_MCLK1), LN2_PIN(CDC_MCLK2), 353 LN2_PIN(DSP_CLKIN), 354 LN2_PIN(PSIA1_MCLK), LN2_PIN(PSIA2_MCLK), 355 LN2_PINS(SPDIF_AIF), 356 LN2_PINS(USB_AIF1), LN2_PINS(USB_AIF2), 357 LN2_PINS(ADAT_AIF), 358 LN2_PINS(SOUNDCARD_AIF), 359 }; 360 361 #define LN_AIF_PINS(REV, ID) \ 362 LOCHNAGAR##REV##_PIN_##ID##_BCLK, \ 363 LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \ 364 LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \ 365 LOCHNAGAR##REV##_PIN_##ID##_RXDAT, 366 367 #define LN1_AIF(ID, CTRL) \ 368 static const struct lochnagar_aif lochnagar1_##ID##_aif = { \ 369 .name = LN_##ID##_STR, \ 370 .pins = { LN_AIF_PINS(1, ID) }, \ 371 .src_reg = LOCHNAGAR1_##ID##_SEL, \ 372 .src_mask = LOCHNAGAR1_SRC_MASK, \ 373 .ctrl_reg = LOCHNAGAR1_##CTRL, \ 374 .ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \ 375 .master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \ 376 LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \ 377 } 378 379 #define LN2_AIF(ID) \ 380 static const struct lochnagar_aif lochnagar2_##ID##_aif = { \ 381 .name = LN_##ID##_STR, \ 382 .pins = { LN_AIF_PINS(2, ID) }, \ 383 .src_reg = LOCHNAGAR2_##ID##_CTRL, \ 384 .src_mask = LOCHNAGAR2_AIF_SRC_MASK, \ 385 .ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \ 386 .ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \ 387 .master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \ 388 LOCHNAGAR2_AIF_BCLK_DIR_MASK, \ 389 } 390 391 struct lochnagar_aif { 392 const char name[16]; 393 394 unsigned int pins[4]; 395 396 u16 src_reg; 397 u16 src_mask; 398 399 u16 ctrl_reg; 400 u16 ena_mask; 401 u16 master_mask; 402 }; 403 404 LN1_AIF(CDC_AIF1, CDC_AIF_CTRL1); 405 LN1_AIF(CDC_AIF2, CDC_AIF_CTRL1); 406 LN1_AIF(CDC_AIF3, CDC_AIF_CTRL2); 407 LN1_AIF(DSP_AIF1, DSP_AIF); 408 LN1_AIF(DSP_AIF2, DSP_AIF); 409 LN1_AIF(PSIA1, PSIA_AIF); 410 LN1_AIF(PSIA2, PSIA_AIF); 411 LN1_AIF(GF_AIF1, GF_AIF1); 412 LN1_AIF(GF_AIF2, GF_AIF2); 413 LN1_AIF(GF_AIF3, GF_AIF1); 414 LN1_AIF(GF_AIF4, GF_AIF2); 415 LN1_AIF(SPDIF_AIF, EXT_AIF_CTRL); 416 417 LN2_AIF(CDC_AIF1); 418 LN2_AIF(CDC_AIF2); 419 LN2_AIF(CDC_AIF3); 420 LN2_AIF(DSP_AIF1); 421 LN2_AIF(DSP_AIF2); 422 LN2_AIF(PSIA1); 423 LN2_AIF(PSIA2); 424 LN2_AIF(GF_AIF1); 425 LN2_AIF(GF_AIF2); 426 LN2_AIF(GF_AIF3); 427 LN2_AIF(GF_AIF4); 428 LN2_AIF(SPDIF_AIF); 429 LN2_AIF(USB_AIF1); 430 LN2_AIF(USB_AIF2); 431 LN2_AIF(ADAT_AIF); 432 LN2_AIF(SOUNDCARD_AIF); 433 434 #define LN2_OP_AIF 0x00 435 #define LN2_OP_GPIO 0xFE 436 437 #define LN_FUNC(NAME, TYPE, OP) \ 438 { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP } 439 440 #define LN_FUNC_PIN(REV, ID, OP) \ 441 LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP) 442 443 #define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP) 444 #define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP) 445 446 #define LN_FUNC_AIF(REV, ID, OP) \ 447 LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP) 448 449 #define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP) 450 #define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP) 451 452 #define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \ 453 LN2_FUNC_AIF(ID, OP), \ 454 LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \ 455 LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \ 456 LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \ 457 LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP) 458 459 enum lochnagar_func_type { 460 LN_FTYPE_PIN, 461 LN_FTYPE_AIF, 462 LN_FTYPE_COUNT, 463 }; 464 465 struct lochnagar_func { 466 const char * const name; 467 468 enum lochnagar_func_type type; 469 470 u8 op; 471 }; 472 473 static const struct lochnagar_func lochnagar1_funcs[] = { 474 LN_FUNC("dsp-gpio1", PIN, 0x01), 475 LN_FUNC("dsp-gpio2", PIN, 0x02), 476 LN_FUNC("dsp-gpio3", PIN, 0x03), 477 LN_FUNC("codec-gpio1", PIN, 0x04), 478 LN_FUNC("codec-gpio2", PIN, 0x05), 479 LN_FUNC("codec-gpio3", PIN, 0x06), 480 LN_FUNC("codec-gpio4", PIN, 0x07), 481 LN_FUNC("codec-gpio5", PIN, 0x08), 482 LN_FUNC("codec-gpio6", PIN, 0x09), 483 LN_FUNC("codec-gpio7", PIN, 0x0A), 484 LN_FUNC("codec-gpio8", PIN, 0x0B), 485 LN1_FUNC_PIN(GF_GPIO2, 0x0C), 486 LN1_FUNC_PIN(GF_GPIO3, 0x0D), 487 LN1_FUNC_PIN(GF_GPIO7, 0x0E), 488 489 LN1_FUNC_AIF(SPDIF_AIF, 0x01), 490 LN1_FUNC_AIF(PSIA1, 0x02), 491 LN1_FUNC_AIF(PSIA2, 0x03), 492 LN1_FUNC_AIF(CDC_AIF1, 0x04), 493 LN1_FUNC_AIF(CDC_AIF2, 0x05), 494 LN1_FUNC_AIF(CDC_AIF3, 0x06), 495 LN1_FUNC_AIF(DSP_AIF1, 0x07), 496 LN1_FUNC_AIF(DSP_AIF2, 0x08), 497 LN1_FUNC_AIF(GF_AIF3, 0x09), 498 LN1_FUNC_AIF(GF_AIF4, 0x0A), 499 LN1_FUNC_AIF(GF_AIF1, 0x0B), 500 LN1_FUNC_AIF(GF_AIF2, 0x0C), 501 }; 502 503 static const struct lochnagar_func lochnagar2_funcs[] = { 504 LN_FUNC("aif", PIN, LN2_OP_AIF), 505 LN2_FUNC_PIN(FPGA_GPIO1, 0x01), 506 LN2_FUNC_PIN(FPGA_GPIO2, 0x02), 507 LN2_FUNC_PIN(FPGA_GPIO3, 0x03), 508 LN2_FUNC_PIN(FPGA_GPIO4, 0x04), 509 LN2_FUNC_PIN(FPGA_GPIO5, 0x05), 510 LN2_FUNC_PIN(FPGA_GPIO6, 0x06), 511 LN2_FUNC_PIN(CDC_GPIO1, 0x07), 512 LN2_FUNC_PIN(CDC_GPIO2, 0x08), 513 LN2_FUNC_PIN(CDC_GPIO3, 0x09), 514 LN2_FUNC_PIN(CDC_GPIO4, 0x0A), 515 LN2_FUNC_PIN(CDC_GPIO5, 0x0B), 516 LN2_FUNC_PIN(CDC_GPIO6, 0x0C), 517 LN2_FUNC_PIN(CDC_GPIO7, 0x0D), 518 LN2_FUNC_PIN(CDC_GPIO8, 0x0E), 519 LN2_FUNC_PIN(DSP_GPIO1, 0x0F), 520 LN2_FUNC_PIN(DSP_GPIO2, 0x10), 521 LN2_FUNC_PIN(DSP_GPIO3, 0x11), 522 LN2_FUNC_PIN(DSP_GPIO4, 0x12), 523 LN2_FUNC_PIN(DSP_GPIO5, 0x13), 524 LN2_FUNC_PIN(DSP_GPIO6, 0x14), 525 LN2_FUNC_PIN(GF_GPIO2, 0x15), 526 LN2_FUNC_PIN(GF_GPIO3, 0x16), 527 LN2_FUNC_PIN(GF_GPIO7, 0x17), 528 LN2_FUNC_PIN(GF_GPIO1, 0x18), 529 LN2_FUNC_PIN(GF_GPIO5, 0x19), 530 LN2_FUNC_PIN(DSP_GPIO20, 0x1A), 531 LN_FUNC("codec-clkout", PIN, 0x20), 532 LN_FUNC("dsp-clkout", PIN, 0x21), 533 LN_FUNC("pmic-32k", PIN, 0x22), 534 LN_FUNC("spdif-clkout", PIN, 0x23), 535 LN_FUNC("clk-12m288", PIN, 0x24), 536 LN_FUNC("clk-11m2986", PIN, 0x25), 537 LN_FUNC("clk-24m576", PIN, 0x26), 538 LN_FUNC("clk-22m5792", PIN, 0x27), 539 LN_FUNC("xmos-mclk", PIN, 0x29), 540 LN_FUNC("gf-clkout1", PIN, 0x2A), 541 LN_FUNC("gf-mclk1", PIN, 0x2B), 542 LN_FUNC("gf-mclk3", PIN, 0x2C), 543 LN_FUNC("gf-mclk2", PIN, 0x2D), 544 LN_FUNC("gf-clkout2", PIN, 0x2E), 545 LN2_FUNC_PIN(CDC_MCLK1, 0x2F), 546 LN2_FUNC_PIN(CDC_MCLK2, 0x30), 547 LN2_FUNC_PIN(DSP_CLKIN, 0x31), 548 LN2_FUNC_PIN(PSIA1_MCLK, 0x32), 549 LN2_FUNC_PIN(PSIA2_MCLK, 0x33), 550 LN_FUNC("spdif-mclk", PIN, 0x34), 551 LN_FUNC("codec-irq", PIN, 0x42), 552 LN2_FUNC_PIN(CDC_RESET, 0x43), 553 LN2_FUNC_PIN(DSP_RESET, 0x44), 554 LN_FUNC("dsp-irq", PIN, 0x45), 555 LN2_FUNC_PIN(DSP_STANDBY, 0x46), 556 LN2_FUNC_PIN(CDC_PDMCLK1, 0x90), 557 LN2_FUNC_PIN(CDC_PDMDAT1, 0x91), 558 LN2_FUNC_PIN(CDC_PDMCLK2, 0x92), 559 LN2_FUNC_PIN(CDC_PDMDAT2, 0x93), 560 LN2_FUNC_PIN(CDC_DMICCLK1, 0xA0), 561 LN2_FUNC_PIN(CDC_DMICDAT1, 0xA1), 562 LN2_FUNC_PIN(CDC_DMICCLK2, 0xA2), 563 LN2_FUNC_PIN(CDC_DMICDAT2, 0xA3), 564 LN2_FUNC_PIN(CDC_DMICCLK3, 0xA4), 565 LN2_FUNC_PIN(CDC_DMICDAT3, 0xA5), 566 LN2_FUNC_PIN(CDC_DMICCLK4, 0xA6), 567 LN2_FUNC_PIN(CDC_DMICDAT4, 0xA7), 568 LN2_FUNC_PIN(DSP_DMICCLK1, 0xA8), 569 LN2_FUNC_PIN(DSP_DMICDAT1, 0xA9), 570 LN2_FUNC_PIN(DSP_DMICCLK2, 0xAA), 571 LN2_FUNC_PIN(DSP_DMICDAT2, 0xAB), 572 LN2_FUNC_PIN(DSP_UART1_RX, 0xC0), 573 LN2_FUNC_PIN(DSP_UART1_TX, 0xC1), 574 LN2_FUNC_PIN(DSP_UART2_RX, 0xC2), 575 LN2_FUNC_PIN(DSP_UART2_TX, 0xC3), 576 LN2_FUNC_PIN(GF_UART2_RX, 0xC4), 577 LN2_FUNC_PIN(GF_UART2_TX, 0xC5), 578 LN2_FUNC_PIN(USB_UART_RX, 0xC6), 579 LN_FUNC("usb-uart-tx", PIN, 0xC7), 580 LN2_FUNC_PIN(I2C2_SCL, 0xE0), 581 LN2_FUNC_PIN(I2C2_SDA, 0xE1), 582 LN2_FUNC_PIN(I2C3_SCL, 0xE2), 583 LN2_FUNC_PIN(I2C3_SDA, 0xE3), 584 LN2_FUNC_PIN(I2C4_SCL, 0xE4), 585 LN2_FUNC_PIN(I2C4_SDA, 0xE5), 586 587 LN2_FUNC_AIF(SPDIF_AIF, 0x01), 588 LN2_FUNC_GAI(PSIA1, 0x02, 0x50, 0x51, 0x52, 0x53), 589 LN2_FUNC_GAI(PSIA2, 0x03, 0x54, 0x55, 0x56, 0x57), 590 LN2_FUNC_GAI(CDC_AIF1, 0x04, 0x59, 0x5B, 0x5A, 0x58), 591 LN2_FUNC_GAI(CDC_AIF2, 0x05, 0x5D, 0x5F, 0x5E, 0x5C), 592 LN2_FUNC_GAI(CDC_AIF3, 0x06, 0x61, 0x62, 0x63, 0x60), 593 LN2_FUNC_GAI(DSP_AIF1, 0x07, 0x65, 0x67, 0x66, 0x64), 594 LN2_FUNC_GAI(DSP_AIF2, 0x08, 0x69, 0x6B, 0x6A, 0x68), 595 LN2_FUNC_GAI(GF_AIF3, 0x09, 0x6D, 0x6F, 0x6C, 0x6E), 596 LN2_FUNC_GAI(GF_AIF4, 0x0A, 0x71, 0x73, 0x70, 0x72), 597 LN2_FUNC_GAI(GF_AIF1, 0x0B, 0x75, 0x77, 0x74, 0x76), 598 LN2_FUNC_GAI(GF_AIF2, 0x0C, 0x79, 0x7B, 0x78, 0x7A), 599 LN2_FUNC_AIF(USB_AIF1, 0x0D), 600 LN2_FUNC_AIF(USB_AIF2, 0x0E), 601 LN2_FUNC_AIF(ADAT_AIF, 0x0F), 602 LN2_FUNC_AIF(SOUNDCARD_AIF, 0x10), 603 }; 604 605 #define LN_GROUP_PIN(REV, ID) { \ 606 .name = lochnagar##REV##_##ID##_pin.name, \ 607 .type = LN_FTYPE_PIN, \ 608 .pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \ 609 .npins = 1, \ 610 .priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \ 611 } 612 613 #define LN_GROUP_AIF(REV, ID) { \ 614 .name = lochnagar##REV##_##ID##_aif.name, \ 615 .type = LN_FTYPE_AIF, \ 616 .pins = lochnagar##REV##_##ID##_aif.pins, \ 617 .npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \ 618 .priv = &lochnagar##REV##_##ID##_aif, \ 619 } 620 621 #define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID) 622 #define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID) 623 624 #define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID) 625 #define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID) 626 627 #define LN2_GROUP_GAI(ID) \ 628 LN2_GROUP_AIF(ID), \ 629 LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \ 630 LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT) 631 632 struct lochnagar_group { 633 const char * const name; 634 635 enum lochnagar_func_type type; 636 637 const unsigned int *pins; 638 unsigned int npins; 639 640 const void *priv; 641 }; 642 643 static const struct lochnagar_group lochnagar1_groups[] = { 644 LN1_GROUP_PIN(GF_GPIO2), LN1_GROUP_PIN(GF_GPIO3), 645 LN1_GROUP_PIN(GF_GPIO7), 646 LN1_GROUP_PIN(LED1), LN1_GROUP_PIN(LED2), 647 LN1_GROUP_AIF(CDC_AIF1), LN1_GROUP_AIF(CDC_AIF2), 648 LN1_GROUP_AIF(CDC_AIF3), 649 LN1_GROUP_AIF(DSP_AIF1), LN1_GROUP_AIF(DSP_AIF2), 650 LN1_GROUP_AIF(PSIA1), LN1_GROUP_AIF(PSIA2), 651 LN1_GROUP_AIF(GF_AIF1), LN1_GROUP_AIF(GF_AIF2), 652 LN1_GROUP_AIF(GF_AIF3), LN1_GROUP_AIF(GF_AIF4), 653 LN1_GROUP_AIF(SPDIF_AIF), 654 }; 655 656 static const struct lochnagar_group lochnagar2_groups[] = { 657 LN2_GROUP_PIN(FPGA_GPIO1), LN2_GROUP_PIN(FPGA_GPIO2), 658 LN2_GROUP_PIN(FPGA_GPIO3), LN2_GROUP_PIN(FPGA_GPIO4), 659 LN2_GROUP_PIN(FPGA_GPIO5), LN2_GROUP_PIN(FPGA_GPIO6), 660 LN2_GROUP_PIN(CDC_GPIO1), LN2_GROUP_PIN(CDC_GPIO2), 661 LN2_GROUP_PIN(CDC_GPIO3), LN2_GROUP_PIN(CDC_GPIO4), 662 LN2_GROUP_PIN(CDC_GPIO5), LN2_GROUP_PIN(CDC_GPIO6), 663 LN2_GROUP_PIN(CDC_GPIO7), LN2_GROUP_PIN(CDC_GPIO8), 664 LN2_GROUP_PIN(DSP_GPIO1), LN2_GROUP_PIN(DSP_GPIO2), 665 LN2_GROUP_PIN(DSP_GPIO3), LN2_GROUP_PIN(DSP_GPIO4), 666 LN2_GROUP_PIN(DSP_GPIO5), LN2_GROUP_PIN(DSP_GPIO6), 667 LN2_GROUP_PIN(DSP_GPIO20), 668 LN2_GROUP_PIN(GF_GPIO1), 669 LN2_GROUP_PIN(GF_GPIO2), LN2_GROUP_PIN(GF_GPIO5), 670 LN2_GROUP_PIN(GF_GPIO3), LN2_GROUP_PIN(GF_GPIO7), 671 LN2_GROUP_PIN(DSP_UART1_RX), LN2_GROUP_PIN(DSP_UART1_TX), 672 LN2_GROUP_PIN(DSP_UART2_RX), LN2_GROUP_PIN(DSP_UART2_TX), 673 LN2_GROUP_PIN(GF_UART2_RX), LN2_GROUP_PIN(GF_UART2_TX), 674 LN2_GROUP_PIN(USB_UART_RX), 675 LN2_GROUP_PIN(CDC_PDMCLK1), LN2_GROUP_PIN(CDC_PDMDAT1), 676 LN2_GROUP_PIN(CDC_PDMCLK2), LN2_GROUP_PIN(CDC_PDMDAT2), 677 LN2_GROUP_PIN(CDC_DMICCLK1), LN2_GROUP_PIN(CDC_DMICDAT1), 678 LN2_GROUP_PIN(CDC_DMICCLK2), LN2_GROUP_PIN(CDC_DMICDAT2), 679 LN2_GROUP_PIN(CDC_DMICCLK3), LN2_GROUP_PIN(CDC_DMICDAT3), 680 LN2_GROUP_PIN(CDC_DMICCLK4), LN2_GROUP_PIN(CDC_DMICDAT4), 681 LN2_GROUP_PIN(DSP_DMICCLK1), LN2_GROUP_PIN(DSP_DMICDAT1), 682 LN2_GROUP_PIN(DSP_DMICCLK2), LN2_GROUP_PIN(DSP_DMICDAT2), 683 LN2_GROUP_PIN(I2C2_SCL), LN2_GROUP_PIN(I2C2_SDA), 684 LN2_GROUP_PIN(I2C3_SCL), LN2_GROUP_PIN(I2C3_SDA), 685 LN2_GROUP_PIN(I2C4_SCL), LN2_GROUP_PIN(I2C4_SDA), 686 LN2_GROUP_PIN(DSP_STANDBY), 687 LN2_GROUP_PIN(CDC_MCLK1), LN2_GROUP_PIN(CDC_MCLK2), 688 LN2_GROUP_PIN(DSP_CLKIN), 689 LN2_GROUP_PIN(PSIA1_MCLK), LN2_GROUP_PIN(PSIA2_MCLK), 690 LN2_GROUP_GAI(CDC_AIF1), LN2_GROUP_GAI(CDC_AIF2), 691 LN2_GROUP_GAI(CDC_AIF3), 692 LN2_GROUP_GAI(DSP_AIF1), LN2_GROUP_GAI(DSP_AIF2), 693 LN2_GROUP_GAI(PSIA1), LN2_GROUP_GAI(PSIA2), 694 LN2_GROUP_GAI(GF_AIF1), LN2_GROUP_GAI(GF_AIF2), 695 LN2_GROUP_GAI(GF_AIF3), LN2_GROUP_GAI(GF_AIF4), 696 LN2_GROUP_AIF(SPDIF_AIF), 697 LN2_GROUP_AIF(USB_AIF1), LN2_GROUP_AIF(USB_AIF2), 698 LN2_GROUP_AIF(ADAT_AIF), 699 LN2_GROUP_AIF(SOUNDCARD_AIF), 700 }; 701 702 struct lochnagar_func_groups { 703 const char **groups; 704 unsigned int ngroups; 705 }; 706 707 struct lochnagar_pin_priv { 708 struct lochnagar *lochnagar; 709 struct device *dev; 710 711 const struct lochnagar_func *funcs; 712 unsigned int nfuncs; 713 714 const struct pinctrl_pin_desc *pins; 715 unsigned int npins; 716 717 const struct lochnagar_group *groups; 718 unsigned int ngroups; 719 720 struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT]; 721 722 struct gpio_chip gpio_chip; 723 }; 724 725 static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev) 726 { 727 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 728 729 return priv->ngroups; 730 } 731 732 static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev, 733 unsigned int group_idx) 734 { 735 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 736 737 return priv->groups[group_idx].name; 738 } 739 740 static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev, 741 unsigned int group_idx, 742 const unsigned int **pins, 743 unsigned int *num_pins) 744 { 745 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 746 747 *pins = priv->groups[group_idx].pins; 748 *num_pins = priv->groups[group_idx].npins; 749 750 return 0; 751 } 752 753 static const struct pinctrl_ops lochnagar_pin_group_ops = { 754 .get_groups_count = lochnagar_get_groups_count, 755 .get_group_name = lochnagar_get_group_name, 756 .get_group_pins = lochnagar_get_group_pins, 757 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 758 .dt_free_map = pinctrl_utils_free_map, 759 }; 760 761 static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev) 762 { 763 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 764 765 return priv->nfuncs; 766 } 767 768 static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev, 769 unsigned int func_idx) 770 { 771 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 772 773 return priv->funcs[func_idx].name; 774 } 775 776 static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev, 777 unsigned int func_idx, 778 const char * const **groups, 779 unsigned int * const num_groups) 780 { 781 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 782 int func_type; 783 784 func_type = priv->funcs[func_idx].type; 785 786 *groups = priv->func_groups[func_type].groups; 787 *num_groups = priv->func_groups[func_type].ngroups; 788 789 return 0; 790 } 791 792 static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv, 793 unsigned int op) 794 { 795 struct regmap *regmap = priv->lochnagar->regmap; 796 unsigned int val; 797 int free = -1; 798 int i, ret; 799 800 for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) { 801 ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val); 802 if (ret) 803 return ret; 804 805 val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK; 806 807 if (val == op) 808 return i + 1; 809 810 if (free < 0 && !val) 811 free = i; 812 } 813 814 if (free >= 0) { 815 ret = regmap_update_bits(regmap, 816 LOCHNAGAR2_GPIO_CHANNEL1 + free, 817 LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op); 818 if (ret) 819 return ret; 820 821 free++; 822 823 dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op); 824 825 return free; 826 } 827 828 return -ENOSPC; 829 } 830 831 static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv, 832 const struct lochnagar_pin *pin, 833 unsigned int op) 834 { 835 int ret; 836 837 switch (priv->lochnagar->type) { 838 case LOCHNAGAR1: 839 break; 840 default: 841 ret = lochnagar2_get_gpio_chan(priv, op); 842 if (ret < 0) { 843 dev_err(priv->dev, "Failed to get channel for %s: %d\n", 844 pin->name, ret); 845 return ret; 846 } 847 848 op = ret; 849 break; 850 } 851 852 dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op); 853 854 ret = regmap_write(priv->lochnagar->regmap, pin->reg, op); 855 if (ret) 856 dev_err(priv->dev, "Failed to set %s mux: %d\n", 857 pin->name, ret); 858 859 return 0; 860 } 861 862 static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv, 863 const struct lochnagar_group *group, 864 unsigned int op) 865 { 866 struct regmap *regmap = priv->lochnagar->regmap; 867 const struct lochnagar_aif *aif = group->priv; 868 const struct lochnagar_pin *pin; 869 int i, ret; 870 871 ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op); 872 if (ret) { 873 dev_err(priv->dev, "Failed to set %s source: %d\n", 874 group->name, ret); 875 return ret; 876 } 877 878 ret = regmap_update_bits(regmap, aif->ctrl_reg, 879 aif->ena_mask, aif->ena_mask); 880 if (ret) { 881 dev_err(priv->dev, "Failed to set %s enable: %d\n", 882 group->name, ret); 883 return ret; 884 } 885 886 for (i = 0; i < group->npins; i++) { 887 pin = priv->pins[group->pins[i]].drv_data; 888 889 if (pin->type != LN_PTYPE_MUX) 890 continue; 891 892 dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name); 893 894 ret = regmap_update_bits(regmap, pin->reg, 895 LOCHNAGAR2_GPIO_SRC_MASK, 896 LN2_OP_AIF); 897 if (ret) { 898 dev_err(priv->dev, "Failed to set %s to AIF: %d\n", 899 pin->name, ret); 900 return ret; 901 } 902 } 903 904 return 0; 905 } 906 907 static int lochnagar_set_mux(struct pinctrl_dev *pctldev, 908 unsigned int func_idx, unsigned int group_idx) 909 { 910 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 911 const struct lochnagar_func *func = &priv->funcs[func_idx]; 912 const struct lochnagar_group *group = &priv->groups[group_idx]; 913 const struct lochnagar_pin *pin; 914 915 switch (func->type) { 916 case LN_FTYPE_AIF: 917 dev_dbg(priv->dev, "Set group %s to %s\n", 918 group->name, func->name); 919 920 return lochnagar_aif_set_mux(priv, group, func->op); 921 case LN_FTYPE_PIN: 922 pin = priv->pins[*group->pins].drv_data; 923 924 dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name); 925 926 return lochnagar_pin_set_mux(priv, pin, func->op); 927 default: 928 return -EINVAL; 929 } 930 } 931 932 static int lochnagar_gpio_request(struct pinctrl_dev *pctldev, 933 struct pinctrl_gpio_range *range, 934 unsigned int offset) 935 { 936 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 937 struct lochnagar *lochnagar = priv->lochnagar; 938 const struct lochnagar_pin *pin = priv->pins[offset].drv_data; 939 int ret; 940 941 dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name); 942 943 if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX) 944 return 0; 945 946 ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO); 947 if (ret < 0) { 948 dev_err(priv->dev, "Failed to get low channel: %d\n", ret); 949 return ret; 950 } 951 952 ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1); 953 if (ret < 0) { 954 dev_err(priv->dev, "Failed to get high channel: %d\n", ret); 955 return ret; 956 } 957 958 return 0; 959 } 960 961 static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev, 962 struct pinctrl_gpio_range *range, 963 unsigned int offset, 964 bool input) 965 { 966 /* The GPIOs only support output */ 967 if (input) 968 return -EINVAL; 969 970 return 0; 971 } 972 973 static const struct pinmux_ops lochnagar_pin_mux_ops = { 974 .get_functions_count = lochnagar_get_funcs_count, 975 .get_function_name = lochnagar_get_func_name, 976 .get_function_groups = lochnagar_get_func_groups, 977 .set_mux = lochnagar_set_mux, 978 979 .gpio_request_enable = lochnagar_gpio_request, 980 .gpio_set_direction = lochnagar_gpio_set_direction, 981 982 .strict = true, 983 }; 984 985 static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv, 986 unsigned int group_idx, bool master) 987 { 988 struct regmap *regmap = priv->lochnagar->regmap; 989 const struct lochnagar_group *group = &priv->groups[group_idx]; 990 const struct lochnagar_aif *aif = group->priv; 991 unsigned int val = 0; 992 int ret; 993 994 if (group->type != LN_FTYPE_AIF) 995 return -EINVAL; 996 997 if (!master) 998 val = aif->master_mask; 999 1000 dev_dbg(priv->dev, "Set AIF %s to %s\n", 1001 group->name, master ? "master" : "slave"); 1002 1003 ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val); 1004 if (ret) { 1005 dev_err(priv->dev, "Failed to set %s mode: %d\n", 1006 group->name, ret); 1007 return ret; 1008 } 1009 1010 return 0; 1011 } 1012 1013 static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev, 1014 unsigned int group_idx, 1015 unsigned long *configs, 1016 unsigned int num_configs) 1017 { 1018 struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev); 1019 int i, ret; 1020 1021 for (i = 0; i < num_configs; i++) { 1022 unsigned int param = pinconf_to_config_param(*configs); 1023 1024 switch (param) { 1025 case PIN_CONFIG_OUTPUT_ENABLE: 1026 ret = lochnagar_aif_set_master(priv, group_idx, true); 1027 if (ret) 1028 return ret; 1029 break; 1030 case PIN_CONFIG_INPUT_ENABLE: 1031 ret = lochnagar_aif_set_master(priv, group_idx, false); 1032 if (ret) 1033 return ret; 1034 break; 1035 default: 1036 return -ENOTSUPP; 1037 } 1038 1039 configs++; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static const struct pinconf_ops lochnagar_pin_conf_ops = { 1046 .pin_config_group_set = lochnagar_conf_group_set, 1047 }; 1048 1049 static const struct pinctrl_desc lochnagar_pin_desc = { 1050 .name = "lochnagar-pinctrl", 1051 .owner = THIS_MODULE, 1052 1053 .pctlops = &lochnagar_pin_group_ops, 1054 .pmxops = &lochnagar_pin_mux_ops, 1055 .confops = &lochnagar_pin_conf_ops, 1056 }; 1057 1058 static void lochnagar_gpio_set(struct gpio_chip *chip, 1059 unsigned int offset, int value) 1060 { 1061 struct lochnagar_pin_priv *priv = gpiochip_get_data(chip); 1062 struct lochnagar *lochnagar = priv->lochnagar; 1063 const struct lochnagar_pin *pin = priv->pins[offset].drv_data; 1064 int ret; 1065 1066 value = !!value; 1067 1068 dev_dbg(priv->dev, "Set GPIO %s to %s\n", 1069 pin->name, value ? "high" : "low"); 1070 1071 switch (pin->type) { 1072 case LN_PTYPE_MUX: 1073 value |= LN2_OP_GPIO; 1074 1075 ret = lochnagar_pin_set_mux(priv, pin, value); 1076 break; 1077 case LN_PTYPE_GPIO: 1078 if (pin->invert) 1079 value = !value; 1080 1081 ret = regmap_update_bits(lochnagar->regmap, pin->reg, 1082 BIT(pin->shift), value << pin->shift); 1083 break; 1084 default: 1085 ret = -EINVAL; 1086 break; 1087 } 1088 1089 if (ret < 0) 1090 dev_err(chip->parent, "Failed to set %s value: %d\n", 1091 pin->name, ret); 1092 } 1093 1094 static int lochnagar_gpio_direction_out(struct gpio_chip *chip, 1095 unsigned int offset, int value) 1096 { 1097 lochnagar_gpio_set(chip, offset, value); 1098 1099 return pinctrl_gpio_direction_output(chip->base + offset); 1100 } 1101 1102 static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv) 1103 { 1104 struct lochnagar_func_groups *funcs; 1105 int i; 1106 1107 for (i = 0; i < priv->ngroups; i++) 1108 priv->func_groups[priv->groups[i].type].ngroups++; 1109 1110 for (i = 0; i < LN_FTYPE_COUNT; i++) { 1111 funcs = &priv->func_groups[i]; 1112 1113 if (!funcs->ngroups) 1114 continue; 1115 1116 funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups, 1117 sizeof(*funcs->groups), 1118 GFP_KERNEL); 1119 if (!funcs->groups) 1120 return -ENOMEM; 1121 1122 funcs->ngroups = 0; 1123 } 1124 1125 for (i = 0; i < priv->ngroups; i++) { 1126 funcs = &priv->func_groups[priv->groups[i].type]; 1127 1128 funcs->groups[funcs->ngroups++] = priv->groups[i].name; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int lochnagar_pin_probe(struct platform_device *pdev) 1135 { 1136 struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent); 1137 struct lochnagar_pin_priv *priv; 1138 struct pinctrl_desc *desc; 1139 struct pinctrl_dev *pctl; 1140 struct device *dev = &pdev->dev; 1141 int ret; 1142 1143 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1144 if (!priv) 1145 return -ENOMEM; 1146 1147 priv->dev = dev; 1148 priv->lochnagar = lochnagar; 1149 1150 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 1151 if (!desc) 1152 return -ENOMEM; 1153 1154 *desc = lochnagar_pin_desc; 1155 1156 priv->gpio_chip.label = dev_name(dev); 1157 priv->gpio_chip.request = gpiochip_generic_request; 1158 priv->gpio_chip.free = gpiochip_generic_free; 1159 priv->gpio_chip.direction_output = lochnagar_gpio_direction_out; 1160 priv->gpio_chip.set = lochnagar_gpio_set; 1161 priv->gpio_chip.can_sleep = true; 1162 priv->gpio_chip.parent = dev; 1163 priv->gpio_chip.base = -1; 1164 #ifdef CONFIG_OF_GPIO 1165 priv->gpio_chip.of_node = dev->of_node; 1166 #endif 1167 1168 switch (lochnagar->type) { 1169 case LOCHNAGAR1: 1170 priv->funcs = lochnagar1_funcs; 1171 priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs); 1172 priv->pins = lochnagar1_pins; 1173 priv->npins = ARRAY_SIZE(lochnagar1_pins); 1174 priv->groups = lochnagar1_groups; 1175 priv->ngroups = ARRAY_SIZE(lochnagar1_groups); 1176 1177 priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS; 1178 break; 1179 case LOCHNAGAR2: 1180 priv->funcs = lochnagar2_funcs; 1181 priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs); 1182 priv->pins = lochnagar2_pins; 1183 priv->npins = ARRAY_SIZE(lochnagar2_pins); 1184 priv->groups = lochnagar2_groups; 1185 priv->ngroups = ARRAY_SIZE(lochnagar2_groups); 1186 1187 priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS; 1188 break; 1189 default: 1190 dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type); 1191 return -EINVAL; 1192 } 1193 1194 ret = lochnagar_fill_func_groups(priv); 1195 if (ret < 0) 1196 return ret; 1197 1198 desc->pins = priv->pins; 1199 desc->npins = priv->npins; 1200 1201 pctl = devm_pinctrl_register(dev, desc, priv); 1202 if (IS_ERR(pctl)) { 1203 ret = PTR_ERR(pctl); 1204 dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret); 1205 return ret; 1206 } 1207 1208 ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv); 1209 if (ret < 0) { 1210 dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret); 1211 return ret; 1212 } 1213 1214 return 0; 1215 } 1216 1217 static const struct of_device_id lochnagar_of_match[] = { 1218 { .compatible = "cirrus,lochnagar-pinctrl" }, 1219 {} 1220 }; 1221 MODULE_DEVICE_TABLE(of, lochnagar_of_match); 1222 1223 static struct platform_driver lochnagar_pin_driver = { 1224 .driver = { 1225 .name = "lochnagar-pinctrl", 1226 .of_match_table = of_match_ptr(lochnagar_of_match), 1227 }, 1228 1229 .probe = lochnagar_pin_probe, 1230 }; 1231 module_platform_driver(lochnagar_pin_driver); 1232 1233 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); 1234 MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board"); 1235 MODULE_LICENSE("GPL v2"); 1236