1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2012 Intel Corporation. All rights reserved. 8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * BSD LICENSE 15 * 16 * Copyright(c) 2012 Intel Corporation. All rights reserved. 17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 23 * * Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * * Redistributions in binary form must reproduce the above copy 26 * notice, this list of conditions and the following disclaimer in 27 * the documentation and/or other materials provided with the 28 * distribution. 29 * * Neither the name of Intel Corporation nor the names of its 30 * contributors may be used to endorse or promote products derived 31 * from this software without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 44 * 45 * Intel PCIe NTB Linux driver 46 * 47 * Contact Information: 48 * Jon Mason <jon.mason@intel.com> 49 */ 50 51 #ifndef NTB_HW_INTEL_H 52 #define NTB_HW_INTEL_H 53 54 #include <linux/ntb.h> 55 #include <linux/pci.h> 56 57 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 58 #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 59 #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 60 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D 61 #define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E 62 #define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F 63 #define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D 64 #define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E 65 #define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F 66 #define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D 67 #define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E 68 #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F 69 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D 70 #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E 71 #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F 72 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C 73 74 /* Intel Xeon hardware */ 75 76 #define XEON_PBAR23LMT_OFFSET 0x0000 77 #define XEON_PBAR45LMT_OFFSET 0x0008 78 #define XEON_PBAR4LMT_OFFSET 0x0008 79 #define XEON_PBAR5LMT_OFFSET 0x000c 80 #define XEON_PBAR23XLAT_OFFSET 0x0010 81 #define XEON_PBAR45XLAT_OFFSET 0x0018 82 #define XEON_PBAR4XLAT_OFFSET 0x0018 83 #define XEON_PBAR5XLAT_OFFSET 0x001c 84 #define XEON_SBAR23LMT_OFFSET 0x0020 85 #define XEON_SBAR45LMT_OFFSET 0x0028 86 #define XEON_SBAR4LMT_OFFSET 0x0028 87 #define XEON_SBAR5LMT_OFFSET 0x002c 88 #define XEON_SBAR23XLAT_OFFSET 0x0030 89 #define XEON_SBAR45XLAT_OFFSET 0x0038 90 #define XEON_SBAR4XLAT_OFFSET 0x0038 91 #define XEON_SBAR5XLAT_OFFSET 0x003c 92 #define XEON_SBAR0BASE_OFFSET 0x0040 93 #define XEON_SBAR23BASE_OFFSET 0x0048 94 #define XEON_SBAR45BASE_OFFSET 0x0050 95 #define XEON_SBAR4BASE_OFFSET 0x0050 96 #define XEON_SBAR5BASE_OFFSET 0x0054 97 #define XEON_SBDF_OFFSET 0x005c 98 #define XEON_NTBCNTL_OFFSET 0x0058 99 #define XEON_PDOORBELL_OFFSET 0x0060 100 #define XEON_PDBMSK_OFFSET 0x0062 101 #define XEON_SDOORBELL_OFFSET 0x0064 102 #define XEON_SDBMSK_OFFSET 0x0066 103 #define XEON_USMEMMISS_OFFSET 0x0070 104 #define XEON_SPAD_OFFSET 0x0080 105 #define XEON_PBAR23SZ_OFFSET 0x00d0 106 #define XEON_PBAR45SZ_OFFSET 0x00d1 107 #define XEON_PBAR4SZ_OFFSET 0x00d1 108 #define XEON_SBAR23SZ_OFFSET 0x00d2 109 #define XEON_SBAR45SZ_OFFSET 0x00d3 110 #define XEON_SBAR4SZ_OFFSET 0x00d3 111 #define XEON_PPD_OFFSET 0x00d4 112 #define XEON_PBAR5SZ_OFFSET 0x00d5 113 #define XEON_SBAR5SZ_OFFSET 0x00d6 114 #define XEON_WCCNTRL_OFFSET 0x00e0 115 #define XEON_UNCERRSTS_OFFSET 0x014c 116 #define XEON_CORERRSTS_OFFSET 0x0158 117 #define XEON_LINK_STATUS_OFFSET 0x01a2 118 #define XEON_SPCICMD_OFFSET 0x0504 119 #define XEON_DEVCTRL_OFFSET 0x0598 120 #define XEON_DEVSTS_OFFSET 0x059a 121 #define XEON_SLINK_STATUS_OFFSET 0x05a2 122 #define XEON_B2B_SPAD_OFFSET 0x0100 123 #define XEON_B2B_DOORBELL_OFFSET 0x0140 124 #define XEON_B2B_XLAT_OFFSETL 0x0144 125 #define XEON_B2B_XLAT_OFFSETU 0x0148 126 #define XEON_PPD_CONN_MASK 0x03 127 #define XEON_PPD_CONN_TRANSPARENT 0x00 128 #define XEON_PPD_CONN_B2B 0x01 129 #define XEON_PPD_CONN_RP 0x02 130 #define XEON_PPD_DEV_MASK 0x10 131 #define XEON_PPD_DEV_USD 0x00 132 #define XEON_PPD_DEV_DSD 0x10 133 #define XEON_PPD_SPLIT_BAR_MASK 0x40 134 135 #define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK) 136 #define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD) 137 #define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD) 138 #define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD) 139 #define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD) 140 #define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD) 141 #define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD) 142 143 #define XEON_MW_COUNT 2 144 #define HSX_SPLIT_BAR_MW_COUNT 3 145 #define XEON_DB_COUNT 15 146 #define XEON_DB_LINK 15 147 #define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK) 148 #define XEON_DB_MSIX_VECTOR_COUNT 4 149 #define XEON_DB_MSIX_VECTOR_SHIFT 5 150 #define XEON_DB_TOTAL_SHIFT 16 151 #define XEON_SPAD_COUNT 16 152 153 /* Intel Skylake Xeon hardware */ 154 #define SKX_IMBAR1SZ_OFFSET 0x00d0 155 #define SKX_IMBAR2SZ_OFFSET 0x00d1 156 #define SKX_EMBAR1SZ_OFFSET 0x00d2 157 #define SKX_EMBAR2SZ_OFFSET 0x00d3 158 #define SKX_DEVCTRL_OFFSET 0x0098 159 #define SKX_DEVSTS_OFFSET 0x009a 160 #define SKX_UNCERRSTS_OFFSET 0x014c 161 #define SKX_CORERRSTS_OFFSET 0x0158 162 #define SKX_LINK_STATUS_OFFSET 0x01a2 163 164 #define SKX_NTBCNTL_OFFSET 0x0000 165 #define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */ 166 #define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */ 167 #define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */ 168 #define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */ 169 #define SKX_IM_INT_STATUS_OFFSET 0x0040 170 #define SKX_IM_INT_DISABLE_OFFSET 0x0048 171 #define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */ 172 #define SKX_USMEMMISS_OFFSET 0x0070 173 #define SKX_INTVEC_OFFSET 0x00d0 174 #define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */ 175 #define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */ 176 #define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */ 177 #define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */ 178 #define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */ 179 #define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */ 180 #define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */ 181 #define SKX_EM_INT_STATUS_OFFSET 0x4040 182 #define SKX_EM_INT_DISABLE_OFFSET 0x4048 183 #define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */ 184 #define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */ 185 #define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */ 186 #define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */ 187 #define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */ 188 #define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */ 189 190 #define SKX_DB_COUNT 32 191 #define SKX_DB_LINK 32 192 #define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK) 193 #define SKX_DB_MSIX_VECTOR_COUNT 33 194 #define SKX_DB_MSIX_VECTOR_SHIFT 1 195 #define SKX_DB_TOTAL_SHIFT 33 196 #define SKX_SPAD_COUNT 16 197 198 /* Ntb control and link status */ 199 200 #define NTB_CTL_CFG_LOCK BIT(0) 201 #define NTB_CTL_DISABLE BIT(1) 202 #define NTB_CTL_S2P_BAR2_SNOOP BIT(2) 203 #define NTB_CTL_P2S_BAR2_SNOOP BIT(4) 204 #define NTB_CTL_S2P_BAR4_SNOOP BIT(6) 205 #define NTB_CTL_P2S_BAR4_SNOOP BIT(8) 206 #define NTB_CTL_S2P_BAR5_SNOOP BIT(12) 207 #define NTB_CTL_P2S_BAR5_SNOOP BIT(14) 208 209 #define NTB_LNK_STA_ACTIVE_BIT 0x2000 210 #define NTB_LNK_STA_SPEED_MASK 0x000f 211 #define NTB_LNK_STA_WIDTH_MASK 0x03f0 212 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT)) 213 #define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) 214 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) 215 216 /* Use the following addresses for translation between b2b ntb devices in case 217 * the hardware default values are not reliable. */ 218 #define XEON_B2B_BAR0_ADDR 0x1000000000000000ull 219 #define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull 220 #define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull 221 #define XEON_B2B_BAR4_ADDR32 0x20000000u 222 #define XEON_B2B_BAR5_ADDR32 0x40000000u 223 224 /* The peer ntb secondary config space is 32KB fixed size */ 225 #define XEON_B2B_MIN_SIZE 0x8000 226 227 /* flags to indicate hardware errata */ 228 #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0) 229 #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1) 230 #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2) 231 #define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3) 232 233 /* flags to indicate unsafe api */ 234 #define NTB_UNSAFE_DB BIT_ULL(0) 235 #define NTB_UNSAFE_SPAD BIT_ULL(1) 236 237 #define NTB_BAR_MASK_64 ~(0xfull) 238 #define NTB_BAR_MASK_32 ~(0xfu) 239 240 struct intel_ntb_dev; 241 242 struct intel_ntb_reg { 243 int (*poll_link)(struct intel_ntb_dev *ndev); 244 int (*link_is_up)(struct intel_ntb_dev *ndev); 245 u64 (*db_ioread)(void __iomem *mmio); 246 void (*db_iowrite)(u64 db_bits, void __iomem *mmio); 247 unsigned long ntb_ctl; 248 resource_size_t db_size; 249 int mw_bar[]; 250 }; 251 252 struct intel_ntb_alt_reg { 253 unsigned long db_bell; 254 unsigned long db_mask; 255 unsigned long db_clear; 256 unsigned long spad; 257 }; 258 259 struct intel_ntb_xlat_reg { 260 unsigned long bar0_base; 261 unsigned long bar2_xlat; 262 unsigned long bar2_limit; 263 }; 264 265 struct intel_b2b_addr { 266 phys_addr_t bar0_addr; 267 phys_addr_t bar2_addr64; 268 phys_addr_t bar4_addr64; 269 phys_addr_t bar4_addr32; 270 phys_addr_t bar5_addr32; 271 }; 272 273 struct intel_ntb_vec { 274 struct intel_ntb_dev *ndev; 275 int num; 276 }; 277 278 struct intel_ntb_dev { 279 struct ntb_dev ntb; 280 281 /* offset of peer bar0 in b2b bar */ 282 unsigned long b2b_off; 283 /* mw idx used to access peer bar0 */ 284 unsigned int b2b_idx; 285 286 /* BAR45 is split into BAR4 and BAR5 */ 287 bool bar4_split; 288 289 u32 ntb_ctl; 290 u32 lnk_sta; 291 292 unsigned char mw_count; 293 unsigned char spad_count; 294 unsigned char db_count; 295 unsigned char db_vec_count; 296 unsigned char db_vec_shift; 297 298 u64 db_valid_mask; 299 u64 db_link_mask; 300 u64 db_mask; 301 302 /* synchronize rmw access of db_mask and hw reg */ 303 spinlock_t db_mask_lock; 304 305 struct msix_entry *msix; 306 struct intel_ntb_vec *vec; 307 308 const struct intel_ntb_reg *reg; 309 const struct intel_ntb_alt_reg *self_reg; 310 const struct intel_ntb_alt_reg *peer_reg; 311 const struct intel_ntb_xlat_reg *xlat_reg; 312 void __iomem *self_mmio; 313 void __iomem *peer_mmio; 314 phys_addr_t peer_addr; 315 316 unsigned long last_ts; 317 struct delayed_work hb_timer; 318 319 unsigned long hwerr_flags; 320 unsigned long unsafe_flags; 321 unsigned long unsafe_flags_ignore; 322 323 struct dentry *debugfs_dir; 324 struct dentry *debugfs_info; 325 }; 326 327 #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb) 328 #define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \ 329 hb_timer.work) 330 331 #endif 332