1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 4 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com> 5 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> 6 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com> 7 8 Based on the original rt2800pci.c and rt2800usb.c. 9 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 10 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 11 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 12 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 13 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 14 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 15 <http://rt2x00.serialmonkey.com> 16 17 */ 18 19 /* 20 Module: rt2800lib 21 Abstract: rt2800 generic device routines. 22 */ 23 24 #include <linux/crc-ccitt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "rt2x00.h" 30 #include "rt2800lib.h" 31 #include "rt2800.h" 32 33 static bool modparam_watchdog; 34 module_param_named(watchdog, modparam_watchdog, bool, S_IRUGO); 35 MODULE_PARM_DESC(watchdog, "Enable watchdog to detect tx/rx hangs and reset hardware if detected"); 36 37 /* 38 * Register access. 39 * All access to the CSR registers will go through the methods 40 * rt2800_register_read and rt2800_register_write. 41 * BBP and RF register require indirect register access, 42 * and use the CSR registers BBPCSR and RFCSR to achieve this. 43 * These indirect registers work with busy bits, 44 * and we will try maximal REGISTER_BUSY_COUNT times to access 45 * the register while taking a REGISTER_BUSY_DELAY us delay 46 * between each attampt. When the busy bit is still set at that time, 47 * the access attempt is considered to have failed, 48 * and we will print an error. 49 * The _lock versions must be used if you already hold the csr_mutex 50 */ 51 #define WAIT_FOR_BBP(__dev, __reg) \ 52 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 53 #define WAIT_FOR_RFCSR(__dev, __reg) \ 54 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg)) 55 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \ 56 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \ 57 (__reg)) 58 #define WAIT_FOR_RF(__dev, __reg) \ 59 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg)) 60 #define WAIT_FOR_MCU(__dev, __reg) \ 61 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 62 H2M_MAILBOX_CSR_OWNER, (__reg)) 63 64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev) 65 { 66 /* check for rt2872 on SoC */ 67 if (!rt2x00_is_soc(rt2x00dev) || 68 !rt2x00_rt(rt2x00dev, RT2872)) 69 return false; 70 71 /* we know for sure that these rf chipsets are used on rt305x boards */ 72 if (rt2x00_rf(rt2x00dev, RF3020) || 73 rt2x00_rf(rt2x00dev, RF3021) || 74 rt2x00_rf(rt2x00dev, RF3022)) 75 return true; 76 77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n"); 78 return false; 79 } 80 81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 82 const unsigned int word, const u8 value) 83 { 84 u32 reg; 85 86 mutex_lock(&rt2x00dev->csr_mutex); 87 88 /* 89 * Wait until the BBP becomes available, afterwards we 90 * can safely write the new data into the register. 91 */ 92 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 93 reg = 0; 94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); 95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); 98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 99 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 101 } 102 103 mutex_unlock(&rt2x00dev->csr_mutex); 104 } 105 106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word) 107 { 108 u32 reg; 109 u8 value; 110 111 mutex_lock(&rt2x00dev->csr_mutex); 112 113 /* 114 * Wait until the BBP becomes available, afterwards we 115 * can safely write the read request into the register. 116 * After the data has been written, we wait until hardware 117 * returns the correct value, if at any time the register 118 * doesn't become available in time, reg will be 0xffffffff 119 * which means we return 0xff to the caller. 120 */ 121 if (WAIT_FOR_BBP(rt2x00dev, ®)) { 122 reg = 0; 123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); 124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); 125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); 126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); 127 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); 129 130 WAIT_FOR_BBP(rt2x00dev, ®); 131 } 132 133 value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); 134 135 mutex_unlock(&rt2x00dev->csr_mutex); 136 137 return value; 138 } 139 140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev, 141 const unsigned int word, const u8 value) 142 { 143 u32 reg; 144 145 mutex_lock(&rt2x00dev->csr_mutex); 146 147 /* 148 * Wait until the RFCSR becomes available, afterwards we 149 * can safely write the new data into the register. 150 */ 151 switch (rt2x00dev->chip.rt) { 152 case RT6352: 153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 154 reg = 0; 155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); 156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 157 word); 158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); 159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 160 161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 162 } 163 break; 164 165 default: 166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 167 reg = 0; 168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); 169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); 171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 172 173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 174 } 175 break; 176 } 177 178 mutex_unlock(&rt2x00dev->csr_mutex); 179 } 180 181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 182 const unsigned int reg, const u8 value) 183 { 184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value); 185 } 186 187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev, 188 const unsigned int reg, const u8 value) 189 { 190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value); 191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value); 192 } 193 194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev, 195 const unsigned int reg, const u8 value) 196 { 197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value); 198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value); 199 } 200 201 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev, 202 const unsigned int word) 203 { 204 u32 reg; 205 u8 value; 206 207 mutex_lock(&rt2x00dev->csr_mutex); 208 209 /* 210 * Wait until the RFCSR becomes available, afterwards we 211 * can safely write the read request into the register. 212 * After the data has been written, we wait until hardware 213 * returns the correct value, if at any time the register 214 * doesn't become available in time, reg will be 0xffffffff 215 * which means we return 0xff to the caller. 216 */ 217 switch (rt2x00dev->chip.rt) { 218 case RT6352: 219 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { 220 reg = 0; 221 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, 222 word); 223 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); 224 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); 225 226 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 227 228 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); 229 } 230 231 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); 232 break; 233 234 default: 235 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { 236 reg = 0; 237 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); 238 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); 239 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); 240 241 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); 242 243 WAIT_FOR_RFCSR(rt2x00dev, ®); 244 } 245 246 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); 247 break; 248 } 249 250 mutex_unlock(&rt2x00dev->csr_mutex); 251 252 return value; 253 } 254 255 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank, 256 const unsigned int reg) 257 { 258 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6))); 259 } 260 261 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev, 262 const unsigned int word, const u32 value) 263 { 264 u32 reg; 265 266 mutex_lock(&rt2x00dev->csr_mutex); 267 268 /* 269 * Wait until the RF becomes available, afterwards we 270 * can safely write the new data into the register. 271 */ 272 if (WAIT_FOR_RF(rt2x00dev, ®)) { 273 reg = 0; 274 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); 275 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); 276 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); 277 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); 278 279 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); 280 rt2x00_rf_write(rt2x00dev, word, value); 281 } 282 283 mutex_unlock(&rt2x00dev->csr_mutex); 284 } 285 286 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = { 287 [EEPROM_CHIP_ID] = 0x0000, 288 [EEPROM_VERSION] = 0x0001, 289 [EEPROM_MAC_ADDR_0] = 0x0002, 290 [EEPROM_MAC_ADDR_1] = 0x0003, 291 [EEPROM_MAC_ADDR_2] = 0x0004, 292 [EEPROM_NIC_CONF0] = 0x001a, 293 [EEPROM_NIC_CONF1] = 0x001b, 294 [EEPROM_FREQ] = 0x001d, 295 [EEPROM_LED_AG_CONF] = 0x001e, 296 [EEPROM_LED_ACT_CONF] = 0x001f, 297 [EEPROM_LED_POLARITY] = 0x0020, 298 [EEPROM_NIC_CONF2] = 0x0021, 299 [EEPROM_LNA] = 0x0022, 300 [EEPROM_RSSI_BG] = 0x0023, 301 [EEPROM_RSSI_BG2] = 0x0024, 302 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */ 303 [EEPROM_RSSI_A] = 0x0025, 304 [EEPROM_RSSI_A2] = 0x0026, 305 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */ 306 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027, 307 [EEPROM_TXPOWER_DELTA] = 0x0028, 308 [EEPROM_TXPOWER_BG1] = 0x0029, 309 [EEPROM_TXPOWER_BG2] = 0x0030, 310 [EEPROM_TSSI_BOUND_BG1] = 0x0037, 311 [EEPROM_TSSI_BOUND_BG2] = 0x0038, 312 [EEPROM_TSSI_BOUND_BG3] = 0x0039, 313 [EEPROM_TSSI_BOUND_BG4] = 0x003a, 314 [EEPROM_TSSI_BOUND_BG5] = 0x003b, 315 [EEPROM_TXPOWER_A1] = 0x003c, 316 [EEPROM_TXPOWER_A2] = 0x0053, 317 [EEPROM_TXPOWER_INIT] = 0x0068, 318 [EEPROM_TSSI_BOUND_A1] = 0x006a, 319 [EEPROM_TSSI_BOUND_A2] = 0x006b, 320 [EEPROM_TSSI_BOUND_A3] = 0x006c, 321 [EEPROM_TSSI_BOUND_A4] = 0x006d, 322 [EEPROM_TSSI_BOUND_A5] = 0x006e, 323 [EEPROM_TXPOWER_BYRATE] = 0x006f, 324 [EEPROM_BBP_START] = 0x0078, 325 }; 326 327 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { 328 [EEPROM_CHIP_ID] = 0x0000, 329 [EEPROM_VERSION] = 0x0001, 330 [EEPROM_MAC_ADDR_0] = 0x0002, 331 [EEPROM_MAC_ADDR_1] = 0x0003, 332 [EEPROM_MAC_ADDR_2] = 0x0004, 333 [EEPROM_NIC_CONF0] = 0x001a, 334 [EEPROM_NIC_CONF1] = 0x001b, 335 [EEPROM_NIC_CONF2] = 0x001c, 336 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020, 337 [EEPROM_FREQ] = 0x0022, 338 [EEPROM_LED_AG_CONF] = 0x0023, 339 [EEPROM_LED_ACT_CONF] = 0x0024, 340 [EEPROM_LED_POLARITY] = 0x0025, 341 [EEPROM_LNA] = 0x0026, 342 [EEPROM_EXT_LNA2] = 0x0027, 343 [EEPROM_RSSI_BG] = 0x0028, 344 [EEPROM_RSSI_BG2] = 0x0029, 345 [EEPROM_RSSI_A] = 0x002a, 346 [EEPROM_RSSI_A2] = 0x002b, 347 [EEPROM_TXPOWER_BG1] = 0x0030, 348 [EEPROM_TXPOWER_BG2] = 0x0037, 349 [EEPROM_EXT_TXPOWER_BG3] = 0x003e, 350 [EEPROM_TSSI_BOUND_BG1] = 0x0045, 351 [EEPROM_TSSI_BOUND_BG2] = 0x0046, 352 [EEPROM_TSSI_BOUND_BG3] = 0x0047, 353 [EEPROM_TSSI_BOUND_BG4] = 0x0048, 354 [EEPROM_TSSI_BOUND_BG5] = 0x0049, 355 [EEPROM_TXPOWER_A1] = 0x004b, 356 [EEPROM_TXPOWER_A2] = 0x0065, 357 [EEPROM_EXT_TXPOWER_A3] = 0x007f, 358 [EEPROM_TSSI_BOUND_A1] = 0x009a, 359 [EEPROM_TSSI_BOUND_A2] = 0x009b, 360 [EEPROM_TSSI_BOUND_A3] = 0x009c, 361 [EEPROM_TSSI_BOUND_A4] = 0x009d, 362 [EEPROM_TSSI_BOUND_A5] = 0x009e, 363 [EEPROM_TXPOWER_BYRATE] = 0x00a0, 364 }; 365 366 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev, 367 const enum rt2800_eeprom_word word) 368 { 369 const unsigned int *map; 370 unsigned int index; 371 372 if (WARN_ONCE(word >= EEPROM_WORD_COUNT, 373 "%s: invalid EEPROM word %d\n", 374 wiphy_name(rt2x00dev->hw->wiphy), word)) 375 return 0; 376 377 if (rt2x00_rt(rt2x00dev, RT3593) || 378 rt2x00_rt(rt2x00dev, RT3883)) 379 map = rt2800_eeprom_map_ext; 380 else 381 map = rt2800_eeprom_map; 382 383 index = map[word]; 384 385 /* Index 0 is valid only for EEPROM_CHIP_ID. 386 * Otherwise it means that the offset of the 387 * given word is not initialized in the map, 388 * or that the field is not usable on the 389 * actual chipset. 390 */ 391 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0, 392 "%s: invalid access of EEPROM word %d\n", 393 wiphy_name(rt2x00dev->hw->wiphy), word); 394 395 return index; 396 } 397 398 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev, 399 const enum rt2800_eeprom_word word) 400 { 401 unsigned int index; 402 403 index = rt2800_eeprom_word_index(rt2x00dev, word); 404 return rt2x00_eeprom_addr(rt2x00dev, index); 405 } 406 407 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev, 408 const enum rt2800_eeprom_word word) 409 { 410 unsigned int index; 411 412 index = rt2800_eeprom_word_index(rt2x00dev, word); 413 return rt2x00_eeprom_read(rt2x00dev, index); 414 } 415 416 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev, 417 const enum rt2800_eeprom_word word, u16 data) 418 { 419 unsigned int index; 420 421 index = rt2800_eeprom_word_index(rt2x00dev, word); 422 rt2x00_eeprom_write(rt2x00dev, index, data); 423 } 424 425 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev, 426 const enum rt2800_eeprom_word array, 427 unsigned int offset) 428 { 429 unsigned int index; 430 431 index = rt2800_eeprom_word_index(rt2x00dev, array); 432 return rt2x00_eeprom_read(rt2x00dev, index + offset); 433 } 434 435 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) 436 { 437 u32 reg; 438 int i, count; 439 440 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 441 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); 442 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); 443 rt2x00_set_field32(®, WLAN_CLK_EN, 0); 444 rt2x00_set_field32(®, WLAN_EN, 1); 445 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 446 447 udelay(REGISTER_BUSY_DELAY); 448 449 count = 0; 450 do { 451 /* 452 * Check PLL_LD & XTAL_RDY. 453 */ 454 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 455 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 456 if (rt2x00_get_field32(reg, PLL_LD) && 457 rt2x00_get_field32(reg, XTAL_RDY)) 458 break; 459 udelay(REGISTER_BUSY_DELAY); 460 } 461 462 if (i >= REGISTER_BUSY_COUNT) { 463 464 if (count >= 10) 465 return -EIO; 466 467 rt2800_register_write(rt2x00dev, 0x58, 0x018); 468 udelay(REGISTER_BUSY_DELAY); 469 rt2800_register_write(rt2x00dev, 0x58, 0x418); 470 udelay(REGISTER_BUSY_DELAY); 471 rt2800_register_write(rt2x00dev, 0x58, 0x618); 472 udelay(REGISTER_BUSY_DELAY); 473 count++; 474 } else { 475 count = 0; 476 } 477 478 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 479 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); 480 rt2x00_set_field32(®, WLAN_CLK_EN, 1); 481 rt2x00_set_field32(®, WLAN_RESET, 1); 482 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 483 udelay(10); 484 rt2x00_set_field32(®, WLAN_RESET, 0); 485 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 486 udelay(10); 487 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff); 488 } while (count != 0); 489 490 return 0; 491 } 492 493 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev, 494 const u8 command, const u8 token, 495 const u8 arg0, const u8 arg1) 496 { 497 u32 reg; 498 499 /* 500 * SOC devices don't support MCU requests. 501 */ 502 if (rt2x00_is_soc(rt2x00dev)) 503 return; 504 505 mutex_lock(&rt2x00dev->csr_mutex); 506 507 /* 508 * Wait until the MCU becomes available, afterwards we 509 * can safely write the new data into the register. 510 */ 511 if (WAIT_FOR_MCU(rt2x00dev, ®)) { 512 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); 513 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); 514 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); 515 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); 516 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); 517 518 reg = 0; 519 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); 520 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); 521 } 522 523 mutex_unlock(&rt2x00dev->csr_mutex); 524 } 525 EXPORT_SYMBOL_GPL(rt2800_mcu_request); 526 527 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) 528 { 529 unsigned int i = 0; 530 u32 reg; 531 532 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 533 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 534 if (reg && reg != ~0) 535 return 0; 536 msleep(1); 537 } 538 539 rt2x00_err(rt2x00dev, "Unstable hardware\n"); 540 return -EBUSY; 541 } 542 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 543 544 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 545 { 546 unsigned int i; 547 u32 reg; 548 549 /* 550 * Some devices are really slow to respond here. Wait a whole second 551 * before timing out. 552 */ 553 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 554 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 555 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 556 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 557 return 0; 558 559 msleep(10); 560 } 561 562 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); 563 return -EACCES; 564 } 565 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 566 567 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) 568 { 569 u32 reg; 570 571 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 572 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 573 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 574 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 575 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 576 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 577 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 578 } 579 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma); 580 581 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev, 582 unsigned short *txwi_size, 583 unsigned short *rxwi_size) 584 { 585 switch (rt2x00dev->chip.rt) { 586 case RT3593: 587 case RT3883: 588 *txwi_size = TXWI_DESC_SIZE_4WORDS; 589 *rxwi_size = RXWI_DESC_SIZE_5WORDS; 590 break; 591 592 case RT5592: 593 case RT6352: 594 *txwi_size = TXWI_DESC_SIZE_5WORDS; 595 *rxwi_size = RXWI_DESC_SIZE_6WORDS; 596 break; 597 598 default: 599 *txwi_size = TXWI_DESC_SIZE_4WORDS; 600 *rxwi_size = RXWI_DESC_SIZE_4WORDS; 601 break; 602 } 603 } 604 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size); 605 606 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len) 607 { 608 u16 fw_crc; 609 u16 crc; 610 611 /* 612 * The last 2 bytes in the firmware array are the crc checksum itself, 613 * this means that we should never pass those 2 bytes to the crc 614 * algorithm. 615 */ 616 fw_crc = (data[len - 2] << 8 | data[len - 1]); 617 618 /* 619 * Use the crc ccitt algorithm. 620 * This will return the same value as the legacy driver which 621 * used bit ordering reversion on the both the firmware bytes 622 * before input input as well as on the final output. 623 * Obviously using crc ccitt directly is much more efficient. 624 */ 625 crc = crc_ccitt(~0, data, len - 2); 626 627 /* 628 * There is a small difference between the crc-itu-t + bitrev and 629 * the crc-ccitt crc calculation. In the latter method the 2 bytes 630 * will be swapped, use swab16 to convert the crc to the correct 631 * value. 632 */ 633 crc = swab16(crc); 634 635 return fw_crc == crc; 636 } 637 638 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev, 639 const u8 *data, const size_t len) 640 { 641 size_t offset = 0; 642 size_t fw_len; 643 bool multiple; 644 645 /* 646 * PCI(e) & SOC devices require firmware with a length 647 * of 8kb. USB devices require firmware files with a length 648 * of 4kb. Certain USB chipsets however require different firmware, 649 * which Ralink only provides attached to the original firmware 650 * file. Thus for USB devices, firmware files have a length 651 * which is a multiple of 4kb. The firmware for rt3290 chip also 652 * have a length which is a multiple of 4kb. 653 */ 654 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290)) 655 fw_len = 4096; 656 else 657 fw_len = 8192; 658 659 multiple = true; 660 /* 661 * Validate the firmware length 662 */ 663 if (len != fw_len && (!multiple || (len % fw_len) != 0)) 664 return FW_BAD_LENGTH; 665 666 /* 667 * Check if the chipset requires one of the upper parts 668 * of the firmware. 669 */ 670 if (rt2x00_is_usb(rt2x00dev) && 671 !rt2x00_rt(rt2x00dev, RT2860) && 672 !rt2x00_rt(rt2x00dev, RT2872) && 673 !rt2x00_rt(rt2x00dev, RT3070) && 674 ((len / fw_len) == 1)) 675 return FW_BAD_VERSION; 676 677 /* 678 * 8kb firmware files must be checked as if it were 679 * 2 separate firmware files. 680 */ 681 while (offset < len) { 682 if (!rt2800_check_firmware_crc(data + offset, fw_len)) 683 return FW_BAD_CRC; 684 685 offset += fw_len; 686 } 687 688 return FW_OK; 689 } 690 EXPORT_SYMBOL_GPL(rt2800_check_firmware); 691 692 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, 693 const u8 *data, const size_t len) 694 { 695 unsigned int i; 696 u32 reg; 697 int retval; 698 699 if (rt2x00_rt(rt2x00dev, RT3290)) { 700 retval = rt2800_enable_wlan_rt3290(rt2x00dev); 701 if (retval) 702 return -EBUSY; 703 } 704 705 /* 706 * If driver doesn't wake up firmware here, 707 * rt2800_load_firmware will hang forever when interface is up again. 708 */ 709 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 710 711 /* 712 * Wait for stable hardware. 713 */ 714 if (rt2800_wait_csr_ready(rt2x00dev)) 715 return -EBUSY; 716 717 if (rt2x00_is_pci(rt2x00dev)) { 718 if (rt2x00_rt(rt2x00dev, RT3290) || 719 rt2x00_rt(rt2x00dev, RT3572) || 720 rt2x00_rt(rt2x00dev, RT5390) || 721 rt2x00_rt(rt2x00dev, RT5392)) { 722 reg = rt2800_register_read(rt2x00dev, AUX_CTRL); 723 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); 724 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); 725 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); 726 } 727 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 728 } 729 730 rt2800_disable_wpdma(rt2x00dev); 731 732 /* 733 * Write firmware to the device. 734 */ 735 rt2800_drv_write_firmware(rt2x00dev, data, len); 736 737 /* 738 * Wait for device to stabilize. 739 */ 740 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 741 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); 742 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 743 break; 744 msleep(1); 745 } 746 747 if (i == REGISTER_BUSY_COUNT) { 748 rt2x00_err(rt2x00dev, "PBF system register not ready\n"); 749 return -EBUSY; 750 } 751 752 /* 753 * Disable DMA, will be reenabled later when enabling 754 * the radio. 755 */ 756 rt2800_disable_wpdma(rt2x00dev); 757 758 /* 759 * Initialize firmware. 760 */ 761 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 762 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 763 if (rt2x00_is_usb(rt2x00dev)) { 764 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 765 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 766 } 767 msleep(1); 768 769 return 0; 770 } 771 EXPORT_SYMBOL_GPL(rt2800_load_firmware); 772 773 void rt2800_write_tx_data(struct queue_entry *entry, 774 struct txentry_desc *txdesc) 775 { 776 __le32 *txwi = rt2800_drv_get_txwi(entry); 777 u32 word; 778 int i; 779 780 /* 781 * Initialize TX Info descriptor 782 */ 783 word = rt2x00_desc_read(txwi, 0); 784 rt2x00_set_field32(&word, TXWI_W0_FRAG, 785 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 786 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 787 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags)); 788 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); 789 rt2x00_set_field32(&word, TXWI_W0_TS, 790 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 791 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 792 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 793 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, 794 txdesc->u.ht.mpdu_density); 795 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); 796 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); 797 rt2x00_set_field32(&word, TXWI_W0_BW, 798 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 799 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 800 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 801 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); 802 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 803 rt2x00_desc_write(txwi, 0, word); 804 805 word = rt2x00_desc_read(txwi, 1); 806 rt2x00_set_field32(&word, TXWI_W1_ACK, 807 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 808 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 809 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 810 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); 811 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 812 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 813 txdesc->key_idx : txdesc->u.ht.wcid); 814 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 815 txdesc->length); 816 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); 817 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); 818 rt2x00_desc_write(txwi, 1, word); 819 820 /* 821 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert 822 * the IV from the IVEIV register when TXD_W3_WIV is set to 0. 823 * When TXD_W3_WIV is set to 1 it will use the IV data 824 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 825 * crypto entry in the registers should be used to encrypt the frame. 826 * 827 * Nulify all remaining words as well, we don't know how to program them. 828 */ 829 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++) 830 _rt2x00_desc_write(txwi, i, 0); 831 } 832 EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 833 834 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2) 835 { 836 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0); 837 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1); 838 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2); 839 u16 eeprom; 840 u8 offset0; 841 u8 offset1; 842 u8 offset2; 843 844 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 845 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 846 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0); 847 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1); 848 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 849 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2); 850 } else { 851 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 852 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0); 853 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1); 854 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 855 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2); 856 } 857 858 /* 859 * Convert the value from the descriptor into the RSSI value 860 * If the value in the descriptor is 0, it is considered invalid 861 * and the default (extremely low) rssi value is assumed 862 */ 863 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128; 864 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128; 865 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128; 866 867 /* 868 * mac80211 only accepts a single RSSI value. Calculating the 869 * average doesn't deliver a fair answer either since -60:-60 would 870 * be considered equally good as -50:-70 while the second is the one 871 * which gives less energy... 872 */ 873 rssi0 = max(rssi0, rssi1); 874 return (int)max(rssi0, rssi2); 875 } 876 877 void rt2800_process_rxwi(struct queue_entry *entry, 878 struct rxdone_entry_desc *rxdesc) 879 { 880 __le32 *rxwi = (__le32 *) entry->skb->data; 881 u32 word; 882 883 word = rt2x00_desc_read(rxwi, 0); 884 885 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); 886 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); 887 888 word = rt2x00_desc_read(rxwi, 1); 889 890 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) 891 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; 892 893 if (rt2x00_get_field32(word, RXWI_W1_BW)) 894 rxdesc->bw = RATE_INFO_BW_40; 895 896 /* 897 * Detect RX rate, always use MCS as signal type. 898 */ 899 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 900 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS); 901 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE); 902 903 /* 904 * Mask of 0x8 bit to remove the short preamble flag. 905 */ 906 if (rxdesc->rate_mode == RATE_MODE_CCK) 907 rxdesc->signal &= ~0x8; 908 909 word = rt2x00_desc_read(rxwi, 2); 910 911 /* 912 * Convert descriptor AGC value to RSSI value. 913 */ 914 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 915 /* 916 * Remove RXWI descriptor from start of the buffer. 917 */ 918 skb_pull(entry->skb, entry->queue->winfo_size); 919 } 920 EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 921 922 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc, 923 u32 status, enum nl80211_band band) 924 { 925 u8 flags = 0; 926 u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 927 928 switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) { 929 case RATE_MODE_HT_GREENFIELD: 930 flags |= IEEE80211_TX_RC_GREEN_FIELD; 931 /* fall through */ 932 case RATE_MODE_HT_MIX: 933 flags |= IEEE80211_TX_RC_MCS; 934 break; 935 case RATE_MODE_OFDM: 936 if (band == NL80211_BAND_2GHZ) 937 idx += 4; 938 break; 939 case RATE_MODE_CCK: 940 if (idx >= 8) 941 idx -= 8; 942 break; 943 } 944 945 if (rt2x00_get_field32(status, TX_STA_FIFO_BW)) 946 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 947 948 if (rt2x00_get_field32(status, TX_STA_FIFO_SGI)) 949 flags |= IEEE80211_TX_RC_SHORT_GI; 950 951 skbdesc->tx_rate_idx = idx; 952 skbdesc->tx_rate_flags = flags; 953 } 954 955 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) 956 { 957 __le32 *txwi; 958 u32 word; 959 int wcid, ack, pid; 960 int tx_wcid, tx_ack, tx_pid, is_agg; 961 962 /* 963 * This frames has returned with an IO error, 964 * so the status report is not intended for this 965 * frame. 966 */ 967 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) 968 return false; 969 970 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); 971 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); 972 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); 973 is_agg = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE); 974 975 /* 976 * Validate if this TX status report is intended for 977 * this entry by comparing the WCID/ACK/PID fields. 978 */ 979 txwi = rt2800_drv_get_txwi(entry); 980 981 word = rt2x00_desc_read(txwi, 1); 982 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); 983 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); 984 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); 985 986 if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) { 987 rt2x00_dbg(entry->queue->rt2x00dev, 988 "TX status report missed for queue %d entry %d\n", 989 entry->queue->qid, entry->entry_idx); 990 return false; 991 } 992 993 return true; 994 } 995 996 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, 997 bool match) 998 { 999 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1000 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1001 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1002 struct txdone_entry_desc txdesc; 1003 u32 word; 1004 u16 mcs, real_mcs; 1005 int aggr, ampdu, wcid, ack_req; 1006 1007 /* 1008 * Obtain the status about this packet. 1009 */ 1010 txdesc.flags = 0; 1011 word = rt2x00_desc_read(txwi, 0); 1012 1013 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 1014 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); 1015 1016 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS); 1017 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE); 1018 wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); 1019 ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED); 1020 1021 /* 1022 * If a frame was meant to be sent as a single non-aggregated MPDU 1023 * but ended up in an aggregate the used tx rate doesn't correlate 1024 * with the one specified in the TXWI as the whole aggregate is sent 1025 * with the same rate. 1026 * 1027 * For example: two frames are sent to rt2x00, the first one sets 1028 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0 1029 * and requests MCS15. If the hw aggregates both frames into one 1030 * AMDPU the tx status for both frames will contain MCS7 although 1031 * the frame was sent successfully. 1032 * 1033 * Hence, replace the requested rate with the real tx rate to not 1034 * confuse the rate control algortihm by providing clearly wrong 1035 * data. 1036 * 1037 * FIXME: if we do not find matching entry, we tell that frame was 1038 * posted without any retries. We need to find a way to fix that 1039 * and provide retry count. 1040 */ 1041 if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) { 1042 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band); 1043 mcs = real_mcs; 1044 } 1045 1046 if (aggr == 1 || ampdu == 1) 1047 __set_bit(TXDONE_AMPDU, &txdesc.flags); 1048 1049 if (!ack_req) 1050 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags); 1051 1052 /* 1053 * Ralink has a retry mechanism using a global fallback 1054 * table. We setup this fallback table to try the immediate 1055 * lower rate for all rates. In the TX_STA_FIFO, the MCS field 1056 * always contains the MCS used for the last transmission, be 1057 * it successful or not. 1058 */ 1059 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) { 1060 /* 1061 * Transmission succeeded. The number of retries is 1062 * mcs - real_mcs 1063 */ 1064 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 1065 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0); 1066 } else { 1067 /* 1068 * Transmission failed. The number of retries is 1069 * always 7 in this case (for a total number of 8 1070 * frames sent). 1071 */ 1072 __set_bit(TXDONE_FAILURE, &txdesc.flags); 1073 txdesc.retry = rt2x00dev->long_retry; 1074 } 1075 1076 /* 1077 * the frame was retried at least once 1078 * -> hw used fallback rates 1079 */ 1080 if (txdesc.retry) 1081 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 1082 1083 if (!match) { 1084 /* RCU assures non-null sta will not be freed by mac80211. */ 1085 rcu_read_lock(); 1086 if (likely(wcid >= WCID_START && wcid <= WCID_END)) 1087 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START]; 1088 else 1089 skbdesc->sta = NULL; 1090 rt2x00lib_txdone_nomatch(entry, &txdesc); 1091 rcu_read_unlock(); 1092 } else { 1093 rt2x00lib_txdone(entry, &txdesc); 1094 } 1095 } 1096 EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 1097 1098 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota) 1099 { 1100 struct data_queue *queue; 1101 struct queue_entry *entry; 1102 u32 reg; 1103 u8 qid; 1104 bool match; 1105 1106 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { 1107 /* 1108 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is 1109 * guaranteed to be one of the TX QIDs . 1110 */ 1111 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); 1112 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); 1113 1114 if (unlikely(rt2x00queue_empty(queue))) { 1115 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n", 1116 qid); 1117 break; 1118 } 1119 1120 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1121 1122 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1123 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) { 1124 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n", 1125 entry->entry_idx, qid); 1126 break; 1127 } 1128 1129 match = rt2800_txdone_entry_check(entry, reg); 1130 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match); 1131 } 1132 } 1133 EXPORT_SYMBOL_GPL(rt2800_txdone); 1134 1135 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev, 1136 struct queue_entry *entry) 1137 { 1138 bool ret; 1139 unsigned long tout; 1140 1141 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1142 return false; 1143 1144 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags)) 1145 tout = msecs_to_jiffies(50); 1146 else 1147 tout = msecs_to_jiffies(2000); 1148 1149 ret = time_after(jiffies, entry->last_action + tout); 1150 if (unlikely(ret)) 1151 rt2x00_dbg(entry->queue->rt2x00dev, 1152 "TX status timeout for entry %d in queue %d\n", 1153 entry->entry_idx, entry->queue->qid); 1154 return ret; 1155 } 1156 1157 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev) 1158 { 1159 struct data_queue *queue; 1160 struct queue_entry *entry; 1161 1162 tx_queue_for_each(rt2x00dev, queue) { 1163 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1164 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1165 return true; 1166 } 1167 1168 return false; 1169 } 1170 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout); 1171 1172 /* 1173 * test if there is an entry in any TX queue for which DMA is done 1174 * but the TX status has not been returned yet 1175 */ 1176 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev) 1177 { 1178 struct data_queue *queue; 1179 1180 tx_queue_for_each(rt2x00dev, queue) { 1181 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) != 1182 rt2x00queue_get_entry(queue, Q_INDEX_DONE)) 1183 return true; 1184 } 1185 return false; 1186 } 1187 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending); 1188 1189 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev) 1190 { 1191 struct data_queue *queue; 1192 struct queue_entry *entry; 1193 1194 /* 1195 * Process any trailing TX status reports for IO failures, 1196 * we loop until we find the first non-IO error entry. This 1197 * can either be a frame which is free, is being uploaded, 1198 * or has completed the upload but didn't have an entry 1199 * in the TX_STAT_FIFO register yet. 1200 */ 1201 tx_queue_for_each(rt2x00dev, queue) { 1202 while (!rt2x00queue_empty(queue)) { 1203 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1204 1205 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) || 1206 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags)) 1207 break; 1208 1209 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) || 1210 rt2800_entry_txstatus_timeout(rt2x00dev, entry)) 1211 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); 1212 else 1213 break; 1214 } 1215 } 1216 } 1217 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus); 1218 1219 static int rt2800_check_hung(struct data_queue *queue) 1220 { 1221 unsigned int cur_idx = rt2800_drv_get_dma_done(queue); 1222 1223 if (queue->wd_idx != cur_idx) 1224 queue->wd_count = 0; 1225 else 1226 queue->wd_count++; 1227 1228 return queue->wd_count > 16; 1229 } 1230 1231 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev) 1232 { 1233 struct data_queue *queue; 1234 bool hung_tx = false; 1235 bool hung_rx = false; 1236 1237 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) 1238 return; 1239 1240 queue_for_each(rt2x00dev, queue) { 1241 switch (queue->qid) { 1242 case QID_AC_VO: 1243 case QID_AC_VI: 1244 case QID_AC_BE: 1245 case QID_AC_BK: 1246 case QID_MGMT: 1247 if (rt2x00queue_empty(queue)) 1248 continue; 1249 hung_tx = rt2800_check_hung(queue); 1250 break; 1251 case QID_RX: 1252 /* For station mode we should reactive at least 1253 * beacons. TODO: need to find good way detect 1254 * RX hung for AP mode. 1255 */ 1256 if (rt2x00dev->intf_sta_count == 0) 1257 continue; 1258 hung_rx = rt2800_check_hung(queue); 1259 break; 1260 default: 1261 break; 1262 } 1263 } 1264 1265 if (hung_tx) 1266 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n"); 1267 1268 if (hung_rx) 1269 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n"); 1270 1271 if (hung_tx || hung_rx) 1272 ieee80211_restart_hw(rt2x00dev->hw); 1273 } 1274 EXPORT_SYMBOL_GPL(rt2800_watchdog); 1275 1276 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev, 1277 unsigned int index) 1278 { 1279 return HW_BEACON_BASE(index); 1280 } 1281 1282 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev, 1283 unsigned int index) 1284 { 1285 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index)); 1286 } 1287 1288 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) 1289 { 1290 struct data_queue *queue = rt2x00dev->bcn; 1291 struct queue_entry *entry; 1292 int i, bcn_num = 0; 1293 u64 off, reg = 0; 1294 u32 bssid_dw1; 1295 1296 /* 1297 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers. 1298 */ 1299 for (i = 0; i < queue->limit; i++) { 1300 entry = &queue->entries[i]; 1301 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags)) 1302 continue; 1303 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx); 1304 reg |= off << (8 * bcn_num); 1305 bcn_num++; 1306 } 1307 1308 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); 1309 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); 1310 1311 /* 1312 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. 1313 */ 1314 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); 1315 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, 1316 bcn_num > 0 ? bcn_num - 1 : 0); 1317 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); 1318 } 1319 1320 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 1321 { 1322 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1323 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1324 unsigned int beacon_base; 1325 unsigned int padding_len; 1326 u32 orig_reg, reg; 1327 const int txwi_desc_size = entry->queue->winfo_size; 1328 1329 /* 1330 * Disable beaconing while we are reloading the beacon data, 1331 * otherwise we might be sending out invalid data. 1332 */ 1333 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1334 orig_reg = reg; 1335 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1336 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1337 1338 /* 1339 * Add space for the TXWI in front of the skb. 1340 */ 1341 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size); 1342 1343 /* 1344 * Register descriptor details in skb frame descriptor. 1345 */ 1346 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 1347 skbdesc->desc = entry->skb->data; 1348 skbdesc->desc_len = txwi_desc_size; 1349 1350 /* 1351 * Add the TXWI for the beacon to the skb. 1352 */ 1353 rt2800_write_tx_data(entry, txdesc); 1354 1355 /* 1356 * Dump beacon to userspace through debugfs. 1357 */ 1358 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); 1359 1360 /* 1361 * Write entire beacon with TXWI and padding to register. 1362 */ 1363 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1364 if (padding_len && skb_pad(entry->skb, padding_len)) { 1365 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); 1366 /* skb freed by skb_pad() on failure */ 1367 entry->skb = NULL; 1368 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1369 return; 1370 } 1371 1372 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx); 1373 1374 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1375 entry->skb->len + padding_len); 1376 __set_bit(ENTRY_BCN_ENABLED, &entry->flags); 1377 1378 /* 1379 * Change global beacons settings. 1380 */ 1381 rt2800_update_beacons_setup(rt2x00dev); 1382 1383 /* 1384 * Restore beaconing state. 1385 */ 1386 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1387 1388 /* 1389 * Clean up beacon skb. 1390 */ 1391 dev_kfree_skb_any(entry->skb); 1392 entry->skb = NULL; 1393 } 1394 EXPORT_SYMBOL_GPL(rt2800_write_beacon); 1395 1396 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev, 1397 unsigned int index) 1398 { 1399 int i; 1400 const int txwi_desc_size = rt2x00dev->bcn->winfo_size; 1401 unsigned int beacon_base; 1402 1403 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index); 1404 1405 /* 1406 * For the Beacon base registers we only need to clear 1407 * the whole TXWI which (when set to 0) will invalidate 1408 * the entire beacon. 1409 */ 1410 for (i = 0; i < txwi_desc_size; i += sizeof(__le32)) 1411 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 1412 } 1413 1414 void rt2800_clear_beacon(struct queue_entry *entry) 1415 { 1416 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1417 u32 orig_reg, reg; 1418 1419 /* 1420 * Disable beaconing while we are reloading the beacon data, 1421 * otherwise we might be sending out invalid data. 1422 */ 1423 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1424 reg = orig_reg; 1425 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 1426 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1427 1428 /* 1429 * Clear beacon. 1430 */ 1431 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx); 1432 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags); 1433 1434 /* 1435 * Change global beacons settings. 1436 */ 1437 rt2800_update_beacons_setup(rt2x00dev); 1438 /* 1439 * Restore beaconing state. 1440 */ 1441 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 1442 } 1443 EXPORT_SYMBOL_GPL(rt2800_clear_beacon); 1444 1445 #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1446 const struct rt2x00debug rt2800_rt2x00debug = { 1447 .owner = THIS_MODULE, 1448 .csr = { 1449 .read = rt2800_register_read, 1450 .write = rt2800_register_write, 1451 .flags = RT2X00DEBUGFS_OFFSET, 1452 .word_base = CSR_REG_BASE, 1453 .word_size = sizeof(u32), 1454 .word_count = CSR_REG_SIZE / sizeof(u32), 1455 }, 1456 .eeprom = { 1457 /* NOTE: The local EEPROM access functions can't 1458 * be used here, use the generic versions instead. 1459 */ 1460 .read = rt2x00_eeprom_read, 1461 .write = rt2x00_eeprom_write, 1462 .word_base = EEPROM_BASE, 1463 .word_size = sizeof(u16), 1464 .word_count = EEPROM_SIZE / sizeof(u16), 1465 }, 1466 .bbp = { 1467 .read = rt2800_bbp_read, 1468 .write = rt2800_bbp_write, 1469 .word_base = BBP_BASE, 1470 .word_size = sizeof(u8), 1471 .word_count = BBP_SIZE / sizeof(u8), 1472 }, 1473 .rf = { 1474 .read = rt2x00_rf_read, 1475 .write = rt2800_rf_write, 1476 .word_base = RF_BASE, 1477 .word_size = sizeof(u32), 1478 .word_count = RF_SIZE / sizeof(u32), 1479 }, 1480 .rfcsr = { 1481 .read = rt2800_rfcsr_read, 1482 .write = rt2800_rfcsr_write, 1483 .word_base = RFCSR_BASE, 1484 .word_size = sizeof(u8), 1485 .word_count = RFCSR_SIZE / sizeof(u8), 1486 }, 1487 }; 1488 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug); 1489 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1490 1491 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) 1492 { 1493 u32 reg; 1494 1495 if (rt2x00_rt(rt2x00dev, RT3290)) { 1496 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 1497 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); 1498 } else { 1499 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 1500 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); 1501 } 1502 } 1503 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 1504 1505 #ifdef CONFIG_RT2X00_LIB_LEDS 1506 static void rt2800_brightness_set(struct led_classdev *led_cdev, 1507 enum led_brightness brightness) 1508 { 1509 struct rt2x00_led *led = 1510 container_of(led_cdev, struct rt2x00_led, led_dev); 1511 unsigned int enabled = brightness != LED_OFF; 1512 unsigned int bg_mode = 1513 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); 1514 unsigned int polarity = 1515 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1516 EEPROM_FREQ_LED_POLARITY); 1517 unsigned int ledmode = 1518 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg, 1519 EEPROM_FREQ_LED_MODE); 1520 u32 reg; 1521 1522 /* Check for SoC (SOC devices don't support MCU requests) */ 1523 if (rt2x00_is_soc(led->rt2x00dev)) { 1524 reg = rt2800_register_read(led->rt2x00dev, LED_CFG); 1525 1526 /* Set LED Polarity */ 1527 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); 1528 1529 /* Set LED Mode */ 1530 if (led->type == LED_TYPE_RADIO) { 1531 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 1532 enabled ? 3 : 0); 1533 } else if (led->type == LED_TYPE_ASSOC) { 1534 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 1535 enabled ? 3 : 0); 1536 } else if (led->type == LED_TYPE_QUALITY) { 1537 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 1538 enabled ? 3 : 0); 1539 } 1540 1541 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 1542 1543 } else { 1544 if (led->type == LED_TYPE_RADIO) { 1545 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1546 enabled ? 0x20 : 0); 1547 } else if (led->type == LED_TYPE_ASSOC) { 1548 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode, 1549 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20); 1550 } else if (led->type == LED_TYPE_QUALITY) { 1551 /* 1552 * The brightness is divided into 6 levels (0 - 5), 1553 * The specs tell us the following levels: 1554 * 0, 1 ,3, 7, 15, 31 1555 * to determine the level in a simple way we can simply 1556 * work with bitshifting: 1557 * (1 << level) - 1 1558 */ 1559 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, 1560 (1 << brightness / (LED_FULL / 6)) - 1, 1561 polarity); 1562 } 1563 } 1564 } 1565 1566 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev, 1567 struct rt2x00_led *led, enum led_type type) 1568 { 1569 led->rt2x00dev = rt2x00dev; 1570 led->type = type; 1571 led->led_dev.brightness_set = rt2800_brightness_set; 1572 led->flags = LED_INITIALIZED; 1573 } 1574 #endif /* CONFIG_RT2X00_LIB_LEDS */ 1575 1576 /* 1577 * Configuration handlers. 1578 */ 1579 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev, 1580 const u8 *address, 1581 int wcid) 1582 { 1583 struct mac_wcid_entry wcid_entry; 1584 u32 offset; 1585 1586 offset = MAC_WCID_ENTRY(wcid); 1587 1588 memset(&wcid_entry, 0xff, sizeof(wcid_entry)); 1589 if (address) 1590 memcpy(wcid_entry.mac, address, ETH_ALEN); 1591 1592 rt2800_register_multiwrite(rt2x00dev, offset, 1593 &wcid_entry, sizeof(wcid_entry)); 1594 } 1595 1596 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid) 1597 { 1598 u32 offset; 1599 offset = MAC_WCID_ATTR_ENTRY(wcid); 1600 rt2800_register_write(rt2x00dev, offset, 0); 1601 } 1602 1603 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, 1604 int wcid, u32 bssidx) 1605 { 1606 u32 offset = MAC_WCID_ATTR_ENTRY(wcid); 1607 u32 reg; 1608 1609 /* 1610 * The BSS Idx numbers is split in a main value of 3 bits, 1611 * and a extended field for adding one additional bit to the value. 1612 */ 1613 reg = rt2800_register_read(rt2x00dev, offset); 1614 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); 1615 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, 1616 (bssidx & 0x8) >> 3); 1617 rt2800_register_write(rt2x00dev, offset, reg); 1618 } 1619 1620 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, 1621 struct rt2x00lib_crypto *crypto, 1622 struct ieee80211_key_conf *key) 1623 { 1624 struct mac_iveiv_entry iveiv_entry; 1625 u32 offset; 1626 u32 reg; 1627 1628 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 1629 1630 if (crypto->cmd == SET_KEY) { 1631 reg = rt2800_register_read(rt2x00dev, offset); 1632 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 1633 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 1634 /* 1635 * Both the cipher as the BSS Idx numbers are split in a main 1636 * value of 3 bits, and a extended field for adding one additional 1637 * bit to the value. 1638 */ 1639 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 1640 (crypto->cipher & 0x7)); 1641 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 1642 (crypto->cipher & 0x8) >> 3); 1643 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 1644 rt2800_register_write(rt2x00dev, offset, reg); 1645 } else { 1646 /* Delete the cipher without touching the bssidx */ 1647 reg = rt2800_register_read(rt2x00dev, offset); 1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); 1649 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); 1650 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); 1651 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); 1652 rt2800_register_write(rt2x00dev, offset, reg); 1653 } 1654 1655 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 1656 return; 1657 1658 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 1659 1660 memset(&iveiv_entry, 0, sizeof(iveiv_entry)); 1661 if ((crypto->cipher == CIPHER_TKIP) || 1662 (crypto->cipher == CIPHER_TKIP_NO_MIC) || 1663 (crypto->cipher == CIPHER_AES)) 1664 iveiv_entry.iv[3] |= 0x20; 1665 iveiv_entry.iv[3] |= key->keyidx << 6; 1666 rt2800_register_multiwrite(rt2x00dev, offset, 1667 &iveiv_entry, sizeof(iveiv_entry)); 1668 } 1669 1670 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, 1671 struct rt2x00lib_crypto *crypto, 1672 struct ieee80211_key_conf *key) 1673 { 1674 struct hw_key_entry key_entry; 1675 struct rt2x00_field32 field; 1676 u32 offset; 1677 u32 reg; 1678 1679 if (crypto->cmd == SET_KEY) { 1680 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx; 1681 1682 memcpy(key_entry.key, crypto->key, 1683 sizeof(key_entry.key)); 1684 memcpy(key_entry.tx_mic, crypto->tx_mic, 1685 sizeof(key_entry.tx_mic)); 1686 memcpy(key_entry.rx_mic, crypto->rx_mic, 1687 sizeof(key_entry.rx_mic)); 1688 1689 offset = SHARED_KEY_ENTRY(key->hw_key_idx); 1690 rt2800_register_multiwrite(rt2x00dev, offset, 1691 &key_entry, sizeof(key_entry)); 1692 } 1693 1694 /* 1695 * The cipher types are stored over multiple registers 1696 * starting with SHARED_KEY_MODE_BASE each word will have 1697 * 32 bits and contains the cipher types for 2 bssidx each. 1698 * Using the correct defines correctly will cause overhead, 1699 * so just calculate the correct offset. 1700 */ 1701 field.bit_offset = 4 * (key->hw_key_idx % 8); 1702 field.bit_mask = 0x7 << field.bit_offset; 1703 1704 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 1705 1706 reg = rt2800_register_read(rt2x00dev, offset); 1707 rt2x00_set_field32(®, field, 1708 (crypto->cmd == SET_KEY) * crypto->cipher); 1709 rt2800_register_write(rt2x00dev, offset, reg); 1710 1711 /* 1712 * Update WCID information 1713 */ 1714 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx); 1715 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx, 1716 crypto->bssidx); 1717 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1718 1719 return 0; 1720 } 1721 EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1722 1723 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1724 struct rt2x00lib_crypto *crypto, 1725 struct ieee80211_key_conf *key) 1726 { 1727 struct hw_key_entry key_entry; 1728 u32 offset; 1729 1730 if (crypto->cmd == SET_KEY) { 1731 /* 1732 * Allow key configuration only for STAs that are 1733 * known by the hw. 1734 */ 1735 if (crypto->wcid > WCID_END) 1736 return -ENOSPC; 1737 key->hw_key_idx = crypto->wcid; 1738 1739 memcpy(key_entry.key, crypto->key, 1740 sizeof(key_entry.key)); 1741 memcpy(key_entry.tx_mic, crypto->tx_mic, 1742 sizeof(key_entry.tx_mic)); 1743 memcpy(key_entry.rx_mic, crypto->rx_mic, 1744 sizeof(key_entry.rx_mic)); 1745 1746 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx); 1747 rt2800_register_multiwrite(rt2x00dev, offset, 1748 &key_entry, sizeof(key_entry)); 1749 } 1750 1751 /* 1752 * Update WCID information 1753 */ 1754 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key); 1755 1756 return 0; 1757 } 1758 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key); 1759 1760 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) 1761 { 1762 u8 i, max_psdu; 1763 u32 reg; 1764 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1765 1766 for (i = 0; i < 3; i++) 1767 if (drv_data->ampdu_factor_cnt[i] > 0) 1768 break; 1769 1770 max_psdu = min(drv_data->max_psdu, i); 1771 1772 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 1773 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); 1774 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1775 } 1776 1777 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1778 struct ieee80211_sta *sta) 1779 { 1780 struct rt2x00_dev *rt2x00dev = hw->priv; 1781 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1782 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1783 int wcid; 1784 1785 /* 1786 * Limit global maximum TX AMPDU length to smallest value of all 1787 * connected stations. In AP mode this can be suboptimal, but we 1788 * do not have a choice if some connected STA is not capable to 1789 * receive the same amount of data like the others. 1790 */ 1791 if (sta->ht_cap.ht_supported) { 1792 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++; 1793 rt2800_set_max_psdu_len(rt2x00dev); 1794 } 1795 1796 /* 1797 * Search for the first free WCID entry and return the corresponding 1798 * index. 1799 */ 1800 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START; 1801 1802 /* 1803 * Store selected wcid even if it is invalid so that we can 1804 * later decide if the STA is uploaded into the hw. 1805 */ 1806 sta_priv->wcid = wcid; 1807 1808 /* 1809 * No space left in the device, however, we can still communicate 1810 * with the STA -> No error. 1811 */ 1812 if (wcid > WCID_END) 1813 return 0; 1814 1815 __set_bit(wcid - WCID_START, drv_data->sta_ids); 1816 drv_data->wcid_to_sta[wcid - WCID_START] = sta; 1817 1818 /* 1819 * Clean up WCID attributes and write STA address to the device. 1820 */ 1821 rt2800_delete_wcid_attr(rt2x00dev, wcid); 1822 rt2800_config_wcid(rt2x00dev, sta->addr, wcid); 1823 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid, 1824 rt2x00lib_get_bssidx(rt2x00dev, vif)); 1825 return 0; 1826 } 1827 EXPORT_SYMBOL_GPL(rt2800_sta_add); 1828 1829 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1830 struct ieee80211_sta *sta) 1831 { 1832 struct rt2x00_dev *rt2x00dev = hw->priv; 1833 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1834 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta); 1835 int wcid = sta_priv->wcid; 1836 1837 if (sta->ht_cap.ht_supported) { 1838 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--; 1839 rt2800_set_max_psdu_len(rt2x00dev); 1840 } 1841 1842 if (wcid > WCID_END) 1843 return 0; 1844 /* 1845 * Remove WCID entry, no need to clean the attributes as they will 1846 * get renewed when the WCID is reused. 1847 */ 1848 rt2800_config_wcid(rt2x00dev, NULL, wcid); 1849 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1850 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1851 1852 return 0; 1853 } 1854 EXPORT_SYMBOL_GPL(rt2800_sta_remove); 1855 1856 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev) 1857 { 1858 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 1859 struct data_queue *queue = rt2x00dev->bcn; 1860 struct queue_entry *entry; 1861 int i, wcid; 1862 1863 for (wcid = WCID_START; wcid < WCID_END; wcid++) { 1864 drv_data->wcid_to_sta[wcid - WCID_START] = NULL; 1865 __clear_bit(wcid - WCID_START, drv_data->sta_ids); 1866 } 1867 1868 for (i = 0; i < queue->limit; i++) { 1869 entry = &queue->entries[i]; 1870 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags); 1871 } 1872 } 1873 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw); 1874 1875 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, 1876 const unsigned int filter_flags) 1877 { 1878 u32 reg; 1879 1880 /* 1881 * Start configuration steps. 1882 * Note that the version error will always be dropped 1883 * and broadcast frames will always be accepted since 1884 * there is no filter for it at this time. 1885 */ 1886 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); 1887 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, 1888 !(filter_flags & FIF_FCSFAIL)); 1889 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, 1890 !(filter_flags & FIF_PLCPFAIL)); 1891 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, 1892 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); 1893 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); 1894 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); 1895 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, 1896 !(filter_flags & FIF_ALLMULTI)); 1897 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); 1898 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); 1899 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, 1900 !(filter_flags & FIF_CONTROL)); 1901 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, 1902 !(filter_flags & FIF_CONTROL)); 1903 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, 1904 !(filter_flags & FIF_CONTROL)); 1905 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, 1906 !(filter_flags & FIF_CONTROL)); 1907 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, 1908 !(filter_flags & FIF_CONTROL)); 1909 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, 1910 !(filter_flags & FIF_PSPOLL)); 1911 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); 1912 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 1913 !(filter_flags & FIF_CONTROL)); 1914 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, 1915 !(filter_flags & FIF_CONTROL)); 1916 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); 1917 } 1918 EXPORT_SYMBOL_GPL(rt2800_config_filter); 1919 1920 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, 1921 struct rt2x00intf_conf *conf, const unsigned int flags) 1922 { 1923 u32 reg; 1924 bool update_bssid = false; 1925 1926 if (flags & CONFIG_UPDATE_TYPE) { 1927 /* 1928 * Enable synchronisation. 1929 */ 1930 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 1931 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1932 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1933 1934 if (conf->sync == TSF_SYNC_AP_NONE) { 1935 /* 1936 * Tune beacon queue transmit parameters for AP mode 1937 */ 1938 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1939 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); 1940 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); 1941 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1942 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); 1943 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1944 } else { 1945 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); 1946 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); 1947 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); 1948 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); 1949 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); 1950 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); 1951 } 1952 } 1953 1954 if (flags & CONFIG_UPDATE_MAC) { 1955 if (flags & CONFIG_UPDATE_TYPE && 1956 conf->sync == TSF_SYNC_AP_NONE) { 1957 /* 1958 * The BSSID register has to be set to our own mac 1959 * address in AP mode. 1960 */ 1961 memcpy(conf->bssid, conf->mac, sizeof(conf->mac)); 1962 update_bssid = true; 1963 } 1964 1965 if (!is_zero_ether_addr((const u8 *)conf->mac)) { 1966 reg = le32_to_cpu(conf->mac[1]); 1967 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); 1968 conf->mac[1] = cpu_to_le32(reg); 1969 } 1970 1971 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0, 1972 conf->mac, sizeof(conf->mac)); 1973 } 1974 1975 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) { 1976 if (!is_zero_ether_addr((const u8 *)conf->bssid)) { 1977 reg = le32_to_cpu(conf->bssid[1]); 1978 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); 1979 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); 1980 conf->bssid[1] = cpu_to_le32(reg); 1981 } 1982 1983 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0, 1984 conf->bssid, sizeof(conf->bssid)); 1985 } 1986 } 1987 EXPORT_SYMBOL_GPL(rt2800_config_intf); 1988 1989 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, 1990 struct rt2x00lib_erp *erp) 1991 { 1992 bool any_sta_nongf = !!(erp->ht_opmode & 1993 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); 1994 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION; 1995 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode; 1996 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate; 1997 u32 reg; 1998 1999 /* default protection rate for HT20: OFDM 24M */ 2000 mm20_rate = gf20_rate = 0x4004; 2001 2002 /* default protection rate for HT40: duplicate OFDM 24M */ 2003 mm40_rate = gf40_rate = 0x4084; 2004 2005 switch (protection) { 2006 case IEEE80211_HT_OP_MODE_PROTECTION_NONE: 2007 /* 2008 * All STAs in this BSS are HT20/40 but there might be 2009 * STAs not supporting greenfield mode. 2010 * => Disable protection for HT transmissions. 2011 */ 2012 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0; 2013 2014 break; 2015 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: 2016 /* 2017 * All STAs in this BSS are HT20 or HT20/40 but there 2018 * might be STAs not supporting greenfield mode. 2019 * => Protect all HT40 transmissions. 2020 */ 2021 mm20_mode = gf20_mode = 0; 2022 mm40_mode = gf40_mode = 1; 2023 2024 break; 2025 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: 2026 /* 2027 * Nonmember protection: 2028 * According to 802.11n we _should_ protect all 2029 * HT transmissions (but we don't have to). 2030 * 2031 * But if cts_protection is enabled we _shall_ protect 2032 * all HT transmissions using a CCK rate. 2033 * 2034 * And if any station is non GF we _shall_ protect 2035 * GF transmissions. 2036 * 2037 * We decide to protect everything 2038 * -> fall through to mixed mode. 2039 */ 2040 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: 2041 /* 2042 * Legacy STAs are present 2043 * => Protect all HT transmissions. 2044 */ 2045 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1; 2046 2047 /* 2048 * If erp protection is needed we have to protect HT 2049 * transmissions with CCK 11M long preamble. 2050 */ 2051 if (erp->cts_protection) { 2052 /* don't duplicate RTS/CTS in CCK mode */ 2053 mm20_rate = mm40_rate = 0x0003; 2054 gf20_rate = gf40_rate = 0x0003; 2055 } 2056 break; 2057 } 2058 2059 /* check for STAs not supporting greenfield mode */ 2060 if (any_sta_nongf) 2061 gf20_mode = gf40_mode = 1; 2062 2063 /* Update HT protection config */ 2064 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 2065 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); 2066 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); 2067 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 2068 2069 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 2070 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); 2071 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); 2072 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 2073 2074 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 2075 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); 2076 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); 2077 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 2078 2079 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 2080 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); 2081 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); 2082 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 2083 } 2084 2085 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, 2086 u32 changed) 2087 { 2088 u32 reg; 2089 2090 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2091 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 2092 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 2093 !!erp->short_preamble); 2094 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 2095 } 2096 2097 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2098 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 2099 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 2100 erp->cts_protection ? 2 : 0); 2101 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 2102 } 2103 2104 if (changed & BSS_CHANGED_BASIC_RATES) { 2105 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 2106 0xff0 | erp->basic_rates); 2107 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 2108 } 2109 2110 if (changed & BSS_CHANGED_ERP_SLOT) { 2111 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 2112 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 2113 erp->slot_time); 2114 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2115 2116 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 2117 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); 2118 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 2119 } 2120 2121 if (changed & BSS_CHANGED_BEACON_INT) { 2122 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 2123 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 2124 erp->beacon_int * 16); 2125 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2126 } 2127 2128 if (changed & BSS_CHANGED_HT) 2129 rt2800_config_ht_opmode(rt2x00dev, erp); 2130 } 2131 EXPORT_SYMBOL_GPL(rt2800_config_erp); 2132 2133 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) 2134 { 2135 u32 reg; 2136 u16 eeprom; 2137 u8 led_ctrl, led_g_mode, led_r_mode; 2138 2139 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 2140 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { 2141 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); 2142 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); 2143 } else { 2144 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); 2145 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); 2146 } 2147 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 2148 2149 reg = rt2800_register_read(rt2x00dev, LED_CFG); 2150 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; 2151 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; 2152 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || 2153 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { 2154 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 2155 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); 2156 if (led_ctrl == 0 || led_ctrl > 0x40) { 2157 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); 2158 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); 2159 rt2800_register_write(rt2x00dev, LED_CFG, reg); 2160 } else { 2161 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, 2162 (led_g_mode << 2) | led_r_mode, 1); 2163 } 2164 } 2165 } 2166 2167 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 2168 enum antenna ant) 2169 { 2170 u32 reg; 2171 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0; 2172 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; 2173 2174 if (rt2x00_is_pci(rt2x00dev)) { 2175 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); 2176 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); 2177 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); 2178 } else if (rt2x00_is_usb(rt2x00dev)) 2179 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, 2180 eesk_pin, 0); 2181 2182 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2183 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 2184 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); 2185 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2186 } 2187 2188 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 2189 { 2190 u8 r1; 2191 u8 r3; 2192 u16 eeprom; 2193 2194 r1 = rt2800_bbp_read(rt2x00dev, 1); 2195 r3 = rt2800_bbp_read(rt2x00dev, 3); 2196 2197 if (rt2x00_rt(rt2x00dev, RT3572) && 2198 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2199 rt2800_config_3572bt_ant(rt2x00dev); 2200 2201 /* 2202 * Configure the TX antenna. 2203 */ 2204 switch (ant->tx_chain_num) { 2205 case 1: 2206 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 2207 break; 2208 case 2: 2209 if (rt2x00_rt(rt2x00dev, RT3572) && 2210 rt2x00_has_cap_bt_coexist(rt2x00dev)) 2211 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); 2212 else 2213 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2214 break; 2215 case 3: 2216 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 2217 break; 2218 } 2219 2220 /* 2221 * Configure the RX antenna. 2222 */ 2223 switch (ant->rx_chain_num) { 2224 case 1: 2225 if (rt2x00_rt(rt2x00dev, RT3070) || 2226 rt2x00_rt(rt2x00dev, RT3090) || 2227 rt2x00_rt(rt2x00dev, RT3352) || 2228 rt2x00_rt(rt2x00dev, RT3390)) { 2229 eeprom = rt2800_eeprom_read(rt2x00dev, 2230 EEPROM_NIC_CONF1); 2231 if (rt2x00_get_field16(eeprom, 2232 EEPROM_NIC_CONF1_ANT_DIVERSITY)) 2233 rt2800_set_ant_diversity(rt2x00dev, 2234 rt2x00dev->default_ant.rx); 2235 } 2236 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 2237 break; 2238 case 2: 2239 if (rt2x00_rt(rt2x00dev, RT3572) && 2240 rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2241 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); 2242 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2243 rt2x00dev->curr_band == NL80211_BAND_5GHZ); 2244 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); 2245 } else { 2246 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 2247 } 2248 break; 2249 case 3: 2250 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 2251 break; 2252 } 2253 2254 rt2800_bbp_write(rt2x00dev, 3, r3); 2255 rt2800_bbp_write(rt2x00dev, 1, r1); 2256 2257 if (rt2x00_rt(rt2x00dev, RT3593) || 2258 rt2x00_rt(rt2x00dev, RT3883)) { 2259 if (ant->rx_chain_num == 1) 2260 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2261 else 2262 rt2800_bbp_write(rt2x00dev, 86, 0x46); 2263 } 2264 } 2265 EXPORT_SYMBOL_GPL(rt2800_config_ant); 2266 2267 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev, 2268 struct rt2x00lib_conf *libconf) 2269 { 2270 u16 eeprom; 2271 short lna_gain; 2272 2273 if (libconf->rf.channel <= 14) { 2274 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2275 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG); 2276 } else if (libconf->rf.channel <= 64) { 2277 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 2278 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0); 2279 } else if (libconf->rf.channel <= 128) { 2280 if (rt2x00_rt(rt2x00dev, RT3593) || 2281 rt2x00_rt(rt2x00dev, RT3883)) { 2282 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2283 lna_gain = rt2x00_get_field16(eeprom, 2284 EEPROM_EXT_LNA2_A1); 2285 } else { 2286 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 2287 lna_gain = rt2x00_get_field16(eeprom, 2288 EEPROM_RSSI_BG2_LNA_A1); 2289 } 2290 } else { 2291 if (rt2x00_rt(rt2x00dev, RT3593) || 2292 rt2x00_rt(rt2x00dev, RT3883)) { 2293 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 2294 lna_gain = rt2x00_get_field16(eeprom, 2295 EEPROM_EXT_LNA2_A2); 2296 } else { 2297 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 2298 lna_gain = rt2x00_get_field16(eeprom, 2299 EEPROM_RSSI_A2_LNA_A2); 2300 } 2301 } 2302 2303 rt2x00dev->lna_gain = lna_gain; 2304 } 2305 2306 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev) 2307 { 2308 return clk_get_rate(rt2x00dev->clk) == 20000000; 2309 } 2310 2311 #define FREQ_OFFSET_BOUND 0x5f 2312 2313 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev) 2314 { 2315 u8 freq_offset, prev_freq_offset; 2316 u8 rfcsr, prev_rfcsr; 2317 2318 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE); 2319 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND); 2320 2321 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 2322 prev_rfcsr = rfcsr; 2323 2324 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset); 2325 if (rfcsr == prev_rfcsr) 2326 return; 2327 2328 if (rt2x00_is_usb(rt2x00dev)) { 2329 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff, 2330 freq_offset, prev_rfcsr); 2331 return; 2332 } 2333 2334 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE); 2335 while (prev_freq_offset != freq_offset) { 2336 if (prev_freq_offset < freq_offset) 2337 prev_freq_offset++; 2338 else 2339 prev_freq_offset--; 2340 2341 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset); 2342 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 2343 2344 usleep_range(1000, 1500); 2345 } 2346 } 2347 2348 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev, 2349 struct ieee80211_conf *conf, 2350 struct rf_channel *rf, 2351 struct channel_info *info) 2352 { 2353 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 2354 2355 if (rt2x00dev->default_ant.tx_chain_num == 1) 2356 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 2357 2358 if (rt2x00dev->default_ant.rx_chain_num == 1) { 2359 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 2360 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2361 } else if (rt2x00dev->default_ant.rx_chain_num == 2) 2362 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 2363 2364 if (rf->channel > 14) { 2365 /* 2366 * When TX power is below 0, we should increase it by 7 to 2367 * make it a positive value (Minimum value is -7). 2368 * However this means that values between 0 and 7 have 2369 * double meaning, and we should set a 7DBm boost flag. 2370 */ 2371 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, 2372 (info->default_power1 >= 0)); 2373 2374 if (info->default_power1 < 0) 2375 info->default_power1 += 7; 2376 2377 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); 2378 2379 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, 2380 (info->default_power2 >= 0)); 2381 2382 if (info->default_power2 < 0) 2383 info->default_power2 += 7; 2384 2385 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); 2386 } else { 2387 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); 2388 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); 2389 } 2390 2391 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); 2392 2393 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2394 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2395 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2396 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2397 2398 udelay(200); 2399 2400 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2401 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2402 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); 2403 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2404 2405 udelay(200); 2406 2407 rt2800_rf_write(rt2x00dev, 1, rf->rf1); 2408 rt2800_rf_write(rt2x00dev, 2, rf->rf2); 2409 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 2410 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 2411 } 2412 2413 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, 2414 struct ieee80211_conf *conf, 2415 struct rf_channel *rf, 2416 struct channel_info *info) 2417 { 2418 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2419 u8 rfcsr, calib_tx, calib_rx; 2420 2421 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2422 2423 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2424 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3); 2425 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2426 2427 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2428 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2429 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2430 2431 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2432 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1); 2433 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2434 2435 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2436 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2); 2437 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2438 2439 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2440 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2441 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 2442 rt2x00dev->default_ant.rx_chain_num <= 1); 2443 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 2444 rt2x00dev->default_ant.rx_chain_num <= 2); 2445 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2446 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 2447 rt2x00dev->default_ant.tx_chain_num <= 1); 2448 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 2449 rt2x00dev->default_ant.tx_chain_num <= 2); 2450 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2451 2452 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2453 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2454 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2455 2456 if (rt2x00_rt(rt2x00dev, RT3390)) { 2457 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f; 2458 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f; 2459 } else { 2460 if (conf_is_ht40(conf)) { 2461 calib_tx = drv_data->calibration_bw40; 2462 calib_rx = drv_data->calibration_bw40; 2463 } else { 2464 calib_tx = drv_data->calibration_bw20; 2465 calib_rx = drv_data->calibration_bw20; 2466 } 2467 } 2468 2469 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24); 2470 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx); 2471 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr); 2472 2473 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 2474 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx); 2475 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2476 2477 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2478 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2479 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2480 2481 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2482 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2483 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2484 2485 usleep_range(1000, 1500); 2486 2487 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2488 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2489 } 2490 2491 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, 2492 struct ieee80211_conf *conf, 2493 struct rf_channel *rf, 2494 struct channel_info *info) 2495 { 2496 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2497 u8 rfcsr; 2498 u32 reg; 2499 2500 if (rf->channel <= 14) { 2501 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2502 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2503 } else { 2504 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2505 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2506 } 2507 2508 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); 2509 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 2510 2511 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2512 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); 2513 if (rf->channel <= 14) 2514 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); 2515 else 2516 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); 2517 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2518 2519 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5); 2520 if (rf->channel <= 14) 2521 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); 2522 else 2523 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); 2524 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); 2525 2526 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2527 if (rf->channel <= 14) { 2528 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); 2529 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2530 info->default_power1); 2531 } else { 2532 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); 2533 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, 2534 (info->default_power1 & 0x3) | 2535 ((info->default_power1 & 0xC) << 1)); 2536 } 2537 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2538 2539 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 2540 if (rf->channel <= 14) { 2541 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); 2542 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2543 info->default_power2); 2544 } else { 2545 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); 2546 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, 2547 (info->default_power2 & 0x3) | 2548 ((info->default_power2 & 0xC) << 1)); 2549 } 2550 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 2551 2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2553 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2554 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2555 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2556 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2557 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2558 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2559 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 2560 if (rf->channel <= 14) { 2561 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2562 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2563 } 2564 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2565 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2566 } else { 2567 switch (rt2x00dev->default_ant.tx_chain_num) { 2568 case 1: 2569 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2570 /* fall through */ 2571 case 2: 2572 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2573 break; 2574 } 2575 2576 switch (rt2x00dev->default_ant.rx_chain_num) { 2577 case 1: 2578 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2579 /* fall through */ 2580 case 2: 2581 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2582 break; 2583 } 2584 } 2585 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2586 2587 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23); 2588 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 2589 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 2590 2591 if (conf_is_ht40(conf)) { 2592 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40); 2593 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40); 2594 } else { 2595 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20); 2596 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20); 2597 } 2598 2599 if (rf->channel <= 14) { 2600 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 2601 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 2602 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2603 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 2604 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 2605 rfcsr = 0x4c; 2606 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2607 drv_data->txmixer_gain_24g); 2608 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2609 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2610 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 2611 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 2612 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 2613 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 2614 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 2615 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 2616 } else { 2617 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2618 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1); 2619 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0); 2620 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1); 2621 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0); 2622 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2623 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 2624 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 2625 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 2626 rt2800_rfcsr_write(rt2x00dev, 15, 0x43); 2627 rfcsr = 0x7a; 2628 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN, 2629 drv_data->txmixer_gain_5g); 2630 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 2631 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 2632 if (rf->channel <= 64) { 2633 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); 2634 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); 2635 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 2636 } else if (rf->channel <= 128) { 2637 rt2800_rfcsr_write(rt2x00dev, 19, 0x74); 2638 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); 2639 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2640 } else { 2641 rt2800_rfcsr_write(rt2x00dev, 19, 0x72); 2642 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); 2643 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 2644 } 2645 rt2800_rfcsr_write(rt2x00dev, 26, 0x87); 2646 rt2800_rfcsr_write(rt2x00dev, 27, 0x01); 2647 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); 2648 } 2649 2650 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 2651 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 2652 if (rf->channel <= 14) 2653 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 2654 else 2655 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); 2656 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 2657 2658 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 2659 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2660 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2661 } 2662 2663 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev, 2664 struct ieee80211_conf *conf, 2665 struct rf_channel *rf, 2666 struct channel_info *info) 2667 { 2668 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 2669 u8 txrx_agc_fc; 2670 u8 txrx_h20m; 2671 u8 rfcsr; 2672 u8 bbp; 2673 const bool txbf_enabled = false; /* TODO */ 2674 2675 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */ 2676 bbp = rt2800_bbp_read(rt2x00dev, 109); 2677 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0); 2678 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0); 2679 rt2800_bbp_write(rt2x00dev, 109, bbp); 2680 2681 bbp = rt2800_bbp_read(rt2x00dev, 110); 2682 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0); 2683 rt2800_bbp_write(rt2x00dev, 110, bbp); 2684 2685 if (rf->channel <= 14) { 2686 /* Restore BBP 25 & 26 for 2.4 GHz */ 2687 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25); 2688 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26); 2689 } else { 2690 /* Hard code BBP 25 & 26 for 5GHz */ 2691 2692 /* Enable IQ Phase correction */ 2693 rt2800_bbp_write(rt2x00dev, 25, 0x09); 2694 /* Setup IQ Phase correction value */ 2695 rt2800_bbp_write(rt2x00dev, 26, 0xff); 2696 } 2697 2698 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2699 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf); 2700 2701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2702 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3)); 2703 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2704 2705 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 2706 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1); 2707 if (rf->channel <= 14) 2708 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1); 2709 else 2710 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2); 2711 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 2712 2713 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53); 2714 if (rf->channel <= 14) { 2715 rfcsr = 0; 2716 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2717 info->default_power1 & 0x1f); 2718 } else { 2719 if (rt2x00_is_usb(rt2x00dev)) 2720 rfcsr = 0x40; 2721 2722 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER, 2723 ((info->default_power1 & 0x18) << 1) | 2724 (info->default_power1 & 7)); 2725 } 2726 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr); 2727 2728 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55); 2729 if (rf->channel <= 14) { 2730 rfcsr = 0; 2731 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2732 info->default_power2 & 0x1f); 2733 } else { 2734 if (rt2x00_is_usb(rt2x00dev)) 2735 rfcsr = 0x40; 2736 2737 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER, 2738 ((info->default_power2 & 0x18) << 1) | 2739 (info->default_power2 & 7)); 2740 } 2741 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr); 2742 2743 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54); 2744 if (rf->channel <= 14) { 2745 rfcsr = 0; 2746 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2747 info->default_power3 & 0x1f); 2748 } else { 2749 if (rt2x00_is_usb(rt2x00dev)) 2750 rfcsr = 0x40; 2751 2752 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER, 2753 ((info->default_power3 & 0x18) << 1) | 2754 (info->default_power3 & 7)); 2755 } 2756 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr); 2757 2758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2759 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2760 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2761 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2762 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 2763 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 2764 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 2765 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 2766 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 2767 2768 switch (rt2x00dev->default_ant.tx_chain_num) { 2769 case 3: 2770 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 2771 /* fallthrough */ 2772 case 2: 2773 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 2774 /* fallthrough */ 2775 case 1: 2776 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2777 break; 2778 } 2779 2780 switch (rt2x00dev->default_ant.rx_chain_num) { 2781 case 3: 2782 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 2783 /* fallthrough */ 2784 case 2: 2785 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 2786 /* fallthrough */ 2787 case 1: 2788 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2789 break; 2790 } 2791 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2792 2793 rt2800_freq_cal_mode1(rt2x00dev); 2794 2795 if (conf_is_ht40(conf)) { 2796 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40, 2797 RFCSR24_TX_AGC_FC); 2798 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40, 2799 RFCSR24_TX_H20M); 2800 } else { 2801 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20, 2802 RFCSR24_TX_AGC_FC); 2803 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20, 2804 RFCSR24_TX_H20M); 2805 } 2806 2807 /* NOTE: the reference driver does not writes the new value 2808 * back to RFCSR 32 2809 */ 2810 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32); 2811 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc); 2812 2813 if (rf->channel <= 14) 2814 rfcsr = 0xa0; 2815 else 2816 rfcsr = 0x80; 2817 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 2818 2819 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2820 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m); 2821 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m); 2822 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2823 2824 /* Band selection */ 2825 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 2826 if (rf->channel <= 14) 2827 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 2828 else 2829 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 2830 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 2831 2832 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34); 2833 if (rf->channel <= 14) 2834 rfcsr = 0x3c; 2835 else 2836 rfcsr = 0x20; 2837 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 2838 2839 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12); 2840 if (rf->channel <= 14) 2841 rfcsr = 0x1a; 2842 else 2843 rfcsr = 0x12; 2844 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 2845 2846 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 2847 if (rf->channel >= 1 && rf->channel <= 14) 2848 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2849 else if (rf->channel >= 36 && rf->channel <= 64) 2850 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2851 else if (rf->channel >= 100 && rf->channel <= 128) 2852 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2); 2853 else 2854 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1); 2855 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 2856 2857 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 2858 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 2859 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2860 2861 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 2862 2863 if (rf->channel <= 14) { 2864 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 2865 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2866 } else { 2867 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8); 2868 rt2800_rfcsr_write(rt2x00dev, 13, 0x23); 2869 } 2870 2871 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2872 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1); 2873 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2874 2875 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 2876 if (rf->channel <= 14) { 2877 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5); 2878 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3); 2879 } else { 2880 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4); 2881 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2); 2882 } 2883 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 2884 2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 2886 if (rf->channel <= 14) 2887 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3); 2888 else 2889 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2); 2890 2891 if (txbf_enabled) 2892 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1); 2893 2894 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2895 2896 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 2897 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0); 2898 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 2899 2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 2901 if (rf->channel <= 14) 2902 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b); 2903 else 2904 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f); 2905 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr); 2906 2907 if (rf->channel <= 14) { 2908 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 2909 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 2910 } else { 2911 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 2912 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 2913 } 2914 2915 /* Initiate VCO calibration */ 2916 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 2917 if (rf->channel <= 14) { 2918 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2919 } else { 2920 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1); 2921 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1); 2922 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1); 2923 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1); 2924 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1); 2925 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 2926 } 2927 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 2928 2929 if (rf->channel >= 1 && rf->channel <= 14) { 2930 rfcsr = 0x23; 2931 if (txbf_enabled) 2932 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2933 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2934 2935 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 2936 } else if (rf->channel >= 36 && rf->channel <= 64) { 2937 rfcsr = 0x36; 2938 if (txbf_enabled) 2939 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2940 rt2800_rfcsr_write(rt2x00dev, 39, 0x36); 2941 2942 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb); 2943 } else if (rf->channel >= 100 && rf->channel <= 128) { 2944 rfcsr = 0x32; 2945 if (txbf_enabled) 2946 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2947 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2948 2949 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3); 2950 } else { 2951 rfcsr = 0x30; 2952 if (txbf_enabled) 2953 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1); 2954 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 2955 2956 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b); 2957 } 2958 } 2959 2960 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev, 2961 struct ieee80211_conf *conf, 2962 struct rf_channel *rf, 2963 struct channel_info *info) 2964 { 2965 u8 rfcsr; 2966 u8 bbp; 2967 u8 pwr1, pwr2, pwr3; 2968 2969 const bool txbf_enabled = false; /* TODO */ 2970 2971 /* TODO: add band selection */ 2972 2973 if (rf->channel <= 14) 2974 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2975 else if (rf->channel < 132) 2976 rt2800_rfcsr_write(rt2x00dev, 6, 0x80); 2977 else 2978 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 2979 2980 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 2981 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 2982 2983 if (rf->channel <= 14) 2984 rt2800_rfcsr_write(rt2x00dev, 11, 0x46); 2985 else 2986 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 2987 2988 if (rf->channel <= 14) 2989 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 2990 else 2991 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 2992 2993 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 2994 2995 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 2996 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 2997 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 2998 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 2999 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3000 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3001 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3002 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3003 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3004 3005 switch (rt2x00dev->default_ant.tx_chain_num) { 3006 case 3: 3007 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); 3008 /* fallthrough */ 3009 case 2: 3010 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3011 /* fallthrough */ 3012 case 1: 3013 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3014 break; 3015 } 3016 3017 switch (rt2x00dev->default_ant.rx_chain_num) { 3018 case 3: 3019 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); 3020 /* fallthrough */ 3021 case 2: 3022 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3023 /* fallthrough */ 3024 case 1: 3025 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3026 break; 3027 } 3028 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3029 3030 rt2800_freq_cal_mode1(rt2x00dev); 3031 3032 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 3033 if (!conf_is_ht40(conf)) 3034 rfcsr &= ~(0x06); 3035 else 3036 rfcsr |= 0x06; 3037 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 3038 3039 if (rf->channel <= 14) 3040 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0); 3041 else 3042 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3043 3044 if (conf_is_ht40(conf)) 3045 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3046 else 3047 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 3048 3049 if (rf->channel <= 14) 3050 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 3051 else 3052 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 3053 3054 /* loopback RF_BS */ 3055 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36); 3056 if (rf->channel <= 14) 3057 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1); 3058 else 3059 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0); 3060 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr); 3061 3062 if (rf->channel <= 14) 3063 rfcsr = 0x23; 3064 else if (rf->channel < 100) 3065 rfcsr = 0x36; 3066 else if (rf->channel < 132) 3067 rfcsr = 0x32; 3068 else 3069 rfcsr = 0x30; 3070 3071 if (txbf_enabled) 3072 rfcsr |= 0x40; 3073 3074 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 3075 3076 if (rf->channel <= 14) 3077 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 3078 else 3079 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b); 3080 3081 if (rf->channel <= 14) 3082 rfcsr = 0xbb; 3083 else if (rf->channel < 100) 3084 rfcsr = 0xeb; 3085 else if (rf->channel < 132) 3086 rfcsr = 0xb3; 3087 else 3088 rfcsr = 0x9b; 3089 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr); 3090 3091 if (rf->channel <= 14) 3092 rfcsr = 0x8e; 3093 else 3094 rfcsr = 0x8a; 3095 3096 if (txbf_enabled) 3097 rfcsr |= 0x20; 3098 3099 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3100 3101 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 3102 3103 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 3104 if (rf->channel <= 14) 3105 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 3106 else 3107 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 3108 3109 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52); 3110 if (rf->channel <= 14) 3111 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 3112 else 3113 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 3114 3115 if (rf->channel <= 14) { 3116 pwr1 = info->default_power1 & 0x1f; 3117 pwr2 = info->default_power2 & 0x1f; 3118 pwr3 = info->default_power3 & 0x1f; 3119 } else { 3120 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) | 3121 (info->default_power1 & 0x7); 3122 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) | 3123 (info->default_power2 & 0x7); 3124 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) | 3125 (info->default_power3 & 0x7); 3126 } 3127 3128 rt2800_rfcsr_write(rt2x00dev, 53, pwr1); 3129 rt2800_rfcsr_write(rt2x00dev, 54, pwr2); 3130 rt2800_rfcsr_write(rt2x00dev, 55, pwr3); 3131 3132 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n", 3133 rf->channel, pwr1, pwr2, pwr3); 3134 3135 bbp = (info->default_power1 >> 5) | 3136 ((info->default_power2 & 0xe0) >> 1); 3137 rt2800_bbp_write(rt2x00dev, 109, bbp); 3138 3139 bbp = rt2800_bbp_read(rt2x00dev, 110); 3140 bbp &= 0x0f; 3141 bbp |= (info->default_power3 & 0xe0) >> 1; 3142 rt2800_bbp_write(rt2x00dev, 110, bbp); 3143 3144 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57); 3145 if (rf->channel <= 14) 3146 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 3147 else 3148 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 3149 3150 /* Enable RF tuning */ 3151 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3152 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3153 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3154 3155 udelay(2000); 3156 3157 bbp = rt2800_bbp_read(rt2x00dev, 49); 3158 /* clear update flag */ 3159 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe); 3160 rt2800_bbp_write(rt2x00dev, 49, bbp); 3161 3162 /* TODO: add calibration for TxBF */ 3163 } 3164 3165 #define POWER_BOUND 0x27 3166 #define POWER_BOUND_5G 0x2b 3167 3168 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 3169 struct ieee80211_conf *conf, 3170 struct rf_channel *rf, 3171 struct channel_info *info) 3172 { 3173 u8 rfcsr; 3174 3175 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3176 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3177 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3178 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3179 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3180 3181 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3182 if (info->default_power1 > POWER_BOUND) 3183 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3184 else 3185 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3186 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3187 3188 rt2800_freq_cal_mode1(rt2x00dev); 3189 3190 if (rf->channel <= 14) { 3191 if (rf->channel == 6) 3192 rt2800_bbp_write(rt2x00dev, 68, 0x0c); 3193 else 3194 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3195 3196 if (rf->channel >= 1 && rf->channel <= 6) 3197 rt2800_bbp_write(rt2x00dev, 59, 0x0f); 3198 else if (rf->channel >= 7 && rf->channel <= 11) 3199 rt2800_bbp_write(rt2x00dev, 59, 0x0e); 3200 else if (rf->channel >= 12 && rf->channel <= 14) 3201 rt2800_bbp_write(rt2x00dev, 59, 0x0d); 3202 } 3203 } 3204 3205 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev, 3206 struct ieee80211_conf *conf, 3207 struct rf_channel *rf, 3208 struct channel_info *info) 3209 { 3210 u8 rfcsr; 3211 3212 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3213 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3214 3215 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 3216 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 3217 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 3218 3219 if (info->default_power1 > POWER_BOUND) 3220 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND); 3221 else 3222 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1); 3223 3224 if (info->default_power2 > POWER_BOUND) 3225 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND); 3226 else 3227 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 3228 3229 rt2800_freq_cal_mode1(rt2x00dev); 3230 3231 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3232 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3233 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3234 3235 if ( rt2x00dev->default_ant.tx_chain_num == 2 ) 3236 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3237 else 3238 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); 3239 3240 if ( rt2x00dev->default_ant.rx_chain_num == 2 ) 3241 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3242 else 3243 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); 3244 3245 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3246 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3247 3248 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3249 3250 rt2800_rfcsr_write(rt2x00dev, 31, 80); 3251 } 3252 3253 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 3254 struct ieee80211_conf *conf, 3255 struct rf_channel *rf, 3256 struct channel_info *info) 3257 { 3258 u8 rfcsr; 3259 int idx = rf->channel-1; 3260 3261 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1); 3262 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3); 3263 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3264 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2); 3265 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3266 3267 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3268 if (info->default_power1 > POWER_BOUND) 3269 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND); 3270 else 3271 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3272 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3273 3274 if (rt2x00_rt(rt2x00dev, RT5392)) { 3275 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3276 if (info->default_power2 > POWER_BOUND) 3277 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND); 3278 else 3279 rt2x00_set_field8(&rfcsr, RFCSR50_TX, 3280 info->default_power2); 3281 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3282 } 3283 3284 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3285 if (rt2x00_rt(rt2x00dev, RT5392)) { 3286 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 3287 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 3288 } 3289 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3290 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3291 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 3292 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 3293 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3294 3295 rt2800_freq_cal_mode1(rt2x00dev); 3296 3297 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 3298 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3299 /* r55/r59 value array of channel 1~14 */ 3300 static const char r55_bt_rev[] = {0x83, 0x83, 3301 0x83, 0x73, 0x73, 0x63, 0x53, 0x53, 3302 0x53, 0x43, 0x43, 0x43, 0x43, 0x43}; 3303 static const char r59_bt_rev[] = {0x0e, 0x0e, 3304 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09, 3305 0x07, 0x07, 0x07, 0x07, 0x07, 0x07}; 3306 3307 rt2800_rfcsr_write(rt2x00dev, 55, 3308 r55_bt_rev[idx]); 3309 rt2800_rfcsr_write(rt2x00dev, 59, 3310 r59_bt_rev[idx]); 3311 } else { 3312 static const char r59_bt[] = {0x8b, 0x8b, 0x8b, 3313 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89, 3314 0x88, 0x88, 0x86, 0x85, 0x84}; 3315 3316 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]); 3317 } 3318 } else { 3319 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 3320 static const char r55_nonbt_rev[] = {0x23, 0x23, 3321 0x23, 0x23, 0x13, 0x13, 0x03, 0x03, 3322 0x03, 0x03, 0x03, 0x03, 0x03, 0x03}; 3323 static const char r59_nonbt_rev[] = {0x07, 0x07, 3324 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 3325 0x07, 0x07, 0x06, 0x05, 0x04, 0x04}; 3326 3327 rt2800_rfcsr_write(rt2x00dev, 55, 3328 r55_nonbt_rev[idx]); 3329 rt2800_rfcsr_write(rt2x00dev, 59, 3330 r59_nonbt_rev[idx]); 3331 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3332 rt2x00_rt(rt2x00dev, RT5392) || 3333 rt2x00_rt(rt2x00dev, RT6352)) { 3334 static const char r59_non_bt[] = {0x8f, 0x8f, 3335 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 3336 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; 3337 3338 rt2800_rfcsr_write(rt2x00dev, 59, 3339 r59_non_bt[idx]); 3340 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 3341 static const char r59_non_bt[] = {0x0b, 0x0b, 3342 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 3343 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06}; 3344 3345 rt2800_rfcsr_write(rt2x00dev, 59, 3346 r59_non_bt[idx]); 3347 } 3348 } 3349 } 3350 3351 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, 3352 struct ieee80211_conf *conf, 3353 struct rf_channel *rf, 3354 struct channel_info *info) 3355 { 3356 u8 rfcsr, ep_reg; 3357 u32 reg; 3358 int power_bound; 3359 3360 /* TODO */ 3361 const bool is_11b = false; 3362 const bool is_type_ep = false; 3363 3364 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 3365 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3366 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); 3367 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3368 3369 /* Order of values on rf_channel entry: N, K, mod, R */ 3370 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff); 3371 3372 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9); 3373 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf); 3374 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8); 3375 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2); 3376 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr); 3377 3378 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11); 3379 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1); 3380 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3); 3381 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr); 3382 3383 if (rf->channel <= 14) { 3384 rt2800_rfcsr_write(rt2x00dev, 10, 0x90); 3385 /* FIXME: RF11 owerwrite ? */ 3386 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A); 3387 rt2800_rfcsr_write(rt2x00dev, 12, 0x52); 3388 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3389 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3390 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A); 3391 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 3392 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3393 rt2800_rfcsr_write(rt2x00dev, 36, 0x80); 3394 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 3395 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 3396 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B); 3397 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D); 3398 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B); 3399 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5); 3400 rt2800_rfcsr_write(rt2x00dev, 43, 0x72); 3401 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E); 3402 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2); 3403 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B); 3404 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 3405 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E); 3406 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 3407 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 3408 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1); 3409 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 3410 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 3411 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 3412 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 3413 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 3414 3415 /* TODO RF27 <- tssi */ 3416 3417 rfcsr = rf->channel <= 10 ? 0x07 : 0x06; 3418 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 3419 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr); 3420 3421 if (is_11b) { 3422 /* CCK */ 3423 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8); 3424 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0); 3425 if (is_type_ep) 3426 rt2800_rfcsr_write(rt2x00dev, 55, 0x06); 3427 else 3428 rt2800_rfcsr_write(rt2x00dev, 55, 0x47); 3429 } else { 3430 /* OFDM */ 3431 if (is_type_ep) 3432 rt2800_rfcsr_write(rt2x00dev, 55, 0x03); 3433 else 3434 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 3435 } 3436 3437 power_bound = POWER_BOUND; 3438 ep_reg = 0x2; 3439 } else { 3440 rt2800_rfcsr_write(rt2x00dev, 10, 0x97); 3441 /* FIMXE: RF11 overwrite */ 3442 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 3443 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF); 3444 rt2800_rfcsr_write(rt2x00dev, 27, 0x42); 3445 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 3446 rt2800_rfcsr_write(rt2x00dev, 37, 0x04); 3447 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 3448 rt2800_rfcsr_write(rt2x00dev, 40, 0x42); 3449 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB); 3450 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7); 3451 rt2800_rfcsr_write(rt2x00dev, 45, 0x41); 3452 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 3453 rt2800_rfcsr_write(rt2x00dev, 57, 0x77); 3454 rt2800_rfcsr_write(rt2x00dev, 60, 0x05); 3455 rt2800_rfcsr_write(rt2x00dev, 61, 0x01); 3456 3457 /* TODO RF27 <- tssi */ 3458 3459 if (rf->channel >= 36 && rf->channel <= 64) { 3460 3461 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E); 3462 rt2800_rfcsr_write(rt2x00dev, 13, 0x22); 3463 rt2800_rfcsr_write(rt2x00dev, 22, 0x60); 3464 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F); 3465 if (rf->channel <= 50) 3466 rt2800_rfcsr_write(rt2x00dev, 24, 0x09); 3467 else if (rf->channel >= 52) 3468 rt2800_rfcsr_write(rt2x00dev, 24, 0x07); 3469 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C); 3470 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B); 3471 rt2800_rfcsr_write(rt2x00dev, 44, 0X40); 3472 rt2800_rfcsr_write(rt2x00dev, 46, 0X00); 3473 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE); 3474 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C); 3475 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8); 3476 if (rf->channel <= 50) { 3477 rt2800_rfcsr_write(rt2x00dev, 55, 0x06), 3478 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3); 3479 } else if (rf->channel >= 52) { 3480 rt2800_rfcsr_write(rt2x00dev, 55, 0x04); 3481 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3482 } 3483 3484 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3485 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F); 3486 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3487 3488 } else if (rf->channel >= 100 && rf->channel <= 165) { 3489 3490 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E); 3491 rt2800_rfcsr_write(rt2x00dev, 13, 0x42); 3492 rt2800_rfcsr_write(rt2x00dev, 22, 0x40); 3493 if (rf->channel <= 153) { 3494 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C); 3495 rt2800_rfcsr_write(rt2x00dev, 24, 0x06); 3496 } else if (rf->channel >= 155) { 3497 rt2800_rfcsr_write(rt2x00dev, 23, 0x38); 3498 rt2800_rfcsr_write(rt2x00dev, 24, 0x05); 3499 } 3500 if (rf->channel <= 138) { 3501 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A); 3502 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B); 3503 rt2800_rfcsr_write(rt2x00dev, 44, 0x20); 3504 rt2800_rfcsr_write(rt2x00dev, 46, 0x18); 3505 } else if (rf->channel >= 140) { 3506 rt2800_rfcsr_write(rt2x00dev, 39, 0x18); 3507 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B); 3508 rt2800_rfcsr_write(rt2x00dev, 44, 0x10); 3509 rt2800_rfcsr_write(rt2x00dev, 46, 0X08); 3510 } 3511 if (rf->channel <= 124) 3512 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC); 3513 else if (rf->channel >= 126) 3514 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC); 3515 if (rf->channel <= 138) 3516 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3517 else if (rf->channel >= 140) 3518 rt2800_rfcsr_write(rt2x00dev, 52, 0x06); 3519 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB); 3520 if (rf->channel <= 138) 3521 rt2800_rfcsr_write(rt2x00dev, 55, 0x01); 3522 else if (rf->channel >= 140) 3523 rt2800_rfcsr_write(rt2x00dev, 55, 0x00); 3524 if (rf->channel <= 128) 3525 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB); 3526 else if (rf->channel >= 130) 3527 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB); 3528 if (rf->channel <= 116) 3529 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D); 3530 else if (rf->channel >= 118) 3531 rt2800_rfcsr_write(rt2x00dev, 58, 0x15); 3532 if (rf->channel <= 138) 3533 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F); 3534 else if (rf->channel >= 140) 3535 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C); 3536 if (rf->channel <= 116) 3537 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D); 3538 else if (rf->channel >= 118) 3539 rt2800_rfcsr_write(rt2x00dev, 62, 0x15); 3540 } 3541 3542 power_bound = POWER_BOUND_5G; 3543 ep_reg = 0x3; 3544 } 3545 3546 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49); 3547 if (info->default_power1 > power_bound) 3548 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound); 3549 else 3550 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 3551 if (is_type_ep) 3552 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg); 3553 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 3554 3555 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 3556 if (info->default_power2 > power_bound) 3557 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound); 3558 else 3559 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2); 3560 if (is_type_ep) 3561 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg); 3562 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 3563 3564 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3565 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 3566 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 3567 3568 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 3569 rt2x00dev->default_ant.tx_chain_num >= 1); 3570 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 3571 rt2x00dev->default_ant.tx_chain_num == 2); 3572 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); 3573 3574 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 3575 rt2x00dev->default_ant.rx_chain_num >= 1); 3576 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 3577 rt2x00dev->default_ant.rx_chain_num == 2); 3578 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); 3579 3580 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3581 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4); 3582 3583 if (conf_is_ht40(conf)) 3584 rt2800_rfcsr_write(rt2x00dev, 30, 0x16); 3585 else 3586 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 3587 3588 if (!is_11b) { 3589 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 3590 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 3591 } 3592 3593 /* TODO proper frequency adjustment */ 3594 rt2800_freq_cal_mode1(rt2x00dev); 3595 3596 /* TODO merge with others */ 3597 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 3598 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 3599 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 3600 3601 /* BBP settings */ 3602 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 3603 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 3604 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 3605 3606 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18); 3607 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08); 3608 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38); 3609 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92); 3610 3611 /* GLRT band configuration */ 3612 rt2800_bbp_write(rt2x00dev, 195, 128); 3613 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0); 3614 rt2800_bbp_write(rt2x00dev, 195, 129); 3615 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E); 3616 rt2800_bbp_write(rt2x00dev, 195, 130); 3617 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28); 3618 rt2800_bbp_write(rt2x00dev, 195, 131); 3619 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20); 3620 rt2800_bbp_write(rt2x00dev, 195, 133); 3621 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F); 3622 rt2800_bbp_write(rt2x00dev, 195, 124); 3623 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); 3624 } 3625 3626 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev, 3627 struct ieee80211_conf *conf, 3628 struct rf_channel *rf, 3629 struct channel_info *info) 3630 { 3631 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 3632 u8 rx_agc_fc, tx_agc_fc; 3633 u8 rfcsr; 3634 3635 /* Frequeny plan setting */ 3636 /* Rdiv setting (set 0x03 if Xtal==20) 3637 * R13[1:0] 3638 */ 3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13); 3640 rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, 3641 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); 3642 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); 3643 3644 /* N setting 3645 * R20[7:0] in rf->rf1 3646 * R21[0] always 0 3647 */ 3648 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 3649 rfcsr = (rf->rf1 & 0x00ff); 3650 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 3651 3652 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3653 rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); 3654 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3655 3656 /* K setting (always 0) 3657 * R16[3:0] (RF PLL freq selection) 3658 */ 3659 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3660 rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); 3661 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3662 3663 /* D setting (always 0) 3664 * R22[2:0] (D=15, R22[2:0]=<111>) 3665 */ 3666 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 3667 rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); 3668 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3669 3670 /* Ksd setting 3671 * Ksd: R17<7:0> in rf->rf2 3672 * R18<7:0> in rf->rf3 3673 * R19<1:0> in rf->rf4 3674 */ 3675 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 3676 rfcsr = rf->rf2; 3677 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3678 3679 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 3680 rfcsr = rf->rf3; 3681 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 3682 3683 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19); 3684 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); 3685 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); 3686 3687 /* Default: XO=20MHz , SDM mode */ 3688 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16); 3689 rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); 3690 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); 3691 3692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 3693 rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); 3694 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3695 3696 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 3697 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, 3698 rt2x00dev->default_ant.tx_chain_num != 1); 3699 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 3700 3701 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 3702 rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, 3703 rt2x00dev->default_ant.tx_chain_num != 1); 3704 rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, 3705 rt2x00dev->default_ant.rx_chain_num != 1); 3706 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3707 3708 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42); 3709 rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, 3710 rt2x00dev->default_ant.tx_chain_num != 1); 3711 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 3712 3713 /* RF for DC Cal BW */ 3714 if (conf_is_ht40(conf)) { 3715 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 3716 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 3717 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 3718 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 3719 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 3720 } else { 3721 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20); 3722 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20); 3723 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00); 3724 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20); 3725 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20); 3726 } 3727 3728 if (conf_is_ht40(conf)) { 3729 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08); 3730 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08); 3731 } else { 3732 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28); 3733 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28); 3734 } 3735 3736 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28); 3737 rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, 3738 conf_is_ht40(conf) && (rf->channel == 11)); 3739 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); 3740 3741 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { 3742 if (conf_is_ht40(conf)) { 3743 rx_agc_fc = drv_data->rx_calibration_bw40; 3744 tx_agc_fc = drv_data->tx_calibration_bw40; 3745 } else { 3746 rx_agc_fc = drv_data->rx_calibration_bw20; 3747 tx_agc_fc = drv_data->tx_calibration_bw20; 3748 } 3749 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 3750 rfcsr &= (~0x3F); 3751 rfcsr |= rx_agc_fc; 3752 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); 3753 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 3754 rfcsr &= (~0x3F); 3755 rfcsr |= rx_agc_fc; 3756 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); 3757 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6); 3758 rfcsr &= (~0x3F); 3759 rfcsr |= rx_agc_fc; 3760 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); 3761 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7); 3762 rfcsr &= (~0x3F); 3763 rfcsr |= rx_agc_fc; 3764 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); 3765 3766 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 3767 rfcsr &= (~0x3F); 3768 rfcsr |= tx_agc_fc; 3769 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); 3770 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 3771 rfcsr &= (~0x3F); 3772 rfcsr |= tx_agc_fc; 3773 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); 3774 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58); 3775 rfcsr &= (~0x3F); 3776 rfcsr |= tx_agc_fc; 3777 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); 3778 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59); 3779 rfcsr &= (~0x3F); 3780 rfcsr |= tx_agc_fc; 3781 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); 3782 } 3783 } 3784 3785 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, 3786 struct ieee80211_channel *chan, 3787 int power_level) { 3788 u16 eeprom, target_power, max_power; 3789 u32 mac_sys_ctrl, mac_status; 3790 u32 reg; 3791 u8 bbp; 3792 int i; 3793 3794 /* hardware unit is 0.5dBm, limited to 23.5dBm */ 3795 power_level *= 2; 3796 if (power_level > 0x2f) 3797 power_level = 0x2f; 3798 3799 max_power = chan->max_power * 2; 3800 if (max_power > 0x2f) 3801 max_power = 0x2f; 3802 3803 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); 3804 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); 3805 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); 3806 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); 3807 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); 3808 3809 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 3810 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) { 3811 /* init base power by eeprom target power */ 3812 target_power = rt2800_eeprom_read(rt2x00dev, 3813 EEPROM_TXPOWER_INIT); 3814 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); 3815 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); 3816 } 3817 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); 3818 3819 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 3820 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); 3821 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 3822 3823 /* Save MAC SYS CTRL registers */ 3824 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 3825 /* Disable Tx/Rx */ 3826 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 3827 /* Check MAC Tx/Rx idle */ 3828 for (i = 0; i < 10000; i++) { 3829 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 3830 if (mac_status & 0x3) 3831 usleep_range(50, 200); 3832 else 3833 break; 3834 } 3835 3836 if (i == 10000) 3837 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n"); 3838 3839 if (chan->center_freq > 2457) { 3840 bbp = rt2800_bbp_read(rt2x00dev, 30); 3841 bbp = 0x40; 3842 rt2800_bbp_write(rt2x00dev, 30, bbp); 3843 rt2800_rfcsr_write(rt2x00dev, 39, 0); 3844 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3845 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb); 3846 else 3847 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b); 3848 } else { 3849 bbp = rt2800_bbp_read(rt2x00dev, 30); 3850 bbp = 0x1f; 3851 rt2800_bbp_write(rt2x00dev, 30, bbp); 3852 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 3853 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) 3854 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb); 3855 else 3856 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); 3857 } 3858 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl); 3859 3860 rt2800_vco_calibration(rt2x00dev); 3861 } 3862 3863 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, 3864 const unsigned int word, 3865 const u8 value) 3866 { 3867 u8 chain, reg; 3868 3869 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) { 3870 reg = rt2800_bbp_read(rt2x00dev, 27); 3871 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); 3872 rt2800_bbp_write(rt2x00dev, 27, reg); 3873 3874 rt2800_bbp_write(rt2x00dev, word, value); 3875 } 3876 } 3877 3878 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel) 3879 { 3880 u8 cal; 3881 3882 /* TX0 IQ Gain */ 3883 rt2800_bbp_write(rt2x00dev, 158, 0x2c); 3884 if (channel <= 14) 3885 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G); 3886 else if (channel >= 36 && channel <= 64) 3887 cal = rt2x00_eeprom_byte(rt2x00dev, 3888 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G); 3889 else if (channel >= 100 && channel <= 138) 3890 cal = rt2x00_eeprom_byte(rt2x00dev, 3891 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G); 3892 else if (channel >= 140 && channel <= 165) 3893 cal = rt2x00_eeprom_byte(rt2x00dev, 3894 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G); 3895 else 3896 cal = 0; 3897 rt2800_bbp_write(rt2x00dev, 159, cal); 3898 3899 /* TX0 IQ Phase */ 3900 rt2800_bbp_write(rt2x00dev, 158, 0x2d); 3901 if (channel <= 14) 3902 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G); 3903 else if (channel >= 36 && channel <= 64) 3904 cal = rt2x00_eeprom_byte(rt2x00dev, 3905 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G); 3906 else if (channel >= 100 && channel <= 138) 3907 cal = rt2x00_eeprom_byte(rt2x00dev, 3908 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G); 3909 else if (channel >= 140 && channel <= 165) 3910 cal = rt2x00_eeprom_byte(rt2x00dev, 3911 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G); 3912 else 3913 cal = 0; 3914 rt2800_bbp_write(rt2x00dev, 159, cal); 3915 3916 /* TX1 IQ Gain */ 3917 rt2800_bbp_write(rt2x00dev, 158, 0x4a); 3918 if (channel <= 14) 3919 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G); 3920 else if (channel >= 36 && channel <= 64) 3921 cal = rt2x00_eeprom_byte(rt2x00dev, 3922 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G); 3923 else if (channel >= 100 && channel <= 138) 3924 cal = rt2x00_eeprom_byte(rt2x00dev, 3925 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G); 3926 else if (channel >= 140 && channel <= 165) 3927 cal = rt2x00_eeprom_byte(rt2x00dev, 3928 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G); 3929 else 3930 cal = 0; 3931 rt2800_bbp_write(rt2x00dev, 159, cal); 3932 3933 /* TX1 IQ Phase */ 3934 rt2800_bbp_write(rt2x00dev, 158, 0x4b); 3935 if (channel <= 14) 3936 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G); 3937 else if (channel >= 36 && channel <= 64) 3938 cal = rt2x00_eeprom_byte(rt2x00dev, 3939 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G); 3940 else if (channel >= 100 && channel <= 138) 3941 cal = rt2x00_eeprom_byte(rt2x00dev, 3942 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G); 3943 else if (channel >= 140 && channel <= 165) 3944 cal = rt2x00_eeprom_byte(rt2x00dev, 3945 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G); 3946 else 3947 cal = 0; 3948 rt2800_bbp_write(rt2x00dev, 159, cal); 3949 3950 /* FIXME: possible RX0, RX1 callibration ? */ 3951 3952 /* RF IQ compensation control */ 3953 rt2800_bbp_write(rt2x00dev, 158, 0x04); 3954 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL); 3955 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3956 3957 /* RF IQ imbalance compensation control */ 3958 rt2800_bbp_write(rt2x00dev, 158, 0x03); 3959 cal = rt2x00_eeprom_byte(rt2x00dev, 3960 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL); 3961 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0); 3962 } 3963 3964 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev, 3965 unsigned int channel, 3966 char txpower) 3967 { 3968 if (rt2x00_rt(rt2x00dev, RT3593) || 3969 rt2x00_rt(rt2x00dev, RT3883)) 3970 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC); 3971 3972 if (channel <= 14) 3973 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER); 3974 3975 if (rt2x00_rt(rt2x00dev, RT3593) || 3976 rt2x00_rt(rt2x00dev, RT3883)) 3977 return clamp_t(char, txpower, MIN_A_TXPOWER_3593, 3978 MAX_A_TXPOWER_3593); 3979 else 3980 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER); 3981 } 3982 3983 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev, 3984 struct rf_channel *rf) 3985 { 3986 u8 bbp; 3987 3988 bbp = (rf->channel > 14) ? 0x48 : 0x38; 3989 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp); 3990 3991 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3992 3993 if (rf->channel <= 14) { 3994 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 3995 } else { 3996 /* Disable CCK packet detection */ 3997 rt2800_bbp_write(rt2x00dev, 70, 0x00); 3998 } 3999 4000 rt2800_bbp_write(rt2x00dev, 73, 0x10); 4001 4002 if (rf->channel > 14) { 4003 rt2800_bbp_write(rt2x00dev, 62, 0x1d); 4004 rt2800_bbp_write(rt2x00dev, 63, 0x1d); 4005 rt2800_bbp_write(rt2x00dev, 64, 0x1d); 4006 } else { 4007 rt2800_bbp_write(rt2x00dev, 62, 0x2d); 4008 rt2800_bbp_write(rt2x00dev, 63, 0x2d); 4009 rt2800_bbp_write(rt2x00dev, 64, 0x2d); 4010 } 4011 } 4012 4013 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 4014 struct ieee80211_conf *conf, 4015 struct rf_channel *rf, 4016 struct channel_info *info) 4017 { 4018 u32 reg; 4019 u32 tx_pin; 4020 u8 bbp, rfcsr; 4021 4022 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4023 info->default_power1); 4024 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4025 info->default_power2); 4026 if (rt2x00dev->default_ant.tx_chain_num > 2) 4027 info->default_power3 = 4028 rt2800_txpower_to_dev(rt2x00dev, rf->channel, 4029 info->default_power3); 4030 4031 switch (rt2x00dev->chip.rt) { 4032 case RT3883: 4033 rt3883_bbp_adjust(rt2x00dev, rf); 4034 break; 4035 } 4036 4037 switch (rt2x00dev->chip.rf) { 4038 case RF2020: 4039 case RF3020: 4040 case RF3021: 4041 case RF3022: 4042 case RF3320: 4043 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 4044 break; 4045 case RF3052: 4046 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 4047 break; 4048 case RF3053: 4049 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info); 4050 break; 4051 case RF3290: 4052 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 4053 break; 4054 case RF3322: 4055 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); 4056 break; 4057 case RF3853: 4058 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info); 4059 break; 4060 case RF3070: 4061 case RF5350: 4062 case RF5360: 4063 case RF5362: 4064 case RF5370: 4065 case RF5372: 4066 case RF5390: 4067 case RF5392: 4068 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 4069 break; 4070 case RF5592: 4071 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); 4072 break; 4073 case RF7620: 4074 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info); 4075 break; 4076 default: 4077 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 4078 } 4079 4080 if (rt2x00_rf(rt2x00dev, RF3070) || 4081 rt2x00_rf(rt2x00dev, RF3290) || 4082 rt2x00_rf(rt2x00dev, RF3322) || 4083 rt2x00_rf(rt2x00dev, RF5350) || 4084 rt2x00_rf(rt2x00dev, RF5360) || 4085 rt2x00_rf(rt2x00dev, RF5362) || 4086 rt2x00_rf(rt2x00dev, RF5370) || 4087 rt2x00_rf(rt2x00dev, RF5372) || 4088 rt2x00_rf(rt2x00dev, RF5390) || 4089 rt2x00_rf(rt2x00dev, RF5392)) { 4090 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 4091 if (rt2x00_rf(rt2x00dev, RF3322)) { 4092 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M, 4093 conf_is_ht40(conf)); 4094 rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M, 4095 conf_is_ht40(conf)); 4096 } else { 4097 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 4098 conf_is_ht40(conf)); 4099 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 4100 conf_is_ht40(conf)); 4101 } 4102 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 4103 4104 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 4105 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 4106 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 4107 } 4108 4109 /* 4110 * Change BBP settings 4111 */ 4112 4113 if (rt2x00_rt(rt2x00dev, RT3352)) { 4114 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4115 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4116 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4117 4118 rt2800_bbp_write(rt2x00dev, 27, 0x0); 4119 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4120 rt2800_bbp_write(rt2x00dev, 27, 0x20); 4121 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain); 4122 rt2800_bbp_write(rt2x00dev, 86, 0x38); 4123 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 4124 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 4125 if (rf->channel > 14) { 4126 /* Disable CCK Packet detection on 5GHz */ 4127 rt2800_bbp_write(rt2x00dev, 70, 0x00); 4128 } else { 4129 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4130 } 4131 4132 if (conf_is_ht40(conf)) 4133 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4134 else 4135 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4136 4137 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4138 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4139 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4140 rt2800_bbp_write(rt2x00dev, 77, 0x98); 4141 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 4142 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4143 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4144 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4145 4146 if (rt2x00dev->default_ant.rx_chain_num > 1) 4147 rt2800_bbp_write(rt2x00dev, 86, 0x46); 4148 else 4149 rt2800_bbp_write(rt2x00dev, 86, 0); 4150 } else { 4151 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 4152 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 4153 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 4154 rt2800_bbp_write(rt2x00dev, 86, 0); 4155 } 4156 4157 if (rf->channel <= 14) { 4158 if (!rt2x00_rt(rt2x00dev, RT5390) && 4159 !rt2x00_rt(rt2x00dev, RT5392) && 4160 !rt2x00_rt(rt2x00dev, RT6352)) { 4161 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4162 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4163 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4164 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4165 } else { 4166 if (rt2x00_rt(rt2x00dev, RT3593)) 4167 rt2800_bbp_write(rt2x00dev, 82, 0x62); 4168 else 4169 rt2800_bbp_write(rt2x00dev, 82, 0x84); 4170 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4171 } 4172 if (rt2x00_rt(rt2x00dev, RT3593) || 4173 rt2x00_rt(rt2x00dev, RT3883)) 4174 rt2800_bbp_write(rt2x00dev, 83, 0x8a); 4175 } 4176 4177 } else { 4178 if (rt2x00_rt(rt2x00dev, RT3572)) 4179 rt2800_bbp_write(rt2x00dev, 82, 0x94); 4180 else if (rt2x00_rt(rt2x00dev, RT3593) || 4181 rt2x00_rt(rt2x00dev, RT3883)) 4182 rt2800_bbp_write(rt2x00dev, 82, 0x82); 4183 else if (!rt2x00_rt(rt2x00dev, RT6352)) 4184 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 4185 4186 if (rt2x00_rt(rt2x00dev, RT3593) || 4187 rt2x00_rt(rt2x00dev, RT3883)) 4188 rt2800_bbp_write(rt2x00dev, 83, 0x9a); 4189 4190 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) 4191 rt2800_bbp_write(rt2x00dev, 75, 0x46); 4192 else 4193 rt2800_bbp_write(rt2x00dev, 75, 0x50); 4194 } 4195 4196 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); 4197 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); 4198 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); 4199 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); 4200 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 4201 4202 if (rt2x00_rt(rt2x00dev, RT3572)) 4203 rt2800_rfcsr_write(rt2x00dev, 8, 0); 4204 4205 if (rt2x00_rt(rt2x00dev, RT6352)) { 4206 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 4207 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); 4208 } else { 4209 tx_pin = 0; 4210 } 4211 4212 switch (rt2x00dev->default_ant.tx_chain_num) { 4213 case 3: 4214 /* Turn on tertiary PAs */ 4215 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 4216 rf->channel > 14); 4217 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 4218 rf->channel <= 14); 4219 /* fall-through */ 4220 case 2: 4221 /* Turn on secondary PAs */ 4222 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 4223 rf->channel > 14); 4224 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 4225 rf->channel <= 14); 4226 /* fall-through */ 4227 case 1: 4228 /* Turn on primary PAs */ 4229 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 4230 rf->channel > 14); 4231 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) 4232 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 4233 else 4234 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 4235 rf->channel <= 14); 4236 break; 4237 } 4238 4239 switch (rt2x00dev->default_ant.rx_chain_num) { 4240 case 3: 4241 /* Turn on tertiary LNAs */ 4242 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); 4243 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); 4244 /* fall-through */ 4245 case 2: 4246 /* Turn on secondary LNAs */ 4247 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 4248 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 4249 /* fall-through */ 4250 case 1: 4251 /* Turn on primary LNAs */ 4252 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); 4253 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 4254 break; 4255 } 4256 4257 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 4258 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 4259 4260 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 4261 4262 if (rt2x00_rt(rt2x00dev, RT3572)) { 4263 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 4264 4265 /* AGC init */ 4266 if (rf->channel <= 14) 4267 reg = 0x1c + (2 * rt2x00dev->lna_gain); 4268 else 4269 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4270 4271 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4272 } 4273 4274 if (rt2x00_rt(rt2x00dev, RT3593)) { 4275 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 4276 4277 /* Band selection */ 4278 if (rt2x00_is_usb(rt2x00dev) || 4279 rt2x00_is_pcie(rt2x00dev)) { 4280 /* GPIO #8 controls all paths */ 4281 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); 4282 if (rf->channel <= 14) 4283 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); 4284 else 4285 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); 4286 } 4287 4288 /* LNA PE control. */ 4289 if (rt2x00_is_usb(rt2x00dev)) { 4290 /* GPIO #4 controls PE0 and PE1, 4291 * GPIO #7 controls PE2 4292 */ 4293 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4294 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); 4295 4296 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4297 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); 4298 } else if (rt2x00_is_pcie(rt2x00dev)) { 4299 /* GPIO #4 controls PE0, PE1 and PE2 */ 4300 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); 4301 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); 4302 } 4303 4304 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 4305 4306 /* AGC init */ 4307 if (rf->channel <= 14) 4308 reg = 0x1c + 2 * rt2x00dev->lna_gain; 4309 else 4310 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); 4311 4312 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4313 4314 usleep_range(1000, 1500); 4315 } 4316 4317 if (rt2x00_rt(rt2x00dev, RT3883)) { 4318 if (!conf_is_ht40(conf)) 4319 rt2800_bbp_write(rt2x00dev, 105, 0x34); 4320 else 4321 rt2800_bbp_write(rt2x00dev, 105, 0x04); 4322 4323 /* AGC init */ 4324 if (rf->channel <= 14) 4325 reg = 0x2e + rt2x00dev->lna_gain; 4326 else 4327 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3); 4328 4329 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4330 4331 usleep_range(1000, 1500); 4332 } 4333 4334 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { 4335 reg = 0x10; 4336 if (!conf_is_ht40(conf)) { 4337 if (rt2x00_rt(rt2x00dev, RT6352) && 4338 rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 4339 reg |= 0x5; 4340 } else { 4341 reg |= 0xa; 4342 } 4343 } 4344 rt2800_bbp_write(rt2x00dev, 195, 141); 4345 rt2800_bbp_write(rt2x00dev, 196, reg); 4346 4347 /* AGC init. 4348 * Despite the vendor driver using different values here for 4349 * RT6352 chip, we use 0x1c for now. This may have to be changed 4350 * once TSSI got implemented. 4351 */ 4352 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain; 4353 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); 4354 4355 rt2800_iq_calibrate(rt2x00dev, rf->channel); 4356 } 4357 4358 bbp = rt2800_bbp_read(rt2x00dev, 4); 4359 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 4360 rt2800_bbp_write(rt2x00dev, 4, bbp); 4361 4362 bbp = rt2800_bbp_read(rt2x00dev, 3); 4363 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf)); 4364 rt2800_bbp_write(rt2x00dev, 3, bbp); 4365 4366 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 4367 if (conf_is_ht40(conf)) { 4368 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 4369 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 4370 rt2800_bbp_write(rt2x00dev, 73, 0x16); 4371 } else { 4372 rt2800_bbp_write(rt2x00dev, 69, 0x16); 4373 rt2800_bbp_write(rt2x00dev, 70, 0x08); 4374 rt2800_bbp_write(rt2x00dev, 73, 0x11); 4375 } 4376 } 4377 4378 usleep_range(1000, 1500); 4379 4380 /* 4381 * Clear channel statistic counters 4382 */ 4383 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 4384 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 4385 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 4386 4387 /* 4388 * Clear update flag 4389 */ 4390 if (rt2x00_rt(rt2x00dev, RT3352) || 4391 rt2x00_rt(rt2x00dev, RT5350)) { 4392 bbp = rt2800_bbp_read(rt2x00dev, 49); 4393 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0); 4394 rt2800_bbp_write(rt2x00dev, 49, bbp); 4395 } 4396 } 4397 4398 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 4399 { 4400 u8 tssi_bounds[9]; 4401 u8 current_tssi; 4402 u16 eeprom; 4403 u8 step; 4404 int i; 4405 4406 /* 4407 * First check if temperature compensation is supported. 4408 */ 4409 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 4410 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC)) 4411 return 0; 4412 4413 /* 4414 * Read TSSI boundaries for temperature compensation from 4415 * the EEPROM. 4416 * 4417 * Array idx 0 1 2 3 4 5 6 7 8 4418 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4 4419 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00 4420 */ 4421 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 4422 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1); 4423 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4424 EEPROM_TSSI_BOUND_BG1_MINUS4); 4425 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4426 EEPROM_TSSI_BOUND_BG1_MINUS3); 4427 4428 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2); 4429 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4430 EEPROM_TSSI_BOUND_BG2_MINUS2); 4431 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4432 EEPROM_TSSI_BOUND_BG2_MINUS1); 4433 4434 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3); 4435 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4436 EEPROM_TSSI_BOUND_BG3_REF); 4437 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4438 EEPROM_TSSI_BOUND_BG3_PLUS1); 4439 4440 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4); 4441 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4442 EEPROM_TSSI_BOUND_BG4_PLUS2); 4443 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4444 EEPROM_TSSI_BOUND_BG4_PLUS3); 4445 4446 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5); 4447 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4448 EEPROM_TSSI_BOUND_BG5_PLUS4); 4449 4450 step = rt2x00_get_field16(eeprom, 4451 EEPROM_TSSI_BOUND_BG5_AGC_STEP); 4452 } else { 4453 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1); 4454 tssi_bounds[0] = rt2x00_get_field16(eeprom, 4455 EEPROM_TSSI_BOUND_A1_MINUS4); 4456 tssi_bounds[1] = rt2x00_get_field16(eeprom, 4457 EEPROM_TSSI_BOUND_A1_MINUS3); 4458 4459 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2); 4460 tssi_bounds[2] = rt2x00_get_field16(eeprom, 4461 EEPROM_TSSI_BOUND_A2_MINUS2); 4462 tssi_bounds[3] = rt2x00_get_field16(eeprom, 4463 EEPROM_TSSI_BOUND_A2_MINUS1); 4464 4465 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3); 4466 tssi_bounds[4] = rt2x00_get_field16(eeprom, 4467 EEPROM_TSSI_BOUND_A3_REF); 4468 tssi_bounds[5] = rt2x00_get_field16(eeprom, 4469 EEPROM_TSSI_BOUND_A3_PLUS1); 4470 4471 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4); 4472 tssi_bounds[6] = rt2x00_get_field16(eeprom, 4473 EEPROM_TSSI_BOUND_A4_PLUS2); 4474 tssi_bounds[7] = rt2x00_get_field16(eeprom, 4475 EEPROM_TSSI_BOUND_A4_PLUS3); 4476 4477 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5); 4478 tssi_bounds[8] = rt2x00_get_field16(eeprom, 4479 EEPROM_TSSI_BOUND_A5_PLUS4); 4480 4481 step = rt2x00_get_field16(eeprom, 4482 EEPROM_TSSI_BOUND_A5_AGC_STEP); 4483 } 4484 4485 /* 4486 * Check if temperature compensation is supported. 4487 */ 4488 if (tssi_bounds[4] == 0xff || step == 0xff) 4489 return 0; 4490 4491 /* 4492 * Read current TSSI (BBP 49). 4493 */ 4494 current_tssi = rt2800_bbp_read(rt2x00dev, 49); 4495 4496 /* 4497 * Compare TSSI value (BBP49) with the compensation boundaries 4498 * from the EEPROM and increase or decrease tx power. 4499 */ 4500 for (i = 0; i <= 3; i++) { 4501 if (current_tssi > tssi_bounds[i]) 4502 break; 4503 } 4504 4505 if (i == 4) { 4506 for (i = 8; i >= 5; i--) { 4507 if (current_tssi < tssi_bounds[i]) 4508 break; 4509 } 4510 } 4511 4512 return (i - 4) * step; 4513 } 4514 4515 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev, 4516 enum nl80211_band band) 4517 { 4518 u16 eeprom; 4519 u8 comp_en; 4520 u8 comp_type; 4521 int comp_value = 0; 4522 4523 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA); 4524 4525 /* 4526 * HT40 compensation not required. 4527 */ 4528 if (eeprom == 0xffff || 4529 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4530 return 0; 4531 4532 if (band == NL80211_BAND_2GHZ) { 4533 comp_en = rt2x00_get_field16(eeprom, 4534 EEPROM_TXPOWER_DELTA_ENABLE_2G); 4535 if (comp_en) { 4536 comp_type = rt2x00_get_field16(eeprom, 4537 EEPROM_TXPOWER_DELTA_TYPE_2G); 4538 comp_value = rt2x00_get_field16(eeprom, 4539 EEPROM_TXPOWER_DELTA_VALUE_2G); 4540 if (!comp_type) 4541 comp_value = -comp_value; 4542 } 4543 } else { 4544 comp_en = rt2x00_get_field16(eeprom, 4545 EEPROM_TXPOWER_DELTA_ENABLE_5G); 4546 if (comp_en) { 4547 comp_type = rt2x00_get_field16(eeprom, 4548 EEPROM_TXPOWER_DELTA_TYPE_5G); 4549 comp_value = rt2x00_get_field16(eeprom, 4550 EEPROM_TXPOWER_DELTA_VALUE_5G); 4551 if (!comp_type) 4552 comp_value = -comp_value; 4553 } 4554 } 4555 4556 return comp_value; 4557 } 4558 4559 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, 4560 int power_level, int max_power) 4561 { 4562 int delta; 4563 4564 if (rt2x00_has_cap_power_limit(rt2x00dev)) 4565 return 0; 4566 4567 /* 4568 * XXX: We don't know the maximum transmit power of our hardware since 4569 * the EEPROM doesn't expose it. We only know that we are calibrated 4570 * to 100% tx power. 4571 * 4572 * Hence, we assume the regulatory limit that cfg80211 calulated for 4573 * the current channel is our maximum and if we are requested to lower 4574 * the value we just reduce our tx power accordingly. 4575 */ 4576 delta = power_level - max_power; 4577 return min(delta, 0); 4578 } 4579 4580 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, 4581 enum nl80211_band band, int power_level, 4582 u8 txpower, int delta) 4583 { 4584 u16 eeprom; 4585 u8 criterion; 4586 u8 eirp_txpower; 4587 u8 eirp_txpower_criterion; 4588 u8 reg_limit; 4589 4590 if (rt2x00_rt(rt2x00dev, RT3593)) 4591 return min_t(u8, txpower, 0xc); 4592 4593 if (rt2x00_rt(rt2x00dev, RT3883)) 4594 return min_t(u8, txpower, 0xf); 4595 4596 if (rt2x00_has_cap_power_limit(rt2x00dev)) { 4597 /* 4598 * Check if eirp txpower exceed txpower_limit. 4599 * We use OFDM 6M as criterion and its eirp txpower 4600 * is stored at EEPROM_EIRP_MAX_TX_POWER. 4601 * .11b data rate need add additional 4dbm 4602 * when calculating eirp txpower. 4603 */ 4604 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 4605 EEPROM_TXPOWER_BYRATE, 4606 1); 4607 criterion = rt2x00_get_field16(eeprom, 4608 EEPROM_TXPOWER_BYRATE_RATE0); 4609 4610 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 4611 4612 if (band == NL80211_BAND_2GHZ) 4613 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4614 EEPROM_EIRP_MAX_TX_POWER_2GHZ); 4615 else 4616 eirp_txpower_criterion = rt2x00_get_field16(eeprom, 4617 EEPROM_EIRP_MAX_TX_POWER_5GHZ); 4618 4619 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) + 4620 (is_rate_b ? 4 : 0) + delta; 4621 4622 reg_limit = (eirp_txpower > power_level) ? 4623 (eirp_txpower - power_level) : 0; 4624 } else 4625 reg_limit = 0; 4626 4627 txpower = max(0, txpower + delta - reg_limit); 4628 return min_t(u8, txpower, 0xc); 4629 } 4630 4631 4632 enum { 4633 TX_PWR_CFG_0_IDX, 4634 TX_PWR_CFG_1_IDX, 4635 TX_PWR_CFG_2_IDX, 4636 TX_PWR_CFG_3_IDX, 4637 TX_PWR_CFG_4_IDX, 4638 TX_PWR_CFG_5_IDX, 4639 TX_PWR_CFG_6_IDX, 4640 TX_PWR_CFG_7_IDX, 4641 TX_PWR_CFG_8_IDX, 4642 TX_PWR_CFG_9_IDX, 4643 TX_PWR_CFG_0_EXT_IDX, 4644 TX_PWR_CFG_1_EXT_IDX, 4645 TX_PWR_CFG_2_EXT_IDX, 4646 TX_PWR_CFG_3_EXT_IDX, 4647 TX_PWR_CFG_4_EXT_IDX, 4648 TX_PWR_CFG_IDX_COUNT, 4649 }; 4650 4651 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev, 4652 struct ieee80211_channel *chan, 4653 int power_level) 4654 { 4655 u8 txpower; 4656 u16 eeprom; 4657 u32 regs[TX_PWR_CFG_IDX_COUNT]; 4658 unsigned int offset; 4659 enum nl80211_band band = chan->band; 4660 int delta; 4661 int i; 4662 4663 memset(regs, '\0', sizeof(regs)); 4664 4665 /* TODO: adapt TX power reduction from the rt28xx code */ 4666 4667 /* calculate temperature compensation delta */ 4668 delta = rt2800_get_gain_calibration_delta(rt2x00dev); 4669 4670 if (band == NL80211_BAND_5GHZ) 4671 offset = 16; 4672 else 4673 offset = 0; 4674 4675 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 4676 offset += 8; 4677 4678 /* read the next four txpower values */ 4679 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4680 offset); 4681 4682 /* CCK 1MBS,2MBS */ 4683 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4684 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4685 txpower, delta); 4686 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4687 TX_PWR_CFG_0_CCK1_CH0, txpower); 4688 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4689 TX_PWR_CFG_0_CCK1_CH1, txpower); 4690 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4691 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower); 4692 4693 /* CCK 5.5MBS,11MBS */ 4694 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4695 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level, 4696 txpower, delta); 4697 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4698 TX_PWR_CFG_0_CCK5_CH0, txpower); 4699 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4700 TX_PWR_CFG_0_CCK5_CH1, txpower); 4701 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4702 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower); 4703 4704 /* OFDM 6MBS,9MBS */ 4705 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4706 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4707 txpower, delta); 4708 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4709 TX_PWR_CFG_0_OFDM6_CH0, txpower); 4710 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4711 TX_PWR_CFG_0_OFDM6_CH1, txpower); 4712 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4713 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower); 4714 4715 /* OFDM 12MBS,18MBS */ 4716 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4717 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4718 txpower, delta); 4719 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4720 TX_PWR_CFG_0_OFDM12_CH0, txpower); 4721 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], 4722 TX_PWR_CFG_0_OFDM12_CH1, txpower); 4723 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], 4724 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower); 4725 4726 /* read the next four txpower values */ 4727 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4728 offset + 1); 4729 4730 /* OFDM 24MBS,36MBS */ 4731 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4732 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4733 txpower, delta); 4734 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4735 TX_PWR_CFG_1_OFDM24_CH0, txpower); 4736 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4737 TX_PWR_CFG_1_OFDM24_CH1, txpower); 4738 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4739 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower); 4740 4741 /* OFDM 48MBS */ 4742 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4743 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4744 txpower, delta); 4745 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4746 TX_PWR_CFG_1_OFDM48_CH0, txpower); 4747 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4748 TX_PWR_CFG_1_OFDM48_CH1, txpower); 4749 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4750 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower); 4751 4752 /* OFDM 54MBS */ 4753 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4754 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4755 txpower, delta); 4756 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4757 TX_PWR_CFG_7_OFDM54_CH0, txpower); 4758 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4759 TX_PWR_CFG_7_OFDM54_CH1, txpower); 4760 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4761 TX_PWR_CFG_7_OFDM54_CH2, txpower); 4762 4763 /* read the next four txpower values */ 4764 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4765 offset + 2); 4766 4767 /* MCS 0,1 */ 4768 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4769 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4770 txpower, delta); 4771 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4772 TX_PWR_CFG_1_MCS0_CH0, txpower); 4773 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4774 TX_PWR_CFG_1_MCS0_CH1, txpower); 4775 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4776 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower); 4777 4778 /* MCS 2,3 */ 4779 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4780 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4781 txpower, delta); 4782 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4783 TX_PWR_CFG_1_MCS2_CH0, txpower); 4784 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], 4785 TX_PWR_CFG_1_MCS2_CH1, txpower); 4786 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], 4787 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower); 4788 4789 /* MCS 4,5 */ 4790 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4791 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4792 txpower, delta); 4793 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4794 TX_PWR_CFG_2_MCS4_CH0, txpower); 4795 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4796 TX_PWR_CFG_2_MCS4_CH1, txpower); 4797 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4798 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower); 4799 4800 /* MCS 6 */ 4801 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4802 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4803 txpower, delta); 4804 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4805 TX_PWR_CFG_2_MCS6_CH0, txpower); 4806 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4807 TX_PWR_CFG_2_MCS6_CH1, txpower); 4808 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4809 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower); 4810 4811 /* read the next four txpower values */ 4812 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4813 offset + 3); 4814 4815 /* MCS 7 */ 4816 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4817 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4818 txpower, delta); 4819 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4820 TX_PWR_CFG_7_MCS7_CH0, txpower); 4821 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4822 TX_PWR_CFG_7_MCS7_CH1, txpower); 4823 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], 4824 TX_PWR_CFG_7_MCS7_CH2, txpower); 4825 4826 /* MCS 8,9 */ 4827 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4828 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4829 txpower, delta); 4830 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4831 TX_PWR_CFG_2_MCS8_CH0, txpower); 4832 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4833 TX_PWR_CFG_2_MCS8_CH1, txpower); 4834 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4835 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower); 4836 4837 /* MCS 10,11 */ 4838 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4839 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4840 txpower, delta); 4841 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4842 TX_PWR_CFG_2_MCS10_CH0, txpower); 4843 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], 4844 TX_PWR_CFG_2_MCS10_CH1, txpower); 4845 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], 4846 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower); 4847 4848 /* MCS 12,13 */ 4849 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4850 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4851 txpower, delta); 4852 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4853 TX_PWR_CFG_3_MCS12_CH0, txpower); 4854 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4855 TX_PWR_CFG_3_MCS12_CH1, txpower); 4856 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4857 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower); 4858 4859 /* read the next four txpower values */ 4860 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4861 offset + 4); 4862 4863 /* MCS 14 */ 4864 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4865 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4866 txpower, delta); 4867 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4868 TX_PWR_CFG_3_MCS14_CH0, txpower); 4869 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4870 TX_PWR_CFG_3_MCS14_CH1, txpower); 4871 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4872 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower); 4873 4874 /* MCS 15 */ 4875 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4876 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4877 txpower, delta); 4878 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4879 TX_PWR_CFG_8_MCS15_CH0, txpower); 4880 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4881 TX_PWR_CFG_8_MCS15_CH1, txpower); 4882 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4883 TX_PWR_CFG_8_MCS15_CH2, txpower); 4884 4885 /* MCS 16,17 */ 4886 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4887 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4888 txpower, delta); 4889 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4890 TX_PWR_CFG_5_MCS16_CH0, txpower); 4891 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4892 TX_PWR_CFG_5_MCS16_CH1, txpower); 4893 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4894 TX_PWR_CFG_5_MCS16_CH2, txpower); 4895 4896 /* MCS 18,19 */ 4897 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4898 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4899 txpower, delta); 4900 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4901 TX_PWR_CFG_5_MCS18_CH0, txpower); 4902 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4903 TX_PWR_CFG_5_MCS18_CH1, txpower); 4904 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], 4905 TX_PWR_CFG_5_MCS18_CH2, txpower); 4906 4907 /* read the next four txpower values */ 4908 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4909 offset + 5); 4910 4911 /* MCS 20,21 */ 4912 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4913 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4914 txpower, delta); 4915 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4916 TX_PWR_CFG_6_MCS20_CH0, txpower); 4917 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4918 TX_PWR_CFG_6_MCS20_CH1, txpower); 4919 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4920 TX_PWR_CFG_6_MCS20_CH2, txpower); 4921 4922 /* MCS 22 */ 4923 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4924 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4925 txpower, delta); 4926 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4927 TX_PWR_CFG_6_MCS22_CH0, txpower); 4928 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4929 TX_PWR_CFG_6_MCS22_CH1, txpower); 4930 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], 4931 TX_PWR_CFG_6_MCS22_CH2, txpower); 4932 4933 /* MCS 23 */ 4934 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4935 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4936 txpower, delta); 4937 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4938 TX_PWR_CFG_8_MCS23_CH0, txpower); 4939 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4940 TX_PWR_CFG_8_MCS23_CH1, txpower); 4941 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], 4942 TX_PWR_CFG_8_MCS23_CH2, txpower); 4943 4944 /* read the next four txpower values */ 4945 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4946 offset + 6); 4947 4948 /* STBC, MCS 0,1 */ 4949 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4950 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4951 txpower, delta); 4952 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4953 TX_PWR_CFG_3_STBC0_CH0, txpower); 4954 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4955 TX_PWR_CFG_3_STBC0_CH1, txpower); 4956 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4957 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower); 4958 4959 /* STBC, MCS 2,3 */ 4960 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1); 4961 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4962 txpower, delta); 4963 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4964 TX_PWR_CFG_3_STBC2_CH0, txpower); 4965 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], 4966 TX_PWR_CFG_3_STBC2_CH1, txpower); 4967 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], 4968 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower); 4969 4970 /* STBC, MCS 4,5 */ 4971 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2); 4972 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4973 txpower, delta); 4974 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); 4975 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); 4976 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, 4977 txpower); 4978 4979 /* STBC, MCS 6 */ 4980 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3); 4981 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4982 txpower, delta); 4983 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); 4984 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); 4985 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, 4986 txpower); 4987 4988 /* read the next four txpower values */ 4989 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, 4990 offset + 7); 4991 4992 /* STBC, MCS 7 */ 4993 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0); 4994 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level, 4995 txpower, delta); 4996 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4997 TX_PWR_CFG_9_STBC7_CH0, txpower); 4998 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 4999 TX_PWR_CFG_9_STBC7_CH1, txpower); 5000 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], 5001 TX_PWR_CFG_9_STBC7_CH2, txpower); 5002 5003 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]); 5004 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]); 5005 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]); 5006 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]); 5007 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]); 5008 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]); 5009 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]); 5010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]); 5011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]); 5012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]); 5013 5014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT, 5015 regs[TX_PWR_CFG_0_EXT_IDX]); 5016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT, 5017 regs[TX_PWR_CFG_1_EXT_IDX]); 5018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT, 5019 regs[TX_PWR_CFG_2_EXT_IDX]); 5020 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT, 5021 regs[TX_PWR_CFG_3_EXT_IDX]); 5022 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT, 5023 regs[TX_PWR_CFG_4_EXT_IDX]); 5024 5025 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++) 5026 rt2x00_dbg(rt2x00dev, 5027 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n", 5028 (band == NL80211_BAND_5GHZ) ? '5' : '2', 5029 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ? 5030 '4' : '2', 5031 (i > TX_PWR_CFG_9_IDX) ? 5032 (i - TX_PWR_CFG_9_IDX - 1) : i, 5033 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "", 5034 (unsigned long) regs[i]); 5035 } 5036 5037 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, 5038 struct ieee80211_channel *chan, 5039 int power_level) 5040 { 5041 u32 reg, pwreg; 5042 u16 eeprom; 5043 u32 data, gdata; 5044 u8 t, i; 5045 enum nl80211_band band = chan->band; 5046 int delta; 5047 5048 /* Warn user if bw_comp is set in EEPROM */ 5049 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5050 5051 if (delta) 5052 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", 5053 delta); 5054 5055 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit 5056 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor 5057 * driver does as well, though it looks kinda wrong. 5058 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe 5059 * the hardware has a problem handling 0x20, and as the code initially 5060 * used a fixed offset between HT20 and HT40 rates they had to work- 5061 * around that issue and most likely just forgot about it later on. 5062 * Maybe we should use rt2800_get_txpower_bw_comp() here as well, 5063 * however, the corresponding EEPROM value is not respected by the 5064 * vendor driver, so maybe this is rather being taken care of the 5065 * TXALC and the driver doesn't need to handle it...? 5066 * Though this is all very awkward, just do as they did, as that's what 5067 * board vendors expected when they populated the EEPROM... 5068 */ 5069 for (i = 0; i < 5; i++) { 5070 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5071 EEPROM_TXPOWER_BYRATE, 5072 i * 2); 5073 5074 data = eeprom; 5075 5076 t = eeprom & 0x3f; 5077 if (t == 32) 5078 t++; 5079 5080 gdata = t; 5081 5082 t = (eeprom & 0x3f00) >> 8; 5083 if (t == 32) 5084 t++; 5085 5086 gdata |= (t << 8); 5087 5088 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5089 EEPROM_TXPOWER_BYRATE, 5090 (i * 2) + 1); 5091 5092 t = eeprom & 0x3f; 5093 if (t == 32) 5094 t++; 5095 5096 gdata |= (t << 16); 5097 5098 t = (eeprom & 0x3f00) >> 8; 5099 if (t == 32) 5100 t++; 5101 5102 gdata |= (t << 24); 5103 data |= (eeprom << 16); 5104 5105 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) { 5106 /* HT20 */ 5107 if (data != 0xffffffff) 5108 rt2800_register_write(rt2x00dev, 5109 TX_PWR_CFG_0 + (i * 4), 5110 data); 5111 } else { 5112 /* HT40 */ 5113 if (gdata != 0xffffffff) 5114 rt2800_register_write(rt2x00dev, 5115 TX_PWR_CFG_0 + (i * 4), 5116 gdata); 5117 } 5118 } 5119 5120 /* Aparently Ralink ran out of space in the BYRATE calibration section 5121 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x 5122 * registers. As recent 2T chips use 8-bit instead of 4-bit values for 5123 * power-offsets more space would be needed. Ralink decided to keep the 5124 * EEPROM layout untouched and rather have some shared values covering 5125 * multiple bitrates. 5126 * Populate the registers not covered by the EEPROM in the same way the 5127 * vendor driver does. 5128 */ 5129 5130 /* For OFDM 54MBS use value from OFDM 48MBS */ 5131 pwreg = 0; 5132 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); 5133 t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); 5134 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); 5135 5136 /* For MCS 7 use value from MCS 6 */ 5137 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); 5138 t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); 5139 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); 5140 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); 5141 5142 /* For MCS 15 use value from MCS 14 */ 5143 pwreg = 0; 5144 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); 5145 t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); 5146 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); 5147 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); 5148 5149 /* For STBC MCS 7 use value from STBC MCS 6 */ 5150 pwreg = 0; 5151 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); 5152 t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); 5153 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); 5154 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); 5155 5156 rt2800_config_alc(rt2x00dev, chan, power_level); 5157 5158 /* TODO: temperature compensation code! */ 5159 } 5160 5161 /* 5162 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and 5163 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, 5164 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power 5165 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm. 5166 * Reference per rate transmit power values are located in the EEPROM at 5167 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to 5168 * current conditions (i.e. band, bandwidth, temperature, user settings). 5169 */ 5170 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, 5171 struct ieee80211_channel *chan, 5172 int power_level) 5173 { 5174 u8 txpower, r1; 5175 u16 eeprom; 5176 u32 reg, offset; 5177 int i, is_rate_b, delta, power_ctrl; 5178 enum nl80211_band band = chan->band; 5179 5180 /* 5181 * Calculate HT40 compensation. For 40MHz we need to add or subtract 5182 * value read from EEPROM (different for 2GHz and for 5GHz). 5183 */ 5184 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band); 5185 5186 /* 5187 * Calculate temperature compensation. Depends on measurement of current 5188 * TSSI (Transmitter Signal Strength Indication) we know TX power (due 5189 * to temperature or maybe other factors) is smaller or bigger than 5190 * expected. We adjust it, based on TSSI reference and boundaries values 5191 * provided in EEPROM. 5192 */ 5193 switch (rt2x00dev->chip.rt) { 5194 case RT2860: 5195 case RT2872: 5196 case RT2883: 5197 case RT3070: 5198 case RT3071: 5199 case RT3090: 5200 case RT3572: 5201 delta += rt2800_get_gain_calibration_delta(rt2x00dev); 5202 break; 5203 default: 5204 /* TODO: temperature compensation code for other chips. */ 5205 break; 5206 } 5207 5208 /* 5209 * Decrease power according to user settings, on devices with unknown 5210 * maximum tx power. For other devices we take user power_level into 5211 * consideration on rt2800_compensate_txpower(). 5212 */ 5213 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level, 5214 chan->max_power); 5215 5216 /* 5217 * BBP_R1 controls TX power for all rates, it allow to set the following 5218 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively. 5219 * 5220 * TODO: we do not use +6 dBm option to do not increase power beyond 5221 * regulatory limit, however this could be utilized for devices with 5222 * CAPABILITY_POWER_LIMIT. 5223 */ 5224 if (delta <= -12) { 5225 power_ctrl = 2; 5226 delta += 12; 5227 } else if (delta <= -6) { 5228 power_ctrl = 1; 5229 delta += 6; 5230 } else { 5231 power_ctrl = 0; 5232 } 5233 r1 = rt2800_bbp_read(rt2x00dev, 1); 5234 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl); 5235 rt2800_bbp_write(rt2x00dev, 1, r1); 5236 5237 offset = TX_PWR_CFG_0; 5238 5239 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 5240 /* just to be safe */ 5241 if (offset > TX_PWR_CFG_4) 5242 break; 5243 5244 reg = rt2800_register_read(rt2x00dev, offset); 5245 5246 /* read the next four txpower values */ 5247 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5248 EEPROM_TXPOWER_BYRATE, 5249 i); 5250 5251 is_rate_b = i ? 0 : 1; 5252 /* 5253 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 5254 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 5255 * TX_PWR_CFG_4: unknown 5256 */ 5257 txpower = rt2x00_get_field16(eeprom, 5258 EEPROM_TXPOWER_BYRATE_RATE0); 5259 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5260 power_level, txpower, delta); 5261 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); 5262 5263 /* 5264 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 5265 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 5266 * TX_PWR_CFG_4: unknown 5267 */ 5268 txpower = rt2x00_get_field16(eeprom, 5269 EEPROM_TXPOWER_BYRATE_RATE1); 5270 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5271 power_level, txpower, delta); 5272 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); 5273 5274 /* 5275 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS, 5276 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 5277 * TX_PWR_CFG_4: unknown 5278 */ 5279 txpower = rt2x00_get_field16(eeprom, 5280 EEPROM_TXPOWER_BYRATE_RATE2); 5281 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5282 power_level, txpower, delta); 5283 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); 5284 5285 /* 5286 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 5287 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 5288 * TX_PWR_CFG_4: unknown 5289 */ 5290 txpower = rt2x00_get_field16(eeprom, 5291 EEPROM_TXPOWER_BYRATE_RATE3); 5292 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5293 power_level, txpower, delta); 5294 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); 5295 5296 /* read the next four txpower values */ 5297 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 5298 EEPROM_TXPOWER_BYRATE, 5299 i + 1); 5300 5301 is_rate_b = 0; 5302 /* 5303 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 5304 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 5305 * TX_PWR_CFG_4: unknown 5306 */ 5307 txpower = rt2x00_get_field16(eeprom, 5308 EEPROM_TXPOWER_BYRATE_RATE0); 5309 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5310 power_level, txpower, delta); 5311 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); 5312 5313 /* 5314 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 5315 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 5316 * TX_PWR_CFG_4: unknown 5317 */ 5318 txpower = rt2x00_get_field16(eeprom, 5319 EEPROM_TXPOWER_BYRATE_RATE1); 5320 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5321 power_level, txpower, delta); 5322 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); 5323 5324 /* 5325 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 5326 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 5327 * TX_PWR_CFG_4: unknown 5328 */ 5329 txpower = rt2x00_get_field16(eeprom, 5330 EEPROM_TXPOWER_BYRATE_RATE2); 5331 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5332 power_level, txpower, delta); 5333 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); 5334 5335 /* 5336 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 5337 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 5338 * TX_PWR_CFG_4: unknown 5339 */ 5340 txpower = rt2x00_get_field16(eeprom, 5341 EEPROM_TXPOWER_BYRATE_RATE3); 5342 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band, 5343 power_level, txpower, delta); 5344 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); 5345 5346 rt2800_register_write(rt2x00dev, offset, reg); 5347 5348 /* next TX_PWR_CFG register */ 5349 offset += 4; 5350 } 5351 } 5352 5353 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 5354 struct ieee80211_channel *chan, 5355 int power_level) 5356 { 5357 if (rt2x00_rt(rt2x00dev, RT3593) || 5358 rt2x00_rt(rt2x00dev, RT3883)) 5359 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); 5360 else if (rt2x00_rt(rt2x00dev, RT6352)) 5361 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); 5362 else 5363 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); 5364 } 5365 5366 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 5367 { 5368 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan, 5369 rt2x00dev->tx_power); 5370 } 5371 EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 5372 5373 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) 5374 { 5375 u32 tx_pin; 5376 u8 rfcsr; 5377 unsigned long min_sleep = 0; 5378 5379 /* 5380 * A voltage-controlled oscillator(VCO) is an electronic oscillator 5381 * designed to be controlled in oscillation frequency by a voltage 5382 * input. Maybe the temperature will affect the frequency of 5383 * oscillation to be shifted. The VCO calibration will be called 5384 * periodically to adjust the frequency to be precision. 5385 */ 5386 5387 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5388 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; 5389 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5390 5391 switch (rt2x00dev->chip.rf) { 5392 case RF2020: 5393 case RF3020: 5394 case RF3021: 5395 case RF3022: 5396 case RF3320: 5397 case RF3052: 5398 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7); 5399 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 5400 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 5401 break; 5402 case RF3053: 5403 case RF3070: 5404 case RF3290: 5405 case RF3853: 5406 case RF5350: 5407 case RF5360: 5408 case RF5362: 5409 case RF5370: 5410 case RF5372: 5411 case RF5390: 5412 case RF5392: 5413 case RF5592: 5414 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3); 5415 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); 5416 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); 5417 min_sleep = 1000; 5418 break; 5419 case RF7620: 5420 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 5421 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 5422 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4); 5423 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1); 5424 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr); 5425 min_sleep = 2000; 5426 break; 5427 default: 5428 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration", 5429 rt2x00dev->chip.rf); 5430 return; 5431 } 5432 5433 if (min_sleep > 0) 5434 usleep_range(min_sleep, min_sleep * 2); 5435 5436 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); 5437 if (rt2x00dev->rf_channel <= 14) { 5438 switch (rt2x00dev->default_ant.tx_chain_num) { 5439 case 3: 5440 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); 5441 /* fall through */ 5442 case 2: 5443 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 5444 /* fall through */ 5445 case 1: 5446 default: 5447 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); 5448 break; 5449 } 5450 } else { 5451 switch (rt2x00dev->default_ant.tx_chain_num) { 5452 case 3: 5453 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); 5454 /* fall through */ 5455 case 2: 5456 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 5457 /* fall through */ 5458 case 1: 5459 default: 5460 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); 5461 break; 5462 } 5463 } 5464 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 5465 5466 if (rt2x00_rt(rt2x00dev, RT6352)) { 5467 if (rt2x00dev->default_ant.rx_chain_num == 1) { 5468 rt2800_bbp_write(rt2x00dev, 91, 0x07); 5469 rt2800_bbp_write(rt2x00dev, 95, 0x1A); 5470 rt2800_bbp_write(rt2x00dev, 195, 128); 5471 rt2800_bbp_write(rt2x00dev, 196, 0xA0); 5472 rt2800_bbp_write(rt2x00dev, 195, 170); 5473 rt2800_bbp_write(rt2x00dev, 196, 0x12); 5474 rt2800_bbp_write(rt2x00dev, 195, 171); 5475 rt2800_bbp_write(rt2x00dev, 196, 0x10); 5476 } else { 5477 rt2800_bbp_write(rt2x00dev, 91, 0x06); 5478 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 5479 rt2800_bbp_write(rt2x00dev, 195, 128); 5480 rt2800_bbp_write(rt2x00dev, 196, 0xE0); 5481 rt2800_bbp_write(rt2x00dev, 195, 170); 5482 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5483 rt2800_bbp_write(rt2x00dev, 195, 171); 5484 rt2800_bbp_write(rt2x00dev, 196, 0x30); 5485 } 5486 5487 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { 5488 rt2800_bbp_write(rt2x00dev, 75, 0x68); 5489 rt2800_bbp_write(rt2x00dev, 76, 0x4C); 5490 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 5491 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 5492 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 5493 } 5494 5495 /* On 11A, We should delay and wait RF/BBP to be stable 5496 * and the appropriate time should be 1000 micro seconds 5497 * 2005/06/05 - On 11G, we also need this delay time. 5498 * Otherwise it's difficult to pass the WHQL. 5499 */ 5500 usleep_range(1000, 1500); 5501 } 5502 } 5503 EXPORT_SYMBOL_GPL(rt2800_vco_calibration); 5504 5505 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, 5506 struct rt2x00lib_conf *libconf) 5507 { 5508 u32 reg; 5509 5510 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5511 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 5512 libconf->conf->short_frame_max_tx_count); 5513 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 5514 libconf->conf->long_frame_max_tx_count); 5515 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5516 } 5517 5518 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, 5519 struct rt2x00lib_conf *libconf) 5520 { 5521 enum dev_state state = 5522 (libconf->conf->flags & IEEE80211_CONF_PS) ? 5523 STATE_SLEEP : STATE_AWAKE; 5524 u32 reg; 5525 5526 if (state == STATE_SLEEP) { 5527 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 5528 5529 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5530 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 5531 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 5532 libconf->conf->listen_interval - 1); 5533 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); 5534 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5535 5536 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5537 } else { 5538 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); 5539 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 5540 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 5541 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); 5542 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 5543 5544 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 5545 } 5546 } 5547 5548 void rt2800_config(struct rt2x00_dev *rt2x00dev, 5549 struct rt2x00lib_conf *libconf, 5550 const unsigned int flags) 5551 { 5552 /* Always recalculate LNA gain before changing configuration */ 5553 rt2800_config_lna_gain(rt2x00dev, libconf); 5554 5555 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 5556 rt2800_config_channel(rt2x00dev, libconf->conf, 5557 &libconf->rf, &libconf->channel); 5558 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5559 libconf->conf->power_level); 5560 } 5561 if (flags & IEEE80211_CONF_CHANGE_POWER) 5562 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan, 5563 libconf->conf->power_level); 5564 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 5565 rt2800_config_retry_limit(rt2x00dev, libconf); 5566 if (flags & IEEE80211_CONF_CHANGE_PS) 5567 rt2800_config_ps(rt2x00dev, libconf); 5568 } 5569 EXPORT_SYMBOL_GPL(rt2800_config); 5570 5571 /* 5572 * Link tuning 5573 */ 5574 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5575 { 5576 u32 reg; 5577 5578 /* 5579 * Update FCS error count from register. 5580 */ 5581 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 5582 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 5583 } 5584 EXPORT_SYMBOL_GPL(rt2800_link_stats); 5585 5586 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 5587 { 5588 u8 vgc; 5589 5590 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) { 5591 if (rt2x00_rt(rt2x00dev, RT3070) || 5592 rt2x00_rt(rt2x00dev, RT3071) || 5593 rt2x00_rt(rt2x00dev, RT3090) || 5594 rt2x00_rt(rt2x00dev, RT3290) || 5595 rt2x00_rt(rt2x00dev, RT3390) || 5596 rt2x00_rt(rt2x00dev, RT3572) || 5597 rt2x00_rt(rt2x00dev, RT3593) || 5598 rt2x00_rt(rt2x00dev, RT5390) || 5599 rt2x00_rt(rt2x00dev, RT5392) || 5600 rt2x00_rt(rt2x00dev, RT5592) || 5601 rt2x00_rt(rt2x00dev, RT6352)) 5602 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 5603 else 5604 vgc = 0x2e + rt2x00dev->lna_gain; 5605 } else { /* 5GHZ band */ 5606 if (rt2x00_rt(rt2x00dev, RT3593) || 5607 rt2x00_rt(rt2x00dev, RT3883)) 5608 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; 5609 else if (rt2x00_rt(rt2x00dev, RT5592)) 5610 vgc = 0x24 + (2 * rt2x00dev->lna_gain); 5611 else { 5612 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 5613 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 5614 else 5615 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3; 5616 } 5617 } 5618 5619 return vgc; 5620 } 5621 5622 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, 5623 struct link_qual *qual, u8 vgc_level) 5624 { 5625 if (qual->vgc_level != vgc_level) { 5626 if (rt2x00_rt(rt2x00dev, RT3572) || 5627 rt2x00_rt(rt2x00dev, RT3593) || 5628 rt2x00_rt(rt2x00dev, RT3883)) { 5629 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, 5630 vgc_level); 5631 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5632 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); 5633 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); 5634 } else { 5635 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 5636 } 5637 5638 qual->vgc_level = vgc_level; 5639 qual->vgc_level_reg = vgc_level; 5640 } 5641 } 5642 5643 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) 5644 { 5645 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev)); 5646 } 5647 EXPORT_SYMBOL_GPL(rt2800_reset_tuner); 5648 5649 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 5650 const u32 count) 5651 { 5652 u8 vgc; 5653 5654 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 5655 return; 5656 5657 /* When RSSI is better than a certain threshold, increase VGC 5658 * with a chip specific value in order to improve the balance 5659 * between sensibility and noise isolation. 5660 */ 5661 5662 vgc = rt2800_get_default_vgc(rt2x00dev); 5663 5664 switch (rt2x00dev->chip.rt) { 5665 case RT3572: 5666 case RT3593: 5667 if (qual->rssi > -65) { 5668 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) 5669 vgc += 0x20; 5670 else 5671 vgc += 0x10; 5672 } 5673 break; 5674 5675 case RT3883: 5676 if (qual->rssi > -65) 5677 vgc += 0x10; 5678 break; 5679 5680 case RT5592: 5681 if (qual->rssi > -65) 5682 vgc += 0x20; 5683 break; 5684 5685 default: 5686 if (qual->rssi > -80) 5687 vgc += 0x10; 5688 break; 5689 } 5690 5691 rt2800_set_vgc(rt2x00dev, qual, vgc); 5692 } 5693 EXPORT_SYMBOL_GPL(rt2800_link_tuner); 5694 5695 /* 5696 * Initialization functions. 5697 */ 5698 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 5699 { 5700 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5701 u32 reg; 5702 u16 eeprom; 5703 unsigned int i; 5704 int ret; 5705 5706 rt2800_disable_wpdma(rt2x00dev); 5707 5708 ret = rt2800_drv_init_registers(rt2x00dev); 5709 if (ret) 5710 return ret; 5711 5712 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5713 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 5714 5715 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 5716 5717 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); 5718 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); 5719 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); 5720 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); 5721 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); 5722 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); 5723 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 5724 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 5725 5726 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); 5727 5728 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); 5729 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); 5730 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 5731 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 5732 5733 if (rt2x00_rt(rt2x00dev, RT3290)) { 5734 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); 5735 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { 5736 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); 5737 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); 5738 } 5739 5740 reg = rt2800_register_read(rt2x00dev, CMB_CTRL); 5741 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { 5742 rt2x00_set_field32(®, LDO0_EN, 1); 5743 rt2x00_set_field32(®, LDO_BGSEL, 3); 5744 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); 5745 } 5746 5747 reg = rt2800_register_read(rt2x00dev, OSC_CTRL); 5748 rt2x00_set_field32(®, OSC_ROSC_EN, 1); 5749 rt2x00_set_field32(®, OSC_CAL_REQ, 1); 5750 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); 5751 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); 5752 5753 reg = rt2800_register_read(rt2x00dev, COEX_CFG0); 5754 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); 5755 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); 5756 5757 reg = rt2800_register_read(rt2x00dev, COEX_CFG2); 5758 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); 5759 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); 5760 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); 5761 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); 5762 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); 5763 5764 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); 5765 rt2x00_set_field32(®, PLL_CONTROL, 1); 5766 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); 5767 } 5768 5769 if (rt2x00_rt(rt2x00dev, RT3071) || 5770 rt2x00_rt(rt2x00dev, RT3090) || 5771 rt2x00_rt(rt2x00dev, RT3290) || 5772 rt2x00_rt(rt2x00dev, RT3390)) { 5773 5774 if (rt2x00_rt(rt2x00dev, RT3290)) 5775 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5776 0x00000404); 5777 else 5778 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 5779 0x00000400); 5780 5781 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5782 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 5783 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 5784 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 5785 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5786 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 5787 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5788 0x0000002c); 5789 else 5790 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5791 0x0000000f); 5792 } else { 5793 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5794 } 5795 } else if (rt2x00_rt(rt2x00dev, RT3070)) { 5796 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5797 5798 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 5799 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5800 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c); 5801 } else { 5802 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5803 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5804 } 5805 } else if (rt2800_is_305x_soc(rt2x00dev)) { 5806 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5807 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5808 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 5809 } else if (rt2x00_rt(rt2x00dev, RT3352)) { 5810 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5811 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5812 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5813 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 5814 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 5815 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5816 } else if (rt2x00_rt(rt2x00dev, RT3593)) { 5817 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5818 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5819 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) { 5820 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 5821 if (rt2x00_get_field16(eeprom, 5822 EEPROM_NIC_CONF1_DAC_TEST)) 5823 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5824 0x0000001f); 5825 else 5826 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5827 0x0000000f); 5828 } else { 5829 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 5830 0x00000000); 5831 } 5832 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5833 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5834 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5835 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); 5836 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); 5837 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); 5838 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5839 rt2x00_rt(rt2x00dev, RT5392)) { 5840 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5841 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5842 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5843 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5844 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5845 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5846 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5847 } else if (rt2x00_rt(rt2x00dev, RT5350)) { 5848 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5849 } else if (rt2x00_rt(rt2x00dev, RT6352)) { 5850 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); 5851 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); 5852 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5853 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000); 5854 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0); 5855 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0); 5856 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C); 5857 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C); 5858 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 5859 0x3630363A); 5860 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 5861 0x3630363A); 5862 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 5863 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 5864 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 5865 } else { 5866 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5867 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5868 } 5869 5870 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); 5871 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5872 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5873 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5874 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5875 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5876 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5877 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5878 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5879 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5880 5881 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); 5882 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5883 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5884 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5885 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5886 5887 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); 5888 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5889 if (rt2x00_is_usb(rt2x00dev)) { 5890 drv_data->max_psdu = 3; 5891 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5892 rt2x00_rt(rt2x00dev, RT2883) || 5893 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5894 drv_data->max_psdu = 2; 5895 } else { 5896 drv_data->max_psdu = 1; 5897 } 5898 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); 5899 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5900 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5901 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5902 5903 reg = rt2800_register_read(rt2x00dev, LED_CFG); 5904 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5905 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5906 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5907 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5908 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5909 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5910 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5911 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5912 5913 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5914 5915 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); 5916 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); 5917 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); 5918 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5919 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5920 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5921 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5922 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5923 5924 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); 5925 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5926 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5927 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5928 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5929 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5930 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5931 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5932 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5933 5934 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 5935 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5936 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5937 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5938 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5939 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5940 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5941 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5942 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5943 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5944 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5945 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5946 5947 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 5948 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5949 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5950 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5951 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5952 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5953 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5954 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5955 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5956 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5957 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5958 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5959 5960 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 5961 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5962 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5963 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5964 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5965 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5966 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5967 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5968 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5969 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5970 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5971 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5972 5973 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 5974 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5975 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5976 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5977 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5978 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5979 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5980 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5981 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5982 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5983 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5984 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5985 5986 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 5987 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5988 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5989 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5990 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5991 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5992 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5993 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5994 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5995 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5996 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5997 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5998 5999 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 6000 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 6001 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 6002 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 6003 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 6004 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 6005 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 6006 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 6007 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 6008 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 6009 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 6010 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 6011 6012 if (rt2x00_is_usb(rt2x00dev)) { 6013 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 6014 6015 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 6016 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 6017 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 6018 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 6019 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 6020 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 6021 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 6022 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 6023 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 6024 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 6025 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 6026 } 6027 6028 /* 6029 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 6030 * although it is reserved. 6031 */ 6032 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); 6033 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 6034 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 6035 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 6036 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 6037 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 6038 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 6039 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 6040 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 6041 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 6042 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 6043 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 6044 6045 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 6046 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 6047 6048 if (rt2x00_rt(rt2x00dev, RT3883)) { 6049 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); 6050 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); 6051 } 6052 6053 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 6054 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); 6055 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, 6056 IEEE80211_MAX_RTS_THRESHOLD); 6057 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); 6058 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 6059 6060 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 6061 6062 /* 6063 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS 6064 * time should be set to 16. However, the original Ralink driver uses 6065 * 16 for both and indeed using a value of 10 for CCK SIFS results in 6066 * connection problems with 11g + CTS protection. Hence, use the same 6067 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. 6068 */ 6069 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); 6070 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); 6071 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); 6072 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 6073 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); 6074 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 6075 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 6076 6077 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 6078 6079 /* 6080 * ASIC will keep garbage value after boot, clear encryption keys. 6081 */ 6082 for (i = 0; i < 4; i++) 6083 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0); 6084 6085 for (i = 0; i < 256; i++) { 6086 rt2800_config_wcid(rt2x00dev, NULL, i); 6087 rt2800_delete_wcid_attr(rt2x00dev, i); 6088 } 6089 6090 /* 6091 * Clear encryption initialization vectors on start, but keep them 6092 * for watchdog reset. Otherwise we will have wrong IVs and not be 6093 * able to keep connections after reset. 6094 */ 6095 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags)) 6096 for (i = 0; i < 256; i++) 6097 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 6098 6099 /* 6100 * Clear all beacons 6101 */ 6102 for (i = 0; i < 8; i++) 6103 rt2800_clear_beacon_register(rt2x00dev, i); 6104 6105 if (rt2x00_is_usb(rt2x00dev)) { 6106 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6107 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); 6108 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6109 } else if (rt2x00_is_pcie(rt2x00dev)) { 6110 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); 6111 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); 6112 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 6113 } 6114 6115 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); 6116 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); 6117 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); 6118 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); 6119 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); 6120 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); 6121 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); 6122 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); 6123 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); 6124 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); 6125 6126 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); 6127 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); 6128 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); 6129 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); 6130 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); 6131 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); 6132 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); 6133 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); 6134 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); 6135 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); 6136 6137 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); 6138 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); 6139 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); 6140 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); 6141 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); 6142 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); 6143 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); 6144 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); 6145 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); 6146 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); 6147 6148 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); 6149 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); 6150 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); 6151 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); 6152 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); 6153 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); 6154 6155 /* 6156 * Do not force the BA window size, we use the TXWI to set it 6157 */ 6158 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); 6159 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); 6160 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); 6161 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); 6162 6163 /* 6164 * We must clear the error counters. 6165 * These registers are cleared on read, 6166 * so we may pass a useless variable to store the value. 6167 */ 6168 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); 6169 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); 6170 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); 6171 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); 6172 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); 6173 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); 6174 6175 /* 6176 * Setup leadtime for pre tbtt interrupt to 6ms 6177 */ 6178 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); 6179 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); 6180 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); 6181 6182 /* 6183 * Set up channel statistics timer 6184 */ 6185 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); 6186 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); 6187 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); 6188 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); 6189 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); 6190 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); 6191 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); 6192 6193 return 0; 6194 } 6195 6196 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) 6197 { 6198 unsigned int i; 6199 u32 reg; 6200 6201 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6202 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); 6203 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 6204 return 0; 6205 6206 udelay(REGISTER_BUSY_DELAY); 6207 } 6208 6209 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n"); 6210 return -EACCES; 6211 } 6212 6213 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) 6214 { 6215 unsigned int i; 6216 u8 value; 6217 6218 /* 6219 * BBP was enabled after firmware was loaded, 6220 * but we need to reactivate it now. 6221 */ 6222 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 6223 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 6224 msleep(1); 6225 6226 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 6227 value = rt2800_bbp_read(rt2x00dev, 0); 6228 if ((value != 0xff) && (value != 0x00)) 6229 return 0; 6230 udelay(REGISTER_BUSY_DELAY); 6231 } 6232 6233 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); 6234 return -EACCES; 6235 } 6236 6237 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev) 6238 { 6239 u8 value; 6240 6241 value = rt2800_bbp_read(rt2x00dev, 4); 6242 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 6243 rt2800_bbp_write(rt2x00dev, 4, value); 6244 } 6245 6246 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev) 6247 { 6248 rt2800_bbp_write(rt2x00dev, 142, 1); 6249 rt2800_bbp_write(rt2x00dev, 143, 57); 6250 } 6251 6252 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev) 6253 { 6254 static const u8 glrt_table[] = { 6255 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */ 6256 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */ 6257 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */ 6258 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */ 6259 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */ 6260 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */ 6261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */ 6262 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */ 6263 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */ 6264 }; 6265 int i; 6266 6267 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) { 6268 rt2800_bbp_write(rt2x00dev, 195, 128 + i); 6269 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]); 6270 } 6271 }; 6272 6273 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev) 6274 { 6275 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6276 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6277 rt2800_bbp_write(rt2x00dev, 68, 0x0B); 6278 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6279 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6280 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6281 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6282 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6283 rt2800_bbp_write(rt2x00dev, 83, 0x6A); 6284 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6285 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6286 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6287 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6288 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6289 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6290 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6291 } 6292 6293 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev) 6294 { 6295 u16 eeprom; 6296 u8 value; 6297 6298 value = rt2800_bbp_read(rt2x00dev, 138); 6299 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 6300 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 6301 value |= 0x20; 6302 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 6303 value &= ~0x02; 6304 rt2800_bbp_write(rt2x00dev, 138, value); 6305 } 6306 6307 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev) 6308 { 6309 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6310 6311 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6312 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6313 6314 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6315 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6316 6317 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6318 6319 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6320 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6321 6322 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6323 6324 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6325 6326 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6327 6328 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6329 6330 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6331 6332 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6333 6334 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6335 6336 rt2800_bbp_write(rt2x00dev, 105, 0x01); 6337 6338 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6339 } 6340 6341 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev) 6342 { 6343 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6344 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6345 6346 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 6347 rt2800_bbp_write(rt2x00dev, 69, 0x16); 6348 rt2800_bbp_write(rt2x00dev, 73, 0x12); 6349 } else { 6350 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6351 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6352 } 6353 6354 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6355 6356 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6357 6358 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6359 6360 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6361 6362 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 6363 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6364 else 6365 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6366 6367 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6368 6369 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6370 6371 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6372 6373 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6374 6375 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6376 6377 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6378 } 6379 6380 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev) 6381 { 6382 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6383 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6384 6385 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6386 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6387 6388 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6389 6390 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6391 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6392 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6393 6394 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6395 6396 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6397 6398 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6399 6400 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6401 6402 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6403 6404 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6405 6406 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 6407 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 6408 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E)) 6409 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6410 else 6411 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6412 6413 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6414 6415 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6416 6417 if (rt2x00_rt(rt2x00dev, RT3071) || 6418 rt2x00_rt(rt2x00dev, RT3090)) 6419 rt2800_disable_unused_dac_adc(rt2x00dev); 6420 } 6421 6422 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev) 6423 { 6424 u8 value; 6425 6426 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6427 6428 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6429 6430 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6431 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6432 6433 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6434 6435 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6436 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6437 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6438 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6439 6440 rt2800_bbp_write(rt2x00dev, 77, 0x58); 6441 6442 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6443 6444 rt2800_bbp_write(rt2x00dev, 74, 0x0b); 6445 rt2800_bbp_write(rt2x00dev, 79, 0x18); 6446 rt2800_bbp_write(rt2x00dev, 80, 0x09); 6447 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6448 6449 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6450 6451 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6452 6453 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6454 6455 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6456 6457 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6458 6459 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6460 6461 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6462 6463 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6464 6465 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 6466 6467 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6468 6469 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6470 6471 rt2800_bbp_write(rt2x00dev, 67, 0x24); 6472 rt2800_bbp_write(rt2x00dev, 143, 0x04); 6473 rt2800_bbp_write(rt2x00dev, 142, 0x99); 6474 rt2800_bbp_write(rt2x00dev, 150, 0x30); 6475 rt2800_bbp_write(rt2x00dev, 151, 0x2e); 6476 rt2800_bbp_write(rt2x00dev, 152, 0x20); 6477 rt2800_bbp_write(rt2x00dev, 153, 0x34); 6478 rt2800_bbp_write(rt2x00dev, 154, 0x40); 6479 rt2800_bbp_write(rt2x00dev, 155, 0x3b); 6480 rt2800_bbp_write(rt2x00dev, 253, 0x04); 6481 6482 value = rt2800_bbp_read(rt2x00dev, 47); 6483 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1); 6484 rt2800_bbp_write(rt2x00dev, 47, value); 6485 6486 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */ 6487 value = rt2800_bbp_read(rt2x00dev, 3); 6488 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1); 6489 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1); 6490 rt2800_bbp_write(rt2x00dev, 3, value); 6491 } 6492 6493 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev) 6494 { 6495 rt2800_bbp_write(rt2x00dev, 3, 0x00); 6496 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6497 6498 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6499 6500 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6501 6502 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6503 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6504 6505 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6506 6507 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6508 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6509 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6510 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6511 6512 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6513 6514 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6515 6516 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 6517 rt2800_bbp_write(rt2x00dev, 80, 0x08); 6518 rt2800_bbp_write(rt2x00dev, 81, 0x37); 6519 6520 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6521 6522 if (rt2x00_rt(rt2x00dev, RT5350)) { 6523 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6524 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6525 } else { 6526 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6527 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6528 } 6529 6530 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6531 6532 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6533 6534 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6535 6536 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6537 6538 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6539 6540 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6541 6542 if (rt2x00_rt(rt2x00dev, RT5350)) { 6543 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6544 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6545 } else { 6546 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6547 rt2800_bbp_write(rt2x00dev, 106, 0x05); 6548 } 6549 6550 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6551 6552 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6553 6554 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 6555 /* Set ITxBF timeout to 0x9c40=1000msec */ 6556 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6557 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6558 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6559 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6560 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6561 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6562 /* Reprogram the inband interface to put right values in RXWI */ 6563 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6564 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6565 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6566 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6567 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6568 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6569 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6570 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6571 6572 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6573 6574 if (rt2x00_rt(rt2x00dev, RT5350)) { 6575 /* Antenna Software OFDM */ 6576 rt2800_bbp_write(rt2x00dev, 150, 0x40); 6577 /* Antenna Software CCK */ 6578 rt2800_bbp_write(rt2x00dev, 151, 0x30); 6579 rt2800_bbp_write(rt2x00dev, 152, 0xa3); 6580 /* Clear previously selected antenna */ 6581 rt2800_bbp_write(rt2x00dev, 154, 0); 6582 } 6583 } 6584 6585 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev) 6586 { 6587 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6588 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6589 6590 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6591 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6592 6593 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6594 6595 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6596 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6597 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6598 6599 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6600 6601 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6602 6603 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6604 6605 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6606 6607 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6608 6609 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6610 6611 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E)) 6612 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6613 else 6614 rt2800_bbp_write(rt2x00dev, 103, 0x00); 6615 6616 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6617 6618 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6619 6620 rt2800_disable_unused_dac_adc(rt2x00dev); 6621 } 6622 6623 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev) 6624 { 6625 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6626 6627 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6628 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6629 6630 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6631 rt2800_bbp_write(rt2x00dev, 73, 0x10); 6632 6633 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6634 6635 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6636 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6637 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6638 6639 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6640 6641 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 6642 6643 rt2800_bbp_write(rt2x00dev, 84, 0x99); 6644 6645 rt2800_bbp_write(rt2x00dev, 86, 0x00); 6646 6647 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6648 6649 rt2800_bbp_write(rt2x00dev, 92, 0x00); 6650 6651 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6652 6653 rt2800_bbp_write(rt2x00dev, 105, 0x05); 6654 6655 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6656 6657 rt2800_disable_unused_dac_adc(rt2x00dev); 6658 } 6659 6660 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev) 6661 { 6662 rt2800_init_bbp_early(rt2x00dev); 6663 6664 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6665 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6666 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6667 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6668 6669 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6670 6671 /* Enable DC filter */ 6672 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E)) 6673 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6674 } 6675 6676 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev) 6677 { 6678 rt2800_init_bbp_early(rt2x00dev); 6679 6680 rt2800_bbp_write(rt2x00dev, 4, 0x50); 6681 rt2800_bbp_write(rt2x00dev, 47, 0x48); 6682 6683 rt2800_bbp_write(rt2x00dev, 86, 0x46); 6684 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6685 6686 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6687 6688 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6689 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6690 rt2800_bbp_write(rt2x00dev, 105, 0x34); 6691 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6692 rt2800_bbp_write(rt2x00dev, 120, 0x50); 6693 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 6694 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 6695 6696 /* Set ITxBF timeout to 0x9C40=1000msec */ 6697 rt2800_bbp_write(rt2x00dev, 179, 0x02); 6698 rt2800_bbp_write(rt2x00dev, 180, 0x00); 6699 rt2800_bbp_write(rt2x00dev, 182, 0x40); 6700 rt2800_bbp_write(rt2x00dev, 180, 0x01); 6701 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 6702 6703 rt2800_bbp_write(rt2x00dev, 179, 0x00); 6704 6705 /* Reprogram the inband interface to put right values in RXWI */ 6706 rt2800_bbp_write(rt2x00dev, 142, 0x04); 6707 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 6708 rt2800_bbp_write(rt2x00dev, 142, 0x06); 6709 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 6710 rt2800_bbp_write(rt2x00dev, 142, 0x07); 6711 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 6712 rt2800_bbp_write(rt2x00dev, 142, 0x08); 6713 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 6714 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 6715 } 6716 6717 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) 6718 { 6719 int ant, div_mode; 6720 u16 eeprom; 6721 u8 value; 6722 6723 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6724 6725 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6726 6727 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 6728 rt2800_bbp_write(rt2x00dev, 66, 0x38); 6729 6730 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 6731 6732 rt2800_bbp_write(rt2x00dev, 69, 0x12); 6733 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6734 rt2800_bbp_write(rt2x00dev, 75, 0x46); 6735 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6736 6737 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6738 6739 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 6740 6741 rt2800_bbp_write(rt2x00dev, 79, 0x13); 6742 rt2800_bbp_write(rt2x00dev, 80, 0x05); 6743 rt2800_bbp_write(rt2x00dev, 81, 0x33); 6744 6745 rt2800_bbp_write(rt2x00dev, 82, 0x62); 6746 6747 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 6748 6749 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 6750 6751 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6752 6753 if (rt2x00_rt(rt2x00dev, RT5392)) 6754 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6755 6756 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6757 6758 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6759 6760 if (rt2x00_rt(rt2x00dev, RT5392)) { 6761 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6762 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6763 } 6764 6765 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6766 6767 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6768 6769 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 6770 6771 if (rt2x00_rt(rt2x00dev, RT5390)) 6772 rt2800_bbp_write(rt2x00dev, 106, 0x03); 6773 else if (rt2x00_rt(rt2x00dev, RT5392)) 6774 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6775 else 6776 WARN_ON(1); 6777 6778 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6779 6780 if (rt2x00_rt(rt2x00dev, RT5392)) { 6781 rt2800_bbp_write(rt2x00dev, 134, 0xd0); 6782 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 6783 } 6784 6785 rt2800_disable_unused_dac_adc(rt2x00dev); 6786 6787 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6788 div_mode = rt2x00_get_field16(eeprom, 6789 EEPROM_NIC_CONF1_ANT_DIVERSITY); 6790 ant = (div_mode == 3) ? 1 : 0; 6791 6792 /* check if this is a Bluetooth combo card */ 6793 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { 6794 u32 reg; 6795 6796 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 6797 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); 6798 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); 6799 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); 6800 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); 6801 if (ant == 0) 6802 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); 6803 else if (ant == 1) 6804 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); 6805 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 6806 } 6807 6808 /* These chips have hardware RX antenna diversity */ 6809 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 6810 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 6811 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */ 6812 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */ 6813 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */ 6814 } 6815 6816 value = rt2800_bbp_read(rt2x00dev, 152); 6817 if (ant == 0) 6818 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6819 else 6820 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6821 rt2800_bbp_write(rt2x00dev, 152, value); 6822 6823 rt2800_init_freq_calibration(rt2x00dev); 6824 } 6825 6826 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev) 6827 { 6828 int ant, div_mode; 6829 u16 eeprom; 6830 u8 value; 6831 6832 rt2800_init_bbp_early(rt2x00dev); 6833 6834 value = rt2800_bbp_read(rt2x00dev, 105); 6835 rt2x00_set_field8(&value, BBP105_MLD, 6836 rt2x00dev->default_ant.rx_chain_num == 2); 6837 rt2800_bbp_write(rt2x00dev, 105, value); 6838 6839 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6840 6841 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6842 rt2800_bbp_write(rt2x00dev, 31, 0x08); 6843 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6844 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6845 rt2800_bbp_write(rt2x00dev, 69, 0x1A); 6846 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6847 rt2800_bbp_write(rt2x00dev, 73, 0x13); 6848 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6849 rt2800_bbp_write(rt2x00dev, 75, 0x4F); 6850 rt2800_bbp_write(rt2x00dev, 76, 0x28); 6851 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6852 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6853 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6854 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6855 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6856 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6857 rt2800_bbp_write(rt2x00dev, 95, 0x9a); 6858 rt2800_bbp_write(rt2x00dev, 98, 0x12); 6859 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6860 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6861 /* FIXME BBP105 owerwrite */ 6862 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6863 rt2800_bbp_write(rt2x00dev, 106, 0x35); 6864 rt2800_bbp_write(rt2x00dev, 128, 0x12); 6865 rt2800_bbp_write(rt2x00dev, 134, 0xD0); 6866 rt2800_bbp_write(rt2x00dev, 135, 0xF6); 6867 rt2800_bbp_write(rt2x00dev, 137, 0x0F); 6868 6869 /* Initialize GLRT (Generalized Likehood Radio Test) */ 6870 rt2800_init_bbp_5592_glrt(rt2x00dev); 6871 6872 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6873 6874 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 6875 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY); 6876 ant = (div_mode == 3) ? 1 : 0; 6877 value = rt2800_bbp_read(rt2x00dev, 152); 6878 if (ant == 0) { 6879 /* Main antenna */ 6880 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); 6881 } else { 6882 /* Auxiliary antenna */ 6883 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 6884 } 6885 rt2800_bbp_write(rt2x00dev, 152, value); 6886 6887 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) { 6888 value = rt2800_bbp_read(rt2x00dev, 254); 6889 rt2x00_set_field8(&value, BBP254_BIT7, 1); 6890 rt2800_bbp_write(rt2x00dev, 254, value); 6891 } 6892 6893 rt2800_init_freq_calibration(rt2x00dev); 6894 6895 rt2800_bbp_write(rt2x00dev, 84, 0x19); 6896 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 6897 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 6898 } 6899 6900 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev, 6901 const u8 reg, const u8 value) 6902 { 6903 rt2800_bbp_write(rt2x00dev, 195, reg); 6904 rt2800_bbp_write(rt2x00dev, 196, value); 6905 } 6906 6907 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev, 6908 const u8 reg, const u8 value) 6909 { 6910 rt2800_bbp_write(rt2x00dev, 158, reg); 6911 rt2800_bbp_write(rt2x00dev, 159, value); 6912 } 6913 6914 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg) 6915 { 6916 rt2800_bbp_write(rt2x00dev, 158, reg); 6917 return rt2800_bbp_read(rt2x00dev, 159); 6918 } 6919 6920 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) 6921 { 6922 u8 bbp; 6923 6924 /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */ 6925 bbp = rt2800_bbp_read(rt2x00dev, 105); 6926 rt2x00_set_field8(&bbp, BBP105_MLD, 6927 rt2x00dev->default_ant.rx_chain_num == 2); 6928 rt2800_bbp_write(rt2x00dev, 105, bbp); 6929 6930 /* Avoid data loss and CRC errors */ 6931 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 6932 6933 /* Fix I/Q swap issue */ 6934 bbp = rt2800_bbp_read(rt2x00dev, 1); 6935 bbp |= 0x04; 6936 rt2800_bbp_write(rt2x00dev, 1, bbp); 6937 6938 /* BBP for G band */ 6939 rt2800_bbp_write(rt2x00dev, 3, 0x08); 6940 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */ 6941 rt2800_bbp_write(rt2x00dev, 6, 0x08); 6942 rt2800_bbp_write(rt2x00dev, 14, 0x09); 6943 rt2800_bbp_write(rt2x00dev, 15, 0xFF); 6944 rt2800_bbp_write(rt2x00dev, 16, 0x01); 6945 rt2800_bbp_write(rt2x00dev, 20, 0x06); 6946 rt2800_bbp_write(rt2x00dev, 21, 0x00); 6947 rt2800_bbp_write(rt2x00dev, 22, 0x00); 6948 rt2800_bbp_write(rt2x00dev, 27, 0x00); 6949 rt2800_bbp_write(rt2x00dev, 28, 0x00); 6950 rt2800_bbp_write(rt2x00dev, 30, 0x00); 6951 rt2800_bbp_write(rt2x00dev, 31, 0x48); 6952 rt2800_bbp_write(rt2x00dev, 47, 0x40); 6953 rt2800_bbp_write(rt2x00dev, 62, 0x00); 6954 rt2800_bbp_write(rt2x00dev, 63, 0x00); 6955 rt2800_bbp_write(rt2x00dev, 64, 0x00); 6956 rt2800_bbp_write(rt2x00dev, 65, 0x2C); 6957 rt2800_bbp_write(rt2x00dev, 66, 0x1C); 6958 rt2800_bbp_write(rt2x00dev, 67, 0x20); 6959 rt2800_bbp_write(rt2x00dev, 68, 0xDD); 6960 rt2800_bbp_write(rt2x00dev, 69, 0x10); 6961 rt2800_bbp_write(rt2x00dev, 70, 0x05); 6962 rt2800_bbp_write(rt2x00dev, 73, 0x18); 6963 rt2800_bbp_write(rt2x00dev, 74, 0x0F); 6964 rt2800_bbp_write(rt2x00dev, 75, 0x60); 6965 rt2800_bbp_write(rt2x00dev, 76, 0x44); 6966 rt2800_bbp_write(rt2x00dev, 77, 0x59); 6967 rt2800_bbp_write(rt2x00dev, 78, 0x1E); 6968 rt2800_bbp_write(rt2x00dev, 79, 0x1C); 6969 rt2800_bbp_write(rt2x00dev, 80, 0x0C); 6970 rt2800_bbp_write(rt2x00dev, 81, 0x3A); 6971 rt2800_bbp_write(rt2x00dev, 82, 0xB6); 6972 rt2800_bbp_write(rt2x00dev, 83, 0x9A); 6973 rt2800_bbp_write(rt2x00dev, 84, 0x9A); 6974 rt2800_bbp_write(rt2x00dev, 86, 0x38); 6975 rt2800_bbp_write(rt2x00dev, 88, 0x90); 6976 rt2800_bbp_write(rt2x00dev, 91, 0x04); 6977 rt2800_bbp_write(rt2x00dev, 92, 0x02); 6978 rt2800_bbp_write(rt2x00dev, 95, 0x9A); 6979 rt2800_bbp_write(rt2x00dev, 96, 0x00); 6980 rt2800_bbp_write(rt2x00dev, 103, 0xC0); 6981 rt2800_bbp_write(rt2x00dev, 104, 0x92); 6982 /* FIXME BBP105 owerwrite */ 6983 rt2800_bbp_write(rt2x00dev, 105, 0x3C); 6984 rt2800_bbp_write(rt2x00dev, 106, 0x12); 6985 rt2800_bbp_write(rt2x00dev, 109, 0x00); 6986 rt2800_bbp_write(rt2x00dev, 134, 0x10); 6987 rt2800_bbp_write(rt2x00dev, 135, 0xA6); 6988 rt2800_bbp_write(rt2x00dev, 137, 0x04); 6989 rt2800_bbp_write(rt2x00dev, 142, 0x30); 6990 rt2800_bbp_write(rt2x00dev, 143, 0xF7); 6991 rt2800_bbp_write(rt2x00dev, 160, 0xEC); 6992 rt2800_bbp_write(rt2x00dev, 161, 0xC4); 6993 rt2800_bbp_write(rt2x00dev, 162, 0x77); 6994 rt2800_bbp_write(rt2x00dev, 163, 0xF9); 6995 rt2800_bbp_write(rt2x00dev, 164, 0x00); 6996 rt2800_bbp_write(rt2x00dev, 165, 0x00); 6997 rt2800_bbp_write(rt2x00dev, 186, 0x00); 6998 rt2800_bbp_write(rt2x00dev, 187, 0x00); 6999 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7000 rt2800_bbp_write(rt2x00dev, 186, 0x00); 7001 rt2800_bbp_write(rt2x00dev, 187, 0x01); 7002 rt2800_bbp_write(rt2x00dev, 188, 0x00); 7003 rt2800_bbp_write(rt2x00dev, 189, 0x00); 7004 7005 rt2800_bbp_write(rt2x00dev, 91, 0x06); 7006 rt2800_bbp_write(rt2x00dev, 92, 0x04); 7007 rt2800_bbp_write(rt2x00dev, 93, 0x54); 7008 rt2800_bbp_write(rt2x00dev, 99, 0x50); 7009 rt2800_bbp_write(rt2x00dev, 148, 0x84); 7010 rt2800_bbp_write(rt2x00dev, 167, 0x80); 7011 rt2800_bbp_write(rt2x00dev, 178, 0xFF); 7012 rt2800_bbp_write(rt2x00dev, 106, 0x13); 7013 7014 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */ 7015 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00); 7016 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); 7017 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20); 7018 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A); 7019 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16); 7020 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06); 7021 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02); 7022 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07); 7023 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05); 7024 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09); 7025 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20); 7026 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08); 7027 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A); 7028 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00); 7029 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00); 7030 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0); 7031 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F); 7032 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F); 7033 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32); 7034 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08); 7035 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28); 7036 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19); 7037 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A); 7038 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16); 7039 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10); 7040 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10); 7041 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A); 7042 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36); 7043 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C); 7044 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26); 7045 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24); 7046 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42); 7047 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40); 7048 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30); 7049 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29); 7050 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C); 7051 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46); 7052 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D); 7053 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40); 7054 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E); 7055 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38); 7056 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D); 7057 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F); 7058 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C); 7059 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34); 7060 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C); 7061 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F); 7062 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C); 7063 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35); 7064 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E); 7065 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F); 7066 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49); 7067 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41); 7068 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36); 7069 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39); 7070 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30); 7071 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30); 7072 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E); 7073 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D); 7074 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28); 7075 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21); 7076 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C); 7077 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16); 7078 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50); 7079 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A); 7080 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43); 7081 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50); 7082 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10); 7083 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10); 7084 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10); 7085 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10); 7086 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D); 7087 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14); 7088 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32); 7089 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C); 7090 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36); 7091 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C); 7092 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43); 7093 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C); 7094 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E); 7095 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36); 7096 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30); 7097 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E); 7098 7099 /* BBP for G band DCOC function */ 7100 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C); 7101 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00); 7102 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10); 7103 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10); 7104 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10); 7105 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10); 7106 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08); 7107 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40); 7108 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04); 7109 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04); 7110 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08); 7111 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08); 7112 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03); 7113 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03); 7114 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03); 7115 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02); 7116 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40); 7117 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40); 7118 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64); 7119 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7120 7121 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7122 } 7123 7124 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 7125 { 7126 unsigned int i; 7127 u16 eeprom; 7128 u8 reg_id; 7129 u8 value; 7130 7131 if (rt2800_is_305x_soc(rt2x00dev)) 7132 rt2800_init_bbp_305x_soc(rt2x00dev); 7133 7134 switch (rt2x00dev->chip.rt) { 7135 case RT2860: 7136 case RT2872: 7137 case RT2883: 7138 rt2800_init_bbp_28xx(rt2x00dev); 7139 break; 7140 case RT3070: 7141 case RT3071: 7142 case RT3090: 7143 rt2800_init_bbp_30xx(rt2x00dev); 7144 break; 7145 case RT3290: 7146 rt2800_init_bbp_3290(rt2x00dev); 7147 break; 7148 case RT3352: 7149 case RT5350: 7150 rt2800_init_bbp_3352(rt2x00dev); 7151 break; 7152 case RT3390: 7153 rt2800_init_bbp_3390(rt2x00dev); 7154 break; 7155 case RT3572: 7156 rt2800_init_bbp_3572(rt2x00dev); 7157 break; 7158 case RT3593: 7159 rt2800_init_bbp_3593(rt2x00dev); 7160 return; 7161 case RT3883: 7162 rt2800_init_bbp_3883(rt2x00dev); 7163 return; 7164 case RT5390: 7165 case RT5392: 7166 rt2800_init_bbp_53xx(rt2x00dev); 7167 break; 7168 case RT5592: 7169 rt2800_init_bbp_5592(rt2x00dev); 7170 return; 7171 case RT6352: 7172 rt2800_init_bbp_6352(rt2x00dev); 7173 break; 7174 } 7175 7176 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 7177 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, 7178 EEPROM_BBP_START, i); 7179 7180 if (eeprom != 0xffff && eeprom != 0x0000) { 7181 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); 7182 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); 7183 rt2800_bbp_write(rt2x00dev, reg_id, value); 7184 } 7185 } 7186 } 7187 7188 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) 7189 { 7190 u32 reg; 7191 7192 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); 7193 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); 7194 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 7195 } 7196 7197 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40, 7198 u8 filter_target) 7199 { 7200 unsigned int i; 7201 u8 bbp; 7202 u8 rfcsr; 7203 u8 passband; 7204 u8 stopband; 7205 u8 overtuned = 0; 7206 u8 rfcsr24 = (bw40) ? 0x27 : 0x07; 7207 7208 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7209 7210 bbp = rt2800_bbp_read(rt2x00dev, 4); 7211 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 7212 rt2800_bbp_write(rt2x00dev, 4, bbp); 7213 7214 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31); 7215 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40); 7216 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr); 7217 7218 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7219 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 7220 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7221 7222 /* 7223 * Set power & frequency of passband test tone 7224 */ 7225 rt2800_bbp_write(rt2x00dev, 24, 0); 7226 7227 for (i = 0; i < 100; i++) { 7228 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7229 msleep(1); 7230 7231 passband = rt2800_bbp_read(rt2x00dev, 55); 7232 if (passband) 7233 break; 7234 } 7235 7236 /* 7237 * Set power & frequency of stopband test tone 7238 */ 7239 rt2800_bbp_write(rt2x00dev, 24, 0x06); 7240 7241 for (i = 0; i < 100; i++) { 7242 rt2800_bbp_write(rt2x00dev, 25, 0x90); 7243 msleep(1); 7244 7245 stopband = rt2800_bbp_read(rt2x00dev, 55); 7246 7247 if ((passband - stopband) <= filter_target) { 7248 rfcsr24++; 7249 overtuned += ((passband - stopband) == filter_target); 7250 } else 7251 break; 7252 7253 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7254 } 7255 7256 rfcsr24 -= !!overtuned; 7257 7258 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 7259 return rfcsr24; 7260 } 7261 7262 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev, 7263 const unsigned int rf_reg) 7264 { 7265 u8 rfcsr; 7266 7267 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg); 7268 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1); 7269 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7270 msleep(1); 7271 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0); 7272 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr); 7273 } 7274 7275 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev) 7276 { 7277 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7278 u8 filter_tgt_bw20; 7279 u8 filter_tgt_bw40; 7280 u8 rfcsr, bbp; 7281 7282 /* 7283 * TODO: sync filter_tgt values with vendor driver 7284 */ 7285 if (rt2x00_rt(rt2x00dev, RT3070)) { 7286 filter_tgt_bw20 = 0x16; 7287 filter_tgt_bw40 = 0x19; 7288 } else { 7289 filter_tgt_bw20 = 0x13; 7290 filter_tgt_bw40 = 0x15; 7291 } 7292 7293 drv_data->calibration_bw20 = 7294 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20); 7295 drv_data->calibration_bw40 = 7296 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40); 7297 7298 /* 7299 * Save BBP 25 & 26 values for later use in channel switching (for 3052) 7300 */ 7301 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7302 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7303 7304 /* 7305 * Set back to initial state 7306 */ 7307 rt2800_bbp_write(rt2x00dev, 24, 0); 7308 7309 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 7310 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 7311 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 7312 7313 /* 7314 * Set BBP back to BW20 7315 */ 7316 bbp = rt2800_bbp_read(rt2x00dev, 4); 7317 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 7318 rt2800_bbp_write(rt2x00dev, 4, bbp); 7319 } 7320 7321 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) 7322 { 7323 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7324 u8 min_gain, rfcsr, bbp; 7325 u16 eeprom; 7326 7327 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17); 7328 7329 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 7330 if (rt2x00_rt(rt2x00dev, RT3070) || 7331 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7332 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 7333 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 7334 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) 7335 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 7336 } 7337 7338 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2; 7339 if (drv_data->txmixer_gain_24g >= min_gain) { 7340 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 7341 drv_data->txmixer_gain_24g); 7342 } 7343 7344 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 7345 7346 if (rt2x00_rt(rt2x00dev, RT3090)) { 7347 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7348 bbp = rt2800_bbp_read(rt2x00dev, 138); 7349 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7350 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7351 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 7352 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7353 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1); 7354 rt2800_bbp_write(rt2x00dev, 138, bbp); 7355 } 7356 7357 if (rt2x00_rt(rt2x00dev, RT3070)) { 7358 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27); 7359 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) 7360 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 7361 else 7362 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 7363 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0); 7364 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0); 7365 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0); 7366 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 7367 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7368 rt2x00_rt(rt2x00dev, RT3090) || 7369 rt2x00_rt(rt2x00dev, RT3390)) { 7370 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7371 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7372 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); 7373 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); 7374 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); 7375 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); 7376 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7377 7378 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15); 7379 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0); 7380 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr); 7381 7382 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 7383 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0); 7384 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 7385 7386 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21); 7387 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0); 7388 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 7389 } 7390 } 7391 7392 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev) 7393 { 7394 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7395 u8 rfcsr; 7396 u8 tx_gain; 7397 7398 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50); 7399 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0); 7400 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7401 7402 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51); 7403 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g, 7404 RFCSR17_TXMIXER_GAIN); 7405 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain); 7406 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr); 7407 7408 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38); 7409 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); 7410 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); 7411 7412 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39); 7413 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0); 7414 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr); 7415 7416 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 7417 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 7418 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1); 7419 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 7420 7421 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30); 7422 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2); 7423 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 7424 7425 /* TODO: enable stream mode */ 7426 } 7427 7428 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev) 7429 { 7430 u8 reg; 7431 u16 eeprom; 7432 7433 /* Turn off unused DAC1 and ADC1 to reduce power consumption */ 7434 reg = rt2800_bbp_read(rt2x00dev, 138); 7435 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 7436 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 7437 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); 7438 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1) 7439 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); 7440 rt2800_bbp_write(rt2x00dev, 138, reg); 7441 7442 reg = rt2800_rfcsr_read(rt2x00dev, 38); 7443 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); 7444 rt2800_rfcsr_write(rt2x00dev, 38, reg); 7445 7446 reg = rt2800_rfcsr_read(rt2x00dev, 39); 7447 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); 7448 rt2800_rfcsr_write(rt2x00dev, 39, reg); 7449 7450 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7451 7452 reg = rt2800_rfcsr_read(rt2x00dev, 30); 7453 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); 7454 rt2800_rfcsr_write(rt2x00dev, 30, reg); 7455 } 7456 7457 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 7458 { 7459 rt2800_rf_init_calibration(rt2x00dev, 30); 7460 7461 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 7462 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 7463 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 7464 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 7465 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7466 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7467 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7468 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 7469 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 7470 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7471 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 7472 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7473 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 7474 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 7475 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7476 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7477 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7478 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7479 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7480 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7481 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7482 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7483 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7484 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 7485 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7486 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 7487 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 7488 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 7489 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 7490 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 7491 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 7492 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 7493 } 7494 7495 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 7496 { 7497 u8 rfcsr; 7498 u16 eeprom; 7499 u32 reg; 7500 7501 /* XXX vendor driver do this only for 3070 */ 7502 rt2800_rf_init_calibration(rt2x00dev, 30); 7503 7504 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7505 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 7506 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 7507 rt2800_rfcsr_write(rt2x00dev, 7, 0x60); 7508 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 7509 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 7510 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7511 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 7512 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7513 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 7514 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 7515 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 7516 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 7517 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7518 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 7519 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 7520 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7521 rt2800_rfcsr_write(rt2x00dev, 25, 0x03); 7522 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 7523 7524 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 7525 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7526 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7527 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7528 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7529 } else if (rt2x00_rt(rt2x00dev, RT3071) || 7530 rt2x00_rt(rt2x00dev, RT3090)) { 7531 rt2800_rfcsr_write(rt2x00dev, 31, 0x14); 7532 7533 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7534 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7535 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7536 7537 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7538 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7539 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7540 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { 7541 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 7542 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST)) 7543 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7544 else 7545 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7546 } 7547 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7548 7549 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7550 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7551 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7552 } 7553 7554 rt2800_rx_filter_calibration(rt2x00dev); 7555 7556 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 7557 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 7558 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) 7559 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7560 7561 rt2800_led_open_drain_enable(rt2x00dev); 7562 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7563 } 7564 7565 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 7566 { 7567 u8 rfcsr; 7568 7569 rt2800_rf_init_calibration(rt2x00dev, 2); 7570 7571 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 7572 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 7573 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7574 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7575 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 7576 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); 7577 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7578 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7579 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7580 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7581 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7582 rt2800_rfcsr_write(rt2x00dev, 18, 0x02); 7583 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7584 rt2800_rfcsr_write(rt2x00dev, 25, 0x83); 7585 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 7586 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 7587 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 7588 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7589 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7590 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7591 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7592 rt2800_rfcsr_write(rt2x00dev, 34, 0x05); 7593 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 7594 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 7595 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 7596 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 7597 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 7598 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 7599 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 7600 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); 7601 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 7602 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 7603 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 7604 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 7605 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 7606 rt2800_rfcsr_write(rt2x00dev, 49, 0x98); 7607 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 7608 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 7609 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 7610 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 7611 rt2800_rfcsr_write(rt2x00dev, 56, 0x02); 7612 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 7613 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 7614 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 7615 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 7616 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 7617 7618 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29); 7619 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3); 7620 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr); 7621 7622 rt2800_led_open_drain_enable(rt2x00dev); 7623 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7624 } 7625 7626 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 7627 { 7628 int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0, 7629 &rt2x00dev->cap_flags); 7630 int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1, 7631 &rt2x00dev->cap_flags); 7632 u8 rfcsr; 7633 7634 rt2800_rf_init_calibration(rt2x00dev, 30); 7635 7636 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7637 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7638 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7639 rt2800_rfcsr_write(rt2x00dev, 3, 0x18); 7640 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 7641 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7642 rt2800_rfcsr_write(rt2x00dev, 6, 0x33); 7643 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7644 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7645 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7646 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); 7647 rt2800_rfcsr_write(rt2x00dev, 11, 0x42); 7648 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); 7649 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 7650 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); 7651 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7652 rt2800_rfcsr_write(rt2x00dev, 16, 0x01); 7653 rt2800_rfcsr_write(rt2x00dev, 18, 0x45); 7654 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 7655 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7656 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7657 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7658 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7659 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7660 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7661 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7662 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7663 rt2800_rfcsr_write(rt2x00dev, 28, 0x03); 7664 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 7665 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7666 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7667 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 7668 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 7669 rfcsr = 0x01; 7670 if (tx0_ext_pa) 7671 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1); 7672 if (tx1_ext_pa) 7673 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1); 7674 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr); 7675 rt2800_rfcsr_write(rt2x00dev, 35, 0x03); 7676 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); 7677 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); 7678 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); 7679 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); 7680 rt2800_rfcsr_write(rt2x00dev, 40, 0x33); 7681 rfcsr = 0x52; 7682 if (!tx0_ext_pa) { 7683 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1); 7684 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1); 7685 } 7686 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr); 7687 rfcsr = 0x52; 7688 if (!tx1_ext_pa) { 7689 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1); 7690 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1); 7691 } 7692 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); 7693 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); 7694 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); 7695 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); 7696 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); 7697 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); 7698 rt2800_rfcsr_write(rt2x00dev, 48, 0x14); 7699 rt2800_rfcsr_write(rt2x00dev, 49, 0x00); 7700 rfcsr = 0x2d; 7701 if (tx0_ext_pa) 7702 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1); 7703 if (tx1_ext_pa) 7704 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1); 7705 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr); 7706 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f)); 7707 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00)); 7708 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52)); 7709 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b)); 7710 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f)); 7711 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00)); 7712 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52)); 7713 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b)); 7714 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 7715 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 7716 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 7717 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 7718 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 7719 7720 rt2800_rx_filter_calibration(rt2x00dev); 7721 rt2800_led_open_drain_enable(rt2x00dev); 7722 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7723 } 7724 7725 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 7726 { 7727 u32 reg; 7728 7729 rt2800_rf_init_calibration(rt2x00dev, 30); 7730 7731 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 7732 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 7733 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7734 rt2800_rfcsr_write(rt2x00dev, 3, 0x62); 7735 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 7736 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); 7737 rt2800_rfcsr_write(rt2x00dev, 6, 0x42); 7738 rt2800_rfcsr_write(rt2x00dev, 7, 0x34); 7739 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 7740 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); 7741 rt2800_rfcsr_write(rt2x00dev, 10, 0x61); 7742 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 7743 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); 7744 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); 7745 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 7746 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7747 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); 7748 rt2800_rfcsr_write(rt2x00dev, 17, 0x94); 7749 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); 7750 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); 7751 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); 7752 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); 7753 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7754 rt2800_rfcsr_write(rt2x00dev, 23, 0x14); 7755 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 7756 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); 7757 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7758 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7759 rt2800_rfcsr_write(rt2x00dev, 28, 0x41); 7760 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 7761 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 7762 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 7763 7764 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7765 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); 7766 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7767 7768 rt2800_rx_filter_calibration(rt2x00dev); 7769 7770 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) 7771 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7772 7773 rt2800_led_open_drain_enable(rt2x00dev); 7774 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7775 } 7776 7777 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 7778 { 7779 u8 rfcsr; 7780 u32 reg; 7781 7782 rt2800_rf_init_calibration(rt2x00dev, 30); 7783 7784 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 7785 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 7786 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 7787 rt2800_rfcsr_write(rt2x00dev, 3, 0x02); 7788 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); 7789 rt2800_rfcsr_write(rt2x00dev, 5, 0x05); 7790 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); 7791 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); 7792 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); 7793 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); 7794 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); 7795 rt2800_rfcsr_write(rt2x00dev, 12, 0x70); 7796 rt2800_rfcsr_write(rt2x00dev, 13, 0x65); 7797 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); 7798 rt2800_rfcsr_write(rt2x00dev, 15, 0x53); 7799 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); 7800 rt2800_rfcsr_write(rt2x00dev, 17, 0x23); 7801 rt2800_rfcsr_write(rt2x00dev, 18, 0xac); 7802 rt2800_rfcsr_write(rt2x00dev, 19, 0x93); 7803 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); 7804 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); 7805 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 7806 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); 7807 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 7808 rt2800_rfcsr_write(rt2x00dev, 25, 0x15); 7809 rt2800_rfcsr_write(rt2x00dev, 26, 0x85); 7810 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 7811 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7812 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 7813 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 7814 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 7815 7816 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 7817 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 7818 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 7819 7820 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7821 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7822 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7823 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7824 msleep(1); 7825 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7826 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7827 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7828 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7829 7830 rt2800_rx_filter_calibration(rt2x00dev); 7831 rt2800_led_open_drain_enable(rt2x00dev); 7832 rt2800_normal_mode_setup_3xxx(rt2x00dev); 7833 } 7834 7835 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev) 7836 { 7837 u8 bbp; 7838 bool txbf_enabled = false; /* FIXME */ 7839 7840 bbp = rt2800_bbp_read(rt2x00dev, 105); 7841 if (rt2x00dev->default_ant.rx_chain_num == 1) 7842 rt2x00_set_field8(&bbp, BBP105_MLD, 0); 7843 else 7844 rt2x00_set_field8(&bbp, BBP105_MLD, 1); 7845 rt2800_bbp_write(rt2x00dev, 105, bbp); 7846 7847 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7848 7849 rt2800_bbp_write(rt2x00dev, 92, 0x02); 7850 rt2800_bbp_write(rt2x00dev, 82, 0x82); 7851 rt2800_bbp_write(rt2x00dev, 106, 0x05); 7852 rt2800_bbp_write(rt2x00dev, 104, 0x92); 7853 rt2800_bbp_write(rt2x00dev, 88, 0x90); 7854 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 7855 rt2800_bbp_write(rt2x00dev, 47, 0x48); 7856 rt2800_bbp_write(rt2x00dev, 120, 0x50); 7857 7858 if (txbf_enabled) 7859 rt2800_bbp_write(rt2x00dev, 163, 0xbd); 7860 else 7861 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 7862 7863 /* SNR mapping */ 7864 rt2800_bbp_write(rt2x00dev, 142, 6); 7865 rt2800_bbp_write(rt2x00dev, 143, 160); 7866 rt2800_bbp_write(rt2x00dev, 142, 7); 7867 rt2800_bbp_write(rt2x00dev, 143, 161); 7868 rt2800_bbp_write(rt2x00dev, 142, 8); 7869 rt2800_bbp_write(rt2x00dev, 143, 162); 7870 7871 /* ADC/DAC control */ 7872 rt2800_bbp_write(rt2x00dev, 31, 0x08); 7873 7874 /* RX AGC energy lower bound in log2 */ 7875 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 7876 7877 /* FIXME: BBP 105 owerwrite? */ 7878 rt2800_bbp_write(rt2x00dev, 105, 0x04); 7879 7880 } 7881 7882 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) 7883 { 7884 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 7885 u32 reg; 7886 u8 rfcsr; 7887 7888 /* Disable GPIO #4 and #7 function for LAN PE control */ 7889 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); 7890 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); 7891 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); 7892 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 7893 7894 /* Initialize default register values */ 7895 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 7896 rt2800_rfcsr_write(rt2x00dev, 3, 0x80); 7897 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 7898 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 7899 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7900 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7901 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 7902 rt2800_rfcsr_write(rt2x00dev, 11, 0x40); 7903 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e); 7904 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 7905 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 7906 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7907 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 7908 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 7909 rt2800_rfcsr_write(rt2x00dev, 32, 0x78); 7910 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b); 7911 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c); 7912 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0); 7913 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 7914 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 7915 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3); 7916 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 7917 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 7918 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 7919 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 7920 rt2800_rfcsr_write(rt2x00dev, 51, 0x75); 7921 rt2800_rfcsr_write(rt2x00dev, 52, 0x45); 7922 rt2800_rfcsr_write(rt2x00dev, 53, 0x18); 7923 rt2800_rfcsr_write(rt2x00dev, 54, 0x18); 7924 rt2800_rfcsr_write(rt2x00dev, 55, 0x18); 7925 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 7926 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e); 7927 7928 /* Initiate calibration */ 7929 /* TODO: use rt2800_rf_init_calibration ? */ 7930 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 7931 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 7932 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 7933 7934 rt2800_freq_cal_mode1(rt2x00dev); 7935 7936 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18); 7937 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); 7938 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); 7939 7940 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7941 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); 7942 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); 7943 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7944 usleep_range(1000, 1500); 7945 reg = rt2800_register_read(rt2x00dev, LDO_CFG0); 7946 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); 7947 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 7948 7949 /* Set initial values for RX filter calibration */ 7950 drv_data->calibration_bw20 = 0x1f; 7951 drv_data->calibration_bw40 = 0x2f; 7952 7953 /* Save BBP 25 & 26 values for later use in channel switching */ 7954 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25); 7955 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26); 7956 7957 rt2800_led_open_drain_enable(rt2x00dev); 7958 rt2800_normal_mode_setup_3593(rt2x00dev); 7959 7960 rt3593_post_bbp_init(rt2x00dev); 7961 7962 /* TODO: enable stream mode support */ 7963 } 7964 7965 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev) 7966 { 7967 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 7968 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 7969 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 7970 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 7971 rt2800_rfcsr_write(rt2x00dev, 4, 0x49); 7972 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 7973 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 7974 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 7975 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); 7976 rt2800_rfcsr_write(rt2x00dev, 9, 0x02); 7977 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 7978 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 7979 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 7980 if (rt2800_clk_is_20mhz(rt2x00dev)) 7981 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f); 7982 else 7983 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 7984 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 7985 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 7986 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0); 7987 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 7988 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 7989 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 7990 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 7991 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 7992 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 7993 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 7994 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 7995 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 7996 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 7997 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 7998 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0); 7999 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8000 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8001 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8002 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8003 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8004 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8005 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8006 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8007 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8008 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8009 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8010 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8011 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8012 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8013 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c); 8014 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6); 8015 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8016 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8017 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8018 rt2800_rfcsr_write(rt2x00dev, 49, 0x80); 8019 rt2800_rfcsr_write(rt2x00dev, 50, 0x00); 8020 rt2800_rfcsr_write(rt2x00dev, 51, 0x00); 8021 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8022 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8023 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8024 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8025 rt2800_rfcsr_write(rt2x00dev, 56, 0x82); 8026 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8027 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8028 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b); 8029 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8030 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8031 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8032 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8033 } 8034 8035 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev) 8036 { 8037 u8 rfcsr; 8038 8039 /* TODO: get the actual ECO value from the SoC */ 8040 const unsigned int eco = 5; 8041 8042 rt2800_rf_init_calibration(rt2x00dev, 2); 8043 8044 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0); 8045 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8046 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 8047 rt2800_rfcsr_write(rt2x00dev, 3, 0x20); 8048 rt2800_rfcsr_write(rt2x00dev, 4, 0x00); 8049 rt2800_rfcsr_write(rt2x00dev, 5, 0x00); 8050 rt2800_rfcsr_write(rt2x00dev, 6, 0x40); 8051 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8052 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b); 8053 rt2800_rfcsr_write(rt2x00dev, 9, 0x08); 8054 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3); 8055 rt2800_rfcsr_write(rt2x00dev, 11, 0x48); 8056 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a); 8057 rt2800_rfcsr_write(rt2x00dev, 13, 0x12); 8058 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8059 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8060 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8061 8062 /* RFCSR 17 will be initialized later based on the 8063 * frequency offset stored in the EEPROM 8064 */ 8065 8066 rt2800_rfcsr_write(rt2x00dev, 18, 0x40); 8067 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8068 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8069 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8070 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8071 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0); 8072 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8073 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8074 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8075 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8076 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8077 rt2800_rfcsr_write(rt2x00dev, 29, 0x00); 8078 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8079 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8080 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8081 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8082 rt2800_rfcsr_write(rt2x00dev, 34, 0x20); 8083 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8084 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8085 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8086 rt2800_rfcsr_write(rt2x00dev, 38, 0x86); 8087 rt2800_rfcsr_write(rt2x00dev, 39, 0x23); 8088 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8089 rt2800_rfcsr_write(rt2x00dev, 41, 0x00); 8090 rt2800_rfcsr_write(rt2x00dev, 42, 0x00); 8091 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8092 rt2800_rfcsr_write(rt2x00dev, 44, 0x93); 8093 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb); 8094 rt2800_rfcsr_write(rt2x00dev, 46, 0x60); 8095 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8096 rt2800_rfcsr_write(rt2x00dev, 48, 0x00); 8097 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e); 8098 rt2800_rfcsr_write(rt2x00dev, 50, 0x86); 8099 rt2800_rfcsr_write(rt2x00dev, 51, 0x51); 8100 rt2800_rfcsr_write(rt2x00dev, 52, 0x05); 8101 rt2800_rfcsr_write(rt2x00dev, 53, 0x76); 8102 rt2800_rfcsr_write(rt2x00dev, 54, 0x76); 8103 rt2800_rfcsr_write(rt2x00dev, 55, 0x76); 8104 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb); 8105 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e); 8106 rt2800_rfcsr_write(rt2x00dev, 58, 0x00); 8107 rt2800_rfcsr_write(rt2x00dev, 59, 0x00); 8108 rt2800_rfcsr_write(rt2x00dev, 60, 0x00); 8109 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 8110 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8111 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8112 8113 /* TODO: rx filter calibration? */ 8114 8115 rt2800_bbp_write(rt2x00dev, 137, 0x0f); 8116 8117 rt2800_bbp_write(rt2x00dev, 163, 0x9d); 8118 8119 rt2800_bbp_write(rt2x00dev, 105, 0x05); 8120 8121 rt2800_bbp_write(rt2x00dev, 179, 0x02); 8122 rt2800_bbp_write(rt2x00dev, 180, 0x00); 8123 rt2800_bbp_write(rt2x00dev, 182, 0x40); 8124 rt2800_bbp_write(rt2x00dev, 180, 0x01); 8125 rt2800_bbp_write(rt2x00dev, 182, 0x9c); 8126 8127 rt2800_bbp_write(rt2x00dev, 179, 0x00); 8128 8129 rt2800_bbp_write(rt2x00dev, 142, 0x04); 8130 rt2800_bbp_write(rt2x00dev, 143, 0x3b); 8131 rt2800_bbp_write(rt2x00dev, 142, 0x06); 8132 rt2800_bbp_write(rt2x00dev, 143, 0xa0); 8133 rt2800_bbp_write(rt2x00dev, 142, 0x07); 8134 rt2800_bbp_write(rt2x00dev, 143, 0xa1); 8135 rt2800_bbp_write(rt2x00dev, 142, 0x08); 8136 rt2800_bbp_write(rt2x00dev, 143, 0xa2); 8137 rt2800_bbp_write(rt2x00dev, 148, 0xc8); 8138 8139 if (eco == 5) { 8140 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8); 8141 rt2800_rfcsr_write(rt2x00dev, 33, 0x32); 8142 } 8143 8144 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2); 8145 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0); 8146 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 8147 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8148 msleep(1); 8149 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 8150 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 8151 8152 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1); 8153 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); 8154 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 8155 8156 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6); 8157 rfcsr |= 0xc0; 8158 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 8159 8160 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22); 8161 rfcsr |= 0x20; 8162 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 8163 8164 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46); 8165 rfcsr |= 0x20; 8166 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr); 8167 8168 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20); 8169 rfcsr &= ~0xee; 8170 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); 8171 } 8172 8173 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 8174 { 8175 rt2800_rf_init_calibration(rt2x00dev, 2); 8176 8177 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 8178 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8179 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8180 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8181 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8182 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8183 else 8184 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); 8185 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8186 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8187 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8188 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8189 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8190 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8191 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8192 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8193 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8194 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8195 8196 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8197 rt2800_rfcsr_write(rt2x00dev, 21, 0x00); 8198 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8199 rt2800_rfcsr_write(rt2x00dev, 23, 0x00); 8200 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8201 if (rt2x00_is_usb(rt2x00dev) && 8202 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8203 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8204 else 8205 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); 8206 rt2800_rfcsr_write(rt2x00dev, 26, 0x00); 8207 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8208 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8209 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8210 8211 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8212 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8213 rt2800_rfcsr_write(rt2x00dev, 32, 0x80); 8214 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8215 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8216 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8217 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8218 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8219 rt2800_rfcsr_write(rt2x00dev, 38, 0x85); 8220 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8221 8222 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); 8223 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8224 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); 8225 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); 8226 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8227 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8228 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8229 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8230 else 8231 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); 8232 rt2800_rfcsr_write(rt2x00dev, 47, 0x00); 8233 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8234 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8235 8236 rt2800_rfcsr_write(rt2x00dev, 52, 0x38); 8237 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8238 rt2800_rfcsr_write(rt2x00dev, 53, 0x00); 8239 else 8240 rt2800_rfcsr_write(rt2x00dev, 53, 0x84); 8241 rt2800_rfcsr_write(rt2x00dev, 54, 0x78); 8242 rt2800_rfcsr_write(rt2x00dev, 55, 0x44); 8243 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) 8244 rt2800_rfcsr_write(rt2x00dev, 56, 0x42); 8245 else 8246 rt2800_rfcsr_write(rt2x00dev, 56, 0x22); 8247 rt2800_rfcsr_write(rt2x00dev, 57, 0x80); 8248 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); 8249 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); 8250 8251 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8252 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { 8253 if (rt2x00_is_usb(rt2x00dev)) 8254 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); 8255 else 8256 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5); 8257 } else { 8258 if (rt2x00_is_usb(rt2x00dev)) 8259 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 8260 else 8261 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5); 8262 } 8263 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 8264 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 8265 8266 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8267 8268 rt2800_led_open_drain_enable(rt2x00dev); 8269 } 8270 8271 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 8272 { 8273 rt2800_rf_init_calibration(rt2x00dev, 2); 8274 8275 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 8276 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 8277 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8278 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); 8279 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8280 rt2800_rfcsr_write(rt2x00dev, 10, 0x53); 8281 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); 8282 rt2800_rfcsr_write(rt2x00dev, 12, 0x46); 8283 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); 8284 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8285 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8286 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8287 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8288 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); 8289 rt2800_rfcsr_write(rt2x00dev, 20, 0x00); 8290 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); 8291 rt2800_rfcsr_write(rt2x00dev, 22, 0x20); 8292 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); 8293 rt2800_rfcsr_write(rt2x00dev, 24, 0x44); 8294 rt2800_rfcsr_write(rt2x00dev, 25, 0x80); 8295 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8296 rt2800_rfcsr_write(rt2x00dev, 27, 0x09); 8297 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8298 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8299 rt2800_rfcsr_write(rt2x00dev, 30, 0x10); 8300 rt2800_rfcsr_write(rt2x00dev, 31, 0x80); 8301 rt2800_rfcsr_write(rt2x00dev, 32, 0x20); 8302 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8303 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8304 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8305 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8306 rt2800_rfcsr_write(rt2x00dev, 37, 0x08); 8307 rt2800_rfcsr_write(rt2x00dev, 38, 0x89); 8308 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); 8309 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); 8310 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); 8311 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); 8312 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); 8313 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); 8314 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); 8315 rt2800_rfcsr_write(rt2x00dev, 46, 0x73); 8316 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); 8317 rt2800_rfcsr_write(rt2x00dev, 48, 0x10); 8318 rt2800_rfcsr_write(rt2x00dev, 49, 0x94); 8319 rt2800_rfcsr_write(rt2x00dev, 50, 0x94); 8320 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); 8321 rt2800_rfcsr_write(rt2x00dev, 52, 0x48); 8322 rt2800_rfcsr_write(rt2x00dev, 53, 0x44); 8323 rt2800_rfcsr_write(rt2x00dev, 54, 0x38); 8324 rt2800_rfcsr_write(rt2x00dev, 55, 0x43); 8325 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); 8326 rt2800_rfcsr_write(rt2x00dev, 57, 0x00); 8327 rt2800_rfcsr_write(rt2x00dev, 58, 0x39); 8328 rt2800_rfcsr_write(rt2x00dev, 59, 0x07); 8329 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 8330 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 8331 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 8332 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8333 8334 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8335 8336 rt2800_led_open_drain_enable(rt2x00dev); 8337 } 8338 8339 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev) 8340 { 8341 rt2800_rf_init_calibration(rt2x00dev, 30); 8342 8343 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F); 8344 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 8345 rt2800_rfcsr_write(rt2x00dev, 5, 0x10); 8346 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4); 8347 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8348 rt2800_rfcsr_write(rt2x00dev, 14, 0x00); 8349 rt2800_rfcsr_write(rt2x00dev, 15, 0x00); 8350 rt2800_rfcsr_write(rt2x00dev, 16, 0x00); 8351 rt2800_rfcsr_write(rt2x00dev, 18, 0x03); 8352 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D); 8353 rt2800_rfcsr_write(rt2x00dev, 20, 0x10); 8354 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D); 8355 rt2800_rfcsr_write(rt2x00dev, 26, 0x82); 8356 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8357 rt2800_rfcsr_write(rt2x00dev, 29, 0x10); 8358 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); 8359 rt2800_rfcsr_write(rt2x00dev, 34, 0x07); 8360 rt2800_rfcsr_write(rt2x00dev, 35, 0x12); 8361 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C); 8362 rt2800_rfcsr_write(rt2x00dev, 53, 0x22); 8363 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 8364 8365 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 8366 msleep(1); 8367 8368 rt2800_freq_cal_mode1(rt2x00dev); 8369 8370 /* Enable DC filter */ 8371 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) 8372 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 8373 8374 rt2800_normal_mode_setup_5xxx(rt2x00dev); 8375 8376 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C)) 8377 rt2800_rfcsr_write(rt2x00dev, 27, 0x03); 8378 8379 rt2800_led_open_drain_enable(rt2x00dev); 8380 } 8381 8382 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, 8383 bool set_bw, bool is_ht40) 8384 { 8385 u8 bbp_val; 8386 8387 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8388 bbp_val |= 0x1; 8389 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8390 usleep_range(100, 200); 8391 8392 if (set_bw) { 8393 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8394 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); 8395 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8396 usleep_range(100, 200); 8397 } 8398 8399 bbp_val = rt2800_bbp_read(rt2x00dev, 21); 8400 bbp_val &= (~0x1); 8401 rt2800_bbp_write(rt2x00dev, 21, bbp_val); 8402 usleep_range(100, 200); 8403 } 8404 8405 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) 8406 { 8407 u8 rf_val; 8408 8409 if (btxcal) 8410 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); 8411 else 8412 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); 8413 8414 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); 8415 8416 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8417 rf_val |= 0x80; 8418 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); 8419 8420 if (btxcal) { 8421 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); 8422 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); 8423 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8424 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8425 rf_val &= (~0x3F); 8426 rf_val |= 0x3F; 8427 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8428 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8429 rf_val &= (~0x3F); 8430 rf_val |= 0x3F; 8431 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8432 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); 8433 } else { 8434 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); 8435 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); 8436 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); 8437 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8438 rf_val &= (~0x3F); 8439 rf_val |= 0x34; 8440 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); 8441 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8442 rf_val &= (~0x3F); 8443 rf_val |= 0x34; 8444 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); 8445 } 8446 8447 return 0; 8448 } 8449 8450 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) 8451 { 8452 unsigned int cnt; 8453 u8 bbp_val; 8454 char cal_val; 8455 8456 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); 8457 8458 cnt = 0; 8459 do { 8460 usleep_range(500, 2000); 8461 bbp_val = rt2800_bbp_read(rt2x00dev, 159); 8462 if (bbp_val == 0x02 || cnt == 20) 8463 break; 8464 8465 cnt++; 8466 } while (cnt < 20); 8467 8468 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39); 8469 cal_val = bbp_val & 0x7F; 8470 if (cal_val >= 0x40) 8471 cal_val -= 128; 8472 8473 return cal_val; 8474 } 8475 8476 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, 8477 bool btxcal) 8478 { 8479 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 8480 u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; 8481 u8 filter_target; 8482 u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; 8483 u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; 8484 int loop = 0, is_ht40, cnt; 8485 u8 bbp_val, rf_val; 8486 char cal_r32_init, cal_r32_val, cal_diff; 8487 u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; 8488 u8 saverfb5r06, saverfb5r07; 8489 u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; 8490 u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; 8491 u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; 8492 u8 saverfb5r58, saverfb5r59; 8493 u8 savebbp159r0, savebbp159r2, savebbpr23; 8494 u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; 8495 8496 /* Save MAC registers */ 8497 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); 8498 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); 8499 8500 /* save BBP registers */ 8501 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23); 8502 8503 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0); 8504 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8505 8506 /* Save RF registers */ 8507 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8508 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8509 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3); 8510 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4); 8511 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5); 8512 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8513 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8514 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8515 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17); 8516 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18); 8517 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19); 8518 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20); 8519 8520 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37); 8521 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38); 8522 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39); 8523 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40); 8524 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41); 8525 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42); 8526 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43); 8527 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44); 8528 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45); 8529 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46); 8530 8531 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8532 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8533 8534 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8535 rf_val |= 0x3; 8536 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8537 8538 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8539 rf_val |= 0x1; 8540 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); 8541 8542 cnt = 0; 8543 do { 8544 usleep_range(500, 2000); 8545 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1); 8546 if (((rf_val & 0x1) == 0x00) || (cnt == 40)) 8547 break; 8548 cnt++; 8549 } while (cnt < 40); 8550 8551 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0); 8552 rf_val &= (~0x3); 8553 rf_val |= 0x1; 8554 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); 8555 8556 /* I-3 */ 8557 bbp_val = rt2800_bbp_read(rt2x00dev, 23); 8558 bbp_val &= (~0x1F); 8559 bbp_val |= 0x10; 8560 rt2800_bbp_write(rt2x00dev, 23, bbp_val); 8561 8562 do { 8563 /* I-4,5,6,7,8,9 */ 8564 if (loop == 0) { 8565 is_ht40 = false; 8566 8567 if (btxcal) 8568 filter_target = tx_filter_target_20m; 8569 else 8570 filter_target = rx_filter_target_20m; 8571 } else { 8572 is_ht40 = true; 8573 8574 if (btxcal) 8575 filter_target = tx_filter_target_40m; 8576 else 8577 filter_target = rx_filter_target_40m; 8578 } 8579 8580 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8); 8581 rf_val &= (~0x04); 8582 if (loop == 1) 8583 rf_val |= 0x4; 8584 8585 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); 8586 8587 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); 8588 8589 rt2800_rf_lp_config(rt2x00dev, btxcal); 8590 if (btxcal) { 8591 tx_agc_fc = 0; 8592 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8593 rf_val &= (~0x7F); 8594 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8595 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8596 rf_val &= (~0x7F); 8597 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8598 } else { 8599 rx_agc_fc = 0; 8600 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8601 rf_val &= (~0x7F); 8602 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8603 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8604 rf_val &= (~0x7F); 8605 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8606 } 8607 8608 usleep_range(1000, 2000); 8609 8610 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8611 bbp_val &= (~0x6); 8612 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8613 8614 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8615 8616 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8617 8618 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2); 8619 bbp_val |= 0x6; 8620 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); 8621 do_cal: 8622 if (btxcal) { 8623 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58); 8624 rf_val &= (~0x7F); 8625 rf_val |= tx_agc_fc; 8626 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); 8627 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59); 8628 rf_val &= (~0x7F); 8629 rf_val |= tx_agc_fc; 8630 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); 8631 } else { 8632 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6); 8633 rf_val &= (~0x7F); 8634 rf_val |= rx_agc_fc; 8635 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); 8636 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7); 8637 rf_val &= (~0x7F); 8638 rf_val |= rx_agc_fc; 8639 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); 8640 } 8641 8642 usleep_range(500, 1000); 8643 8644 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); 8645 8646 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); 8647 8648 cal_diff = cal_r32_init - cal_r32_val; 8649 8650 if (btxcal) 8651 cmm_agc_fc = tx_agc_fc; 8652 else 8653 cmm_agc_fc = rx_agc_fc; 8654 8655 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || 8656 ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { 8657 if (btxcal) 8658 tx_agc_fc = 0; 8659 else 8660 rx_agc_fc = 0; 8661 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { 8662 if (btxcal) 8663 tx_agc_fc++; 8664 else 8665 rx_agc_fc++; 8666 goto do_cal; 8667 } 8668 8669 if (btxcal) { 8670 if (loop == 0) 8671 drv_data->tx_calibration_bw20 = tx_agc_fc; 8672 else 8673 drv_data->tx_calibration_bw40 = tx_agc_fc; 8674 } else { 8675 if (loop == 0) 8676 drv_data->rx_calibration_bw20 = rx_agc_fc; 8677 else 8678 drv_data->rx_calibration_bw40 = rx_agc_fc; 8679 } 8680 8681 loop++; 8682 } while (loop <= 1); 8683 8684 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); 8685 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); 8686 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); 8687 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); 8688 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); 8689 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); 8690 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); 8691 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); 8692 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); 8693 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); 8694 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); 8695 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); 8696 8697 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); 8698 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); 8699 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); 8700 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); 8701 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); 8702 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); 8703 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); 8704 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); 8705 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); 8706 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); 8707 8708 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); 8709 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); 8710 8711 rt2800_bbp_write(rt2x00dev, 23, savebbpr23); 8712 8713 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); 8714 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); 8715 8716 bbp_val = rt2800_bbp_read(rt2x00dev, 4); 8717 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 8718 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); 8719 rt2800_bbp_write(rt2x00dev, 4, bbp_val); 8720 8721 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); 8722 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); 8723 } 8724 8725 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) 8726 { 8727 /* Initialize RF central register to default value */ 8728 rt2800_rfcsr_write(rt2x00dev, 0, 0x02); 8729 rt2800_rfcsr_write(rt2x00dev, 1, 0x03); 8730 rt2800_rfcsr_write(rt2x00dev, 2, 0x33); 8731 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF); 8732 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C); 8733 rt2800_rfcsr_write(rt2x00dev, 5, 0x40); 8734 rt2800_rfcsr_write(rt2x00dev, 6, 0x00); 8735 rt2800_rfcsr_write(rt2x00dev, 7, 0x00); 8736 rt2800_rfcsr_write(rt2x00dev, 8, 0x00); 8737 rt2800_rfcsr_write(rt2x00dev, 9, 0x00); 8738 rt2800_rfcsr_write(rt2x00dev, 10, 0x00); 8739 rt2800_rfcsr_write(rt2x00dev, 11, 0x00); 8740 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset); 8741 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8742 rt2800_rfcsr_write(rt2x00dev, 14, 0x40); 8743 rt2800_rfcsr_write(rt2x00dev, 15, 0x22); 8744 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C); 8745 rt2800_rfcsr_write(rt2x00dev, 17, 0x00); 8746 rt2800_rfcsr_write(rt2x00dev, 18, 0x00); 8747 rt2800_rfcsr_write(rt2x00dev, 19, 0x00); 8748 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0); 8749 rt2800_rfcsr_write(rt2x00dev, 21, 0x12); 8750 rt2800_rfcsr_write(rt2x00dev, 22, 0x07); 8751 rt2800_rfcsr_write(rt2x00dev, 23, 0x13); 8752 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE); 8753 rt2800_rfcsr_write(rt2x00dev, 25, 0x24); 8754 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A); 8755 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8756 rt2800_rfcsr_write(rt2x00dev, 28, 0x00); 8757 rt2800_rfcsr_write(rt2x00dev, 29, 0x05); 8758 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 8759 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 8760 rt2800_rfcsr_write(rt2x00dev, 32, 0x00); 8761 rt2800_rfcsr_write(rt2x00dev, 33, 0x00); 8762 rt2800_rfcsr_write(rt2x00dev, 34, 0x00); 8763 rt2800_rfcsr_write(rt2x00dev, 35, 0x00); 8764 rt2800_rfcsr_write(rt2x00dev, 36, 0x00); 8765 rt2800_rfcsr_write(rt2x00dev, 37, 0x00); 8766 rt2800_rfcsr_write(rt2x00dev, 38, 0x00); 8767 rt2800_rfcsr_write(rt2x00dev, 39, 0x00); 8768 rt2800_rfcsr_write(rt2x00dev, 40, 0x00); 8769 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0); 8770 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B); 8771 rt2800_rfcsr_write(rt2x00dev, 43, 0x00); 8772 8773 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 8774 if (rt2800_clk_is_20mhz(rt2x00dev)) 8775 rt2800_rfcsr_write(rt2x00dev, 13, 0x03); 8776 else 8777 rt2800_rfcsr_write(rt2x00dev, 13, 0x00); 8778 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C); 8779 rt2800_rfcsr_write(rt2x00dev, 16, 0x80); 8780 rt2800_rfcsr_write(rt2x00dev, 17, 0x99); 8781 rt2800_rfcsr_write(rt2x00dev, 18, 0x99); 8782 rt2800_rfcsr_write(rt2x00dev, 19, 0x09); 8783 rt2800_rfcsr_write(rt2x00dev, 20, 0x50); 8784 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0); 8785 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 8786 rt2800_rfcsr_write(rt2x00dev, 23, 0x06); 8787 rt2800_rfcsr_write(rt2x00dev, 24, 0x00); 8788 rt2800_rfcsr_write(rt2x00dev, 25, 0x00); 8789 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D); 8790 rt2800_rfcsr_write(rt2x00dev, 27, 0x00); 8791 rt2800_rfcsr_write(rt2x00dev, 28, 0x61); 8792 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5); 8793 rt2800_rfcsr_write(rt2x00dev, 43, 0x02); 8794 8795 rt2800_rfcsr_write(rt2x00dev, 28, 0x62); 8796 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD); 8797 rt2800_rfcsr_write(rt2x00dev, 39, 0x80); 8798 8799 /* Initialize RF channel register to default value */ 8800 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03); 8801 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00); 8802 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00); 8803 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00); 8804 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00); 8805 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08); 8806 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00); 8807 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51); 8808 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53); 8809 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16); 8810 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61); 8811 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8812 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22); 8813 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); 8814 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8815 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13); 8816 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22); 8817 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27); 8818 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02); 8819 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8820 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01); 8821 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52); 8822 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80); 8823 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3); 8824 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00); 8825 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00); 8826 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00); 8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00); 8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C); 8829 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B); 8830 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B); 8831 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31); 8832 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D); 8833 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00); 8834 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6); 8835 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55); 8836 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00); 8837 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB); 8838 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3); 8839 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3); 8840 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03); 8841 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00); 8842 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00); 8843 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3); 8844 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3); 8845 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8846 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07); 8847 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68); 8848 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF); 8849 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C); 8850 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07); 8851 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8); 8852 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85); 8853 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10); 8854 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07); 8855 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A); 8856 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85); 8857 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10); 8858 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C); 8859 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00); 8860 8861 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5); 8862 8863 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47); 8864 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71); 8865 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33); 8866 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E); 8867 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23); 8868 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4); 8869 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02); 8870 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12); 8871 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C); 8872 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB); 8873 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D); 8874 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6); 8875 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08); 8876 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4); 8877 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8878 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3); 8879 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5); 8880 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27); 8881 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67); 8882 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69); 8883 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF); 8884 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27); 8885 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20); 8886 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8887 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF); 8888 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C); 8889 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20); 8890 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8891 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7); 8892 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09); 8893 8894 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51); 8895 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06); 8896 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7); 8897 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C); 8898 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64); 8899 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51); 8900 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36); 8901 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53); 8902 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16); 8903 8904 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C); 8905 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC); 8906 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F); 8907 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27); 8908 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66); 8909 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B); 8910 8911 /* Initialize RF channel register for DRQFN */ 8912 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3); 8913 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3); 8914 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5); 8915 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28); 8916 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68); 8917 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7); 8918 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02); 8919 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7); 8920 8921 /* Initialize RF DC calibration register to default value */ 8922 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47); 8923 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00); 8924 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00); 8925 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00); 8926 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00); 8927 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8928 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10); 8929 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10); 8930 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04); 8931 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00); 8932 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07); 8933 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01); 8934 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07); 8935 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07); 8936 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07); 8937 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20); 8938 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22); 8939 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00); 8940 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00); 8941 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00); 8942 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00); 8943 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1); 8944 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11); 8945 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02); 8946 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41); 8947 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20); 8948 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00); 8949 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7); 8950 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2); 8951 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20); 8952 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49); 8953 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20); 8954 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04); 8955 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1); 8956 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1); 8957 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01); 8958 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00); 8959 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00); 8960 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00); 8961 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00); 8962 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00); 8963 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00); 8964 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E); 8965 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D); 8966 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E); 8967 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D); 8968 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E); 8969 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D); 8970 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00); 8971 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00); 8972 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00); 8973 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00); 8974 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00); 8975 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10); 8976 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10); 8977 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A); 8978 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00); 8979 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00); 8980 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00); 8981 8982 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08); 8983 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04); 8984 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20); 8985 8986 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); 8987 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); 8988 8989 rt2800_bw_filter_calibration(rt2x00dev, true); 8990 rt2800_bw_filter_calibration(rt2x00dev, false); 8991 } 8992 8993 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 8994 { 8995 if (rt2800_is_305x_soc(rt2x00dev)) { 8996 rt2800_init_rfcsr_305x_soc(rt2x00dev); 8997 return; 8998 } 8999 9000 switch (rt2x00dev->chip.rt) { 9001 case RT3070: 9002 case RT3071: 9003 case RT3090: 9004 rt2800_init_rfcsr_30xx(rt2x00dev); 9005 break; 9006 case RT3290: 9007 rt2800_init_rfcsr_3290(rt2x00dev); 9008 break; 9009 case RT3352: 9010 rt2800_init_rfcsr_3352(rt2x00dev); 9011 break; 9012 case RT3390: 9013 rt2800_init_rfcsr_3390(rt2x00dev); 9014 break; 9015 case RT3883: 9016 rt2800_init_rfcsr_3883(rt2x00dev); 9017 break; 9018 case RT3572: 9019 rt2800_init_rfcsr_3572(rt2x00dev); 9020 break; 9021 case RT3593: 9022 rt2800_init_rfcsr_3593(rt2x00dev); 9023 break; 9024 case RT5350: 9025 rt2800_init_rfcsr_5350(rt2x00dev); 9026 break; 9027 case RT5390: 9028 rt2800_init_rfcsr_5390(rt2x00dev); 9029 break; 9030 case RT5392: 9031 rt2800_init_rfcsr_5392(rt2x00dev); 9032 break; 9033 case RT5592: 9034 rt2800_init_rfcsr_5592(rt2x00dev); 9035 break; 9036 case RT6352: 9037 rt2800_init_rfcsr_6352(rt2x00dev); 9038 break; 9039 } 9040 } 9041 9042 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 9043 { 9044 u32 reg; 9045 u16 word; 9046 9047 /* 9048 * Initialize MAC registers. 9049 */ 9050 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 9051 rt2800_init_registers(rt2x00dev))) 9052 return -EIO; 9053 9054 /* 9055 * Wait BBP/RF to wake up. 9056 */ 9057 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) 9058 return -EIO; 9059 9060 /* 9061 * Send signal during boot time to initialize firmware. 9062 */ 9063 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 9064 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 9065 if (rt2x00_is_usb(rt2x00dev)) 9066 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 9067 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 9068 msleep(1); 9069 9070 /* 9071 * Make sure BBP is up and running. 9072 */ 9073 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) 9074 return -EIO; 9075 9076 /* 9077 * Initialize BBP/RF registers. 9078 */ 9079 rt2800_init_bbp(rt2x00dev); 9080 rt2800_init_rfcsr(rt2x00dev); 9081 9082 if (rt2x00_is_usb(rt2x00dev) && 9083 (rt2x00_rt(rt2x00dev, RT3070) || 9084 rt2x00_rt(rt2x00dev, RT3071) || 9085 rt2x00_rt(rt2x00dev, RT3572))) { 9086 udelay(200); 9087 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 9088 udelay(10); 9089 } 9090 9091 /* 9092 * Enable RX. 9093 */ 9094 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9095 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9096 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9097 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9098 9099 udelay(50); 9100 9101 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); 9102 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 9103 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 9104 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 9105 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 9106 9107 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9108 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); 9109 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); 9110 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9111 9112 /* 9113 * Initialize LED control 9114 */ 9115 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF); 9116 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff, 9117 word & 0xff, (word >> 8) & 0xff); 9118 9119 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF); 9120 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff, 9121 word & 0xff, (word >> 8) & 0xff); 9122 9123 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY); 9124 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff, 9125 word & 0xff, (word >> 8) & 0xff); 9126 9127 return 0; 9128 } 9129 EXPORT_SYMBOL_GPL(rt2800_enable_radio); 9130 9131 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) 9132 { 9133 u32 reg; 9134 9135 rt2800_disable_wpdma(rt2x00dev); 9136 9137 /* Wait for DMA, ignore error */ 9138 rt2800_wait_wpdma_ready(rt2x00dev); 9139 9140 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); 9141 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); 9142 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); 9143 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 9144 } 9145 EXPORT_SYMBOL_GPL(rt2800_disable_radio); 9146 9147 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 9148 { 9149 u32 reg; 9150 u16 efuse_ctrl_reg; 9151 9152 if (rt2x00_rt(rt2x00dev, RT3290)) 9153 efuse_ctrl_reg = EFUSE_CTRL_3290; 9154 else 9155 efuse_ctrl_reg = EFUSE_CTRL; 9156 9157 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); 9158 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 9159 } 9160 EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 9161 9162 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 9163 { 9164 u32 reg; 9165 u16 efuse_ctrl_reg; 9166 u16 efuse_data0_reg; 9167 u16 efuse_data1_reg; 9168 u16 efuse_data2_reg; 9169 u16 efuse_data3_reg; 9170 9171 if (rt2x00_rt(rt2x00dev, RT3290)) { 9172 efuse_ctrl_reg = EFUSE_CTRL_3290; 9173 efuse_data0_reg = EFUSE_DATA0_3290; 9174 efuse_data1_reg = EFUSE_DATA1_3290; 9175 efuse_data2_reg = EFUSE_DATA2_3290; 9176 efuse_data3_reg = EFUSE_DATA3_3290; 9177 } else { 9178 efuse_ctrl_reg = EFUSE_CTRL; 9179 efuse_data0_reg = EFUSE_DATA0; 9180 efuse_data1_reg = EFUSE_DATA1; 9181 efuse_data2_reg = EFUSE_DATA2; 9182 efuse_data3_reg = EFUSE_DATA3; 9183 } 9184 mutex_lock(&rt2x00dev->csr_mutex); 9185 9186 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); 9187 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); 9188 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); 9189 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); 9190 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); 9191 9192 /* Wait until the EEPROM has been loaded */ 9193 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); 9194 /* Apparently the data is read from end to start */ 9195 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); 9196 /* The returned value is in CPU order, but eeprom is le */ 9197 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 9198 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); 9199 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 9200 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); 9201 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 9202 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); 9203 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 9204 9205 mutex_unlock(&rt2x00dev->csr_mutex); 9206 } 9207 9208 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev) 9209 { 9210 unsigned int i; 9211 9212 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8) 9213 rt2800_efuse_read(rt2x00dev, i); 9214 9215 return 0; 9216 } 9217 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse); 9218 9219 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev) 9220 { 9221 u16 word; 9222 9223 if (rt2x00_rt(rt2x00dev, RT3593) || 9224 rt2x00_rt(rt2x00dev, RT3883)) 9225 return 0; 9226 9227 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG); 9228 if ((word & 0x00ff) != 0x00ff) 9229 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL); 9230 9231 return 0; 9232 } 9233 9234 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev) 9235 { 9236 u16 word; 9237 9238 if (rt2x00_rt(rt2x00dev, RT3593) || 9239 rt2x00_rt(rt2x00dev, RT3883)) 9240 return 0; 9241 9242 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A); 9243 if ((word & 0x00ff) != 0x00ff) 9244 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL); 9245 9246 return 0; 9247 } 9248 9249 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev) 9250 { 9251 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 9252 u16 word; 9253 u8 *mac; 9254 u8 default_lna_gain; 9255 int retval; 9256 9257 /* 9258 * Read the EEPROM. 9259 */ 9260 retval = rt2800_read_eeprom(rt2x00dev); 9261 if (retval) 9262 return retval; 9263 9264 /* 9265 * Start validation of the data that has been read. 9266 */ 9267 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 9268 rt2x00lib_set_mac_address(rt2x00dev, mac); 9269 9270 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9271 if (word == 0xffff) { 9272 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9273 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 9274 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 9275 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9276 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); 9277 } else if (rt2x00_rt(rt2x00dev, RT2860) || 9278 rt2x00_rt(rt2x00dev, RT2872)) { 9279 /* 9280 * There is a max of 2 RX streams for RT28x0 series 9281 */ 9282 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2) 9283 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2); 9284 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 9285 } 9286 9287 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9288 if (word == 0xffff) { 9289 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0); 9290 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0); 9291 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0); 9292 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0); 9293 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0); 9294 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0); 9295 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0); 9296 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0); 9297 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0); 9298 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0); 9299 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0); 9300 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0); 9301 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0); 9302 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 9303 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 9304 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 9305 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); 9306 } 9307 9308 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9309 if ((word & 0x00ff) == 0x00ff) { 9310 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 9311 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9312 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); 9313 } 9314 if ((word & 0xff00) == 0xff00) { 9315 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 9316 LED_MODE_TXRX_ACTIVITY); 9317 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0); 9318 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 9319 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 9320 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 9321 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 9322 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word); 9323 } 9324 9325 /* 9326 * During the LNA validation we are going to use 9327 * lna0 as correct value. Note that EEPROM_LNA 9328 * is never validated. 9329 */ 9330 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA); 9331 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0); 9332 9333 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG); 9334 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10) 9335 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0); 9336 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10) 9337 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0); 9338 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word); 9339 9340 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev); 9341 9342 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2); 9343 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10) 9344 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0); 9345 if (!rt2x00_rt(rt2x00dev, RT3593) && 9346 !rt2x00_rt(rt2x00dev, RT3883)) { 9347 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 || 9348 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff) 9349 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1, 9350 default_lna_gain); 9351 } 9352 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word); 9353 9354 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev); 9355 9356 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A); 9357 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10) 9358 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0); 9359 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10) 9360 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0); 9361 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word); 9362 9363 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2); 9364 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10) 9365 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0); 9366 if (!rt2x00_rt(rt2x00dev, RT3593) && 9367 !rt2x00_rt(rt2x00dev, RT3883)) { 9368 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 || 9369 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff) 9370 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2, 9371 default_lna_gain); 9372 } 9373 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 9374 9375 if (rt2x00_rt(rt2x00dev, RT3593) || 9376 rt2x00_rt(rt2x00dev, RT3883)) { 9377 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2); 9378 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 || 9379 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff) 9380 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9381 default_lna_gain); 9382 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 || 9383 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff) 9384 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1, 9385 default_lna_gain); 9386 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word); 9387 } 9388 9389 return 0; 9390 } 9391 9392 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 9393 { 9394 u16 value; 9395 u16 eeprom; 9396 u16 rf; 9397 9398 /* 9399 * Read EEPROM word for configuration. 9400 */ 9401 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0); 9402 9403 /* 9404 * Identify RF chipset by EEPROM value 9405 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 9406 * RT53xx: defined in "EEPROM_CHIP_ID" field 9407 */ 9408 if (rt2x00_rt(rt2x00dev, RT3290) || 9409 rt2x00_rt(rt2x00dev, RT5390) || 9410 rt2x00_rt(rt2x00dev, RT5392) || 9411 rt2x00_rt(rt2x00dev, RT6352)) 9412 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID); 9413 else if (rt2x00_rt(rt2x00dev, RT3352)) 9414 rf = RF3322; 9415 else if (rt2x00_rt(rt2x00dev, RT3883)) 9416 rf = RF3853; 9417 else if (rt2x00_rt(rt2x00dev, RT5350)) 9418 rf = RF5350; 9419 else 9420 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 9421 9422 switch (rf) { 9423 case RF2820: 9424 case RF2850: 9425 case RF2720: 9426 case RF2750: 9427 case RF3020: 9428 case RF2020: 9429 case RF3021: 9430 case RF3022: 9431 case RF3052: 9432 case RF3053: 9433 case RF3070: 9434 case RF3290: 9435 case RF3320: 9436 case RF3322: 9437 case RF3853: 9438 case RF5350: 9439 case RF5360: 9440 case RF5362: 9441 case RF5370: 9442 case RF5372: 9443 case RF5390: 9444 case RF5392: 9445 case RF5592: 9446 case RF7620: 9447 break; 9448 default: 9449 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", 9450 rf); 9451 return -ENODEV; 9452 } 9453 9454 rt2x00_set_rf(rt2x00dev, rf); 9455 9456 /* 9457 * Identify default antenna configuration. 9458 */ 9459 rt2x00dev->default_ant.tx_chain_num = 9460 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 9461 rt2x00dev->default_ant.rx_chain_num = 9462 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 9463 9464 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9465 9466 if (rt2x00_rt(rt2x00dev, RT3070) || 9467 rt2x00_rt(rt2x00dev, RT3090) || 9468 rt2x00_rt(rt2x00dev, RT3352) || 9469 rt2x00_rt(rt2x00dev, RT3390)) { 9470 value = rt2x00_get_field16(eeprom, 9471 EEPROM_NIC_CONF1_ANT_DIVERSITY); 9472 switch (value) { 9473 case 0: 9474 case 1: 9475 case 2: 9476 rt2x00dev->default_ant.tx = ANTENNA_A; 9477 rt2x00dev->default_ant.rx = ANTENNA_A; 9478 break; 9479 case 3: 9480 rt2x00dev->default_ant.tx = ANTENNA_A; 9481 rt2x00dev->default_ant.rx = ANTENNA_B; 9482 break; 9483 } 9484 } else { 9485 rt2x00dev->default_ant.tx = ANTENNA_A; 9486 rt2x00dev->default_ant.rx = ANTENNA_A; 9487 } 9488 9489 /* These chips have hardware RX antenna diversity */ 9490 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) || 9491 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) { 9492 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */ 9493 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */ 9494 } 9495 9496 /* 9497 * Determine external LNA informations. 9498 */ 9499 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G)) 9500 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); 9501 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G)) 9502 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); 9503 9504 /* 9505 * Detect if this device has an hardware controlled radio. 9506 */ 9507 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO)) 9508 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); 9509 9510 /* 9511 * Detect if this device has Bluetooth co-existence. 9512 */ 9513 if (!rt2x00_rt(rt2x00dev, RT3352) && 9514 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) 9515 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags); 9516 9517 /* 9518 * Read frequency offset and RF programming sequence. 9519 */ 9520 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ); 9521 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); 9522 9523 /* 9524 * Store led settings, for correct led behaviour. 9525 */ 9526 #ifdef CONFIG_RT2X00_LIB_LEDS 9527 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 9528 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 9529 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 9530 9531 rt2x00dev->led_mcu_reg = eeprom; 9532 #endif /* CONFIG_RT2X00_LIB_LEDS */ 9533 9534 /* 9535 * Check if support EIRP tx power limit feature. 9536 */ 9537 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER); 9538 9539 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) < 9540 EIRP_MAX_TX_POWER_LIMIT) 9541 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags); 9542 9543 /* 9544 * Detect if device uses internal or external PA 9545 */ 9546 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1); 9547 9548 if (rt2x00_rt(rt2x00dev, RT3352)) { 9549 if (rt2x00_get_field16(eeprom, 9550 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352)) 9551 __set_bit(CAPABILITY_EXTERNAL_PA_TX0, 9552 &rt2x00dev->cap_flags); 9553 if (rt2x00_get_field16(eeprom, 9554 EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352)) 9555 __set_bit(CAPABILITY_EXTERNAL_PA_TX1, 9556 &rt2x00dev->cap_flags); 9557 } 9558 9559 return 0; 9560 } 9561 9562 /* 9563 * RF value list for rt28xx 9564 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 9565 */ 9566 static const struct rf_channel rf_vals[] = { 9567 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b }, 9568 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f }, 9569 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b }, 9570 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f }, 9571 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b }, 9572 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f }, 9573 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b }, 9574 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f }, 9575 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b }, 9576 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f }, 9577 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b }, 9578 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f }, 9579 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b }, 9580 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 }, 9581 9582 /* 802.11 UNI / HyperLan 2 */ 9583 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 }, 9584 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 }, 9585 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 }, 9586 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 }, 9587 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b }, 9588 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b }, 9589 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 }, 9590 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 }, 9591 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b }, 9592 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 }, 9593 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 }, 9594 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 }, 9595 9596 /* 802.11 HyperLan 2 */ 9597 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 }, 9598 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 }, 9599 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 }, 9600 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 }, 9601 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 }, 9602 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b }, 9603 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 }, 9604 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 }, 9605 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 }, 9606 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 }, 9607 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b }, 9608 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 }, 9609 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b }, 9610 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 }, 9611 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b }, 9612 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 }, 9613 9614 /* 802.11 UNII */ 9615 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 }, 9616 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 }, 9617 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f }, 9618 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f }, 9619 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 }, 9620 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 }, 9621 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 }, 9622 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f }, 9623 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 }, 9624 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 }, 9625 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f }, 9626 9627 /* 802.11 Japan */ 9628 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b }, 9629 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 }, 9630 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b }, 9631 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 }, 9632 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 }, 9633 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b }, 9634 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 }, 9635 }; 9636 9637 /* 9638 * RF value list for rt3xxx 9639 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) 9640 */ 9641 static const struct rf_channel rf_vals_3x[] = { 9642 {1, 241, 2, 2 }, 9643 {2, 241, 2, 7 }, 9644 {3, 242, 2, 2 }, 9645 {4, 242, 2, 7 }, 9646 {5, 243, 2, 2 }, 9647 {6, 243, 2, 7 }, 9648 {7, 244, 2, 2 }, 9649 {8, 244, 2, 7 }, 9650 {9, 245, 2, 2 }, 9651 {10, 245, 2, 7 }, 9652 {11, 246, 2, 2 }, 9653 {12, 246, 2, 7 }, 9654 {13, 247, 2, 2 }, 9655 {14, 248, 2, 4 }, 9656 9657 /* 802.11 UNI / HyperLan 2 */ 9658 {36, 0x56, 0, 4}, 9659 {38, 0x56, 0, 6}, 9660 {40, 0x56, 0, 8}, 9661 {44, 0x57, 0, 0}, 9662 {46, 0x57, 0, 2}, 9663 {48, 0x57, 0, 4}, 9664 {52, 0x57, 0, 8}, 9665 {54, 0x57, 0, 10}, 9666 {56, 0x58, 0, 0}, 9667 {60, 0x58, 0, 4}, 9668 {62, 0x58, 0, 6}, 9669 {64, 0x58, 0, 8}, 9670 9671 /* 802.11 HyperLan 2 */ 9672 {100, 0x5b, 0, 8}, 9673 {102, 0x5b, 0, 10}, 9674 {104, 0x5c, 0, 0}, 9675 {108, 0x5c, 0, 4}, 9676 {110, 0x5c, 0, 6}, 9677 {112, 0x5c, 0, 8}, 9678 {116, 0x5d, 0, 0}, 9679 {118, 0x5d, 0, 2}, 9680 {120, 0x5d, 0, 4}, 9681 {124, 0x5d, 0, 8}, 9682 {126, 0x5d, 0, 10}, 9683 {128, 0x5e, 0, 0}, 9684 {132, 0x5e, 0, 4}, 9685 {134, 0x5e, 0, 6}, 9686 {136, 0x5e, 0, 8}, 9687 {140, 0x5f, 0, 0}, 9688 9689 /* 802.11 UNII */ 9690 {149, 0x5f, 0, 9}, 9691 {151, 0x5f, 0, 11}, 9692 {153, 0x60, 0, 1}, 9693 {157, 0x60, 0, 5}, 9694 {159, 0x60, 0, 7}, 9695 {161, 0x60, 0, 9}, 9696 {165, 0x61, 0, 1}, 9697 {167, 0x61, 0, 3}, 9698 {169, 0x61, 0, 5}, 9699 {171, 0x61, 0, 7}, 9700 {173, 0x61, 0, 9}, 9701 }; 9702 9703 /* 9704 * RF value list for rt3xxx with Xtal20MHz 9705 * Supports: 2.4 GHz (all) (RF3322) 9706 */ 9707 static const struct rf_channel rf_vals_3x_xtal20[] = { 9708 {1, 0xE2, 2, 0x14}, 9709 {2, 0xE3, 2, 0x14}, 9710 {3, 0xE4, 2, 0x14}, 9711 {4, 0xE5, 2, 0x14}, 9712 {5, 0xE6, 2, 0x14}, 9713 {6, 0xE7, 2, 0x14}, 9714 {7, 0xE8, 2, 0x14}, 9715 {8, 0xE9, 2, 0x14}, 9716 {9, 0xEA, 2, 0x14}, 9717 {10, 0xEB, 2, 0x14}, 9718 {11, 0xEC, 2, 0x14}, 9719 {12, 0xED, 2, 0x14}, 9720 {13, 0xEE, 2, 0x14}, 9721 {14, 0xF0, 2, 0x18}, 9722 }; 9723 9724 static const struct rf_channel rf_vals_3853[] = { 9725 {1, 241, 6, 2}, 9726 {2, 241, 6, 7}, 9727 {3, 242, 6, 2}, 9728 {4, 242, 6, 7}, 9729 {5, 243, 6, 2}, 9730 {6, 243, 6, 7}, 9731 {7, 244, 6, 2}, 9732 {8, 244, 6, 7}, 9733 {9, 245, 6, 2}, 9734 {10, 245, 6, 7}, 9735 {11, 246, 6, 2}, 9736 {12, 246, 6, 7}, 9737 {13, 247, 6, 2}, 9738 {14, 248, 6, 4}, 9739 9740 {36, 0x56, 8, 4}, 9741 {38, 0x56, 8, 6}, 9742 {40, 0x56, 8, 8}, 9743 {44, 0x57, 8, 0}, 9744 {46, 0x57, 8, 2}, 9745 {48, 0x57, 8, 4}, 9746 {52, 0x57, 8, 8}, 9747 {54, 0x57, 8, 10}, 9748 {56, 0x58, 8, 0}, 9749 {60, 0x58, 8, 4}, 9750 {62, 0x58, 8, 6}, 9751 {64, 0x58, 8, 8}, 9752 9753 {100, 0x5b, 8, 8}, 9754 {102, 0x5b, 8, 10}, 9755 {104, 0x5c, 8, 0}, 9756 {108, 0x5c, 8, 4}, 9757 {110, 0x5c, 8, 6}, 9758 {112, 0x5c, 8, 8}, 9759 {114, 0x5c, 8, 10}, 9760 {116, 0x5d, 8, 0}, 9761 {118, 0x5d, 8, 2}, 9762 {120, 0x5d, 8, 4}, 9763 {124, 0x5d, 8, 8}, 9764 {126, 0x5d, 8, 10}, 9765 {128, 0x5e, 8, 0}, 9766 {132, 0x5e, 8, 4}, 9767 {134, 0x5e, 8, 6}, 9768 {136, 0x5e, 8, 8}, 9769 {140, 0x5f, 8, 0}, 9770 9771 {149, 0x5f, 8, 9}, 9772 {151, 0x5f, 8, 11}, 9773 {153, 0x60, 8, 1}, 9774 {157, 0x60, 8, 5}, 9775 {159, 0x60, 8, 7}, 9776 {161, 0x60, 8, 9}, 9777 {165, 0x61, 8, 1}, 9778 {167, 0x61, 8, 3}, 9779 {169, 0x61, 8, 5}, 9780 {171, 0x61, 8, 7}, 9781 {173, 0x61, 8, 9}, 9782 }; 9783 9784 static const struct rf_channel rf_vals_5592_xtal20[] = { 9785 /* Channel, N, K, mod, R */ 9786 {1, 482, 4, 10, 3}, 9787 {2, 483, 4, 10, 3}, 9788 {3, 484, 4, 10, 3}, 9789 {4, 485, 4, 10, 3}, 9790 {5, 486, 4, 10, 3}, 9791 {6, 487, 4, 10, 3}, 9792 {7, 488, 4, 10, 3}, 9793 {8, 489, 4, 10, 3}, 9794 {9, 490, 4, 10, 3}, 9795 {10, 491, 4, 10, 3}, 9796 {11, 492, 4, 10, 3}, 9797 {12, 493, 4, 10, 3}, 9798 {13, 494, 4, 10, 3}, 9799 {14, 496, 8, 10, 3}, 9800 {36, 172, 8, 12, 1}, 9801 {38, 173, 0, 12, 1}, 9802 {40, 173, 4, 12, 1}, 9803 {42, 173, 8, 12, 1}, 9804 {44, 174, 0, 12, 1}, 9805 {46, 174, 4, 12, 1}, 9806 {48, 174, 8, 12, 1}, 9807 {50, 175, 0, 12, 1}, 9808 {52, 175, 4, 12, 1}, 9809 {54, 175, 8, 12, 1}, 9810 {56, 176, 0, 12, 1}, 9811 {58, 176, 4, 12, 1}, 9812 {60, 176, 8, 12, 1}, 9813 {62, 177, 0, 12, 1}, 9814 {64, 177, 4, 12, 1}, 9815 {100, 183, 4, 12, 1}, 9816 {102, 183, 8, 12, 1}, 9817 {104, 184, 0, 12, 1}, 9818 {106, 184, 4, 12, 1}, 9819 {108, 184, 8, 12, 1}, 9820 {110, 185, 0, 12, 1}, 9821 {112, 185, 4, 12, 1}, 9822 {114, 185, 8, 12, 1}, 9823 {116, 186, 0, 12, 1}, 9824 {118, 186, 4, 12, 1}, 9825 {120, 186, 8, 12, 1}, 9826 {122, 187, 0, 12, 1}, 9827 {124, 187, 4, 12, 1}, 9828 {126, 187, 8, 12, 1}, 9829 {128, 188, 0, 12, 1}, 9830 {130, 188, 4, 12, 1}, 9831 {132, 188, 8, 12, 1}, 9832 {134, 189, 0, 12, 1}, 9833 {136, 189, 4, 12, 1}, 9834 {138, 189, 8, 12, 1}, 9835 {140, 190, 0, 12, 1}, 9836 {149, 191, 6, 12, 1}, 9837 {151, 191, 10, 12, 1}, 9838 {153, 192, 2, 12, 1}, 9839 {155, 192, 6, 12, 1}, 9840 {157, 192, 10, 12, 1}, 9841 {159, 193, 2, 12, 1}, 9842 {161, 193, 6, 12, 1}, 9843 {165, 194, 2, 12, 1}, 9844 {184, 164, 0, 12, 1}, 9845 {188, 164, 4, 12, 1}, 9846 {192, 165, 8, 12, 1}, 9847 {196, 166, 0, 12, 1}, 9848 }; 9849 9850 static const struct rf_channel rf_vals_5592_xtal40[] = { 9851 /* Channel, N, K, mod, R */ 9852 {1, 241, 2, 10, 3}, 9853 {2, 241, 7, 10, 3}, 9854 {3, 242, 2, 10, 3}, 9855 {4, 242, 7, 10, 3}, 9856 {5, 243, 2, 10, 3}, 9857 {6, 243, 7, 10, 3}, 9858 {7, 244, 2, 10, 3}, 9859 {8, 244, 7, 10, 3}, 9860 {9, 245, 2, 10, 3}, 9861 {10, 245, 7, 10, 3}, 9862 {11, 246, 2, 10, 3}, 9863 {12, 246, 7, 10, 3}, 9864 {13, 247, 2, 10, 3}, 9865 {14, 248, 4, 10, 3}, 9866 {36, 86, 4, 12, 1}, 9867 {38, 86, 6, 12, 1}, 9868 {40, 86, 8, 12, 1}, 9869 {42, 86, 10, 12, 1}, 9870 {44, 87, 0, 12, 1}, 9871 {46, 87, 2, 12, 1}, 9872 {48, 87, 4, 12, 1}, 9873 {50, 87, 6, 12, 1}, 9874 {52, 87, 8, 12, 1}, 9875 {54, 87, 10, 12, 1}, 9876 {56, 88, 0, 12, 1}, 9877 {58, 88, 2, 12, 1}, 9878 {60, 88, 4, 12, 1}, 9879 {62, 88, 6, 12, 1}, 9880 {64, 88, 8, 12, 1}, 9881 {100, 91, 8, 12, 1}, 9882 {102, 91, 10, 12, 1}, 9883 {104, 92, 0, 12, 1}, 9884 {106, 92, 2, 12, 1}, 9885 {108, 92, 4, 12, 1}, 9886 {110, 92, 6, 12, 1}, 9887 {112, 92, 8, 12, 1}, 9888 {114, 92, 10, 12, 1}, 9889 {116, 93, 0, 12, 1}, 9890 {118, 93, 2, 12, 1}, 9891 {120, 93, 4, 12, 1}, 9892 {122, 93, 6, 12, 1}, 9893 {124, 93, 8, 12, 1}, 9894 {126, 93, 10, 12, 1}, 9895 {128, 94, 0, 12, 1}, 9896 {130, 94, 2, 12, 1}, 9897 {132, 94, 4, 12, 1}, 9898 {134, 94, 6, 12, 1}, 9899 {136, 94, 8, 12, 1}, 9900 {138, 94, 10, 12, 1}, 9901 {140, 95, 0, 12, 1}, 9902 {149, 95, 9, 12, 1}, 9903 {151, 95, 11, 12, 1}, 9904 {153, 96, 1, 12, 1}, 9905 {155, 96, 3, 12, 1}, 9906 {157, 96, 5, 12, 1}, 9907 {159, 96, 7, 12, 1}, 9908 {161, 96, 9, 12, 1}, 9909 {165, 97, 1, 12, 1}, 9910 {184, 82, 0, 12, 1}, 9911 {188, 82, 4, 12, 1}, 9912 {192, 82, 8, 12, 1}, 9913 {196, 83, 0, 12, 1}, 9914 }; 9915 9916 static const struct rf_channel rf_vals_7620[] = { 9917 {1, 0x50, 0x99, 0x99, 1}, 9918 {2, 0x50, 0x44, 0x44, 2}, 9919 {3, 0x50, 0xEE, 0xEE, 2}, 9920 {4, 0x50, 0x99, 0x99, 3}, 9921 {5, 0x51, 0x44, 0x44, 0}, 9922 {6, 0x51, 0xEE, 0xEE, 0}, 9923 {7, 0x51, 0x99, 0x99, 1}, 9924 {8, 0x51, 0x44, 0x44, 2}, 9925 {9, 0x51, 0xEE, 0xEE, 2}, 9926 {10, 0x51, 0x99, 0x99, 3}, 9927 {11, 0x52, 0x44, 0x44, 0}, 9928 {12, 0x52, 0xEE, 0xEE, 0}, 9929 {13, 0x52, 0x99, 0x99, 1}, 9930 {14, 0x52, 0x33, 0x33, 3}, 9931 }; 9932 9933 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 9934 { 9935 struct hw_mode_spec *spec = &rt2x00dev->spec; 9936 struct channel_info *info; 9937 char *default_power1; 9938 char *default_power2; 9939 char *default_power3; 9940 unsigned int i, tx_chains, rx_chains; 9941 u32 reg; 9942 9943 /* 9944 * Disable powersaving as default. 9945 */ 9946 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 9947 9948 /* 9949 * Change default retry settings to values corresponding more closely 9950 * to rate[0].count setting of minstrel rate control algorithm. 9951 */ 9952 rt2x00dev->hw->wiphy->retry_short = 2; 9953 rt2x00dev->hw->wiphy->retry_long = 2; 9954 9955 /* 9956 * Initialize all hw fields. 9957 */ 9958 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS); 9959 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION); 9960 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); 9961 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); 9962 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); 9963 9964 /* 9965 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices 9966 * unless we are capable of sending the buffered frames out after the 9967 * DTIM transmission using rt2x00lib_beacondone. This will send out 9968 * multicast and broadcast traffic immediately instead of buffering it 9969 * infinitly and thus dropping it after some time. 9970 */ 9971 if (!rt2x00_is_usb(rt2x00dev)) 9972 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); 9973 9974 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE); 9975 9976 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); 9977 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 9978 rt2800_eeprom_addr(rt2x00dev, 9979 EEPROM_MAC_ADDR_0)); 9980 9981 /* 9982 * As rt2800 has a global fallback table we cannot specify 9983 * more then one tx rate per frame but since the hw will 9984 * try several rates (based on the fallback table) we should 9985 * initialize max_report_rates to the maximum number of rates 9986 * we are going to try. Otherwise mac80211 will truncate our 9987 * reported tx rates and the rc algortihm will end up with 9988 * incorrect data. 9989 */ 9990 rt2x00dev->hw->max_rates = 1; 9991 rt2x00dev->hw->max_report_rates = 7; 9992 rt2x00dev->hw->max_rate_tries = 1; 9993 9994 /* 9995 * Initialize hw_mode information. 9996 */ 9997 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 9998 9999 switch (rt2x00dev->chip.rf) { 10000 case RF2720: 10001 case RF2820: 10002 spec->num_channels = 14; 10003 spec->channels = rf_vals; 10004 break; 10005 10006 case RF2750: 10007 case RF2850: 10008 spec->num_channels = ARRAY_SIZE(rf_vals); 10009 spec->channels = rf_vals; 10010 break; 10011 10012 case RF2020: 10013 case RF3020: 10014 case RF3021: 10015 case RF3022: 10016 case RF3070: 10017 case RF3290: 10018 case RF3320: 10019 case RF3322: 10020 case RF5350: 10021 case RF5360: 10022 case RF5362: 10023 case RF5370: 10024 case RF5372: 10025 case RF5390: 10026 case RF5392: 10027 spec->num_channels = 14; 10028 if (rt2800_clk_is_20mhz(rt2x00dev)) 10029 spec->channels = rf_vals_3x_xtal20; 10030 else 10031 spec->channels = rf_vals_3x; 10032 break; 10033 10034 case RF7620: 10035 spec->num_channels = ARRAY_SIZE(rf_vals_7620); 10036 spec->channels = rf_vals_7620; 10037 break; 10038 10039 case RF3052: 10040 case RF3053: 10041 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 10042 spec->channels = rf_vals_3x; 10043 break; 10044 10045 case RF3853: 10046 spec->num_channels = ARRAY_SIZE(rf_vals_3853); 10047 spec->channels = rf_vals_3853; 10048 break; 10049 10050 case RF5592: 10051 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); 10052 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { 10053 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); 10054 spec->channels = rf_vals_5592_xtal40; 10055 } else { 10056 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); 10057 spec->channels = rf_vals_5592_xtal20; 10058 } 10059 break; 10060 } 10061 10062 if (WARN_ON_ONCE(!spec->channels)) 10063 return -ENODEV; 10064 10065 spec->supported_bands = SUPPORT_BAND_2GHZ; 10066 if (spec->num_channels > 14) 10067 spec->supported_bands |= SUPPORT_BAND_5GHZ; 10068 10069 /* 10070 * Initialize HT information. 10071 */ 10072 if (!rt2x00_rf(rt2x00dev, RF2020)) 10073 spec->ht.ht_supported = true; 10074 else 10075 spec->ht.ht_supported = false; 10076 10077 spec->ht.cap = 10078 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 10079 IEEE80211_HT_CAP_GRN_FLD | 10080 IEEE80211_HT_CAP_SGI_20 | 10081 IEEE80211_HT_CAP_SGI_40; 10082 10083 tx_chains = rt2x00dev->default_ant.tx_chain_num; 10084 rx_chains = rt2x00dev->default_ant.rx_chain_num; 10085 10086 if (tx_chains >= 2) 10087 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; 10088 10089 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT; 10090 10091 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2; 10092 spec->ht.ampdu_density = 4; 10093 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 10094 if (tx_chains != rx_chains) { 10095 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 10096 spec->ht.mcs.tx_params |= 10097 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; 10098 } 10099 10100 switch (rx_chains) { 10101 case 3: 10102 spec->ht.mcs.rx_mask[2] = 0xff; 10103 /* fall through */ 10104 case 2: 10105 spec->ht.mcs.rx_mask[1] = 0xff; 10106 /* fall through */ 10107 case 1: 10108 spec->ht.mcs.rx_mask[0] = 0xff; 10109 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */ 10110 break; 10111 } 10112 10113 /* 10114 * Create channel information array 10115 */ 10116 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); 10117 if (!info) 10118 return -ENOMEM; 10119 10120 spec->channels_info = info; 10121 10122 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 10123 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 10124 10125 if (rt2x00dev->default_ant.tx_chain_num > 2) 10126 default_power3 = rt2800_eeprom_addr(rt2x00dev, 10127 EEPROM_EXT_TXPOWER_BG3); 10128 else 10129 default_power3 = NULL; 10130 10131 for (i = 0; i < 14; i++) { 10132 info[i].default_power1 = default_power1[i]; 10133 info[i].default_power2 = default_power2[i]; 10134 if (default_power3) 10135 info[i].default_power3 = default_power3[i]; 10136 } 10137 10138 if (spec->num_channels > 14) { 10139 default_power1 = rt2800_eeprom_addr(rt2x00dev, 10140 EEPROM_TXPOWER_A1); 10141 default_power2 = rt2800_eeprom_addr(rt2x00dev, 10142 EEPROM_TXPOWER_A2); 10143 10144 if (rt2x00dev->default_ant.tx_chain_num > 2) 10145 default_power3 = 10146 rt2800_eeprom_addr(rt2x00dev, 10147 EEPROM_EXT_TXPOWER_A3); 10148 else 10149 default_power3 = NULL; 10150 10151 for (i = 14; i < spec->num_channels; i++) { 10152 info[i].default_power1 = default_power1[i - 14]; 10153 info[i].default_power2 = default_power2[i - 14]; 10154 if (default_power3) 10155 info[i].default_power3 = default_power3[i - 14]; 10156 } 10157 } 10158 10159 switch (rt2x00dev->chip.rf) { 10160 case RF2020: 10161 case RF3020: 10162 case RF3021: 10163 case RF3022: 10164 case RF3320: 10165 case RF3052: 10166 case RF3053: 10167 case RF3070: 10168 case RF3290: 10169 case RF3853: 10170 case RF5350: 10171 case RF5360: 10172 case RF5362: 10173 case RF5370: 10174 case RF5372: 10175 case RF5390: 10176 case RF5392: 10177 case RF5592: 10178 case RF7620: 10179 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); 10180 break; 10181 } 10182 10183 return 0; 10184 } 10185 10186 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) 10187 { 10188 u32 reg; 10189 u32 rt; 10190 u32 rev; 10191 10192 if (rt2x00_rt(rt2x00dev, RT3290)) 10193 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); 10194 else 10195 reg = rt2800_register_read(rt2x00dev, MAC_CSR0); 10196 10197 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); 10198 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); 10199 10200 switch (rt) { 10201 case RT2860: 10202 case RT2872: 10203 case RT2883: 10204 case RT3070: 10205 case RT3071: 10206 case RT3090: 10207 case RT3290: 10208 case RT3352: 10209 case RT3390: 10210 case RT3572: 10211 case RT3593: 10212 case RT3883: 10213 case RT5350: 10214 case RT5390: 10215 case RT5392: 10216 case RT5592: 10217 break; 10218 default: 10219 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", 10220 rt, rev); 10221 return -ENODEV; 10222 } 10223 10224 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) 10225 rt = RT6352; 10226 10227 rt2x00_set_rt(rt2x00dev, rt, rev); 10228 10229 return 0; 10230 } 10231 10232 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 10233 { 10234 int retval; 10235 u32 reg; 10236 10237 retval = rt2800_probe_rt(rt2x00dev); 10238 if (retval) 10239 return retval; 10240 10241 /* 10242 * Allocate eeprom data. 10243 */ 10244 retval = rt2800_validate_eeprom(rt2x00dev); 10245 if (retval) 10246 return retval; 10247 10248 retval = rt2800_init_eeprom(rt2x00dev); 10249 if (retval) 10250 return retval; 10251 10252 /* 10253 * Enable rfkill polling by setting GPIO direction of the 10254 * rfkill switch GPIO pin correctly. 10255 */ 10256 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); 10257 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); 10258 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); 10259 10260 /* 10261 * Initialize hw specifications. 10262 */ 10263 retval = rt2800_probe_hw_mode(rt2x00dev); 10264 if (retval) 10265 return retval; 10266 10267 /* 10268 * Set device capabilities. 10269 */ 10270 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); 10271 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags); 10272 if (!rt2x00_is_usb(rt2x00dev)) 10273 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags); 10274 10275 /* 10276 * Set device requirements. 10277 */ 10278 if (!rt2x00_is_soc(rt2x00dev)) 10279 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); 10280 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags); 10281 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags); 10282 if (!rt2800_hwcrypt_disabled(rt2x00dev)) 10283 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); 10284 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); 10285 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags); 10286 if (rt2x00_is_usb(rt2x00dev)) 10287 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags); 10288 else { 10289 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); 10290 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags); 10291 } 10292 10293 if (modparam_watchdog) { 10294 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags); 10295 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100); 10296 } else { 10297 rt2x00dev->link.watchdog_disabled = true; 10298 } 10299 10300 /* 10301 * Set the rssi offset. 10302 */ 10303 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; 10304 10305 return 0; 10306 } 10307 EXPORT_SYMBOL_GPL(rt2800_probe_hw); 10308 10309 /* 10310 * IEEE80211 stack callback functions. 10311 */ 10312 void rt2800_get_key_seq(struct ieee80211_hw *hw, 10313 struct ieee80211_key_conf *key, 10314 struct ieee80211_key_seq *seq) 10315 { 10316 struct rt2x00_dev *rt2x00dev = hw->priv; 10317 struct mac_iveiv_entry iveiv_entry; 10318 u32 offset; 10319 10320 if (key->cipher != WLAN_CIPHER_SUITE_TKIP) 10321 return; 10322 10323 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 10324 rt2800_register_multiread(rt2x00dev, offset, 10325 &iveiv_entry, sizeof(iveiv_entry)); 10326 10327 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2); 10328 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4); 10329 } 10330 EXPORT_SYMBOL_GPL(rt2800_get_key_seq); 10331 10332 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) 10333 { 10334 struct rt2x00_dev *rt2x00dev = hw->priv; 10335 u32 reg; 10336 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 10337 10338 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); 10339 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); 10340 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 10341 10342 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); 10343 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); 10344 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 10345 10346 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); 10347 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); 10348 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 10349 10350 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); 10351 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); 10352 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 10353 10354 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); 10355 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); 10356 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 10357 10358 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); 10359 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); 10360 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 10361 10362 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); 10363 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); 10364 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 10365 10366 return 0; 10367 } 10368 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold); 10369 10370 int rt2800_conf_tx(struct ieee80211_hw *hw, 10371 struct ieee80211_vif *vif, u16 queue_idx, 10372 const struct ieee80211_tx_queue_params *params) 10373 { 10374 struct rt2x00_dev *rt2x00dev = hw->priv; 10375 struct data_queue *queue; 10376 struct rt2x00_field32 field; 10377 int retval; 10378 u32 reg; 10379 u32 offset; 10380 10381 /* 10382 * First pass the configuration through rt2x00lib, that will 10383 * update the queue settings and validate the input. After that 10384 * we are free to update the registers based on the value 10385 * in the queue parameter. 10386 */ 10387 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params); 10388 if (retval) 10389 return retval; 10390 10391 /* 10392 * We only need to perform additional register initialization 10393 * for WMM queues/ 10394 */ 10395 if (queue_idx >= 4) 10396 return 0; 10397 10398 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); 10399 10400 /* Update WMM TXOP register */ 10401 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 10402 field.bit_offset = (queue_idx & 1) * 16; 10403 field.bit_mask = 0xffff << field.bit_offset; 10404 10405 reg = rt2800_register_read(rt2x00dev, offset); 10406 rt2x00_set_field32(®, field, queue->txop); 10407 rt2800_register_write(rt2x00dev, offset, reg); 10408 10409 /* Update WMM registers */ 10410 field.bit_offset = queue_idx * 4; 10411 field.bit_mask = 0xf << field.bit_offset; 10412 10413 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); 10414 rt2x00_set_field32(®, field, queue->aifs); 10415 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 10416 10417 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); 10418 rt2x00_set_field32(®, field, queue->cw_min); 10419 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 10420 10421 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); 10422 rt2x00_set_field32(®, field, queue->cw_max); 10423 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 10424 10425 /* Update EDCA registers */ 10426 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 10427 10428 reg = rt2800_register_read(rt2x00dev, offset); 10429 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); 10430 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); 10431 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); 10432 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); 10433 rt2800_register_write(rt2x00dev, offset, reg); 10434 10435 return 0; 10436 } 10437 EXPORT_SYMBOL_GPL(rt2800_conf_tx); 10438 10439 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 10440 { 10441 struct rt2x00_dev *rt2x00dev = hw->priv; 10442 u64 tsf; 10443 u32 reg; 10444 10445 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); 10446 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 10447 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); 10448 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 10449 10450 return tsf; 10451 } 10452 EXPORT_SYMBOL_GPL(rt2800_get_tsf); 10453 10454 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 10455 struct ieee80211_ampdu_params *params) 10456 { 10457 struct ieee80211_sta *sta = params->sta; 10458 enum ieee80211_ampdu_mlme_action action = params->action; 10459 u16 tid = params->tid; 10460 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv; 10461 int ret = 0; 10462 10463 /* 10464 * Don't allow aggregation for stations the hardware isn't aware 10465 * of because tx status reports for frames to an unknown station 10466 * always contain wcid=WCID_END+1 and thus we can't distinguish 10467 * between multiple stations which leads to unwanted situations 10468 * when the hw reorders frames due to aggregation. 10469 */ 10470 if (sta_priv->wcid > WCID_END) 10471 return -ENOSPC; 10472 10473 switch (action) { 10474 case IEEE80211_AMPDU_RX_START: 10475 case IEEE80211_AMPDU_RX_STOP: 10476 /* 10477 * The hw itself takes care of setting up BlockAck mechanisms. 10478 * So, we only have to allow mac80211 to nagotiate a BlockAck 10479 * agreement. Once that is done, the hw will BlockAck incoming 10480 * AMPDUs without further setup. 10481 */ 10482 break; 10483 case IEEE80211_AMPDU_TX_START: 10484 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 10485 break; 10486 case IEEE80211_AMPDU_TX_STOP_CONT: 10487 case IEEE80211_AMPDU_TX_STOP_FLUSH: 10488 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 10489 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 10490 break; 10491 case IEEE80211_AMPDU_TX_OPERATIONAL: 10492 break; 10493 default: 10494 rt2x00_warn((struct rt2x00_dev *)hw->priv, 10495 "Unknown AMPDU action\n"); 10496 } 10497 10498 return ret; 10499 } 10500 EXPORT_SYMBOL_GPL(rt2800_ampdu_action); 10501 10502 int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 10503 struct survey_info *survey) 10504 { 10505 struct rt2x00_dev *rt2x00dev = hw->priv; 10506 struct ieee80211_conf *conf = &hw->conf; 10507 u32 idle, busy, busy_ext; 10508 10509 if (idx != 0) 10510 return -ENOENT; 10511 10512 survey->channel = conf->chandef.chan; 10513 10514 idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); 10515 busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); 10516 busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); 10517 10518 if (idle || busy) { 10519 survey->filled = SURVEY_INFO_TIME | 10520 SURVEY_INFO_TIME_BUSY | 10521 SURVEY_INFO_TIME_EXT_BUSY; 10522 10523 survey->time = (idle + busy) / 1000; 10524 survey->time_busy = busy / 1000; 10525 survey->time_ext_busy = busy_ext / 1000; 10526 } 10527 10528 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) 10529 survey->filled |= SURVEY_INFO_IN_USE; 10530 10531 return 0; 10532 10533 } 10534 EXPORT_SYMBOL_GPL(rt2800_get_survey); 10535 10536 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz"); 10537 MODULE_VERSION(DRV_VERSION); 10538 MODULE_DESCRIPTION("Ralink RT2800 library"); 10539 MODULE_LICENSE("GPL"); 10540