1 #include <linux/kernel.h> 2 #include <linux/module.h> 3 4 #include "mt7615.h" 5 #include "regs.h" 6 #include "mac.h" 7 #include "../trace.h" 8 9 const u32 mt7615e_reg_map[] = { 10 [MT_TOP_CFG_BASE] = 0x01000, 11 [MT_HW_BASE] = 0x01000, 12 [MT_PCIE_REMAP_2] = 0x02504, 13 [MT_ARB_BASE] = 0x20c00, 14 [MT_HIF_BASE] = 0x04000, 15 [MT_CSR_BASE] = 0x07000, 16 [MT_PHY_BASE] = 0x10000, 17 [MT_CFG_BASE] = 0x20200, 18 [MT_AGG_BASE] = 0x20a00, 19 [MT_TMAC_BASE] = 0x21000, 20 [MT_RMAC_BASE] = 0x21200, 21 [MT_DMA_BASE] = 0x21800, 22 [MT_WTBL_BASE_ON] = 0x23000, 23 [MT_WTBL_BASE_OFF] = 0x23400, 24 [MT_LPON_BASE] = 0x24200, 25 [MT_MIB_BASE] = 0x24800, 26 [MT_WTBL_BASE_ADDR] = 0x30000, 27 [MT_PCIE_REMAP_BASE2] = 0x80000, 28 [MT_TOP_MISC_BASE] = 0xc0000, 29 [MT_EFUSE_ADDR_BASE] = 0x81070000, 30 }; 31 32 const u32 mt7663e_reg_map[] = { 33 [MT_TOP_CFG_BASE] = 0x01000, 34 [MT_HW_BASE] = 0x02000, 35 [MT_DMA_SHDL_BASE] = 0x06000, 36 [MT_PCIE_REMAP_2] = 0x0700c, 37 [MT_ARB_BASE] = 0x20c00, 38 [MT_HIF_BASE] = 0x04000, 39 [MT_CSR_BASE] = 0x07000, 40 [MT_PHY_BASE] = 0x10000, 41 [MT_CFG_BASE] = 0x20000, 42 [MT_AGG_BASE] = 0x22000, 43 [MT_TMAC_BASE] = 0x24000, 44 [MT_RMAC_BASE] = 0x25000, 45 [MT_DMA_BASE] = 0x27000, 46 [MT_WTBL_BASE_ON] = 0x29000, 47 [MT_WTBL_BASE_OFF] = 0x29800, 48 [MT_LPON_BASE] = 0x2b000, 49 [MT_MIB_BASE] = 0x2d000, 50 [MT_WTBL_BASE_ADDR] = 0x30000, 51 [MT_PCIE_REMAP_BASE2] = 0x90000, 52 [MT_TOP_MISC_BASE] = 0xc0000, 53 [MT_EFUSE_ADDR_BASE] = 0x78011000, 54 }; 55 56 u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr) 57 { 58 u32 base, offset; 59 60 if (is_mt7663(&dev->mt76)) { 61 base = addr & MT7663_MCU_PCIE_REMAP_2_BASE; 62 offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET; 63 } else { 64 base = addr & MT_MCU_PCIE_REMAP_2_BASE; 65 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET; 66 } 67 mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base); 68 69 return MT_PCIE_REMAP_BASE_2 + offset; 70 } 71 72 static void 73 mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 74 { 75 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 76 77 mt7615_irq_enable(dev, MT_INT_RX_DONE(q)); 78 } 79 80 static irqreturn_t mt7615_irq_handler(int irq, void *dev_instance) 81 { 82 struct mt7615_dev *dev = dev_instance; 83 u32 intr; 84 85 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 86 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 87 88 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 89 return IRQ_NONE; 90 91 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 92 93 intr &= dev->mt76.mmio.irqmask; 94 95 if (intr & MT_INT_TX_DONE_ALL) { 96 mt7615_irq_disable(dev, MT_INT_TX_DONE_ALL); 97 napi_schedule(&dev->mt76.tx_napi); 98 } 99 100 if (intr & MT_INT_RX_DONE(0)) { 101 mt7615_irq_disable(dev, MT_INT_RX_DONE(0)); 102 napi_schedule(&dev->mt76.napi[0]); 103 } 104 105 if (intr & MT_INT_RX_DONE(1)) { 106 mt7615_irq_disable(dev, MT_INT_RX_DONE(1)); 107 napi_schedule(&dev->mt76.napi[1]); 108 } 109 110 if (intr & MT_INT_MCU_CMD) { 111 u32 val = mt76_rr(dev, MT_MCU_CMD); 112 113 if (val & MT_MCU_CMD_ERROR_MASK) { 114 dev->reset_state = val; 115 ieee80211_queue_work(mt76_hw(dev), &dev->reset_work); 116 wake_up(&dev->reset_wait); 117 } 118 } 119 120 return IRQ_HANDLED; 121 } 122 123 int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base, 124 int irq, const u32 *map) 125 { 126 static const struct mt76_driver_ops drv_ops = { 127 /* txwi_size = txd size + txp size */ 128 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common), 129 .drv_flags = MT_DRV_TXWI_NO_FREE, 130 .survey_flags = SURVEY_INFO_TIME_TX | 131 SURVEY_INFO_TIME_RX | 132 SURVEY_INFO_TIME_BSS_RX, 133 .tx_prepare_skb = mt7615_tx_prepare_skb, 134 .tx_complete_skb = mt7615_tx_complete_skb, 135 .rx_skb = mt7615_queue_rx_skb, 136 .rx_poll_complete = mt7615_rx_poll_complete, 137 .sta_ps = mt7615_sta_ps, 138 .sta_add = mt7615_mac_sta_add, 139 .sta_remove = mt7615_mac_sta_remove, 140 .update_survey = mt7615_update_channel, 141 }; 142 struct mt7615_dev *dev; 143 struct mt76_dev *mdev; 144 int ret; 145 146 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7615_ops, &drv_ops); 147 if (!mdev) 148 return -ENOMEM; 149 150 dev = container_of(mdev, struct mt7615_dev, mt76); 151 mt76_mmio_init(&dev->mt76, mem_base); 152 153 dev->reg_map = map; 154 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | 155 (mt76_rr(dev, MT_HW_REV) & 0xff); 156 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 157 158 ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler, 159 IRQF_SHARED, KBUILD_MODNAME, dev); 160 if (ret) 161 goto error; 162 163 if (is_mt7663(mdev)) 164 mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1); 165 166 ret = mt7615_register_device(dev); 167 if (ret) 168 goto error; 169 170 return 0; 171 error: 172 ieee80211_free_hw(mt76_hw(dev)); 173 return ret; 174 } 175