1 /* 2 * NXP Wireless LAN device driver: SDIO specific definitions 3 * 4 * Copyright 2011-2020 NXP 5 * 6 * This software file (the "File") is distributed by NXP 7 * under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20 #ifndef _MWIFIEX_SDIO_H 21 #define _MWIFIEX_SDIO_H 22 23 24 #include <linux/completion.h> 25 #include <linux/mmc/sdio.h> 26 #include <linux/mmc/sdio_ids.h> 27 #include <linux/mmc/sdio_func.h> 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/host.h> 30 31 #include "main.h" 32 33 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" 34 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" 35 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" 36 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" 37 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin" 38 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin" 39 #define SD8977_DEFAULT_FW_NAME "mrvl/sd8977_uapsta.bin" 40 #define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin" 41 #define SD8997_DEFAULT_FW_NAME "mrvl/sd8997_uapsta.bin" 42 43 #define BLOCK_MODE 1 44 #define BYTE_MODE 0 45 46 #define REG_PORT 0 47 48 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff 49 50 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 51 52 #define MWIFIEX_MAX_FUNC2_REG_NUM 13 53 #define MWIFIEX_SDIO_SCRATCH_SIZE 10 54 55 #define SDIO_MPA_ADDR_BASE 0x1000 56 #define CTRL_PORT 0 57 #define CTRL_PORT_MASK 0x0001 58 59 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6) 60 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7) 61 #define HOST_TERM_CMD53 (0x1U << 2) 62 #define REG_PORT 0 63 #define MEM_PORT 0x10000 64 65 #define CMD53_NEW_MODE (0x1U << 0) 66 #define CMD_PORT_RD_LEN_EN (0x1U << 2) 67 #define CMD_PORT_AUTO_EN (0x1U << 0) 68 #define CMD_PORT_SLCT 0x8000 69 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 70 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 71 72 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384) 73 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768) 74 /* we leave one block of 256 bytes for DMA alignment*/ 75 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280) 76 77 /* Misc. Config Register : Auto Re-enable interrupts */ 78 #define AUTO_RE_ENABLE_INT BIT(4) 79 80 /* Host Control Registers : Configuration */ 81 #define CONFIGURATION_REG 0x00 82 /* Host Control Registers : Host power up */ 83 #define HOST_POWER_UP (0x1U << 1) 84 85 /* Host Control Registers : Upload host interrupt mask */ 86 #define UP_LD_HOST_INT_MASK (0x1U) 87 /* Host Control Registers : Download host interrupt mask */ 88 #define DN_LD_HOST_INT_MASK (0x2U) 89 90 /* Host Control Registers : Upload host interrupt status */ 91 #define UP_LD_HOST_INT_STATUS (0x1U) 92 /* Host Control Registers : Download host interrupt status */ 93 #define DN_LD_HOST_INT_STATUS (0x2U) 94 95 /* Host Control Registers : Host interrupt status */ 96 #define CARD_INT_STATUS_REG 0x28 97 98 /* Card Control Registers : Card I/O ready */ 99 #define CARD_IO_READY (0x1U << 3) 100 /* Card Control Registers : Download card ready */ 101 #define DN_LD_CARD_RDY (0x1U << 0) 102 103 /* Max retry number of CMD53 write */ 104 #define MAX_WRITE_IOMEM_RETRY 2 105 106 /* SDIO Tx aggregation in progress ? */ 107 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 108 109 /* SDIO Tx aggregation buffer room for next packet ? */ 110 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ 111 <= a->mpa_tx.buf_size) 112 113 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 114 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ 115 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ 116 payload, pkt_len); \ 117 a->mpa_tx.buf_len += pkt_len; \ 118 if (!a->mpa_tx.pkt_cnt) \ 119 a->mpa_tx.start_port = port; \ 120 if (a->mpa_tx.start_port <= port) \ 121 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ 122 else \ 123 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ 124 (a->max_ports - \ 125 a->mp_end_port))); \ 126 a->mpa_tx.pkt_cnt++; \ 127 } while (0) 128 129 /* SDIO Tx aggregation limit ? */ 130 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 131 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) 132 133 /* Reset SDIO Tx aggregation buffer parameters */ 134 #define MP_TX_AGGR_BUF_RESET(a) do { \ 135 a->mpa_tx.pkt_cnt = 0; \ 136 a->mpa_tx.buf_len = 0; \ 137 a->mpa_tx.ports = 0; \ 138 a->mpa_tx.start_port = 0; \ 139 } while (0) 140 141 /* SDIO Rx aggregation limit ? */ 142 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 143 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) 144 145 /* SDIO Rx aggregation in progress ? */ 146 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 147 148 /* SDIO Rx aggregation buffer room for next packet ? */ 149 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 150 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) 151 152 /* Reset SDIO Rx aggregation buffer parameters */ 153 #define MP_RX_AGGR_BUF_RESET(a) do { \ 154 a->mpa_rx.pkt_cnt = 0; \ 155 a->mpa_rx.buf_len = 0; \ 156 a->mpa_rx.ports = 0; \ 157 a->mpa_rx.start_port = 0; \ 158 } while (0) 159 160 /* data structure for SDIO MPA TX */ 161 struct mwifiex_sdio_mpa_tx { 162 /* multiport tx aggregation buffer pointer */ 163 u8 *buf; 164 u32 buf_len; 165 u32 pkt_cnt; 166 u32 ports; 167 u16 start_port; 168 u8 enabled; 169 u32 buf_size; 170 u32 pkt_aggr_limit; 171 }; 172 173 struct mwifiex_sdio_mpa_rx { 174 u8 *buf; 175 u32 buf_len; 176 u32 pkt_cnt; 177 u32 ports; 178 u16 start_port; 179 180 struct sk_buff **skb_arr; 181 u32 *len_arr; 182 183 u8 enabled; 184 u32 buf_size; 185 u32 pkt_aggr_limit; 186 }; 187 188 int mwifiex_bus_register(void); 189 void mwifiex_bus_unregister(void); 190 191 struct mwifiex_sdio_card_reg { 192 u8 start_rd_port; 193 u8 start_wr_port; 194 u8 base_0_reg; 195 u8 base_1_reg; 196 u8 poll_reg; 197 u8 host_int_enable; 198 u8 host_int_rsr_reg; 199 u8 host_int_status_reg; 200 u8 host_int_mask_reg; 201 u8 status_reg_0; 202 u8 status_reg_1; 203 u8 sdio_int_mask; 204 u32 data_port_mask; 205 u8 io_port_0_reg; 206 u8 io_port_1_reg; 207 u8 io_port_2_reg; 208 u8 max_mp_regs; 209 u8 rd_bitmap_l; 210 u8 rd_bitmap_u; 211 u8 rd_bitmap_1l; 212 u8 rd_bitmap_1u; 213 u8 wr_bitmap_l; 214 u8 wr_bitmap_u; 215 u8 wr_bitmap_1l; 216 u8 wr_bitmap_1u; 217 u8 rd_len_p0_l; 218 u8 rd_len_p0_u; 219 u8 card_misc_cfg_reg; 220 u8 card_cfg_2_1_reg; 221 u8 cmd_rd_len_0; 222 u8 cmd_rd_len_1; 223 u8 cmd_rd_len_2; 224 u8 cmd_rd_len_3; 225 u8 cmd_cfg_0; 226 u8 cmd_cfg_1; 227 u8 cmd_cfg_2; 228 u8 cmd_cfg_3; 229 u8 fw_dump_host_ready; 230 u8 fw_dump_ctrl; 231 u8 fw_dump_start; 232 u8 fw_dump_end; 233 u8 func1_dump_reg_start; 234 u8 func1_dump_reg_end; 235 u8 func1_scratch_reg; 236 u8 func1_spec_reg_num; 237 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM]; 238 }; 239 240 struct sdio_mmc_card { 241 struct sdio_func *func; 242 struct mwifiex_adapter *adapter; 243 244 struct completion fw_done; 245 const char *firmware; 246 const struct mwifiex_sdio_card_reg *reg; 247 u8 max_ports; 248 u8 mp_agg_pkt_limit; 249 u16 tx_buf_size; 250 u32 mp_tx_agg_buf_size; 251 u32 mp_rx_agg_buf_size; 252 253 u32 mp_rd_bitmap; 254 u32 mp_wr_bitmap; 255 256 u16 mp_end_port; 257 u32 mp_data_port_mask; 258 259 u8 curr_rd_port; 260 u8 curr_wr_port; 261 262 u8 *mp_regs; 263 bool supports_sdio_new_mode; 264 bool has_control_mask; 265 bool can_dump_fw; 266 bool fw_dump_enh; 267 bool can_auto_tdls; 268 bool can_ext_scan; 269 270 struct mwifiex_sdio_mpa_tx mpa_tx; 271 struct mwifiex_sdio_mpa_rx mpa_rx; 272 273 struct work_struct work; 274 unsigned long work_flags; 275 }; 276 277 struct mwifiex_sdio_device { 278 const char *firmware; 279 const struct mwifiex_sdio_card_reg *reg; 280 u8 max_ports; 281 u8 mp_agg_pkt_limit; 282 u16 tx_buf_size; 283 u32 mp_tx_agg_buf_size; 284 u32 mp_rx_agg_buf_size; 285 bool supports_sdio_new_mode; 286 bool has_control_mask; 287 bool can_dump_fw; 288 bool fw_dump_enh; 289 bool can_auto_tdls; 290 bool can_ext_scan; 291 }; 292 293 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = { 294 .start_rd_port = 1, 295 .start_wr_port = 1, 296 .base_0_reg = 0x0040, 297 .base_1_reg = 0x0041, 298 .poll_reg = 0x30, 299 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK, 300 .host_int_rsr_reg = 0x1, 301 .host_int_mask_reg = 0x02, 302 .host_int_status_reg = 0x03, 303 .status_reg_0 = 0x60, 304 .status_reg_1 = 0x61, 305 .sdio_int_mask = 0x3f, 306 .data_port_mask = 0x0000fffe, 307 .io_port_0_reg = 0x78, 308 .io_port_1_reg = 0x79, 309 .io_port_2_reg = 0x7A, 310 .max_mp_regs = 64, 311 .rd_bitmap_l = 0x04, 312 .rd_bitmap_u = 0x05, 313 .wr_bitmap_l = 0x06, 314 .wr_bitmap_u = 0x07, 315 .rd_len_p0_l = 0x08, 316 .rd_len_p0_u = 0x09, 317 .card_misc_cfg_reg = 0x6c, 318 .func1_dump_reg_start = 0x0, 319 .func1_dump_reg_end = 0x9, 320 .func1_scratch_reg = 0x60, 321 .func1_spec_reg_num = 5, 322 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c}, 323 }; 324 325 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = { 326 .start_rd_port = 0, 327 .start_wr_port = 0, 328 .base_0_reg = 0x60, 329 .base_1_reg = 0x61, 330 .poll_reg = 0x50, 331 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 332 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 333 .host_int_rsr_reg = 0x1, 334 .host_int_status_reg = 0x03, 335 .host_int_mask_reg = 0x02, 336 .status_reg_0 = 0xc0, 337 .status_reg_1 = 0xc1, 338 .sdio_int_mask = 0xff, 339 .data_port_mask = 0xffffffff, 340 .io_port_0_reg = 0xD8, 341 .io_port_1_reg = 0xD9, 342 .io_port_2_reg = 0xDA, 343 .max_mp_regs = 184, 344 .rd_bitmap_l = 0x04, 345 .rd_bitmap_u = 0x05, 346 .rd_bitmap_1l = 0x06, 347 .rd_bitmap_1u = 0x07, 348 .wr_bitmap_l = 0x08, 349 .wr_bitmap_u = 0x09, 350 .wr_bitmap_1l = 0x0a, 351 .wr_bitmap_1u = 0x0b, 352 .rd_len_p0_l = 0x0c, 353 .rd_len_p0_u = 0x0d, 354 .card_misc_cfg_reg = 0xcc, 355 .card_cfg_2_1_reg = 0xcd, 356 .cmd_rd_len_0 = 0xb4, 357 .cmd_rd_len_1 = 0xb5, 358 .cmd_rd_len_2 = 0xb6, 359 .cmd_rd_len_3 = 0xb7, 360 .cmd_cfg_0 = 0xb8, 361 .cmd_cfg_1 = 0xb9, 362 .cmd_cfg_2 = 0xba, 363 .cmd_cfg_3 = 0xbb, 364 .fw_dump_host_ready = 0xee, 365 .fw_dump_ctrl = 0xe2, 366 .fw_dump_start = 0xe3, 367 .fw_dump_end = 0xea, 368 .func1_dump_reg_start = 0x0, 369 .func1_dump_reg_end = 0xb, 370 .func1_scratch_reg = 0xc0, 371 .func1_spec_reg_num = 8, 372 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58, 373 0x59, 0x5c, 0x5d}, 374 }; 375 376 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8977 = { 377 .start_rd_port = 0, 378 .start_wr_port = 0, 379 .base_0_reg = 0xF8, 380 .base_1_reg = 0xF9, 381 .poll_reg = 0x5C, 382 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 383 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 384 .host_int_rsr_reg = 0x4, 385 .host_int_status_reg = 0x0C, 386 .host_int_mask_reg = 0x08, 387 .status_reg_0 = 0xE8, 388 .status_reg_1 = 0xE9, 389 .sdio_int_mask = 0xff, 390 .data_port_mask = 0xffffffff, 391 .io_port_0_reg = 0xE4, 392 .io_port_1_reg = 0xE5, 393 .io_port_2_reg = 0xE6, 394 .max_mp_regs = 196, 395 .rd_bitmap_l = 0x10, 396 .rd_bitmap_u = 0x11, 397 .rd_bitmap_1l = 0x12, 398 .rd_bitmap_1u = 0x13, 399 .wr_bitmap_l = 0x14, 400 .wr_bitmap_u = 0x15, 401 .wr_bitmap_1l = 0x16, 402 .wr_bitmap_1u = 0x17, 403 .rd_len_p0_l = 0x18, 404 .rd_len_p0_u = 0x19, 405 .card_misc_cfg_reg = 0xd8, 406 .card_cfg_2_1_reg = 0xd9, 407 .cmd_rd_len_0 = 0xc0, 408 .cmd_rd_len_1 = 0xc1, 409 .cmd_rd_len_2 = 0xc2, 410 .cmd_rd_len_3 = 0xc3, 411 .cmd_cfg_0 = 0xc4, 412 .cmd_cfg_1 = 0xc5, 413 .cmd_cfg_2 = 0xc6, 414 .cmd_cfg_3 = 0xc7, 415 .fw_dump_host_ready = 0xcc, 416 .fw_dump_ctrl = 0xf0, 417 .fw_dump_start = 0xf1, 418 .fw_dump_end = 0xf8, 419 .func1_dump_reg_start = 0x10, 420 .func1_dump_reg_end = 0x17, 421 .func1_scratch_reg = 0xe8, 422 .func1_spec_reg_num = 13, 423 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 424 0x60, 0x61, 0x62, 0x64, 425 0x65, 0x66, 0x68, 0x69, 426 0x6a}, 427 }; 428 429 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = { 430 .start_rd_port = 0, 431 .start_wr_port = 0, 432 .base_0_reg = 0xF8, 433 .base_1_reg = 0xF9, 434 .poll_reg = 0x5C, 435 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 436 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 437 .host_int_rsr_reg = 0x4, 438 .host_int_status_reg = 0x0C, 439 .host_int_mask_reg = 0x08, 440 .status_reg_0 = 0xE8, 441 .status_reg_1 = 0xE9, 442 .sdio_int_mask = 0xff, 443 .data_port_mask = 0xffffffff, 444 .io_port_0_reg = 0xE4, 445 .io_port_1_reg = 0xE5, 446 .io_port_2_reg = 0xE6, 447 .max_mp_regs = 196, 448 .rd_bitmap_l = 0x10, 449 .rd_bitmap_u = 0x11, 450 .rd_bitmap_1l = 0x12, 451 .rd_bitmap_1u = 0x13, 452 .wr_bitmap_l = 0x14, 453 .wr_bitmap_u = 0x15, 454 .wr_bitmap_1l = 0x16, 455 .wr_bitmap_1u = 0x17, 456 .rd_len_p0_l = 0x18, 457 .rd_len_p0_u = 0x19, 458 .card_misc_cfg_reg = 0xd8, 459 .card_cfg_2_1_reg = 0xd9, 460 .cmd_rd_len_0 = 0xc0, 461 .cmd_rd_len_1 = 0xc1, 462 .cmd_rd_len_2 = 0xc2, 463 .cmd_rd_len_3 = 0xc3, 464 .cmd_cfg_0 = 0xc4, 465 .cmd_cfg_1 = 0xc5, 466 .cmd_cfg_2 = 0xc6, 467 .cmd_cfg_3 = 0xc7, 468 .fw_dump_host_ready = 0xcc, 469 .fw_dump_ctrl = 0xf0, 470 .fw_dump_start = 0xf1, 471 .fw_dump_end = 0xf8, 472 .func1_dump_reg_start = 0x10, 473 .func1_dump_reg_end = 0x17, 474 .func1_scratch_reg = 0xe8, 475 .func1_spec_reg_num = 13, 476 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 477 0x60, 0x61, 0x62, 0x64, 478 0x65, 0x66, 0x68, 0x69, 479 0x6a}, 480 }; 481 482 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = { 483 .start_rd_port = 0, 484 .start_wr_port = 0, 485 .base_0_reg = 0x6C, 486 .base_1_reg = 0x6D, 487 .poll_reg = 0x5C, 488 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 489 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 490 .host_int_rsr_reg = 0x4, 491 .host_int_status_reg = 0x0C, 492 .host_int_mask_reg = 0x08, 493 .status_reg_0 = 0x90, 494 .status_reg_1 = 0x91, 495 .sdio_int_mask = 0xff, 496 .data_port_mask = 0xffffffff, 497 .io_port_0_reg = 0xE4, 498 .io_port_1_reg = 0xE5, 499 .io_port_2_reg = 0xE6, 500 .max_mp_regs = 196, 501 .rd_bitmap_l = 0x10, 502 .rd_bitmap_u = 0x11, 503 .rd_bitmap_1l = 0x12, 504 .rd_bitmap_1u = 0x13, 505 .wr_bitmap_l = 0x14, 506 .wr_bitmap_u = 0x15, 507 .wr_bitmap_1l = 0x16, 508 .wr_bitmap_1u = 0x17, 509 .rd_len_p0_l = 0x18, 510 .rd_len_p0_u = 0x19, 511 .card_misc_cfg_reg = 0xd8, 512 .card_cfg_2_1_reg = 0xd9, 513 .cmd_rd_len_0 = 0xc0, 514 .cmd_rd_len_1 = 0xc1, 515 .cmd_rd_len_2 = 0xc2, 516 .cmd_rd_len_3 = 0xc3, 517 .cmd_cfg_0 = 0xc4, 518 .cmd_cfg_1 = 0xc5, 519 .cmd_cfg_2 = 0xc6, 520 .cmd_cfg_3 = 0xc7, 521 .func1_dump_reg_start = 0x10, 522 .func1_dump_reg_end = 0x17, 523 .func1_scratch_reg = 0x90, 524 .func1_spec_reg_num = 13, 525 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60, 526 0x61, 0x62, 0x64, 0x65, 0x66, 527 0x68, 0x69, 0x6a}, 528 }; 529 530 static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8987 = { 531 .start_rd_port = 0, 532 .start_wr_port = 0, 533 .base_0_reg = 0xF8, 534 .base_1_reg = 0xF9, 535 .poll_reg = 0x5C, 536 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 537 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 538 .host_int_rsr_reg = 0x4, 539 .host_int_status_reg = 0x0C, 540 .host_int_mask_reg = 0x08, 541 .status_reg_0 = 0xE8, 542 .status_reg_1 = 0xE9, 543 .sdio_int_mask = 0xff, 544 .data_port_mask = 0xffffffff, 545 .io_port_0_reg = 0xE4, 546 .io_port_1_reg = 0xE5, 547 .io_port_2_reg = 0xE6, 548 .max_mp_regs = 196, 549 .rd_bitmap_l = 0x10, 550 .rd_bitmap_u = 0x11, 551 .rd_bitmap_1l = 0x12, 552 .rd_bitmap_1u = 0x13, 553 .wr_bitmap_l = 0x14, 554 .wr_bitmap_u = 0x15, 555 .wr_bitmap_1l = 0x16, 556 .wr_bitmap_1u = 0x17, 557 .rd_len_p0_l = 0x18, 558 .rd_len_p0_u = 0x19, 559 .card_misc_cfg_reg = 0xd8, 560 .card_cfg_2_1_reg = 0xd9, 561 .cmd_rd_len_0 = 0xc0, 562 .cmd_rd_len_1 = 0xc1, 563 .cmd_rd_len_2 = 0xc2, 564 .cmd_rd_len_3 = 0xc3, 565 .cmd_cfg_0 = 0xc4, 566 .cmd_cfg_1 = 0xc5, 567 .cmd_cfg_2 = 0xc6, 568 .cmd_cfg_3 = 0xc7, 569 .fw_dump_host_ready = 0xcc, 570 .fw_dump_ctrl = 0xf9, 571 .fw_dump_start = 0xf1, 572 .fw_dump_end = 0xf8, 573 .func1_dump_reg_start = 0x10, 574 .func1_dump_reg_end = 0x17, 575 .func1_scratch_reg = 0xE8, 576 .func1_spec_reg_num = 13, 577 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60, 578 0x61, 0x62, 0x64, 0x65, 0x66, 579 0x68, 0x69, 0x6a}, 580 }; 581 582 static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = { 583 .firmware = SD8786_DEFAULT_FW_NAME, 584 .reg = &mwifiex_reg_sd87xx, 585 .max_ports = 16, 586 .mp_agg_pkt_limit = 8, 587 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 588 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 589 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 590 .supports_sdio_new_mode = false, 591 .has_control_mask = true, 592 .can_dump_fw = false, 593 .can_auto_tdls = false, 594 .can_ext_scan = false, 595 }; 596 597 static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = { 598 .firmware = SD8787_DEFAULT_FW_NAME, 599 .reg = &mwifiex_reg_sd87xx, 600 .max_ports = 16, 601 .mp_agg_pkt_limit = 8, 602 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 603 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 604 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 605 .supports_sdio_new_mode = false, 606 .has_control_mask = true, 607 .can_dump_fw = false, 608 .can_auto_tdls = false, 609 .can_ext_scan = true, 610 }; 611 612 static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = { 613 .firmware = SD8797_DEFAULT_FW_NAME, 614 .reg = &mwifiex_reg_sd87xx, 615 .max_ports = 16, 616 .mp_agg_pkt_limit = 8, 617 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 618 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 619 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 620 .supports_sdio_new_mode = false, 621 .has_control_mask = true, 622 .can_dump_fw = false, 623 .can_auto_tdls = false, 624 .can_ext_scan = true, 625 }; 626 627 static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = { 628 .firmware = SD8897_DEFAULT_FW_NAME, 629 .reg = &mwifiex_reg_sd8897, 630 .max_ports = 32, 631 .mp_agg_pkt_limit = 16, 632 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 633 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 634 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 635 .supports_sdio_new_mode = true, 636 .has_control_mask = false, 637 .can_dump_fw = true, 638 .can_auto_tdls = false, 639 .can_ext_scan = true, 640 }; 641 642 static const struct mwifiex_sdio_device mwifiex_sdio_sd8977 = { 643 .firmware = SD8977_DEFAULT_FW_NAME, 644 .reg = &mwifiex_reg_sd8977, 645 .max_ports = 32, 646 .mp_agg_pkt_limit = 16, 647 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 648 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 649 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 650 .supports_sdio_new_mode = true, 651 .has_control_mask = false, 652 .can_dump_fw = true, 653 .fw_dump_enh = true, 654 .can_auto_tdls = false, 655 .can_ext_scan = true, 656 }; 657 658 static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = { 659 .firmware = SD8997_DEFAULT_FW_NAME, 660 .reg = &mwifiex_reg_sd8997, 661 .max_ports = 32, 662 .mp_agg_pkt_limit = 16, 663 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 664 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 665 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 666 .supports_sdio_new_mode = true, 667 .has_control_mask = false, 668 .can_dump_fw = true, 669 .fw_dump_enh = true, 670 .can_auto_tdls = false, 671 .can_ext_scan = true, 672 }; 673 674 static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = { 675 .firmware = SD8887_DEFAULT_FW_NAME, 676 .reg = &mwifiex_reg_sd8887, 677 .max_ports = 32, 678 .mp_agg_pkt_limit = 16, 679 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 680 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 681 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 682 .supports_sdio_new_mode = true, 683 .has_control_mask = false, 684 .can_dump_fw = false, 685 .can_auto_tdls = true, 686 .can_ext_scan = true, 687 }; 688 689 static const struct mwifiex_sdio_device mwifiex_sdio_sd8987 = { 690 .firmware = SD8987_DEFAULT_FW_NAME, 691 .reg = &mwifiex_reg_sd8987, 692 .max_ports = 32, 693 .mp_agg_pkt_limit = 16, 694 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 695 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 696 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 697 .supports_sdio_new_mode = true, 698 .has_control_mask = false, 699 .can_dump_fw = true, 700 .fw_dump_enh = true, 701 .can_auto_tdls = true, 702 .can_ext_scan = true, 703 }; 704 705 static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = { 706 .firmware = SD8801_DEFAULT_FW_NAME, 707 .reg = &mwifiex_reg_sd87xx, 708 .max_ports = 16, 709 .mp_agg_pkt_limit = 8, 710 .supports_sdio_new_mode = false, 711 .has_control_mask = true, 712 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 713 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 714 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 715 .can_dump_fw = false, 716 .can_auto_tdls = false, 717 .can_ext_scan = true, 718 }; 719 720 /* 721 * .cmdrsp_complete handler 722 */ 723 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, 724 struct sk_buff *skb) 725 { 726 dev_kfree_skb_any(skb); 727 return 0; 728 } 729 730 /* 731 * .event_complete handler 732 */ 733 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, 734 struct sk_buff *skb) 735 { 736 dev_kfree_skb_any(skb); 737 return 0; 738 } 739 740 static inline bool 741 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) 742 { 743 u8 tmp; 744 745 if (card->curr_rd_port < card->mpa_rx.start_port) { 746 if (card->supports_sdio_new_mode) 747 tmp = card->mp_end_port >> 1; 748 else 749 tmp = card->mp_agg_pkt_limit; 750 751 if (((card->max_ports - card->mpa_rx.start_port) + 752 card->curr_rd_port) >= tmp) 753 return true; 754 } 755 756 if (!card->supports_sdio_new_mode) 757 return false; 758 759 if ((card->curr_rd_port - card->mpa_rx.start_port) >= 760 (card->mp_end_port >> 1)) 761 return true; 762 763 return false; 764 } 765 766 static inline bool 767 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) 768 { 769 u16 tmp; 770 771 if (card->curr_wr_port < card->mpa_tx.start_port) { 772 if (card->supports_sdio_new_mode) 773 tmp = card->mp_end_port >> 1; 774 else 775 tmp = card->mp_agg_pkt_limit; 776 777 if (((card->max_ports - card->mpa_tx.start_port) + 778 card->curr_wr_port) >= tmp) 779 return true; 780 } 781 782 if (!card->supports_sdio_new_mode) 783 return false; 784 785 if ((card->curr_wr_port - card->mpa_tx.start_port) >= 786 (card->mp_end_port >> 1)) 787 return true; 788 789 return false; 790 } 791 792 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 793 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, 794 u16 rx_len, u8 port) 795 { 796 card->mpa_rx.buf_len += rx_len; 797 798 if (!card->mpa_rx.pkt_cnt) 799 card->mpa_rx.start_port = port; 800 801 if (card->supports_sdio_new_mode) { 802 card->mpa_rx.ports |= (1 << port); 803 } else { 804 if (card->mpa_rx.start_port <= port) 805 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); 806 else 807 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); 808 } 809 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL; 810 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len; 811 card->mpa_rx.pkt_cnt++; 812 } 813 #endif /* _MWIFIEX_SDIO_H */ 814