1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright (C) 2018 - 2020 Intel Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright (C) 2018 - 2020 Intel Corporation 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 38 * * Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * * Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in 42 * the documentation and/or other materials provided with the 43 * distribution. 44 * * Neither the name Intel Corporation nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 49 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 50 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 51 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 52 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 53 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 54 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 55 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 56 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 57 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 58 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 59 * 60 *****************************************************************************/ 61 62 #include <linux/firmware.h> 63 #include "iwl-drv.h" 64 #include "iwl-trans.h" 65 #include "iwl-dbg-tlv.h" 66 #include "fw/dbg.h" 67 #include "fw/runtime.h" 68 69 /** 70 * enum iwl_dbg_tlv_type - debug TLV types 71 * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV 72 * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV 73 * @IWL_DBG_TLV_TYPE_HCMD: host command TLV 74 * @IWL_DBG_TLV_TYPE_REGION: region TLV 75 * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV 76 * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs 77 */ 78 enum iwl_dbg_tlv_type { 79 IWL_DBG_TLV_TYPE_DEBUG_INFO = 80 IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE, 81 IWL_DBG_TLV_TYPE_BUF_ALLOC, 82 IWL_DBG_TLV_TYPE_HCMD, 83 IWL_DBG_TLV_TYPE_REGION, 84 IWL_DBG_TLV_TYPE_TRIGGER, 85 IWL_DBG_TLV_TYPE_NUM, 86 }; 87 88 /** 89 * struct iwl_dbg_tlv_ver_data - debug TLV version struct 90 * @min_ver: min version supported 91 * @max_ver: max version supported 92 */ 93 struct iwl_dbg_tlv_ver_data { 94 int min_ver; 95 int max_ver; 96 }; 97 98 /** 99 * struct iwl_dbg_tlv_timer_node - timer node struct 100 * @list: list of &struct iwl_dbg_tlv_timer_node 101 * @timer: timer 102 * @fwrt: &struct iwl_fw_runtime 103 * @tlv: TLV attach to the timer node 104 */ 105 struct iwl_dbg_tlv_timer_node { 106 struct list_head list; 107 struct timer_list timer; 108 struct iwl_fw_runtime *fwrt; 109 struct iwl_ucode_tlv *tlv; 110 }; 111 112 static const struct iwl_dbg_tlv_ver_data 113 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = { 114 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = {.min_ver = 1, .max_ver = 1,}, 115 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = {.min_ver = 1, .max_ver = 1,}, 116 [IWL_DBG_TLV_TYPE_HCMD] = {.min_ver = 1, .max_ver = 1,}, 117 [IWL_DBG_TLV_TYPE_REGION] = {.min_ver = 1, .max_ver = 1,}, 118 [IWL_DBG_TLV_TYPE_TRIGGER] = {.min_ver = 1, .max_ver = 1,}, 119 }; 120 121 static int iwl_dbg_tlv_add(struct iwl_ucode_tlv *tlv, struct list_head *list) 122 { 123 u32 len = le32_to_cpu(tlv->length); 124 struct iwl_dbg_tlv_node *node; 125 126 node = kzalloc(sizeof(*node) + len, GFP_KERNEL); 127 if (!node) 128 return -ENOMEM; 129 130 memcpy(&node->tlv, tlv, sizeof(node->tlv) + len); 131 list_add_tail(&node->list, list); 132 133 return 0; 134 } 135 136 static bool iwl_dbg_tlv_ver_support(struct iwl_ucode_tlv *tlv) 137 { 138 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 139 u32 type = le32_to_cpu(tlv->type); 140 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 141 u32 ver = le32_to_cpu(hdr->version); 142 143 if (ver < dbg_ver_table[tlv_idx].min_ver || 144 ver > dbg_ver_table[tlv_idx].max_ver) 145 return false; 146 147 return true; 148 } 149 150 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans, 151 struct iwl_ucode_tlv *tlv) 152 { 153 struct iwl_fw_ini_debug_info_tlv *debug_info = (void *)tlv->data; 154 155 if (le32_to_cpu(tlv->length) != sizeof(*debug_info)) 156 return -EINVAL; 157 158 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n", 159 debug_info->debug_cfg_name); 160 161 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list); 162 } 163 164 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans, 165 struct iwl_ucode_tlv *tlv) 166 { 167 struct iwl_fw_ini_allocation_tlv *alloc = (void *)tlv->data; 168 u32 buf_location; 169 u32 alloc_id; 170 171 if (le32_to_cpu(tlv->length) != sizeof(*alloc)) 172 return -EINVAL; 173 174 buf_location = le32_to_cpu(alloc->buf_location); 175 alloc_id = le32_to_cpu(alloc->alloc_id); 176 177 if (buf_location == IWL_FW_INI_LOCATION_INVALID || 178 buf_location >= IWL_FW_INI_LOCATION_NUM) 179 goto err; 180 181 if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID || 182 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 183 goto err; 184 185 if ((buf_location == IWL_FW_INI_LOCATION_SRAM_PATH || 186 buf_location == IWL_FW_INI_LOCATION_NPK_PATH) && 187 alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 188 goto err; 189 190 trans->dbg.fw_mon_cfg[alloc_id] = *alloc; 191 192 return 0; 193 err: 194 IWL_ERR(trans, 195 "WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n", 196 alloc_id, buf_location); 197 return -EINVAL; 198 } 199 200 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans, 201 struct iwl_ucode_tlv *tlv) 202 { 203 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)tlv->data; 204 u32 tp = le32_to_cpu(hcmd->time_point); 205 206 if (le32_to_cpu(tlv->length) <= sizeof(*hcmd)) 207 return -EINVAL; 208 209 /* Host commands can not be sent in early time point since the FW 210 * is not ready 211 */ 212 if (tp == IWL_FW_INI_TIME_POINT_INVALID || 213 tp >= IWL_FW_INI_TIME_POINT_NUM || 214 tp == IWL_FW_INI_TIME_POINT_EARLY) { 215 IWL_ERR(trans, 216 "WRT: Invalid time point %u for host command TLV\n", 217 tp); 218 return -EINVAL; 219 } 220 221 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list); 222 } 223 224 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans, 225 struct iwl_ucode_tlv *tlv) 226 { 227 struct iwl_fw_ini_region_tlv *reg = (void *)tlv->data; 228 struct iwl_ucode_tlv **active_reg; 229 u32 id = le32_to_cpu(reg->id); 230 u32 type = le32_to_cpu(reg->type); 231 u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length); 232 233 if (le32_to_cpu(tlv->length) < sizeof(*reg)) 234 return -EINVAL; 235 236 if (id >= IWL_FW_INI_MAX_REGION_ID) { 237 IWL_ERR(trans, "WRT: Invalid region id %u\n", id); 238 return -EINVAL; 239 } 240 241 if (type <= IWL_FW_INI_REGION_INVALID || 242 type >= IWL_FW_INI_REGION_NUM) { 243 IWL_ERR(trans, "WRT: Invalid region type %u\n", type); 244 return -EINVAL; 245 } 246 247 if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG && 248 !trans->ops->read_config32) { 249 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type); 250 return -EOPNOTSUPP; 251 } 252 253 active_reg = &trans->dbg.active_regions[id]; 254 if (*active_reg) { 255 IWL_WARN(trans, "WRT: Overriding region id %u\n", id); 256 257 kfree(*active_reg); 258 } 259 260 *active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL); 261 if (!*active_reg) 262 return -ENOMEM; 263 264 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type); 265 266 return 0; 267 } 268 269 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans, 270 struct iwl_ucode_tlv *tlv) 271 { 272 struct iwl_fw_ini_trigger_tlv *trig = (void *)tlv->data; 273 u32 tp = le32_to_cpu(trig->time_point); 274 275 if (le32_to_cpu(tlv->length) < sizeof(*trig)) 276 return -EINVAL; 277 278 if (tp <= IWL_FW_INI_TIME_POINT_INVALID || 279 tp >= IWL_FW_INI_TIME_POINT_NUM) { 280 IWL_ERR(trans, 281 "WRT: Invalid time point %u for trigger TLV\n", 282 tp); 283 return -EINVAL; 284 } 285 286 if (!le32_to_cpu(trig->occurrences)) 287 trig->occurrences = cpu_to_le32(-1); 288 289 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list); 290 } 291 292 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans, 293 struct iwl_ucode_tlv *tlv) = { 294 [IWL_DBG_TLV_TYPE_DEBUG_INFO] = iwl_dbg_tlv_alloc_debug_info, 295 [IWL_DBG_TLV_TYPE_BUF_ALLOC] = iwl_dbg_tlv_alloc_buf_alloc, 296 [IWL_DBG_TLV_TYPE_HCMD] = iwl_dbg_tlv_alloc_hcmd, 297 [IWL_DBG_TLV_TYPE_REGION] = iwl_dbg_tlv_alloc_region, 298 [IWL_DBG_TLV_TYPE_TRIGGER] = iwl_dbg_tlv_alloc_trigger, 299 }; 300 301 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, struct iwl_ucode_tlv *tlv, 302 bool ext) 303 { 304 struct iwl_fw_ini_header *hdr = (void *)&tlv->data[0]; 305 u32 type = le32_to_cpu(tlv->type); 306 u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE; 307 u32 domain = le32_to_cpu(hdr->domain); 308 enum iwl_ini_cfg_state *cfg_state = ext ? 309 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg; 310 int ret; 311 312 if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON && 313 !(domain & trans->dbg.domains_bitmap)) { 314 IWL_DEBUG_FW(trans, 315 "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n", 316 domain, trans->dbg.domains_bitmap); 317 return; 318 } 319 320 if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) { 321 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type); 322 goto out_err; 323 } 324 325 if (!iwl_dbg_tlv_ver_support(tlv)) { 326 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type, 327 le32_to_cpu(hdr->version)); 328 goto out_err; 329 } 330 331 ret = dbg_tlv_alloc[tlv_idx](trans, tlv); 332 if (ret) { 333 IWL_ERR(trans, 334 "WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n", 335 type, ret, ext); 336 goto out_err; 337 } 338 339 if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED) 340 *cfg_state = IWL_INI_CFG_STATE_LOADED; 341 342 return; 343 344 out_err: 345 *cfg_state = IWL_INI_CFG_STATE_CORRUPTED; 346 } 347 348 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans) 349 { 350 struct list_head *timer_list = &trans->dbg.periodic_trig_list; 351 struct iwl_dbg_tlv_timer_node *node, *tmp; 352 353 list_for_each_entry_safe(node, tmp, timer_list, list) { 354 del_timer(&node->timer); 355 list_del(&node->list); 356 kfree(node); 357 } 358 } 359 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers); 360 361 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans, 362 enum iwl_fw_ini_allocation_id alloc_id) 363 { 364 struct iwl_fw_mon *fw_mon; 365 int i; 366 367 if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID || 368 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 369 return; 370 371 fw_mon = &trans->dbg.fw_mon_ini[alloc_id]; 372 373 for (i = 0; i < fw_mon->num_frags; i++) { 374 struct iwl_dram_data *frag = &fw_mon->frags[i]; 375 376 dma_free_coherent(trans->dev, frag->size, frag->block, 377 frag->physical); 378 379 frag->physical = 0; 380 frag->block = NULL; 381 frag->size = 0; 382 } 383 384 kfree(fw_mon->frags); 385 fw_mon->frags = NULL; 386 fw_mon->num_frags = 0; 387 } 388 389 void iwl_dbg_tlv_free(struct iwl_trans *trans) 390 { 391 struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp; 392 int i; 393 394 iwl_dbg_tlv_del_timers(trans); 395 396 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) { 397 struct iwl_ucode_tlv **active_reg = 398 &trans->dbg.active_regions[i]; 399 400 kfree(*active_reg); 401 *active_reg = NULL; 402 } 403 404 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 405 &trans->dbg.debug_info_tlv_list, list) { 406 list_del(&tlv_node->list); 407 kfree(tlv_node); 408 } 409 410 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 411 struct iwl_dbg_tlv_time_point_data *tp = 412 &trans->dbg.time_point[i]; 413 414 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list, 415 list) { 416 list_del(&tlv_node->list); 417 kfree(tlv_node); 418 } 419 420 list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list, 421 list) { 422 list_del(&tlv_node->list); 423 kfree(tlv_node); 424 } 425 426 list_for_each_entry_safe(tlv_node, tlv_node_tmp, 427 &tp->active_trig_list, list) { 428 list_del(&tlv_node->list); 429 kfree(tlv_node); 430 } 431 } 432 433 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++) 434 iwl_dbg_tlv_fragments_free(trans, i); 435 } 436 437 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data, 438 size_t len) 439 { 440 struct iwl_ucode_tlv *tlv; 441 u32 tlv_len; 442 443 while (len >= sizeof(*tlv)) { 444 len -= sizeof(*tlv); 445 tlv = (void *)data; 446 447 tlv_len = le32_to_cpu(tlv->length); 448 449 if (len < tlv_len) { 450 IWL_ERR(trans, "invalid TLV len: %zd/%u\n", 451 len, tlv_len); 452 return -EINVAL; 453 } 454 len -= ALIGN(tlv_len, 4); 455 data += sizeof(*tlv) + ALIGN(tlv_len, 4); 456 457 iwl_dbg_tlv_alloc(trans, tlv, true); 458 } 459 460 return 0; 461 } 462 463 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans) 464 { 465 const struct firmware *fw; 466 int res; 467 468 if (!iwlwifi_mod_params.enable_ini) 469 return; 470 471 res = request_firmware(&fw, "iwl-debug-yoyo.bin", dev); 472 if (res) 473 return; 474 475 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size); 476 477 release_firmware(fw); 478 } 479 480 void iwl_dbg_tlv_init(struct iwl_trans *trans) 481 { 482 int i; 483 484 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list); 485 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list); 486 487 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) { 488 struct iwl_dbg_tlv_time_point_data *tp = 489 &trans->dbg.time_point[i]; 490 491 INIT_LIST_HEAD(&tp->trig_list); 492 INIT_LIST_HEAD(&tp->hcmd_list); 493 INIT_LIST_HEAD(&tp->active_trig_list); 494 } 495 } 496 497 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt, 498 struct iwl_dram_data *frag, u32 pages) 499 { 500 void *block = NULL; 501 dma_addr_t physical; 502 503 if (!frag || frag->size || !pages) 504 return -EIO; 505 506 /* 507 * We try to allocate as many pages as we can, starting with 508 * the requested amount and going down until we can allocate 509 * something. Because of DIV_ROUND_UP(), pages will never go 510 * down to 0 and stop the loop, so stop when pages reaches 1, 511 * which is too small anyway. 512 */ 513 while (pages > 1) { 514 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE, 515 &physical, 516 GFP_KERNEL | __GFP_NOWARN); 517 if (block) 518 break; 519 520 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n", 521 pages * PAGE_SIZE); 522 523 pages = DIV_ROUND_UP(pages, 2); 524 } 525 526 if (!block) 527 return -ENOMEM; 528 529 frag->physical = physical; 530 frag->block = block; 531 frag->size = pages * PAGE_SIZE; 532 533 return pages; 534 } 535 536 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt, 537 enum iwl_fw_ini_allocation_id alloc_id) 538 { 539 struct iwl_fw_mon *fw_mon; 540 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; 541 u32 num_frags, remain_pages, frag_pages; 542 int i; 543 544 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 545 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 546 return -EIO; 547 548 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id]; 549 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 550 551 if (fw_mon->num_frags || 552 fw_mon_cfg->buf_location != 553 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH)) 554 return 0; 555 556 num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num); 557 if (!fw_has_capa(&fwrt->fw->ucode_capa, 558 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) { 559 if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1) 560 return -EIO; 561 num_frags = 1; 562 } 563 564 remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size), 565 PAGE_SIZE); 566 num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS); 567 num_frags = min_t(u32, num_frags, remain_pages); 568 frag_pages = DIV_ROUND_UP(remain_pages, num_frags); 569 570 fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL); 571 if (!fw_mon->frags) 572 return -ENOMEM; 573 574 for (i = 0; i < num_frags; i++) { 575 int pages = min_t(u32, frag_pages, remain_pages); 576 577 IWL_DEBUG_FW(fwrt, 578 "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n", 579 alloc_id, i, pages * PAGE_SIZE); 580 581 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i], 582 pages); 583 if (pages < 0) { 584 u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) - 585 (remain_pages * PAGE_SIZE); 586 587 if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) { 588 iwl_dbg_tlv_fragments_free(fwrt->trans, 589 alloc_id); 590 return pages; 591 } 592 break; 593 } 594 595 remain_pages -= pages; 596 fw_mon->num_frags++; 597 } 598 599 return 0; 600 } 601 602 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt, 603 enum iwl_fw_ini_allocation_id alloc_id) 604 { 605 struct iwl_fw_mon *fw_mon; 606 u32 remain_frags, num_commands; 607 int i, fw_mon_idx = 0; 608 609 if (!fw_has_capa(&fwrt->fw->ucode_capa, 610 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) 611 return 0; 612 613 if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID || 614 alloc_id >= IWL_FW_INI_ALLOCATION_NUM) 615 return -EIO; 616 617 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) != 618 IWL_FW_INI_LOCATION_DRAM_PATH) 619 return 0; 620 621 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 622 623 /* the first fragment of DBGC1 is given to the FW via register 624 * or context info 625 */ 626 if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1) 627 fw_mon_idx++; 628 629 remain_frags = fw_mon->num_frags - fw_mon_idx; 630 if (!remain_frags) 631 return 0; 632 633 num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS); 634 635 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n", 636 alloc_id); 637 638 for (i = 0; i < num_commands; i++) { 639 u32 num_frags = min_t(u32, remain_frags, 640 BUF_ALLOC_MAX_NUM_FRAGS); 641 struct iwl_buf_alloc_cmd data = { 642 .alloc_id = cpu_to_le32(alloc_id), 643 .num_frags = cpu_to_le32(num_frags), 644 .buf_location = 645 cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH), 646 }; 647 struct iwl_host_cmd hcmd = { 648 .id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION), 649 .data[0] = &data, 650 .len[0] = sizeof(data), 651 }; 652 int ret, j; 653 654 for (j = 0; j < num_frags; j++) { 655 struct iwl_buf_alloc_frag *frag = &data.frags[j]; 656 struct iwl_dram_data *fw_mon_frag = 657 &fw_mon->frags[fw_mon_idx++]; 658 659 frag->addr = cpu_to_le64(fw_mon_frag->physical); 660 frag->size = cpu_to_le32(fw_mon_frag->size); 661 } 662 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 663 if (ret) 664 return ret; 665 666 remain_frags -= num_frags; 667 } 668 669 return 0; 670 } 671 672 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt) 673 { 674 int ret, i; 675 676 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 677 ret = iwl_dbg_tlv_apply_buffer(fwrt, i); 678 if (ret) 679 IWL_WARN(fwrt, 680 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n", 681 i, ret); 682 } 683 } 684 685 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt, 686 struct list_head *hcmd_list) 687 { 688 struct iwl_dbg_tlv_node *node; 689 690 list_for_each_entry(node, hcmd_list, list) { 691 struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data; 692 struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd; 693 u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd); 694 struct iwl_host_cmd cmd = { 695 .id = WIDE_ID(hcmd_data->group, hcmd_data->id), 696 .len = { hcmd_len, }, 697 .data = { hcmd_data->data, }, 698 }; 699 700 iwl_trans_send_cmd(fwrt->trans, &cmd); 701 } 702 } 703 704 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t) 705 { 706 struct iwl_dbg_tlv_timer_node *timer_node = 707 from_timer(timer_node, t, timer); 708 struct iwl_fwrt_dump_data dump_data = { 709 .trig = (void *)timer_node->tlv->data, 710 }; 711 int ret; 712 713 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data); 714 if (!ret || ret == -EBUSY) { 715 u32 occur = le32_to_cpu(dump_data.trig->occurrences); 716 u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]); 717 718 if (!occur) 719 return; 720 721 mod_timer(t, jiffies + msecs_to_jiffies(collect_interval)); 722 } 723 } 724 725 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt) 726 { 727 struct iwl_dbg_tlv_node *node; 728 struct list_head *trig_list = 729 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list; 730 731 list_for_each_entry(node, trig_list, list) { 732 struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data; 733 struct iwl_dbg_tlv_timer_node *timer_node; 734 u32 occur = le32_to_cpu(trig->occurrences), collect_interval; 735 u32 min_interval = 100; 736 737 if (!occur) 738 continue; 739 740 /* make sure there is at least one dword of data for the 741 * interval value 742 */ 743 if (le32_to_cpu(node->tlv.length) < 744 sizeof(*trig) + sizeof(__le32)) { 745 IWL_ERR(fwrt, 746 "WRT: Invalid periodic trigger data was not given\n"); 747 continue; 748 } 749 750 if (le32_to_cpu(trig->data[0]) < min_interval) { 751 IWL_WARN(fwrt, 752 "WRT: Override min interval from %u to %u msec\n", 753 le32_to_cpu(trig->data[0]), min_interval); 754 trig->data[0] = cpu_to_le32(min_interval); 755 } 756 757 collect_interval = le32_to_cpu(trig->data[0]); 758 759 timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL); 760 if (!timer_node) { 761 IWL_ERR(fwrt, 762 "WRT: Failed to allocate periodic trigger\n"); 763 continue; 764 } 765 766 timer_node->fwrt = fwrt; 767 timer_node->tlv = &node->tlv; 768 timer_setup(&timer_node->timer, 769 iwl_dbg_tlv_periodic_trig_handler, 0); 770 771 list_add_tail(&timer_node->list, 772 &fwrt->trans->dbg.periodic_trig_list); 773 774 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n"); 775 776 mod_timer(&timer_node->timer, 777 jiffies + msecs_to_jiffies(collect_interval)); 778 } 779 } 780 781 static bool is_trig_data_contained(struct iwl_ucode_tlv *new, 782 struct iwl_ucode_tlv *old) 783 { 784 struct iwl_fw_ini_trigger_tlv *new_trig = (void *)new->data; 785 struct iwl_fw_ini_trigger_tlv *old_trig = (void *)old->data; 786 __le32 *new_data = new_trig->data, *old_data = old_trig->data; 787 u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data); 788 u32 old_dwords_num = iwl_tlv_array_len(new, new_trig, data); 789 int i, j; 790 791 for (i = 0; i < new_dwords_num; i++) { 792 bool match = false; 793 794 for (j = 0; j < old_dwords_num; j++) { 795 if (new_data[i] == old_data[j]) { 796 match = true; 797 break; 798 } 799 } 800 if (!match) 801 return false; 802 } 803 804 return true; 805 } 806 807 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt, 808 struct iwl_ucode_tlv *trig_tlv, 809 struct iwl_dbg_tlv_node *node) 810 { 811 struct iwl_ucode_tlv *node_tlv = &node->tlv; 812 struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data; 813 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 814 u32 policy = le32_to_cpu(trig->apply_policy); 815 u32 size = le32_to_cpu(trig_tlv->length); 816 u32 trig_data_len = size - sizeof(*trig); 817 u32 offset = 0; 818 819 if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) { 820 u32 data_len = le32_to_cpu(node_tlv->length) - 821 sizeof(*node_trig); 822 823 IWL_DEBUG_FW(fwrt, 824 "WRT: Appending trigger data (time point %u)\n", 825 le32_to_cpu(trig->time_point)); 826 827 offset += data_len; 828 size += data_len; 829 } else { 830 IWL_DEBUG_FW(fwrt, 831 "WRT: Overriding trigger data (time point %u)\n", 832 le32_to_cpu(trig->time_point)); 833 } 834 835 if (size != le32_to_cpu(node_tlv->length)) { 836 struct list_head *prev = node->list.prev; 837 struct iwl_dbg_tlv_node *tmp; 838 839 list_del(&node->list); 840 841 tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL); 842 if (!tmp) { 843 IWL_WARN(fwrt, 844 "WRT: No memory to override trigger (time point %u)\n", 845 le32_to_cpu(trig->time_point)); 846 847 list_add(&node->list, prev); 848 849 return -ENOMEM; 850 } 851 852 list_add(&tmp->list, prev); 853 node_tlv = &tmp->tlv; 854 node_trig = (void *)node_tlv->data; 855 } 856 857 memcpy(node_trig->data + offset, trig->data, trig_data_len); 858 node_tlv->length = cpu_to_le32(size); 859 860 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) { 861 IWL_DEBUG_FW(fwrt, 862 "WRT: Overriding trigger configuration (time point %u)\n", 863 le32_to_cpu(trig->time_point)); 864 865 /* the first 11 dwords are configuration related */ 866 memcpy(node_trig, trig, sizeof(__le32) * 11); 867 } 868 869 if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) { 870 IWL_DEBUG_FW(fwrt, 871 "WRT: Overriding trigger regions (time point %u)\n", 872 le32_to_cpu(trig->time_point)); 873 874 node_trig->regions_mask = trig->regions_mask; 875 } else { 876 IWL_DEBUG_FW(fwrt, 877 "WRT: Appending trigger regions (time point %u)\n", 878 le32_to_cpu(trig->time_point)); 879 880 node_trig->regions_mask |= trig->regions_mask; 881 } 882 883 return 0; 884 } 885 886 static int 887 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt, 888 struct list_head *trig_list, 889 struct iwl_ucode_tlv *trig_tlv) 890 { 891 struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data; 892 struct iwl_dbg_tlv_node *node, *match = NULL; 893 u32 policy = le32_to_cpu(trig->apply_policy); 894 895 list_for_each_entry(node, trig_list, list) { 896 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT)) 897 break; 898 899 if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) || 900 is_trig_data_contained(trig_tlv, &node->tlv)) { 901 match = node; 902 break; 903 } 904 } 905 906 if (!match) { 907 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n", 908 le32_to_cpu(trig->time_point)); 909 return iwl_dbg_tlv_add(trig_tlv, trig_list); 910 } 911 912 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match); 913 } 914 915 static void 916 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt, 917 struct iwl_dbg_tlv_time_point_data *tp) 918 { 919 struct iwl_dbg_tlv_node *node; 920 struct list_head *trig_list = &tp->trig_list; 921 struct list_head *active_trig_list = &tp->active_trig_list; 922 923 list_for_each_entry(node, trig_list, list) { 924 struct iwl_ucode_tlv *tlv = &node->tlv; 925 926 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv); 927 } 928 } 929 930 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt, 931 struct iwl_fwrt_dump_data *dump_data, 932 union iwl_dbg_tlv_tp_data *tp_data, 933 u32 trig_data) 934 { 935 struct iwl_rx_packet *pkt = tp_data->fw_pkt; 936 struct iwl_cmd_header *wanted_hdr = (void *)&trig_data; 937 938 if (pkt && ((wanted_hdr->cmd == 0 && wanted_hdr->group_id == 0) || 939 (pkt->hdr.cmd == wanted_hdr->cmd && 940 pkt->hdr.group_id == wanted_hdr->group_id))) { 941 struct iwl_rx_packet *fw_pkt = 942 kmemdup(pkt, 943 sizeof(*pkt) + iwl_rx_packet_payload_len(pkt), 944 GFP_ATOMIC); 945 946 if (!fw_pkt) 947 return false; 948 949 dump_data->fw_pkt = fw_pkt; 950 951 return true; 952 } 953 954 return false; 955 } 956 957 static int 958 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, 959 struct list_head *active_trig_list, 960 union iwl_dbg_tlv_tp_data *tp_data, 961 bool (*data_check)(struct iwl_fw_runtime *fwrt, 962 struct iwl_fwrt_dump_data *dump_data, 963 union iwl_dbg_tlv_tp_data *tp_data, 964 u32 trig_data)) 965 { 966 struct iwl_dbg_tlv_node *node; 967 968 list_for_each_entry(node, active_trig_list, list) { 969 struct iwl_fwrt_dump_data dump_data = { 970 .trig = (void *)node->tlv.data, 971 }; 972 u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig, 973 data); 974 int ret, i; 975 976 if (!num_data) { 977 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 978 if (ret) 979 return ret; 980 } 981 982 for (i = 0; i < num_data; i++) { 983 if (!data_check || 984 data_check(fwrt, &dump_data, tp_data, 985 le32_to_cpu(dump_data.trig->data[i]))) { 986 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data); 987 if (ret) 988 return ret; 989 990 break; 991 } 992 } 993 } 994 995 return 0; 996 } 997 998 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt) 999 { 1000 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest; 1001 int ret, i; 1002 1003 IWL_DEBUG_FW(fwrt, 1004 "WRT: Generating active triggers list, domain 0x%x\n", 1005 fwrt->trans->dbg.domains_bitmap); 1006 1007 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) { 1008 struct iwl_dbg_tlv_time_point_data *tp = 1009 &fwrt->trans->dbg.time_point[i]; 1010 1011 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp); 1012 } 1013 1014 *ini_dest = IWL_FW_INI_LOCATION_INVALID; 1015 for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) { 1016 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 1017 &fwrt->trans->dbg.fw_mon_cfg[i]; 1018 u32 dest = le32_to_cpu(fw_mon_cfg->buf_location); 1019 1020 if (dest == IWL_FW_INI_LOCATION_INVALID) 1021 continue; 1022 1023 if (*ini_dest == IWL_FW_INI_LOCATION_INVALID) 1024 *ini_dest = dest; 1025 1026 if (dest != *ini_dest) 1027 continue; 1028 1029 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i); 1030 if (ret) 1031 IWL_WARN(fwrt, 1032 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n", 1033 i, ret); 1034 } 1035 } 1036 1037 void iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt, 1038 enum iwl_fw_ini_time_point tp_id, 1039 union iwl_dbg_tlv_tp_data *tp_data) 1040 { 1041 struct list_head *hcmd_list, *trig_list; 1042 1043 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 1044 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 1045 tp_id >= IWL_FW_INI_TIME_POINT_NUM) 1046 return; 1047 1048 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list; 1049 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list; 1050 1051 switch (tp_id) { 1052 case IWL_FW_INI_TIME_POINT_EARLY: 1053 iwl_dbg_tlv_init_cfg(fwrt); 1054 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1055 break; 1056 case IWL_FW_INI_TIME_POINT_AFTER_ALIVE: 1057 iwl_dbg_tlv_apply_buffers(fwrt); 1058 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1059 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1060 break; 1061 case IWL_FW_INI_TIME_POINT_PERIODIC: 1062 iwl_dbg_tlv_set_periodic_trigs(fwrt); 1063 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1064 break; 1065 case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF: 1066 case IWL_FW_INI_TIME_POINT_MISSED_BEACONS: 1067 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1068 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, 1069 iwl_dbg_tlv_check_fw_pkt); 1070 break; 1071 default: 1072 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list); 1073 iwl_dbg_tlv_tp_trigger(fwrt, trig_list, tp_data, NULL); 1074 break; 1075 } 1076 } 1077 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_time_point); 1078