1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 #include <linux/firmware.h> 24 25 #include "mac.h" 26 #include "ani.h" 27 #include "eeprom.h" 28 #include "calib.h" 29 #include "reg.h" 30 #include "phy.h" 31 #include "btcoex.h" 32 33 #include "../regd.h" 34 35 #define ATHEROS_VENDOR_ID 0x168c 36 37 #define AR5416_DEVID_PCI 0x0023 38 #define AR5416_DEVID_PCIE 0x0024 39 #define AR9160_DEVID_PCI 0x0027 40 #define AR9280_DEVID_PCI 0x0029 41 #define AR9280_DEVID_PCIE 0x002a 42 #define AR9285_DEVID_PCIE 0x002b 43 #define AR2427_DEVID_PCIE 0x002c 44 #define AR9287_DEVID_PCI 0x002d 45 #define AR9287_DEVID_PCIE 0x002e 46 #define AR9300_DEVID_PCIE 0x0030 47 #define AR9300_DEVID_AR9340 0x0031 48 #define AR9300_DEVID_AR9485_PCIE 0x0032 49 #define AR9300_DEVID_AR9580 0x0033 50 #define AR9300_DEVID_AR9462 0x0034 51 #define AR9300_DEVID_AR9330 0x0035 52 #define AR9300_DEVID_QCA955X 0x0038 53 #define AR9485_DEVID_AR1111 0x0037 54 #define AR9300_DEVID_AR9565 0x0036 55 56 #define AR5416_AR9100_DEVID 0x000b 57 58 #define AR_SUBVENDOR_ID_NOG 0x0e11 59 #define AR_SUBVENDOR_ID_NEW_A 0x7065 60 #define AR5416_MAGIC 0x19641014 61 62 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 63 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 64 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 65 66 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 67 68 #define ATH_DEFAULT_NOISE_FLOOR -95 69 70 #define ATH9K_RSSI_BAD -128 71 72 #define ATH9K_NUM_CHANNELS 38 73 74 /* Register read/write primitives */ 75 #define REG_WRITE(_ah, _reg, _val) \ 76 (_ah)->reg_ops.write((_ah), (_val), (_reg)) 77 78 #define REG_READ(_ah, _reg) \ 79 (_ah)->reg_ops.read((_ah), (_reg)) 80 81 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ 82 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) 83 84 #define REG_RMW(_ah, _reg, _set, _clr) \ 85 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) 86 87 #define ENABLE_REGWRITE_BUFFER(_ah) \ 88 do { \ 89 if ((_ah)->reg_ops.enable_write_buffer) \ 90 (_ah)->reg_ops.enable_write_buffer((_ah)); \ 91 } while (0) 92 93 #define REGWRITE_BUFFER_FLUSH(_ah) \ 94 do { \ 95 if ((_ah)->reg_ops.write_flush) \ 96 (_ah)->reg_ops.write_flush((_ah)); \ 97 } while (0) 98 99 #define PR_EEP(_s, _val) \ 100 do { \ 101 len += snprintf(buf + len, size - len, "%20s : %10d\n", \ 102 _s, (_val)); \ 103 } while (0) 104 105 #define SM(_v, _f) (((_v) << _f##_S) & _f) 106 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 107 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 108 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) 109 #define REG_READ_FIELD(_a, _r, _f) \ 110 (((REG_READ(_a, _r) & _f) >> _f##_S)) 111 #define REG_SET_BIT(_a, _r, _f) \ 112 REG_RMW(_a, _r, (_f), 0) 113 #define REG_CLR_BIT(_a, _r, _f) \ 114 REG_RMW(_a, _r, 0, (_f)) 115 116 #define DO_DELAY(x) do { \ 117 if (((++(x) % 64) == 0) && \ 118 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ 119 != ATH_USB)) \ 120 udelay(1); \ 121 } while (0) 122 123 #define REG_WRITE_ARRAY(iniarray, column, regWr) \ 124 ath9k_hw_write_array(ah, iniarray, column, &(regWr)) 125 126 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 128 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 129 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 130 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 132 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 133 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 134 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 135 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 136 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 137 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 138 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 139 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 140 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 141 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d 142 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e 143 144 #define AR_GPIOD_MASK 0x00001FFF 145 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 146 147 #define BASE_ACTIVATE_DELAY 100 148 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) 149 #define COEF_SCALE_S 24 150 #define HT40_CHANNEL_CENTER_SHIFT 10 151 152 #define ATH9K_ANTENNA0_CHAINMASK 0x1 153 #define ATH9K_ANTENNA1_CHAINMASK 0x2 154 155 #define ATH9K_NUM_DMA_DEBUG_REGS 8 156 #define ATH9K_NUM_QUEUES 10 157 158 #define MAX_RATE_POWER 63 159 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 160 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 161 #define AH_TIME_QUANTUM 10 162 #define AR_KEYTABLE_SIZE 128 163 #define POWER_UP_TIME 10000 164 #define SPUR_RSSI_THRESH 40 165 #define UPPER_5G_SUB_BAND_START 5700 166 #define MID_5G_SUB_BAND_START 5400 167 168 #define CAB_TIMEOUT_VAL 10 169 #define BEACON_TIMEOUT_VAL 10 170 #define MIN_BEACON_TIMEOUT_VAL 1 171 #define SLEEP_SLOP 3 172 173 #define INIT_CONFIG_STATUS 0x00000000 174 #define INIT_RSSI_THR 0x00000700 175 #define INIT_BCON_CNTRL_REG 0x00000000 176 177 #define TU_TO_USEC(_tu) ((_tu) << 10) 178 179 #define ATH9K_HW_RX_HP_QDEPTH 16 180 #define ATH9K_HW_RX_LP_QDEPTH 128 181 182 #define PAPRD_GAIN_TABLE_ENTRIES 32 183 #define PAPRD_TABLE_SZ 24 184 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 185 186 /* 187 * Wake on Wireless 188 */ 189 190 /* Keep Alive Frame */ 191 #define KAL_FRAME_LEN 28 192 #define KAL_FRAME_TYPE 0x2 /* data frame */ 193 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ 194 #define KAL_DURATION_ID 0x3d 195 #define KAL_NUM_DATA_WORDS 6 196 #define KAL_NUM_DESC_WORDS 12 197 #define KAL_ANTENNA_MODE 1 198 #define KAL_TO_DS 1 199 #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ 200 #define KAL_TIMEOUT 900 201 202 #define MAX_PATTERN_SIZE 256 203 #define MAX_PATTERN_MASK_SIZE 32 204 #define MAX_NUM_PATTERN 8 205 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and 206 deauthenticate packets */ 207 208 /* 209 * WoW trigger mapping to hardware code 210 */ 211 212 #define AH_WOW_USER_PATTERN_EN BIT(0) 213 #define AH_WOW_MAGIC_PATTERN_EN BIT(1) 214 #define AH_WOW_LINK_CHANGE BIT(2) 215 #define AH_WOW_BEACON_MISS BIT(3) 216 217 enum ath_hw_txq_subtype { 218 ATH_TXQ_AC_BE = 0, 219 ATH_TXQ_AC_BK = 1, 220 ATH_TXQ_AC_VI = 2, 221 ATH_TXQ_AC_VO = 3, 222 }; 223 224 enum ath_ini_subsys { 225 ATH_INI_PRE = 0, 226 ATH_INI_CORE, 227 ATH_INI_POST, 228 ATH_INI_NUM_SPLIT, 229 }; 230 231 enum ath9k_hw_caps { 232 ATH9K_HW_CAP_HT = BIT(0), 233 ATH9K_HW_CAP_RFSILENT = BIT(1), 234 ATH9K_HW_CAP_AUTOSLEEP = BIT(2), 235 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), 236 ATH9K_HW_CAP_EDMA = BIT(4), 237 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), 238 ATH9K_HW_CAP_LDPC = BIT(6), 239 ATH9K_HW_CAP_FASTCLOCK = BIT(7), 240 ATH9K_HW_CAP_SGI_20 = BIT(8), 241 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), 242 ATH9K_HW_CAP_2GHZ = BIT(11), 243 ATH9K_HW_CAP_5GHZ = BIT(12), 244 ATH9K_HW_CAP_APM = BIT(13), 245 ATH9K_HW_CAP_RTT = BIT(14), 246 ATH9K_HW_CAP_MCI = BIT(15), 247 ATH9K_HW_CAP_DFS = BIT(16), 248 ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(17), 249 ATH9K_HW_WOW_PATTERN_MATCH_EXACT = BIT(18), 250 ATH9K_HW_WOW_PATTERN_MATCH_DWORD = BIT(19), 251 ATH9K_HW_CAP_PAPRD = BIT(20), 252 }; 253 254 /* 255 * WoW device capabilities 256 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. 257 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching 258 * an exact user defined pattern or de-authentication/disassoc pattern. 259 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four 260 * bytes of the pattern for user defined pattern, de-authentication and 261 * disassociation patterns for all types of possible frames recieved 262 * of those types. 263 */ 264 265 struct ath9k_hw_capabilities { 266 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 267 u16 rts_aggr_limit; 268 u8 tx_chainmask; 269 u8 rx_chainmask; 270 u8 max_txchains; 271 u8 max_rxchains; 272 u8 num_gpio_pins; 273 u8 rx_hp_qdepth; 274 u8 rx_lp_qdepth; 275 u8 rx_status_len; 276 u8 tx_desc_len; 277 u8 txs_len; 278 }; 279 280 struct ath9k_ops_config { 281 int dma_beacon_response_time; 282 int sw_beacon_response_time; 283 int additional_swba_backoff; 284 int ack_6mb; 285 u32 cwm_ignore_extcca; 286 bool pcieSerDesWrite; 287 u8 pcie_clock_req; 288 u32 pcie_waen; 289 u8 analog_shiftreg; 290 u32 ofdm_trig_low; 291 u32 ofdm_trig_high; 292 u32 cck_trig_high; 293 u32 cck_trig_low; 294 u32 enable_ani; 295 u32 enable_paprd; 296 int serialize_regmode; 297 bool rx_intr_mitigation; 298 bool tx_intr_mitigation; 299 #define SPUR_DISABLE 0 300 #define SPUR_ENABLE_IOCTL 1 301 #define SPUR_ENABLE_EEPROM 2 302 #define AR_SPUR_5413_1 1640 303 #define AR_SPUR_5413_2 1200 304 #define AR_NO_SPUR 0x8000 305 #define AR_BASE_FREQ_2GHZ 2300 306 #define AR_BASE_FREQ_5GHZ 4900 307 #define AR_SPUR_FEEQ_BOUND_HT40 19 308 #define AR_SPUR_FEEQ_BOUND_HT20 10 309 int spurmode; 310 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 311 u8 max_txtrig_level; 312 u16 ani_poll_interval; /* ANI poll interval in ms */ 313 }; 314 315 enum ath9k_int { 316 ATH9K_INT_RX = 0x00000001, 317 ATH9K_INT_RXDESC = 0x00000002, 318 ATH9K_INT_RXHP = 0x00000001, 319 ATH9K_INT_RXLP = 0x00000002, 320 ATH9K_INT_RXNOFRM = 0x00000008, 321 ATH9K_INT_RXEOL = 0x00000010, 322 ATH9K_INT_RXORN = 0x00000020, 323 ATH9K_INT_TX = 0x00000040, 324 ATH9K_INT_TXDESC = 0x00000080, 325 ATH9K_INT_TIM_TIMER = 0x00000100, 326 ATH9K_INT_MCI = 0x00000200, 327 ATH9K_INT_BB_WATCHDOG = 0x00000400, 328 ATH9K_INT_TXURN = 0x00000800, 329 ATH9K_INT_MIB = 0x00001000, 330 ATH9K_INT_RXPHY = 0x00004000, 331 ATH9K_INT_RXKCM = 0x00008000, 332 ATH9K_INT_SWBA = 0x00010000, 333 ATH9K_INT_BMISS = 0x00040000, 334 ATH9K_INT_BNR = 0x00100000, 335 ATH9K_INT_TIM = 0x00200000, 336 ATH9K_INT_DTIM = 0x00400000, 337 ATH9K_INT_DTIMSYNC = 0x00800000, 338 ATH9K_INT_GPIO = 0x01000000, 339 ATH9K_INT_CABEND = 0x02000000, 340 ATH9K_INT_TSFOOR = 0x04000000, 341 ATH9K_INT_GENTIMER = 0x08000000, 342 ATH9K_INT_CST = 0x10000000, 343 ATH9K_INT_GTT = 0x20000000, 344 ATH9K_INT_FATAL = 0x40000000, 345 ATH9K_INT_GLOBAL = 0x80000000, 346 ATH9K_INT_BMISC = ATH9K_INT_TIM | 347 ATH9K_INT_DTIM | 348 ATH9K_INT_DTIMSYNC | 349 ATH9K_INT_TSFOOR | 350 ATH9K_INT_CABEND, 351 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 352 ATH9K_INT_RXDESC | 353 ATH9K_INT_RXEOL | 354 ATH9K_INT_RXORN | 355 ATH9K_INT_TXURN | 356 ATH9K_INT_TXDESC | 357 ATH9K_INT_MIB | 358 ATH9K_INT_RXPHY | 359 ATH9K_INT_RXKCM | 360 ATH9K_INT_SWBA | 361 ATH9K_INT_BMISS | 362 ATH9K_INT_GPIO, 363 ATH9K_INT_NOCARD = 0xffffffff 364 }; 365 366 #define CHANNEL_CW_INT 0x00002 367 #define CHANNEL_CCK 0x00020 368 #define CHANNEL_OFDM 0x00040 369 #define CHANNEL_2GHZ 0x00080 370 #define CHANNEL_5GHZ 0x00100 371 #define CHANNEL_PASSIVE 0x00200 372 #define CHANNEL_DYN 0x00400 373 #define CHANNEL_HALF 0x04000 374 #define CHANNEL_QUARTER 0x08000 375 #define CHANNEL_HT20 0x10000 376 #define CHANNEL_HT40PLUS 0x20000 377 #define CHANNEL_HT40MINUS 0x40000 378 379 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 380 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 381 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 382 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 383 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 384 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 385 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 386 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 387 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 388 #define CHANNEL_ALL \ 389 (CHANNEL_OFDM| \ 390 CHANNEL_CCK| \ 391 CHANNEL_2GHZ | \ 392 CHANNEL_5GHZ | \ 393 CHANNEL_HT20 | \ 394 CHANNEL_HT40PLUS | \ 395 CHANNEL_HT40MINUS) 396 397 #define MAX_RTT_TABLE_ENTRY 6 398 #define MAX_IQCAL_MEASUREMENT 8 399 #define MAX_CL_TAB_ENTRY 16 400 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) 401 402 struct ath9k_hw_cal_data { 403 u16 channel; 404 u32 channelFlags; 405 u32 chanmode; 406 int32_t CalValid; 407 int8_t iCoff; 408 int8_t qCoff; 409 bool rtt_done; 410 bool paprd_packet_sent; 411 bool paprd_done; 412 bool nfcal_pending; 413 bool nfcal_interference; 414 bool done_txiqcal_once; 415 bool done_txclcal_once; 416 u16 small_signal_gain[AR9300_MAX_CHAINS]; 417 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; 418 u32 num_measures[AR9300_MAX_CHAINS]; 419 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; 420 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; 421 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; 422 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 423 }; 424 425 struct ath9k_channel { 426 struct ieee80211_channel *chan; 427 struct ar5416AniState ani; 428 u16 channel; 429 u32 channelFlags; 430 u32 chanmode; 431 s16 noisefloor; 432 }; 433 434 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 435 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 436 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 437 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 438 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 439 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 440 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 441 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 442 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 443 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 444 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 445 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 446 447 /* These macros check chanmode and not channelFlags */ 448 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 449 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 450 ((_c)->chanmode == CHANNEL_G_HT20)) 451 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 452 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 453 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 454 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 455 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 456 457 enum ath9k_power_mode { 458 ATH9K_PM_AWAKE = 0, 459 ATH9K_PM_FULL_SLEEP, 460 ATH9K_PM_NETWORK_SLEEP, 461 ATH9K_PM_UNDEFINED 462 }; 463 464 enum ser_reg_mode { 465 SER_REG_MODE_OFF = 0, 466 SER_REG_MODE_ON = 1, 467 SER_REG_MODE_AUTO = 2, 468 }; 469 470 enum ath9k_rx_qtype { 471 ATH9K_RX_QUEUE_HP, 472 ATH9K_RX_QUEUE_LP, 473 ATH9K_RX_QUEUE_MAX, 474 }; 475 476 struct ath9k_beacon_state { 477 u32 bs_nexttbtt; 478 u32 bs_nextdtim; 479 u32 bs_intval; 480 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 481 u32 bs_dtimperiod; 482 u16 bs_cfpperiod; 483 u16 bs_cfpmaxduration; 484 u32 bs_cfpnext; 485 u16 bs_timoffset; 486 u16 bs_bmissthreshold; 487 u32 bs_sleepduration; 488 u32 bs_tsfoor_threshold; 489 }; 490 491 struct chan_centers { 492 u16 synth_center; 493 u16 ctl_center; 494 u16 ext_center; 495 }; 496 497 enum { 498 ATH9K_RESET_POWER_ON, 499 ATH9K_RESET_WARM, 500 ATH9K_RESET_COLD, 501 }; 502 503 struct ath9k_hw_version { 504 u32 magic; 505 u16 devid; 506 u16 subvendorid; 507 u32 macVersion; 508 u16 macRev; 509 u16 phyRev; 510 u16 analog5GhzRev; 511 u16 analog2GhzRev; 512 enum ath_usb_dev usbdev; 513 }; 514 515 /* Generic TSF timer definitions */ 516 517 #define ATH_MAX_GEN_TIMER 16 518 519 #define AR_GENTMR_BIT(_index) (1 << (_index)) 520 521 /* 522 * Using de Bruijin sequence to look up 1's index in a 32 bit number 523 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 524 */ 525 #define debruijn32 0x077CB531U 526 527 struct ath_gen_timer_configuration { 528 u32 next_addr; 529 u32 period_addr; 530 u32 mode_addr; 531 u32 mode_mask; 532 }; 533 534 struct ath_gen_timer { 535 void (*trigger)(void *arg); 536 void (*overflow)(void *arg); 537 void *arg; 538 u8 index; 539 }; 540 541 struct ath_gen_timer_table { 542 u32 gen_timer_index[32]; 543 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 544 union { 545 unsigned long timer_bits; 546 u16 val; 547 } timer_mask; 548 }; 549 550 struct ath_hw_antcomb_conf { 551 u8 main_lna_conf; 552 u8 alt_lna_conf; 553 u8 fast_div_bias; 554 u8 main_gaintb; 555 u8 alt_gaintb; 556 int lna1_lna2_delta; 557 u8 div_group; 558 }; 559 560 /** 561 * struct ath_hw_radar_conf - radar detection initialization parameters 562 * 563 * @pulse_inband: threshold for checking the ratio of in-band power 564 * to total power for short radar pulses (half dB steps) 565 * @pulse_inband_step: threshold for checking an in-band power to total 566 * power ratio increase for short radar pulses (half dB steps) 567 * @pulse_height: threshold for detecting the beginning of a short 568 * radar pulse (dB step) 569 * @pulse_rssi: threshold for detecting if a short radar pulse is 570 * gone (dB step) 571 * @pulse_maxlen: maximum pulse length (0.8 us steps) 572 * 573 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) 574 * @radar_inband: threshold for checking the ratio of in-band power 575 * to total power for long radar pulses (half dB steps) 576 * @fir_power: threshold for detecting the end of a long radar pulse (dB) 577 * 578 * @ext_channel: enable extension channel radar detection 579 */ 580 struct ath_hw_radar_conf { 581 unsigned int pulse_inband; 582 unsigned int pulse_inband_step; 583 unsigned int pulse_height; 584 unsigned int pulse_rssi; 585 unsigned int pulse_maxlen; 586 587 unsigned int radar_rssi; 588 unsigned int radar_inband; 589 int fir_power; 590 591 bool ext_channel; 592 }; 593 594 /** 595 * struct ath_hw_private_ops - callbacks used internally by hardware code 596 * 597 * This structure contains private callbacks designed to only be used internally 598 * by the hardware core. 599 * 600 * @init_cal_settings: setup types of calibrations supported 601 * @init_cal: starts actual calibration 602 * 603 * @init_mode_gain_regs: Initialize TX/RX gain registers 604 * 605 * @rf_set_freq: change frequency 606 * @spur_mitigate_freq: spur mitigation 607 * @set_rf_regs: 608 * @compute_pll_control: compute the PLL control value to use for 609 * AR_RTC_PLL_CONTROL for a given channel 610 * @setup_calibration: set up calibration 611 * @iscal_supported: used to query if a type of calibration is supported 612 * 613 * @ani_cache_ini_regs: cache the values for ANI from the initial 614 * register settings through the register initialization. 615 */ 616 struct ath_hw_private_ops { 617 /* Calibration ops */ 618 void (*init_cal_settings)(struct ath_hw *ah); 619 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 620 621 void (*init_mode_gain_regs)(struct ath_hw *ah); 622 void (*setup_calibration)(struct ath_hw *ah, 623 struct ath9k_cal_list *currCal); 624 625 /* PHY ops */ 626 int (*rf_set_freq)(struct ath_hw *ah, 627 struct ath9k_channel *chan); 628 void (*spur_mitigate_freq)(struct ath_hw *ah, 629 struct ath9k_channel *chan); 630 bool (*set_rf_regs)(struct ath_hw *ah, 631 struct ath9k_channel *chan, 632 u16 modesIndex); 633 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 634 void (*init_bb)(struct ath_hw *ah, 635 struct ath9k_channel *chan); 636 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 637 void (*olc_init)(struct ath_hw *ah); 638 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 639 void (*mark_phy_inactive)(struct ath_hw *ah); 640 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 641 bool (*rfbus_req)(struct ath_hw *ah); 642 void (*rfbus_done)(struct ath_hw *ah); 643 void (*restore_chainmask)(struct ath_hw *ah); 644 u32 (*compute_pll_control)(struct ath_hw *ah, 645 struct ath9k_channel *chan); 646 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 647 int param); 648 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 649 void (*set_radar_params)(struct ath_hw *ah, 650 struct ath_hw_radar_conf *conf); 651 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, 652 u8 *ini_reloaded); 653 654 /* ANI */ 655 void (*ani_cache_ini_regs)(struct ath_hw *ah); 656 }; 657 658 /** 659 * struct ath_spec_scan - parameters for Atheros spectral scan 660 * 661 * @enabled: enable/disable spectral scan 662 * @short_repeat: controls whether the chip is in spectral scan mode 663 * for 4 usec (enabled) or 204 usec (disabled) 664 * @count: number of scan results requested. There are special meanings 665 * in some chip revisions: 666 * AR92xx: highest bit set (>=128) for endless mode 667 * (spectral scan won't stopped until explicitly disabled) 668 * AR9300 and newer: 0 for endless mode 669 * @endless: true if endless mode is intended. Otherwise, count value is 670 * corrected to the next possible value. 671 * @period: time duration between successive spectral scan entry points 672 * (period*256*Tclk). Tclk = ath_common->clockrate 673 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS 674 * 675 * Note: Tclk = 40MHz or 44MHz depending upon operating mode. 676 * Typically it's 44MHz in 2/5GHz on later chips, but there's 677 * a "fast clock" check for this in 5GHz. 678 * 679 */ 680 struct ath_spec_scan { 681 bool enabled; 682 bool short_repeat; 683 bool endless; 684 u8 count; 685 u8 period; 686 u8 fft_period; 687 }; 688 689 /** 690 * struct ath_hw_ops - callbacks used by hardware code and driver code 691 * 692 * This structure contains callbacks designed to to be used internally by 693 * hardware code and also by the lower level driver. 694 * 695 * @config_pci_powersave: 696 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 697 * 698 * @spectral_scan_config: set parameters for spectral scan and enable/disable it 699 * @spectral_scan_trigger: trigger a spectral scan run 700 * @spectral_scan_wait: wait for a spectral scan run to finish 701 */ 702 struct ath_hw_ops { 703 void (*config_pci_powersave)(struct ath_hw *ah, 704 bool power_off); 705 void (*rx_enable)(struct ath_hw *ah); 706 void (*set_desc_link)(void *ds, u32 link); 707 bool (*calibrate)(struct ath_hw *ah, 708 struct ath9k_channel *chan, 709 u8 rxchainmask, 710 bool longcal); 711 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 712 void (*set_txdesc)(struct ath_hw *ah, void *ds, 713 struct ath_tx_info *i); 714 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 715 struct ath_tx_status *ts); 716 void (*antdiv_comb_conf_get)(struct ath_hw *ah, 717 struct ath_hw_antcomb_conf *antconf); 718 void (*antdiv_comb_conf_set)(struct ath_hw *ah, 719 struct ath_hw_antcomb_conf *antconf); 720 void (*antctrl_shared_chain_lnadiv)(struct ath_hw *hw, bool enable); 721 void (*spectral_scan_config)(struct ath_hw *ah, 722 struct ath_spec_scan *param); 723 void (*spectral_scan_trigger)(struct ath_hw *ah); 724 void (*spectral_scan_wait)(struct ath_hw *ah); 725 }; 726 727 struct ath_nf_limits { 728 s16 max; 729 s16 min; 730 s16 nominal; 731 }; 732 733 enum ath_cal_list { 734 TX_IQ_CAL = BIT(0), 735 TX_IQ_ON_AGC_CAL = BIT(1), 736 TX_CL_CAL = BIT(2), 737 }; 738 739 /* ah_flags */ 740 #define AH_USE_EEPROM 0x1 741 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ 742 #define AH_FASTCC 0x4 743 744 struct ath_hw { 745 struct ath_ops reg_ops; 746 747 struct device *dev; 748 struct ieee80211_hw *hw; 749 struct ath_common common; 750 struct ath9k_hw_version hw_version; 751 struct ath9k_ops_config config; 752 struct ath9k_hw_capabilities caps; 753 struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; 754 struct ath9k_channel *curchan; 755 756 union { 757 struct ar5416_eeprom_def def; 758 struct ar5416_eeprom_4k map4k; 759 struct ar9287_eeprom map9287; 760 struct ar9300_eeprom ar9300_eep; 761 } eeprom; 762 const struct eeprom_ops *eep_ops; 763 764 bool sw_mgmt_crypto; 765 bool is_pciexpress; 766 bool aspm_enabled; 767 bool is_monitoring; 768 bool need_an_top2_fixup; 769 bool shared_chain_lnadiv; 770 u16 tx_trig_level; 771 772 u32 nf_regs[6]; 773 struct ath_nf_limits nf_2g; 774 struct ath_nf_limits nf_5g; 775 u16 rfsilent; 776 u32 rfkill_gpio; 777 u32 rfkill_polarity; 778 u32 ah_flags; 779 780 bool reset_power_on; 781 bool htc_reset_init; 782 783 enum nl80211_iftype opmode; 784 enum ath9k_power_mode power_mode; 785 786 s8 noise; 787 struct ath9k_hw_cal_data *caldata; 788 struct ath9k_pacal_info pacal_info; 789 struct ar5416Stats stats; 790 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 791 792 enum ath9k_int imask; 793 u32 imrs2_reg; 794 u32 txok_interrupt_mask; 795 u32 txerr_interrupt_mask; 796 u32 txdesc_interrupt_mask; 797 u32 txeol_interrupt_mask; 798 u32 txurn_interrupt_mask; 799 atomic_t intr_ref_cnt; 800 bool chip_fullsleep; 801 u32 atim_window; 802 u32 modes_index; 803 804 /* Calibration */ 805 u32 supp_cals; 806 struct ath9k_cal_list iq_caldata; 807 struct ath9k_cal_list adcgain_caldata; 808 struct ath9k_cal_list adcdc_caldata; 809 struct ath9k_cal_list *cal_list; 810 struct ath9k_cal_list *cal_list_last; 811 struct ath9k_cal_list *cal_list_curr; 812 #define totalPowerMeasI meas0.unsign 813 #define totalPowerMeasQ meas1.unsign 814 #define totalIqCorrMeas meas2.sign 815 #define totalAdcIOddPhase meas0.unsign 816 #define totalAdcIEvenPhase meas1.unsign 817 #define totalAdcQOddPhase meas2.unsign 818 #define totalAdcQEvenPhase meas3.unsign 819 #define totalAdcDcOffsetIOddPhase meas0.sign 820 #define totalAdcDcOffsetIEvenPhase meas1.sign 821 #define totalAdcDcOffsetQOddPhase meas2.sign 822 #define totalAdcDcOffsetQEvenPhase meas3.sign 823 union { 824 u32 unsign[AR5416_MAX_CHAINS]; 825 int32_t sign[AR5416_MAX_CHAINS]; 826 } meas0; 827 union { 828 u32 unsign[AR5416_MAX_CHAINS]; 829 int32_t sign[AR5416_MAX_CHAINS]; 830 } meas1; 831 union { 832 u32 unsign[AR5416_MAX_CHAINS]; 833 int32_t sign[AR5416_MAX_CHAINS]; 834 } meas2; 835 union { 836 u32 unsign[AR5416_MAX_CHAINS]; 837 int32_t sign[AR5416_MAX_CHAINS]; 838 } meas3; 839 u16 cal_samples; 840 u8 enabled_cals; 841 842 u32 sta_id1_defaults; 843 u32 misc_mode; 844 845 /* Private to hardware code */ 846 struct ath_hw_private_ops private_ops; 847 /* Accessed by the lower level driver */ 848 struct ath_hw_ops ops; 849 850 /* Used to program the radio on non single-chip devices */ 851 u32 *analogBank0Data; 852 u32 *analogBank1Data; 853 u32 *analogBank2Data; 854 u32 *analogBank3Data; 855 u32 *analogBank6Data; 856 u32 *analogBank6TPCData; 857 u32 *analogBank7Data; 858 u32 *bank6Temp; 859 860 int coverage_class; 861 u32 slottime; 862 u32 globaltxtimeout; 863 864 /* ANI */ 865 u32 proc_phyerr; 866 u32 aniperiod; 867 enum ath9k_ani_cmd ani_function; 868 u32 ani_skip_count; 869 870 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 871 struct ath_btcoex_hw btcoex_hw; 872 #endif 873 874 u32 intr_txqs; 875 u8 txchainmask; 876 u8 rxchainmask; 877 878 struct ath_hw_radar_conf radar_conf; 879 880 u32 originalGain[22]; 881 int initPDADC; 882 int PDADCdelta; 883 int led_pin; 884 u32 gpio_mask; 885 u32 gpio_val; 886 887 struct ar5416IniArray iniModes; 888 struct ar5416IniArray iniCommon; 889 struct ar5416IniArray iniBank0; 890 struct ar5416IniArray iniBB_RfGain; 891 struct ar5416IniArray iniBank1; 892 struct ar5416IniArray iniBank2; 893 struct ar5416IniArray iniBank3; 894 struct ar5416IniArray iniBank6; 895 struct ar5416IniArray iniBank6TPC; 896 struct ar5416IniArray iniBank7; 897 struct ar5416IniArray iniAddac; 898 struct ar5416IniArray iniPcieSerdes; 899 #ifdef CONFIG_PM_SLEEP 900 struct ar5416IniArray iniPcieSerdesWow; 901 #endif 902 struct ar5416IniArray iniPcieSerdesLowPower; 903 struct ar5416IniArray iniModesFastClock; 904 struct ar5416IniArray iniAdditional; 905 struct ar5416IniArray iniModesRxGain; 906 struct ar5416IniArray ini_modes_rx_gain_bounds; 907 struct ar5416IniArray iniModesTxGain; 908 struct ar5416IniArray iniCckfirNormal; 909 struct ar5416IniArray iniCckfirJapan2484; 910 struct ar5416IniArray iniModes_9271_ANI_reg; 911 struct ar5416IniArray ini_radio_post_sys2ant; 912 913 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 914 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 915 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 916 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 917 918 u32 intr_gen_timer_trigger; 919 u32 intr_gen_timer_thresh; 920 struct ath_gen_timer_table hw_gen_timers; 921 922 struct ar9003_txs *ts_ring; 923 u32 ts_paddr_start; 924 u32 ts_paddr_end; 925 u16 ts_tail; 926 u16 ts_size; 927 928 u32 bb_watchdog_last_status; 929 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 930 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ 931 932 unsigned int paprd_target_power; 933 unsigned int paprd_training_power; 934 unsigned int paprd_ratemask; 935 unsigned int paprd_ratemask_ht40; 936 bool paprd_table_write_done; 937 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; 938 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; 939 /* 940 * Store the permanent value of Reg 0x4004in WARegVal 941 * so we dont have to R/M/W. We should not be reading 942 * this register when in sleep states. 943 */ 944 u32 WARegVal; 945 946 /* Enterprise mode cap */ 947 u32 ent_mode; 948 949 #ifdef CONFIG_PM_SLEEP 950 u32 wow_event_mask; 951 #endif 952 bool is_clk_25mhz; 953 int (*get_mac_revision)(void); 954 int (*external_reset)(void); 955 956 const struct firmware *eeprom_blob; 957 }; 958 959 struct ath_bus_ops { 960 enum ath_bus_type ath_bus_type; 961 void (*read_cachesize)(struct ath_common *common, int *csz); 962 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); 963 void (*bt_coex_prep)(struct ath_common *common); 964 void (*aspm_init)(struct ath_common *common); 965 }; 966 967 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 968 { 969 return &ah->common; 970 } 971 972 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 973 { 974 return &(ath9k_hw_common(ah)->regulatory); 975 } 976 977 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 978 { 979 return &ah->private_ops; 980 } 981 982 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 983 { 984 return &ah->ops; 985 } 986 987 static inline u8 get_streams(int mask) 988 { 989 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); 990 } 991 992 /* Initialization, Detach, Reset */ 993 void ath9k_hw_deinit(struct ath_hw *ah); 994 int ath9k_hw_init(struct ath_hw *ah); 995 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 996 struct ath9k_hw_cal_data *caldata, bool fastcc); 997 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 998 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 999 1000 /* GPIO / RFKILL / Antennae */ 1001 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 1002 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 1003 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 1004 u32 ah_signal_type); 1005 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 1006 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 1007 1008 /* General Operation */ 1009 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 1010 int hw_delay); 1011 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 1012 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 1013 int column, unsigned int *writecnt); 1014 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 1015 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 1016 u8 phy, int kbps, 1017 u32 frameLen, u16 rateix, bool shortPreamble); 1018 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 1019 struct ath9k_channel *chan, 1020 struct chan_centers *centers); 1021 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 1022 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 1023 bool ath9k_hw_phy_disable(struct ath_hw *ah); 1024 bool ath9k_hw_disable(struct ath_hw *ah); 1025 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); 1026 void ath9k_hw_setopmode(struct ath_hw *ah); 1027 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 1028 void ath9k_hw_write_associd(struct ath_hw *ah); 1029 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 1030 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 1031 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 1032 void ath9k_hw_reset_tsf(struct ath_hw *ah); 1033 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); 1034 void ath9k_hw_init_global_settings(struct ath_hw *ah); 1035 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); 1036 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 1037 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 1038 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1039 const struct ath9k_beacon_state *bs); 1040 bool ath9k_hw_check_alive(struct ath_hw *ah); 1041 1042 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 1043 1044 #ifdef CONFIG_ATH9K_DEBUGFS 1045 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause); 1046 #else 1047 static inline void ath9k_debug_sync_cause(struct ath_common *common, 1048 u32 sync_cause) {} 1049 #endif 1050 1051 /* Generic hw timer primitives */ 1052 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 1053 void (*trigger)(void *), 1054 void (*overflow)(void *), 1055 void *arg, 1056 u8 timer_index); 1057 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 1058 struct ath_gen_timer *timer, 1059 u32 timer_next, 1060 u32 timer_period); 1061 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 1062 1063 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 1064 void ath_gen_timer_isr(struct ath_hw *hw); 1065 1066 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 1067 1068 /* PHY */ 1069 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1070 u32 *coef_mantissa, u32 *coef_exponent); 1071 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 1072 bool test); 1073 1074 /* 1075 * Code Specific to AR5008, AR9001 or AR9002, 1076 * we stuff these here to avoid callbacks for AR9003. 1077 */ 1078 int ar9002_hw_rf_claim(struct ath_hw *ah); 1079 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 1080 1081 /* 1082 * Code specific to AR9003, we stuff these here to avoid callbacks 1083 * for older families 1084 */ 1085 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 1086 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 1087 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 1088 void ar9003_hw_disable_phy_restart(struct ath_hw *ah); 1089 void ar9003_paprd_enable(struct ath_hw *ah, bool val); 1090 void ar9003_paprd_populate_single_table(struct ath_hw *ah, 1091 struct ath9k_hw_cal_data *caldata, 1092 int chain); 1093 int ar9003_paprd_create_curve(struct ath_hw *ah, 1094 struct ath9k_hw_cal_data *caldata, int chain); 1095 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); 1096 int ar9003_paprd_init_table(struct ath_hw *ah); 1097 bool ar9003_paprd_is_done(struct ath_hw *ah); 1098 bool ar9003_is_paprd_enabled(struct ath_hw *ah); 1099 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1100 1101 /* Hardware family op attach helpers */ 1102 int ar5008_hw_attach_phy_ops(struct ath_hw *ah); 1103 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 1104 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 1105 1106 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 1107 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 1108 1109 int ar9002_hw_attach_ops(struct ath_hw *ah); 1110 void ar9003_hw_attach_ops(struct ath_hw *ah); 1111 1112 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); 1113 1114 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); 1115 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); 1116 1117 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 1118 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1119 { 1120 return ah->btcoex_hw.enabled; 1121 } 1122 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1123 { 1124 return ah->common.btcoex_enabled && 1125 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); 1126 1127 } 1128 void ath9k_hw_btcoex_enable(struct ath_hw *ah); 1129 static inline enum ath_btcoex_scheme 1130 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1131 { 1132 return ah->btcoex_hw.scheme; 1133 } 1134 #else 1135 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) 1136 { 1137 return false; 1138 } 1139 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) 1140 { 1141 return false; 1142 } 1143 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) 1144 { 1145 } 1146 static inline enum ath_btcoex_scheme 1147 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) 1148 { 1149 return ATH_BTCOEX_CFG_NONE; 1150 } 1151 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 1152 1153 1154 #ifdef CONFIG_PM_SLEEP 1155 const char *ath9k_hw_wow_event_to_string(u32 wow_event); 1156 void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, 1157 u8 *user_mask, int pattern_count, 1158 int pattern_len); 1159 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); 1160 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); 1161 #else 1162 static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) 1163 { 1164 return NULL; 1165 } 1166 static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, 1167 u8 *user_pattern, 1168 u8 *user_mask, 1169 int pattern_count, 1170 int pattern_len) 1171 { 1172 } 1173 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) 1174 { 1175 return 0; 1176 } 1177 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) 1178 { 1179 } 1180 #endif 1181 1182 1183 1184 #define ATH9K_CLOCK_RATE_CCK 22 1185 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 1186 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 1187 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 1188 1189 #endif 1190