1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <linux/time.h> 21 #include <linux/bitops.h> 22 #include <linux/etherdevice.h> 23 #include <linux/gpio.h> 24 #include <asm/unaligned.h> 25 26 #include "hw.h" 27 #include "hw-ops.h" 28 #include "ar9003_mac.h" 29 #include "ar9003_mci.h" 30 #include "ar9003_phy.h" 31 #include "ath9k.h" 32 33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 34 35 MODULE_AUTHOR("Atheros Communications"); 36 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 37 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 38 MODULE_LICENSE("Dual BSD/GPL"); 39 40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 41 { 42 struct ath_common *common = ath9k_hw_common(ah); 43 struct ath9k_channel *chan = ah->curchan; 44 unsigned int clockrate; 45 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 48 clockrate = 117; 49 else if (!chan) /* should really check for CCK instead */ 50 clockrate = ATH9K_CLOCK_RATE_CCK; 51 else if (IS_CHAN_2GHZ(chan)) 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 55 else 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 57 58 if (chan) { 59 if (IS_CHAN_HT40(chan)) 60 clockrate *= 2; 61 if (IS_CHAN_HALF_RATE(chan)) 62 clockrate /= 2; 63 if (IS_CHAN_QUARTER_RATE(chan)) 64 clockrate /= 4; 65 } 66 67 common->clockrate = clockrate; 68 } 69 70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 71 { 72 struct ath_common *common = ath9k_hw_common(ah); 73 74 return usecs * common->clockrate; 75 } 76 77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 78 { 79 int i; 80 81 BUG_ON(timeout < AH_TIME_QUANTUM); 82 83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 84 if ((REG_READ(ah, reg) & mask) == val) 85 return true; 86 87 udelay(AH_TIME_QUANTUM); 88 } 89 90 ath_dbg(ath9k_hw_common(ah), ANY, 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 92 timeout, reg, REG_READ(ah, reg), mask, val); 93 94 return false; 95 } 96 EXPORT_SYMBOL(ath9k_hw_wait); 97 98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 99 int hw_delay) 100 { 101 hw_delay /= 10; 102 103 if (IS_CHAN_HALF_RATE(chan)) 104 hw_delay *= 2; 105 else if (IS_CHAN_QUARTER_RATE(chan)) 106 hw_delay *= 4; 107 108 udelay(hw_delay + BASE_ACTIVATE_DELAY); 109 } 110 111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 112 int column, unsigned int *writecnt) 113 { 114 int r; 115 116 ENABLE_REGWRITE_BUFFER(ah); 117 for (r = 0; r < array->ia_rows; r++) { 118 REG_WRITE(ah, INI_RA(array, r, 0), 119 INI_RA(array, r, column)); 120 DO_DELAY(*writecnt); 121 } 122 REGWRITE_BUFFER_FLUSH(ah); 123 } 124 125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) 126 { 127 u32 *tmp_reg_list, *tmp_data; 128 int i; 129 130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL); 131 if (!tmp_reg_list) { 132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); 133 return; 134 } 135 136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL); 137 if (!tmp_data) { 138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); 139 goto error_tmp_data; 140 } 141 142 for (i = 0; i < size; i++) 143 tmp_reg_list[i] = array[i][0]; 144 145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); 146 147 for (i = 0; i < size; i++) 148 array[i][1] = tmp_data[i]; 149 150 kfree(tmp_data); 151 error_tmp_data: 152 kfree(tmp_reg_list); 153 } 154 155 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 156 { 157 u32 retval; 158 int i; 159 160 for (i = 0, retval = 0; i < n; i++) { 161 retval = (retval << 1) | (val & 1); 162 val >>= 1; 163 } 164 return retval; 165 } 166 167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 168 u8 phy, int kbps, 169 u32 frameLen, u16 rateix, 170 bool shortPreamble) 171 { 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 173 174 if (kbps == 0) 175 return 0; 176 177 switch (phy) { 178 case WLAN_RC_PHY_CCK: 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 180 if (shortPreamble) 181 phyTime >>= 1; 182 numBits = frameLen << 3; 183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 184 break; 185 case WLAN_RC_PHY_OFDM: 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 187 bitsPerSymbol = 188 ((kbps >> 2) * OFDM_SYMBOL_TIME_QUARTER) / 1000; 189 numBits = OFDM_PLCP_BITS + (frameLen << 3); 190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 191 txTime = OFDM_SIFS_TIME_QUARTER 192 + OFDM_PREAMBLE_TIME_QUARTER 193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 194 } else if (ah->curchan && 195 IS_CHAN_HALF_RATE(ah->curchan)) { 196 bitsPerSymbol = 197 ((kbps >> 1) * OFDM_SYMBOL_TIME_HALF) / 1000; 198 numBits = OFDM_PLCP_BITS + (frameLen << 3); 199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 200 txTime = OFDM_SIFS_TIME_HALF + 201 OFDM_PREAMBLE_TIME_HALF 202 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 203 } else { 204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 205 numBits = OFDM_PLCP_BITS + (frameLen << 3); 206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 208 + (numSymbols * OFDM_SYMBOL_TIME); 209 } 210 break; 211 default: 212 ath_err(ath9k_hw_common(ah), 213 "Unknown phy %u (rate ix %u)\n", phy, rateix); 214 txTime = 0; 215 break; 216 } 217 218 return txTime; 219 } 220 EXPORT_SYMBOL(ath9k_hw_computetxtime); 221 222 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 223 struct ath9k_channel *chan, 224 struct chan_centers *centers) 225 { 226 int8_t extoff; 227 228 if (!IS_CHAN_HT40(chan)) { 229 centers->ctl_center = centers->ext_center = 230 centers->synth_center = chan->channel; 231 return; 232 } 233 234 if (IS_CHAN_HT40PLUS(chan)) { 235 centers->synth_center = 236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 237 extoff = 1; 238 } else { 239 centers->synth_center = 240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 241 extoff = -1; 242 } 243 244 centers->ctl_center = 245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 246 /* 25 MHz spacing is supported by hw but not on upper layers */ 247 centers->ext_center = 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 249 } 250 251 /******************/ 252 /* Chip Revisions */ 253 /******************/ 254 255 static void ath9k_hw_read_revisions(struct ath_hw *ah) 256 { 257 u32 val; 258 259 if (ah->get_mac_revision) 260 ah->hw_version.macRev = ah->get_mac_revision(); 261 262 switch (ah->hw_version.devid) { 263 case AR5416_AR9100_DEVID: 264 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 265 break; 266 case AR9300_DEVID_AR9330: 267 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 268 if (!ah->get_mac_revision) { 269 val = REG_READ(ah, AR_SREV); 270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 271 } 272 return; 273 case AR9300_DEVID_AR9340: 274 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 275 return; 276 case AR9300_DEVID_QCA955X: 277 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 278 return; 279 case AR9300_DEVID_AR953X: 280 ah->hw_version.macVersion = AR_SREV_VERSION_9531; 281 return; 282 case AR9300_DEVID_QCA956X: 283 ah->hw_version.macVersion = AR_SREV_VERSION_9561; 284 return; 285 } 286 287 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 288 289 if (val == 0xFF) { 290 val = REG_READ(ah, AR_SREV); 291 ah->hw_version.macVersion = 292 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 293 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 294 295 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 296 ah->is_pciexpress = true; 297 else 298 ah->is_pciexpress = (val & 299 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 300 } else { 301 if (!AR_SREV_9100(ah)) 302 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 303 304 ah->hw_version.macRev = val & AR_SREV_REVISION; 305 306 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 307 ah->is_pciexpress = true; 308 } 309 } 310 311 /************************************/ 312 /* HW Attach, Detach, Init Routines */ 313 /************************************/ 314 315 static void ath9k_hw_disablepcie(struct ath_hw *ah) 316 { 317 if (!AR_SREV_5416(ah)) 318 return; 319 320 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 321 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 322 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 323 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 324 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 325 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 326 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 327 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 328 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 329 330 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 331 } 332 333 /* This should work for all families including legacy */ 334 static bool ath9k_hw_chip_test(struct ath_hw *ah) 335 { 336 struct ath_common *common = ath9k_hw_common(ah); 337 u32 regAddr[2] = { AR_STA_ID0 }; 338 u32 regHold[2]; 339 static const u32 patternData[4] = { 340 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 341 }; 342 int i, j, loop_max; 343 344 if (!AR_SREV_9300_20_OR_LATER(ah)) { 345 loop_max = 2; 346 regAddr[1] = AR_PHY_BASE + (8 << 2); 347 } else 348 loop_max = 1; 349 350 for (i = 0; i < loop_max; i++) { 351 u32 addr = regAddr[i]; 352 u32 wrData, rdData; 353 354 regHold[i] = REG_READ(ah, addr); 355 for (j = 0; j < 0x100; j++) { 356 wrData = (j << 16) | j; 357 REG_WRITE(ah, addr, wrData); 358 rdData = REG_READ(ah, addr); 359 if (rdData != wrData) { 360 ath_err(common, 361 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 362 addr, wrData, rdData); 363 return false; 364 } 365 } 366 for (j = 0; j < 4; j++) { 367 wrData = patternData[j]; 368 REG_WRITE(ah, addr, wrData); 369 rdData = REG_READ(ah, addr); 370 if (wrData != rdData) { 371 ath_err(common, 372 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 373 addr, wrData, rdData); 374 return false; 375 } 376 } 377 REG_WRITE(ah, regAddr[i], regHold[i]); 378 } 379 udelay(100); 380 381 return true; 382 } 383 384 static void ath9k_hw_init_config(struct ath_hw *ah) 385 { 386 struct ath_common *common = ath9k_hw_common(ah); 387 388 ah->config.dma_beacon_response_time = 1; 389 ah->config.sw_beacon_response_time = 6; 390 ah->config.cwm_ignore_extcca = false; 391 ah->config.analog_shiftreg = 1; 392 393 ah->config.rx_intr_mitigation = true; 394 395 if (AR_SREV_9300_20_OR_LATER(ah)) { 396 ah->config.rimt_last = 500; 397 ah->config.rimt_first = 2000; 398 } else { 399 ah->config.rimt_last = 250; 400 ah->config.rimt_first = 700; 401 } 402 403 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 404 ah->config.pll_pwrsave = 7; 405 406 /* 407 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 408 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 409 * This means we use it for all AR5416 devices, and the few 410 * minor PCI AR9280 devices out there. 411 * 412 * Serialization is required because these devices do not handle 413 * well the case of two concurrent reads/writes due to the latency 414 * involved. During one read/write another read/write can be issued 415 * on another CPU while the previous read/write may still be working 416 * on our hardware, if we hit this case the hardware poops in a loop. 417 * We prevent this by serializing reads and writes. 418 * 419 * This issue is not present on PCI-Express devices or pre-AR5416 420 * devices (legacy, 802.11abg). 421 */ 422 if (num_possible_cpus() > 1) 423 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 424 425 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 426 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 427 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 428 !ah->is_pciexpress)) { 429 ah->config.serialize_regmode = SER_REG_MODE_ON; 430 } else { 431 ah->config.serialize_regmode = SER_REG_MODE_OFF; 432 } 433 } 434 435 ath_dbg(common, RESET, "serialize_regmode is %d\n", 436 ah->config.serialize_regmode); 437 438 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 440 else 441 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 442 } 443 444 static void ath9k_hw_init_defaults(struct ath_hw *ah) 445 { 446 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 447 448 regulatory->country_code = CTRY_DEFAULT; 449 regulatory->power_limit = MAX_RATE_POWER; 450 451 ah->hw_version.magic = AR5416_MAGIC; 452 ah->hw_version.subvendorid = 0; 453 454 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | 455 AR_STA_ID1_MCAST_KSRCH; 456 if (AR_SREV_9100(ah)) 457 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 458 459 ah->slottime = 9; 460 ah->globaltxtimeout = (u32) -1; 461 ah->power_mode = ATH9K_PM_UNDEFINED; 462 ah->htc_reset_init = true; 463 464 ah->tpc_enabled = false; 465 466 ah->ani_function = ATH9K_ANI_ALL; 467 if (!AR_SREV_9300_20_OR_LATER(ah)) 468 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 469 470 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 471 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 472 else 473 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 474 } 475 476 static void ath9k_hw_init_macaddr(struct ath_hw *ah) 477 { 478 struct ath_common *common = ath9k_hw_common(ah); 479 int i; 480 u16 eeval; 481 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 482 483 /* MAC address may already be loaded via ath9k_platform_data */ 484 if (is_valid_ether_addr(common->macaddr)) 485 return; 486 487 for (i = 0; i < 3; i++) { 488 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 489 common->macaddr[2 * i] = eeval >> 8; 490 common->macaddr[2 * i + 1] = eeval & 0xff; 491 } 492 493 if (is_valid_ether_addr(common->macaddr)) 494 return; 495 496 ath_err(common, "eeprom contains invalid mac address: %pM\n", 497 common->macaddr); 498 499 random_ether_addr(common->macaddr); 500 ath_err(common, "random mac address will be used: %pM\n", 501 common->macaddr); 502 503 return; 504 } 505 506 static int ath9k_hw_post_init(struct ath_hw *ah) 507 { 508 struct ath_common *common = ath9k_hw_common(ah); 509 int ecode; 510 511 if (common->bus_ops->ath_bus_type != ATH_USB) { 512 if (!ath9k_hw_chip_test(ah)) 513 return -ENODEV; 514 } 515 516 if (!AR_SREV_9300_20_OR_LATER(ah)) { 517 ecode = ar9002_hw_rf_claim(ah); 518 if (ecode != 0) 519 return ecode; 520 } 521 522 ecode = ath9k_hw_eeprom_init(ah); 523 if (ecode != 0) 524 return ecode; 525 526 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 527 ah->eep_ops->get_eeprom_ver(ah), 528 ah->eep_ops->get_eeprom_rev(ah)); 529 530 ath9k_hw_ani_init(ah); 531 532 /* 533 * EEPROM needs to be initialized before we do this. 534 * This is required for regulatory compliance. 535 */ 536 if (AR_SREV_9300_20_OR_LATER(ah)) { 537 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 538 if ((regdmn & 0xF0) == CTL_FCC) { 539 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; 540 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; 541 } 542 } 543 544 return 0; 545 } 546 547 static int ath9k_hw_attach_ops(struct ath_hw *ah) 548 { 549 if (!AR_SREV_9300_20_OR_LATER(ah)) 550 return ar9002_hw_attach_ops(ah); 551 552 ar9003_hw_attach_ops(ah); 553 return 0; 554 } 555 556 /* Called for all hardware families */ 557 static int __ath9k_hw_init(struct ath_hw *ah) 558 { 559 struct ath_common *common = ath9k_hw_common(ah); 560 int r = 0; 561 562 ath9k_hw_read_revisions(ah); 563 564 switch (ah->hw_version.macVersion) { 565 case AR_SREV_VERSION_5416_PCI: 566 case AR_SREV_VERSION_5416_PCIE: 567 case AR_SREV_VERSION_9160: 568 case AR_SREV_VERSION_9100: 569 case AR_SREV_VERSION_9280: 570 case AR_SREV_VERSION_9285: 571 case AR_SREV_VERSION_9287: 572 case AR_SREV_VERSION_9271: 573 case AR_SREV_VERSION_9300: 574 case AR_SREV_VERSION_9330: 575 case AR_SREV_VERSION_9485: 576 case AR_SREV_VERSION_9340: 577 case AR_SREV_VERSION_9462: 578 case AR_SREV_VERSION_9550: 579 case AR_SREV_VERSION_9565: 580 case AR_SREV_VERSION_9531: 581 case AR_SREV_VERSION_9561: 582 break; 583 default: 584 ath_err(common, 585 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 586 ah->hw_version.macVersion, ah->hw_version.macRev); 587 return -EOPNOTSUPP; 588 } 589 590 /* 591 * Read back AR_WA into a permanent copy and set bits 14 and 17. 592 * We need to do this to avoid RMW of this register. We cannot 593 * read the reg when chip is asleep. 594 */ 595 if (AR_SREV_9300_20_OR_LATER(ah)) { 596 ah->WARegVal = REG_READ(ah, AR_WA); 597 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 598 AR_WA_ASPM_TIMER_BASED_DISABLE); 599 } 600 601 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 602 ath_err(common, "Couldn't reset chip\n"); 603 return -EIO; 604 } 605 606 if (AR_SREV_9565(ah)) { 607 ah->WARegVal |= AR_WA_BIT22; 608 REG_WRITE(ah, AR_WA, ah->WARegVal); 609 } 610 611 ath9k_hw_init_defaults(ah); 612 ath9k_hw_init_config(ah); 613 614 r = ath9k_hw_attach_ops(ah); 615 if (r) 616 return r; 617 618 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 619 ath_err(common, "Couldn't wakeup chip\n"); 620 return -EIO; 621 } 622 623 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 624 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 625 ah->is_pciexpress = false; 626 627 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 628 ath9k_hw_init_cal_settings(ah); 629 630 if (!ah->is_pciexpress) 631 ath9k_hw_disablepcie(ah); 632 633 r = ath9k_hw_post_init(ah); 634 if (r) 635 return r; 636 637 ath9k_hw_init_mode_gain_regs(ah); 638 r = ath9k_hw_fill_cap_info(ah); 639 if (r) 640 return r; 641 642 ath9k_hw_init_macaddr(ah); 643 ath9k_hw_init_hang_checks(ah); 644 645 common->state = ATH_HW_INITIALIZED; 646 647 return 0; 648 } 649 650 int ath9k_hw_init(struct ath_hw *ah) 651 { 652 int ret; 653 struct ath_common *common = ath9k_hw_common(ah); 654 655 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 656 switch (ah->hw_version.devid) { 657 case AR5416_DEVID_PCI: 658 case AR5416_DEVID_PCIE: 659 case AR5416_AR9100_DEVID: 660 case AR9160_DEVID_PCI: 661 case AR9280_DEVID_PCI: 662 case AR9280_DEVID_PCIE: 663 case AR9285_DEVID_PCIE: 664 case AR9287_DEVID_PCI: 665 case AR9287_DEVID_PCIE: 666 case AR2427_DEVID_PCIE: 667 case AR9300_DEVID_PCIE: 668 case AR9300_DEVID_AR9485_PCIE: 669 case AR9300_DEVID_AR9330: 670 case AR9300_DEVID_AR9340: 671 case AR9300_DEVID_QCA955X: 672 case AR9300_DEVID_AR9580: 673 case AR9300_DEVID_AR9462: 674 case AR9485_DEVID_AR1111: 675 case AR9300_DEVID_AR9565: 676 case AR9300_DEVID_AR953X: 677 case AR9300_DEVID_QCA956X: 678 break; 679 default: 680 if (common->bus_ops->ath_bus_type == ATH_USB) 681 break; 682 ath_err(common, "Hardware device ID 0x%04x not supported\n", 683 ah->hw_version.devid); 684 return -EOPNOTSUPP; 685 } 686 687 ret = __ath9k_hw_init(ah); 688 if (ret) { 689 ath_err(common, 690 "Unable to initialize hardware; initialization status: %d\n", 691 ret); 692 return ret; 693 } 694 695 ath_dynack_init(ah); 696 697 return 0; 698 } 699 EXPORT_SYMBOL(ath9k_hw_init); 700 701 static void ath9k_hw_init_qos(struct ath_hw *ah) 702 { 703 ENABLE_REGWRITE_BUFFER(ah); 704 705 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 706 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 707 708 REG_WRITE(ah, AR_QOS_NO_ACK, 709 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 710 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 711 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 712 713 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 714 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 715 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 716 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 717 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 718 719 REGWRITE_BUFFER_FLUSH(ah); 720 } 721 722 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 723 { 724 struct ath_common *common = ath9k_hw_common(ah); 725 int i = 0; 726 727 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 728 udelay(100); 729 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 730 731 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 732 733 udelay(100); 734 735 if (WARN_ON_ONCE(i >= 100)) { 736 ath_err(common, "PLL4 measurement not done\n"); 737 break; 738 } 739 740 i++; 741 } 742 743 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 744 } 745 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 746 747 static void ath9k_hw_init_pll(struct ath_hw *ah, 748 struct ath9k_channel *chan) 749 { 750 u32 pll; 751 752 pll = ath9k_hw_compute_pll_control(ah, chan); 753 754 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 755 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 756 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 757 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 759 AR_CH0_DPLL2_KD, 0x40); 760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 761 AR_CH0_DPLL2_KI, 0x4); 762 763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 764 AR_CH0_BB_DPLL1_REFDIV, 0x5); 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 766 AR_CH0_BB_DPLL1_NINI, 0x58); 767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 768 AR_CH0_BB_DPLL1_NFRAC, 0x0); 769 770 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 771 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 773 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 775 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 776 777 /* program BB PLL phase_shift to 0x6 */ 778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 779 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 780 781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 782 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 783 udelay(1000); 784 } else if (AR_SREV_9330(ah)) { 785 u32 ddr_dpll2, pll_control2, kd; 786 787 if (ah->is_clk_25mhz) { 788 ddr_dpll2 = 0x18e82f01; 789 pll_control2 = 0xe04a3d; 790 kd = 0x1d; 791 } else { 792 ddr_dpll2 = 0x19e82f01; 793 pll_control2 = 0x886666; 794 kd = 0x3d; 795 } 796 797 /* program DDR PLL ki and kd value */ 798 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 799 800 /* program DDR PLL phase_shift */ 801 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 802 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 803 804 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 805 pll | AR_RTC_9300_PLL_BYPASS); 806 udelay(1000); 807 808 /* program refdiv, nint, frac to RTC register */ 809 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 810 811 /* program BB PLL kd and ki value */ 812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 814 815 /* program BB PLL phase_shift */ 816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 817 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 818 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 819 AR_SREV_9561(ah)) { 820 u32 regval, pll2_divint, pll2_divfrac, refdiv; 821 822 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 823 pll | AR_RTC_9300_SOC_PLL_BYPASS); 824 udelay(1000); 825 826 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 827 udelay(100); 828 829 if (ah->is_clk_25mhz) { 830 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 831 pll2_divint = 0x1c; 832 pll2_divfrac = 0xa3d2; 833 refdiv = 1; 834 } else { 835 pll2_divint = 0x54; 836 pll2_divfrac = 0x1eb85; 837 refdiv = 3; 838 } 839 } else { 840 if (AR_SREV_9340(ah)) { 841 pll2_divint = 88; 842 pll2_divfrac = 0; 843 refdiv = 5; 844 } else { 845 pll2_divint = 0x11; 846 pll2_divfrac = (AR_SREV_9531(ah) || 847 AR_SREV_9561(ah)) ? 848 0x26665 : 0x26666; 849 refdiv = 1; 850 } 851 } 852 853 regval = REG_READ(ah, AR_PHY_PLL_MODE); 854 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 855 regval |= (0x1 << 22); 856 else 857 regval |= (0x1 << 16); 858 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 859 udelay(100); 860 861 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 862 (pll2_divint << 18) | pll2_divfrac); 863 udelay(100); 864 865 regval = REG_READ(ah, AR_PHY_PLL_MODE); 866 if (AR_SREV_9340(ah)) 867 regval = (regval & 0x80071fff) | 868 (0x1 << 30) | 869 (0x1 << 13) | 870 (0x4 << 26) | 871 (0x18 << 19); 872 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { 873 regval = (regval & 0x01c00fff) | 874 (0x1 << 31) | 875 (0x2 << 29) | 876 (0xa << 25) | 877 (0x1 << 19); 878 879 if (AR_SREV_9531(ah)) 880 regval |= (0x6 << 12); 881 } else 882 regval = (regval & 0x80071fff) | 883 (0x3 << 30) | 884 (0x1 << 13) | 885 (0x4 << 26) | 886 (0x60 << 19); 887 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 888 889 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) 890 REG_WRITE(ah, AR_PHY_PLL_MODE, 891 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); 892 else 893 REG_WRITE(ah, AR_PHY_PLL_MODE, 894 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 895 896 udelay(1000); 897 } 898 899 if (AR_SREV_9565(ah)) 900 pll |= 0x40000; 901 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 902 903 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 904 AR_SREV_9550(ah)) 905 udelay(1000); 906 907 /* Switch the core clock for ar9271 to 117Mhz */ 908 if (AR_SREV_9271(ah)) { 909 udelay(500); 910 REG_WRITE(ah, 0x50040, 0x304); 911 } 912 913 udelay(RTC_PLL_SETTLE_DELAY); 914 915 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 916 } 917 918 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 919 enum nl80211_iftype opmode) 920 { 921 u32 sync_default = AR_INTR_SYNC_DEFAULT; 922 u32 imr_reg = AR_IMR_TXERR | 923 AR_IMR_TXURN | 924 AR_IMR_RXERR | 925 AR_IMR_RXORN | 926 AR_IMR_BCNMISC; 927 u32 msi_cfg = 0; 928 929 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || 930 AR_SREV_9561(ah)) 931 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 932 933 if (AR_SREV_9300_20_OR_LATER(ah)) { 934 imr_reg |= AR_IMR_RXOK_HP; 935 if (ah->config.rx_intr_mitigation) { 936 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 937 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 938 } else { 939 imr_reg |= AR_IMR_RXOK_LP; 940 msi_cfg |= AR_INTCFG_MSI_RXOK; 941 } 942 } else { 943 if (ah->config.rx_intr_mitigation) { 944 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 945 msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR; 946 } else { 947 imr_reg |= AR_IMR_RXOK; 948 msi_cfg |= AR_INTCFG_MSI_RXOK; 949 } 950 } 951 952 if (ah->config.tx_intr_mitigation) { 953 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 954 msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR; 955 } else { 956 imr_reg |= AR_IMR_TXOK; 957 msi_cfg |= AR_INTCFG_MSI_TXOK; 958 } 959 960 ENABLE_REGWRITE_BUFFER(ah); 961 962 REG_WRITE(ah, AR_IMR, imr_reg); 963 ah->imrs2_reg |= AR_IMR_S2_GTT; 964 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 965 966 if (ah->msi_enabled) { 967 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); 968 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN; 969 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; 970 REG_WRITE(ah, AR_INTCFG, msi_cfg); 971 ath_dbg(ath9k_hw_common(ah), ANY, 972 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n", 973 REG_READ(ah, AR_INTCFG), msi_cfg); 974 } 975 976 if (!AR_SREV_9100(ah)) { 977 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 978 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 979 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 980 } 981 982 REGWRITE_BUFFER_FLUSH(ah); 983 984 if (AR_SREV_9300_20_OR_LATER(ah)) { 985 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 986 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 987 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 988 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 989 } 990 } 991 992 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 993 { 994 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 995 val = min(val, (u32) 0xFFFF); 996 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 997 } 998 999 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1000 { 1001 u32 val = ath9k_hw_mac_to_clks(ah, us); 1002 val = min(val, (u32) 0xFFFF); 1003 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1004 } 1005 1006 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1007 { 1008 u32 val = ath9k_hw_mac_to_clks(ah, us); 1009 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1010 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1011 } 1012 1013 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1014 { 1015 u32 val = ath9k_hw_mac_to_clks(ah, us); 1016 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1017 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1018 } 1019 1020 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1021 { 1022 if (tu > 0xFFFF) { 1023 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1024 tu); 1025 ah->globaltxtimeout = (u32) -1; 1026 return false; 1027 } else { 1028 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1029 ah->globaltxtimeout = tu; 1030 return true; 1031 } 1032 } 1033 1034 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1035 { 1036 struct ath_common *common = ath9k_hw_common(ah); 1037 const struct ath9k_channel *chan = ah->curchan; 1038 int acktimeout, ctstimeout, ack_offset = 0; 1039 int slottime; 1040 int sifstime; 1041 int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0; 1042 u32 reg; 1043 1044 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1045 ah->misc_mode); 1046 1047 if (!chan) 1048 return; 1049 1050 if (ah->misc_mode != 0) 1051 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1052 1053 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1054 rx_lat = 41; 1055 else 1056 rx_lat = 37; 1057 tx_lat = 54; 1058 1059 if (IS_CHAN_5GHZ(chan)) 1060 sifstime = 16; 1061 else 1062 sifstime = 10; 1063 1064 if (IS_CHAN_HALF_RATE(chan)) { 1065 eifs = 175; 1066 rx_lat *= 2; 1067 tx_lat *= 2; 1068 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1069 tx_lat += 11; 1070 1071 sifstime = 32; 1072 ack_offset = 16; 1073 ack_shift = 3; 1074 slottime = 13; 1075 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1076 eifs = 340; 1077 rx_lat = (rx_lat * 4) - 1; 1078 tx_lat *= 4; 1079 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1080 tx_lat += 22; 1081 1082 sifstime = 64; 1083 ack_offset = 32; 1084 ack_shift = 1; 1085 slottime = 21; 1086 } else { 1087 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1088 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1089 reg = AR_USEC_ASYNC_FIFO; 1090 } else { 1091 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1092 common->clockrate; 1093 reg = REG_READ(ah, AR_USEC); 1094 } 1095 rx_lat = MS(reg, AR_USEC_RX_LAT); 1096 tx_lat = MS(reg, AR_USEC_TX_LAT); 1097 1098 slottime = ah->slottime; 1099 } 1100 1101 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1102 slottime += 3 * ah->coverage_class; 1103 acktimeout = slottime + sifstime + ack_offset; 1104 ctstimeout = acktimeout; 1105 1106 /* 1107 * Workaround for early ACK timeouts, add an offset to match the 1108 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1109 * This was initially only meant to work around an issue with delayed 1110 * BA frames in some implementations, but it has been found to fix ACK 1111 * timeout issues in other cases as well. 1112 */ 1113 if (IS_CHAN_2GHZ(chan) && 1114 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1115 acktimeout += 64 - sifstime - ah->slottime; 1116 ctstimeout += 48 - sifstime - ah->slottime; 1117 } 1118 1119 if (ah->dynack.enabled) { 1120 acktimeout = ah->dynack.ackto; 1121 ctstimeout = acktimeout; 1122 slottime = (acktimeout - 3) / 2; 1123 } else { 1124 ah->dynack.ackto = acktimeout; 1125 } 1126 1127 ath9k_hw_set_sifs_time(ah, sifstime); 1128 ath9k_hw_setslottime(ah, slottime); 1129 ath9k_hw_set_ack_timeout(ah, acktimeout); 1130 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1131 if (ah->globaltxtimeout != (u32) -1) 1132 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1133 1134 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1135 REG_RMW(ah, AR_USEC, 1136 (common->clockrate - 1) | 1137 SM(rx_lat, AR_USEC_RX_LAT) | 1138 SM(tx_lat, AR_USEC_TX_LAT), 1139 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1140 1141 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) 1142 REG_RMW(ah, AR_TXSIFS, 1143 sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT), 1144 (AR_TXSIFS_TIME | AR_TXSIFS_ACK_SHIFT)); 1145 } 1146 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1147 1148 void ath9k_hw_deinit(struct ath_hw *ah) 1149 { 1150 struct ath_common *common = ath9k_hw_common(ah); 1151 1152 if (common->state < ATH_HW_INITIALIZED) 1153 return; 1154 1155 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1156 } 1157 EXPORT_SYMBOL(ath9k_hw_deinit); 1158 1159 /*******/ 1160 /* INI */ 1161 /*******/ 1162 1163 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1164 { 1165 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1166 1167 if (IS_CHAN_2GHZ(chan)) 1168 ctl |= CTL_11G; 1169 else 1170 ctl |= CTL_11A; 1171 1172 return ctl; 1173 } 1174 1175 /****************************************/ 1176 /* Reset and Channel Switching Routines */ 1177 /****************************************/ 1178 1179 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1180 { 1181 struct ath_common *common = ath9k_hw_common(ah); 1182 int txbuf_size; 1183 1184 ENABLE_REGWRITE_BUFFER(ah); 1185 1186 /* 1187 * set AHB_MODE not to do cacheline prefetches 1188 */ 1189 if (!AR_SREV_9300_20_OR_LATER(ah)) 1190 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1191 1192 /* 1193 * let mac dma reads be in 128 byte chunks 1194 */ 1195 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1196 1197 REGWRITE_BUFFER_FLUSH(ah); 1198 1199 /* 1200 * Restore TX Trigger Level to its pre-reset value. 1201 * The initial value depends on whether aggregation is enabled, and is 1202 * adjusted whenever underruns are detected. 1203 */ 1204 if (!AR_SREV_9300_20_OR_LATER(ah)) 1205 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1206 1207 ENABLE_REGWRITE_BUFFER(ah); 1208 1209 /* 1210 * let mac dma writes be in 128 byte chunks 1211 */ 1212 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1213 1214 /* 1215 * Setup receive FIFO threshold to hold off TX activities 1216 */ 1217 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1218 1219 if (AR_SREV_9300_20_OR_LATER(ah)) { 1220 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1221 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1222 1223 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1224 ah->caps.rx_status_len); 1225 } 1226 1227 /* 1228 * reduce the number of usable entries in PCU TXBUF to avoid 1229 * wrap around issues. 1230 */ 1231 if (AR_SREV_9285(ah)) { 1232 /* For AR9285 the number of Fifos are reduced to half. 1233 * So set the usable tx buf size also to half to 1234 * avoid data/delimiter underruns 1235 */ 1236 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1237 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1238 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1239 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1240 } else { 1241 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1242 } 1243 1244 if (!AR_SREV_9271(ah)) 1245 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1246 1247 REGWRITE_BUFFER_FLUSH(ah); 1248 1249 if (AR_SREV_9300_20_OR_LATER(ah)) 1250 ath9k_hw_reset_txstatus_ring(ah); 1251 } 1252 1253 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1254 { 1255 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1256 u32 set = AR_STA_ID1_KSRCH_MODE; 1257 1258 ENABLE_REG_RMW_BUFFER(ah); 1259 switch (opmode) { 1260 case NL80211_IFTYPE_ADHOC: 1261 if (!AR_SREV_9340_13(ah)) { 1262 set |= AR_STA_ID1_ADHOC; 1263 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1264 break; 1265 } 1266 /* fall through */ 1267 case NL80211_IFTYPE_OCB: 1268 case NL80211_IFTYPE_MESH_POINT: 1269 case NL80211_IFTYPE_AP: 1270 set |= AR_STA_ID1_STA_AP; 1271 /* fall through */ 1272 case NL80211_IFTYPE_STATION: 1273 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1274 break; 1275 default: 1276 if (!ah->is_monitoring) 1277 set = 0; 1278 break; 1279 } 1280 REG_RMW(ah, AR_STA_ID1, set, mask); 1281 REG_RMW_BUFFER_FLUSH(ah); 1282 } 1283 1284 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1285 u32 *coef_mantissa, u32 *coef_exponent) 1286 { 1287 u32 coef_exp, coef_man; 1288 1289 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1290 if ((coef_scaled >> coef_exp) & 0x1) 1291 break; 1292 1293 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1294 1295 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1296 1297 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1298 *coef_exponent = coef_exp - 16; 1299 } 1300 1301 /* AR9330 WAR: 1302 * call external reset function to reset WMAC if: 1303 * - doing a cold reset 1304 * - we have pending frames in the TX queues. 1305 */ 1306 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) 1307 { 1308 int i, npend = 0; 1309 1310 for (i = 0; i < AR_NUM_QCU; i++) { 1311 npend = ath9k_hw_numtxpending(ah, i); 1312 if (npend) 1313 break; 1314 } 1315 1316 if (ah->external_reset && 1317 (npend || type == ATH9K_RESET_COLD)) { 1318 int reset_err = 0; 1319 1320 ath_dbg(ath9k_hw_common(ah), RESET, 1321 "reset MAC via external reset\n"); 1322 1323 reset_err = ah->external_reset(); 1324 if (reset_err) { 1325 ath_err(ath9k_hw_common(ah), 1326 "External reset failed, err=%d\n", 1327 reset_err); 1328 return false; 1329 } 1330 1331 REG_WRITE(ah, AR_RTC_RESET, 1); 1332 } 1333 1334 return true; 1335 } 1336 1337 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1338 { 1339 u32 rst_flags; 1340 u32 tmpReg; 1341 1342 if (AR_SREV_9100(ah)) { 1343 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1344 AR_RTC_DERIVED_CLK_PERIOD, 1); 1345 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1346 } 1347 1348 ENABLE_REGWRITE_BUFFER(ah); 1349 1350 if (AR_SREV_9300_20_OR_LATER(ah)) { 1351 REG_WRITE(ah, AR_WA, ah->WARegVal); 1352 udelay(10); 1353 } 1354 1355 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1356 AR_RTC_FORCE_WAKE_ON_INT); 1357 1358 if (AR_SREV_9100(ah)) { 1359 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1360 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1361 } else { 1362 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1363 if (AR_SREV_9340(ah)) 1364 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1365 else 1366 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1367 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1368 1369 if (tmpReg) { 1370 u32 val; 1371 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1372 1373 val = AR_RC_HOSTIF; 1374 if (!AR_SREV_9300_20_OR_LATER(ah)) 1375 val |= AR_RC_AHB; 1376 REG_WRITE(ah, AR_RC, val); 1377 1378 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1379 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1380 1381 rst_flags = AR_RTC_RC_MAC_WARM; 1382 if (type == ATH9K_RESET_COLD) 1383 rst_flags |= AR_RTC_RC_MAC_COLD; 1384 } 1385 1386 if (AR_SREV_9330(ah)) { 1387 if (!ath9k_hw_ar9330_reset_war(ah, type)) 1388 return false; 1389 } 1390 1391 if (ath9k_hw_mci_is_enabled(ah)) 1392 ar9003_mci_check_gpm_offset(ah); 1393 1394 /* DMA HALT added to resolve ar9300 and ar9580 bus error during 1395 * RTC_RC reg read 1396 */ 1397 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { 1398 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1399 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, 1400 20 * AH_WAIT_TIMEOUT); 1401 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); 1402 } 1403 1404 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1405 1406 REGWRITE_BUFFER_FLUSH(ah); 1407 1408 if (AR_SREV_9300_20_OR_LATER(ah)) 1409 udelay(50); 1410 else if (AR_SREV_9100(ah)) 1411 mdelay(10); 1412 else 1413 udelay(100); 1414 1415 REG_WRITE(ah, AR_RTC_RC, 0); 1416 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1417 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1418 return false; 1419 } 1420 1421 if (!AR_SREV_9100(ah)) 1422 REG_WRITE(ah, AR_RC, 0); 1423 1424 if (AR_SREV_9100(ah)) 1425 udelay(50); 1426 1427 return true; 1428 } 1429 1430 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1431 { 1432 ENABLE_REGWRITE_BUFFER(ah); 1433 1434 if (AR_SREV_9300_20_OR_LATER(ah)) { 1435 REG_WRITE(ah, AR_WA, ah->WARegVal); 1436 udelay(10); 1437 } 1438 1439 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1440 AR_RTC_FORCE_WAKE_ON_INT); 1441 1442 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1443 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1444 1445 REG_WRITE(ah, AR_RTC_RESET, 0); 1446 1447 REGWRITE_BUFFER_FLUSH(ah); 1448 1449 udelay(2); 1450 1451 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1452 REG_WRITE(ah, AR_RC, 0); 1453 1454 REG_WRITE(ah, AR_RTC_RESET, 1); 1455 1456 if (!ath9k_hw_wait(ah, 1457 AR_RTC_STATUS, 1458 AR_RTC_STATUS_M, 1459 AR_RTC_STATUS_ON, 1460 AH_WAIT_TIMEOUT)) { 1461 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1462 return false; 1463 } 1464 1465 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1466 } 1467 1468 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1469 { 1470 bool ret = false; 1471 1472 if (AR_SREV_9300_20_OR_LATER(ah)) { 1473 REG_WRITE(ah, AR_WA, ah->WARegVal); 1474 udelay(10); 1475 } 1476 1477 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1478 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1479 1480 if (!ah->reset_power_on) 1481 type = ATH9K_RESET_POWER_ON; 1482 1483 switch (type) { 1484 case ATH9K_RESET_POWER_ON: 1485 ret = ath9k_hw_set_reset_power_on(ah); 1486 if (ret) 1487 ah->reset_power_on = true; 1488 break; 1489 case ATH9K_RESET_WARM: 1490 case ATH9K_RESET_COLD: 1491 ret = ath9k_hw_set_reset(ah, type); 1492 break; 1493 default: 1494 break; 1495 } 1496 1497 return ret; 1498 } 1499 1500 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1501 struct ath9k_channel *chan) 1502 { 1503 int reset_type = ATH9K_RESET_WARM; 1504 1505 if (AR_SREV_9280(ah)) { 1506 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1507 reset_type = ATH9K_RESET_POWER_ON; 1508 else 1509 reset_type = ATH9K_RESET_COLD; 1510 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1511 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1512 reset_type = ATH9K_RESET_COLD; 1513 1514 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1515 return false; 1516 1517 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1518 return false; 1519 1520 ah->chip_fullsleep = false; 1521 1522 if (AR_SREV_9330(ah)) 1523 ar9003_hw_internal_regulator_apply(ah); 1524 ath9k_hw_init_pll(ah, chan); 1525 1526 return true; 1527 } 1528 1529 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1530 struct ath9k_channel *chan) 1531 { 1532 struct ath_common *common = ath9k_hw_common(ah); 1533 struct ath9k_hw_capabilities *pCap = &ah->caps; 1534 bool band_switch = false, mode_diff = false; 1535 u8 ini_reloaded = 0; 1536 u32 qnum; 1537 int r; 1538 1539 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1540 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; 1541 band_switch = !!(flags_diff & CHANNEL_5GHZ); 1542 mode_diff = !!(flags_diff & ~CHANNEL_HT); 1543 } 1544 1545 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1546 if (ath9k_hw_numtxpending(ah, qnum)) { 1547 ath_dbg(common, QUEUE, 1548 "Transmit frames pending on queue %d\n", qnum); 1549 return false; 1550 } 1551 } 1552 1553 if (!ath9k_hw_rfbus_req(ah)) { 1554 ath_err(common, "Could not kill baseband RX\n"); 1555 return false; 1556 } 1557 1558 if (band_switch || mode_diff) { 1559 ath9k_hw_mark_phy_inactive(ah); 1560 udelay(5); 1561 1562 if (band_switch) 1563 ath9k_hw_init_pll(ah, chan); 1564 1565 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1566 ath_err(common, "Failed to do fast channel change\n"); 1567 return false; 1568 } 1569 } 1570 1571 ath9k_hw_set_channel_regs(ah, chan); 1572 1573 r = ath9k_hw_rf_set_freq(ah, chan); 1574 if (r) { 1575 ath_err(common, "Failed to set channel\n"); 1576 return false; 1577 } 1578 ath9k_hw_set_clockrate(ah); 1579 ath9k_hw_apply_txpower(ah, chan, false); 1580 1581 ath9k_hw_set_delta_slope(ah, chan); 1582 ath9k_hw_spur_mitigate_freq(ah, chan); 1583 1584 if (band_switch || ini_reloaded) 1585 ah->eep_ops->set_board_values(ah, chan); 1586 1587 ath9k_hw_init_bb(ah, chan); 1588 ath9k_hw_rfbus_done(ah); 1589 1590 if (band_switch || ini_reloaded) { 1591 ah->ah_flags |= AH_FASTCC; 1592 ath9k_hw_init_cal(ah, chan); 1593 ah->ah_flags &= ~AH_FASTCC; 1594 } 1595 1596 return true; 1597 } 1598 1599 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1600 { 1601 u32 gpio_mask = ah->gpio_mask; 1602 int i; 1603 1604 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1605 if (!(gpio_mask & 1)) 1606 continue; 1607 1608 ath9k_hw_gpio_request_out(ah, i, NULL, 1609 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1610 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1611 ath9k_hw_gpio_free(ah, i); 1612 } 1613 } 1614 1615 void ath9k_hw_check_nav(struct ath_hw *ah) 1616 { 1617 struct ath_common *common = ath9k_hw_common(ah); 1618 u32 val; 1619 1620 val = REG_READ(ah, AR_NAV); 1621 if (val != 0xdeadbeef && val > 0x7fff) { 1622 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1623 REG_WRITE(ah, AR_NAV, 0); 1624 } 1625 } 1626 EXPORT_SYMBOL(ath9k_hw_check_nav); 1627 1628 bool ath9k_hw_check_alive(struct ath_hw *ah) 1629 { 1630 int count = 50; 1631 u32 reg, last_val; 1632 1633 /* Check if chip failed to wake up */ 1634 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) 1635 return false; 1636 1637 if (AR_SREV_9300(ah)) 1638 return !ath9k_hw_detect_mac_hang(ah); 1639 1640 if (AR_SREV_9285_12_OR_LATER(ah)) 1641 return true; 1642 1643 last_val = REG_READ(ah, AR_OBS_BUS_1); 1644 do { 1645 reg = REG_READ(ah, AR_OBS_BUS_1); 1646 if (reg != last_val) 1647 return true; 1648 1649 udelay(1); 1650 last_val = reg; 1651 if ((reg & 0x7E7FFFEF) == 0x00702400) 1652 continue; 1653 1654 switch (reg & 0x7E000B00) { 1655 case 0x1E000000: 1656 case 0x52000B00: 1657 case 0x18000B00: 1658 continue; 1659 default: 1660 return true; 1661 } 1662 } while (count-- > 0); 1663 1664 return false; 1665 } 1666 EXPORT_SYMBOL(ath9k_hw_check_alive); 1667 1668 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1669 { 1670 /* Setup MFP options for CCMP */ 1671 if (AR_SREV_9280_20_OR_LATER(ah)) { 1672 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1673 * frames when constructing CCMP AAD. */ 1674 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1675 0xc7ff); 1676 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) 1677 ah->sw_mgmt_crypto_tx = true; 1678 else 1679 ah->sw_mgmt_crypto_tx = false; 1680 ah->sw_mgmt_crypto_rx = false; 1681 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1682 /* Disable hardware crypto for management frames */ 1683 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1684 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1685 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1686 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1687 ah->sw_mgmt_crypto_tx = true; 1688 ah->sw_mgmt_crypto_rx = true; 1689 } else { 1690 ah->sw_mgmt_crypto_tx = true; 1691 ah->sw_mgmt_crypto_rx = true; 1692 } 1693 } 1694 1695 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1696 u32 macStaId1, u32 saveDefAntenna) 1697 { 1698 struct ath_common *common = ath9k_hw_common(ah); 1699 1700 ENABLE_REGWRITE_BUFFER(ah); 1701 1702 REG_RMW(ah, AR_STA_ID1, macStaId1 1703 | AR_STA_ID1_RTS_USE_DEF 1704 | ah->sta_id1_defaults, 1705 ~AR_STA_ID1_SADH_MASK); 1706 ath_hw_setbssidmask(common); 1707 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1708 ath9k_hw_write_associd(ah); 1709 REG_WRITE(ah, AR_ISR, ~0); 1710 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1711 1712 REGWRITE_BUFFER_FLUSH(ah); 1713 1714 ath9k_hw_set_operating_mode(ah, ah->opmode); 1715 } 1716 1717 static void ath9k_hw_init_queues(struct ath_hw *ah) 1718 { 1719 int i; 1720 1721 ENABLE_REGWRITE_BUFFER(ah); 1722 1723 for (i = 0; i < AR_NUM_DCU; i++) 1724 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1725 1726 REGWRITE_BUFFER_FLUSH(ah); 1727 1728 ah->intr_txqs = 0; 1729 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1730 ath9k_hw_resettxqueue(ah, i); 1731 } 1732 1733 /* 1734 * For big endian systems turn on swapping for descriptors 1735 */ 1736 static void ath9k_hw_init_desc(struct ath_hw *ah) 1737 { 1738 struct ath_common *common = ath9k_hw_common(ah); 1739 1740 if (AR_SREV_9100(ah)) { 1741 u32 mask; 1742 mask = REG_READ(ah, AR_CFG); 1743 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1744 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1745 mask); 1746 } else { 1747 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1748 REG_WRITE(ah, AR_CFG, mask); 1749 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1750 REG_READ(ah, AR_CFG)); 1751 } 1752 } else { 1753 if (common->bus_ops->ath_bus_type == ATH_USB) { 1754 /* Configure AR9271 target WLAN */ 1755 if (AR_SREV_9271(ah)) 1756 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1757 else 1758 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1759 } 1760 #ifdef __BIG_ENDIAN 1761 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1762 AR_SREV_9550(ah) || AR_SREV_9531(ah) || 1763 AR_SREV_9561(ah)) 1764 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1765 else 1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1767 #endif 1768 } 1769 } 1770 1771 /* 1772 * Fast channel change: 1773 * (Change synthesizer based on channel freq without resetting chip) 1774 */ 1775 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1776 { 1777 struct ath_common *common = ath9k_hw_common(ah); 1778 struct ath9k_hw_capabilities *pCap = &ah->caps; 1779 int ret; 1780 1781 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1782 goto fail; 1783 1784 if (ah->chip_fullsleep) 1785 goto fail; 1786 1787 if (!ah->curchan) 1788 goto fail; 1789 1790 if (chan->channel == ah->curchan->channel) 1791 goto fail; 1792 1793 if ((ah->curchan->channelFlags | chan->channelFlags) & 1794 (CHANNEL_HALF | CHANNEL_QUARTER)) 1795 goto fail; 1796 1797 /* 1798 * If cross-band fcc is not supoprted, bail out if channelFlags differ. 1799 */ 1800 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && 1801 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) 1802 goto fail; 1803 1804 if (!ath9k_hw_check_alive(ah)) 1805 goto fail; 1806 1807 /* 1808 * For AR9462, make sure that calibration data for 1809 * re-using are present. 1810 */ 1811 if (AR_SREV_9462(ah) && (ah->caldata && 1812 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || 1813 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || 1814 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) 1815 goto fail; 1816 1817 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1818 ah->curchan->channel, chan->channel); 1819 1820 ret = ath9k_hw_channel_change(ah, chan); 1821 if (!ret) 1822 goto fail; 1823 1824 if (ath9k_hw_mci_is_enabled(ah)) 1825 ar9003_mci_2g5g_switch(ah, false); 1826 1827 ath9k_hw_loadnf(ah, ah->curchan); 1828 ath9k_hw_start_nfcal(ah, true); 1829 1830 if (AR_SREV_9271(ah)) 1831 ar9002_hw_load_ani_reg(ah, chan); 1832 1833 return 0; 1834 fail: 1835 return -EINVAL; 1836 } 1837 1838 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) 1839 { 1840 struct timespec ts; 1841 s64 usec; 1842 1843 if (!cur) { 1844 getrawmonotonic(&ts); 1845 cur = &ts; 1846 } 1847 1848 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; 1849 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; 1850 1851 return (u32) usec; 1852 } 1853 EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); 1854 1855 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1856 struct ath9k_hw_cal_data *caldata, bool fastcc) 1857 { 1858 struct ath_common *common = ath9k_hw_common(ah); 1859 u32 saveLedState; 1860 u32 saveDefAntenna; 1861 u32 macStaId1; 1862 struct timespec tsf_ts; 1863 u32 tsf_offset; 1864 u64 tsf = 0; 1865 int r; 1866 bool start_mci_reset = false; 1867 bool save_fullsleep = ah->chip_fullsleep; 1868 1869 if (ath9k_hw_mci_is_enabled(ah)) { 1870 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1871 if (start_mci_reset) 1872 return 0; 1873 } 1874 1875 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1876 return -EIO; 1877 1878 if (ah->curchan && !ah->chip_fullsleep) 1879 ath9k_hw_getnf(ah, ah->curchan); 1880 1881 ah->caldata = caldata; 1882 if (caldata && (chan->channel != caldata->channel || 1883 chan->channelFlags != caldata->channelFlags)) { 1884 /* Operating channel changed, reset channel calibration data */ 1885 memset(caldata, 0, sizeof(*caldata)); 1886 ath9k_init_nfcal_hist_buffer(ah, chan); 1887 } else if (caldata) { 1888 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); 1889 } 1890 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); 1891 1892 if (fastcc) { 1893 r = ath9k_hw_do_fastcc(ah, chan); 1894 if (!r) 1895 return r; 1896 } 1897 1898 if (ath9k_hw_mci_is_enabled(ah)) 1899 ar9003_mci_stop_bt(ah, save_fullsleep); 1900 1901 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1902 if (saveDefAntenna == 0) 1903 saveDefAntenna = 1; 1904 1905 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1906 1907 /* Save TSF before chip reset, a cold reset clears it */ 1908 getrawmonotonic(&tsf_ts); 1909 tsf = ath9k_hw_gettsf64(ah); 1910 1911 saveLedState = REG_READ(ah, AR_CFG_LED) & 1912 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1913 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1914 1915 ath9k_hw_mark_phy_inactive(ah); 1916 1917 ah->paprd_table_write_done = false; 1918 1919 /* Only required on the first reset */ 1920 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1921 REG_WRITE(ah, 1922 AR9271_RESET_POWER_DOWN_CONTROL, 1923 AR9271_RADIO_RF_RST); 1924 udelay(50); 1925 } 1926 1927 if (!ath9k_hw_chip_reset(ah, chan)) { 1928 ath_err(common, "Chip reset failed\n"); 1929 return -EINVAL; 1930 } 1931 1932 /* Only required on the first reset */ 1933 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1934 ah->htc_reset_init = false; 1935 REG_WRITE(ah, 1936 AR9271_RESET_POWER_DOWN_CONTROL, 1937 AR9271_GATE_MAC_CTL); 1938 udelay(50); 1939 } 1940 1941 /* Restore TSF */ 1942 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1943 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1944 1945 if (AR_SREV_9280_20_OR_LATER(ah)) 1946 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1947 1948 if (!AR_SREV_9300_20_OR_LATER(ah)) 1949 ar9002_hw_enable_async_fifo(ah); 1950 1951 r = ath9k_hw_process_ini(ah, chan); 1952 if (r) 1953 return r; 1954 1955 ath9k_hw_set_rfmode(ah, chan); 1956 1957 if (ath9k_hw_mci_is_enabled(ah)) 1958 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1959 1960 /* 1961 * Some AR91xx SoC devices frequently fail to accept TSF writes 1962 * right after the chip reset. When that happens, write a new 1963 * value after the initvals have been applied. 1964 */ 1965 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1966 tsf_offset = ath9k_hw_get_tsf_offset(&tsf_ts, NULL); 1967 ath9k_hw_settsf64(ah, tsf + tsf_offset); 1968 } 1969 1970 ath9k_hw_init_mfp(ah); 1971 1972 ath9k_hw_set_delta_slope(ah, chan); 1973 ath9k_hw_spur_mitigate_freq(ah, chan); 1974 ah->eep_ops->set_board_values(ah, chan); 1975 1976 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1977 1978 r = ath9k_hw_rf_set_freq(ah, chan); 1979 if (r) 1980 return r; 1981 1982 ath9k_hw_set_clockrate(ah); 1983 1984 ath9k_hw_init_queues(ah); 1985 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1986 ath9k_hw_ani_cache_ini_regs(ah); 1987 ath9k_hw_init_qos(ah); 1988 1989 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1990 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); 1991 1992 ath9k_hw_init_global_settings(ah); 1993 1994 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1995 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 1996 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 1997 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 1998 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 1999 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2000 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2001 } 2002 2003 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2004 2005 ath9k_hw_set_dma(ah); 2006 2007 if (!ath9k_hw_mci_is_enabled(ah)) 2008 REG_WRITE(ah, AR_OBS, 8); 2009 2010 ENABLE_REG_RMW_BUFFER(ah); 2011 if (ah->config.rx_intr_mitigation) { 2012 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); 2013 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); 2014 } 2015 2016 if (ah->config.tx_intr_mitigation) { 2017 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2018 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2019 } 2020 REG_RMW_BUFFER_FLUSH(ah); 2021 2022 ath9k_hw_init_bb(ah, chan); 2023 2024 if (caldata) { 2025 clear_bit(TXIQCAL_DONE, &caldata->cal_flags); 2026 clear_bit(TXCLCAL_DONE, &caldata->cal_flags); 2027 } 2028 if (!ath9k_hw_init_cal(ah, chan)) 2029 return -EIO; 2030 2031 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2032 return -EIO; 2033 2034 ENABLE_REGWRITE_BUFFER(ah); 2035 2036 ath9k_hw_restore_chainmask(ah); 2037 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2038 2039 REGWRITE_BUFFER_FLUSH(ah); 2040 2041 ath9k_hw_gen_timer_start_tsf2(ah); 2042 2043 ath9k_hw_init_desc(ah); 2044 2045 if (ath9k_hw_btcoex_is_enabled(ah)) 2046 ath9k_hw_btcoex_enable(ah); 2047 2048 if (ath9k_hw_mci_is_enabled(ah)) 2049 ar9003_mci_check_bt(ah); 2050 2051 if (AR_SREV_9300_20_OR_LATER(ah)) { 2052 ath9k_hw_loadnf(ah, chan); 2053 ath9k_hw_start_nfcal(ah, true); 2054 } 2055 2056 if (AR_SREV_9300_20_OR_LATER(ah)) 2057 ar9003_hw_bb_watchdog_config(ah); 2058 2059 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) 2060 ar9003_hw_disable_phy_restart(ah); 2061 2062 ath9k_hw_apply_gpio_override(ah); 2063 2064 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2065 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2066 2067 if (ah->hw->conf.radar_enabled) { 2068 /* set HW specific DFS configuration */ 2069 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); 2070 ath9k_hw_set_radar_params(ah); 2071 } 2072 2073 return 0; 2074 } 2075 EXPORT_SYMBOL(ath9k_hw_reset); 2076 2077 /******************************/ 2078 /* Power Management (Chipset) */ 2079 /******************************/ 2080 2081 /* 2082 * Notify Power Mgt is disabled in self-generated frames. 2083 * If requested, force chip to sleep. 2084 */ 2085 static void ath9k_set_power_sleep(struct ath_hw *ah) 2086 { 2087 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2088 2089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2090 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2091 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2092 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2093 /* xxx Required for WLAN only case ? */ 2094 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2095 udelay(100); 2096 } 2097 2098 /* 2099 * Clear the RTC force wake bit to allow the 2100 * mac to go to sleep. 2101 */ 2102 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2103 2104 if (ath9k_hw_mci_is_enabled(ah)) 2105 udelay(100); 2106 2107 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2108 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2109 2110 /* Shutdown chip. Active low */ 2111 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2112 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2113 udelay(2); 2114 } 2115 2116 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2117 if (AR_SREV_9300_20_OR_LATER(ah)) 2118 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2119 } 2120 2121 /* 2122 * Notify Power Management is enabled in self-generating 2123 * frames. If request, set power mode of chip to 2124 * auto/normal. Duration in units of 128us (1/8 TU). 2125 */ 2126 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2127 { 2128 struct ath9k_hw_capabilities *pCap = &ah->caps; 2129 2130 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2131 2132 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2133 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2134 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2135 AR_RTC_FORCE_WAKE_ON_INT); 2136 } else { 2137 2138 /* When chip goes into network sleep, it could be waken 2139 * up by MCI_INT interrupt caused by BT's HW messages 2140 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2141 * rate (~100us). This will cause chip to leave and 2142 * re-enter network sleep mode frequently, which in 2143 * consequence will have WLAN MCI HW to generate lots of 2144 * SYS_WAKING and SYS_SLEEPING messages which will make 2145 * BT CPU to busy to process. 2146 */ 2147 if (ath9k_hw_mci_is_enabled(ah)) 2148 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2149 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2150 /* 2151 * Clear the RTC force wake bit to allow the 2152 * mac to go to sleep. 2153 */ 2154 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2155 2156 if (ath9k_hw_mci_is_enabled(ah)) 2157 udelay(30); 2158 } 2159 2160 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2161 if (AR_SREV_9300_20_OR_LATER(ah)) 2162 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2163 } 2164 2165 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2166 { 2167 u32 val; 2168 int i; 2169 2170 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2171 if (AR_SREV_9300_20_OR_LATER(ah)) { 2172 REG_WRITE(ah, AR_WA, ah->WARegVal); 2173 udelay(10); 2174 } 2175 2176 if ((REG_READ(ah, AR_RTC_STATUS) & 2177 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2178 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2179 return false; 2180 } 2181 if (!AR_SREV_9300_20_OR_LATER(ah)) 2182 ath9k_hw_init_pll(ah, NULL); 2183 } 2184 if (AR_SREV_9100(ah)) 2185 REG_SET_BIT(ah, AR_RTC_RESET, 2186 AR_RTC_RESET_EN); 2187 2188 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2189 AR_RTC_FORCE_WAKE_EN); 2190 if (AR_SREV_9100(ah)) 2191 mdelay(10); 2192 else 2193 udelay(50); 2194 2195 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2196 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2197 if (val == AR_RTC_STATUS_ON) 2198 break; 2199 udelay(50); 2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2201 AR_RTC_FORCE_WAKE_EN); 2202 } 2203 if (i == 0) { 2204 ath_err(ath9k_hw_common(ah), 2205 "Failed to wakeup in %uus\n", 2206 POWER_UP_TIME / 20); 2207 return false; 2208 } 2209 2210 if (ath9k_hw_mci_is_enabled(ah)) 2211 ar9003_mci_set_power_awake(ah); 2212 2213 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2214 2215 return true; 2216 } 2217 2218 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2219 { 2220 struct ath_common *common = ath9k_hw_common(ah); 2221 int status = true; 2222 static const char *modes[] = { 2223 "AWAKE", 2224 "FULL-SLEEP", 2225 "NETWORK SLEEP", 2226 "UNDEFINED" 2227 }; 2228 2229 if (ah->power_mode == mode) 2230 return status; 2231 2232 ath_dbg(common, RESET, "%s -> %s\n", 2233 modes[ah->power_mode], modes[mode]); 2234 2235 switch (mode) { 2236 case ATH9K_PM_AWAKE: 2237 status = ath9k_hw_set_power_awake(ah); 2238 break; 2239 case ATH9K_PM_FULL_SLEEP: 2240 if (ath9k_hw_mci_is_enabled(ah)) 2241 ar9003_mci_set_full_sleep(ah); 2242 2243 ath9k_set_power_sleep(ah); 2244 ah->chip_fullsleep = true; 2245 break; 2246 case ATH9K_PM_NETWORK_SLEEP: 2247 ath9k_set_power_network_sleep(ah); 2248 break; 2249 default: 2250 ath_err(common, "Unknown power mode %u\n", mode); 2251 return false; 2252 } 2253 ah->power_mode = mode; 2254 2255 /* 2256 * XXX: If this warning never comes up after a while then 2257 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2258 * ath9k_hw_setpower() return type void. 2259 */ 2260 2261 if (!(ah->ah_flags & AH_UNPLUGGED)) 2262 ATH_DBG_WARN_ON_ONCE(!status); 2263 2264 return status; 2265 } 2266 EXPORT_SYMBOL(ath9k_hw_setpower); 2267 2268 /*******************/ 2269 /* Beacon Handling */ 2270 /*******************/ 2271 2272 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2273 { 2274 int flags = 0; 2275 2276 ENABLE_REGWRITE_BUFFER(ah); 2277 2278 switch (ah->opmode) { 2279 case NL80211_IFTYPE_ADHOC: 2280 REG_SET_BIT(ah, AR_TXCFG, 2281 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2282 case NL80211_IFTYPE_MESH_POINT: 2283 case NL80211_IFTYPE_AP: 2284 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2285 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2286 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2287 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2288 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2289 flags |= 2290 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2291 break; 2292 default: 2293 ath_dbg(ath9k_hw_common(ah), BEACON, 2294 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2295 return; 2296 break; 2297 } 2298 2299 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2300 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2301 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2302 2303 REGWRITE_BUFFER_FLUSH(ah); 2304 2305 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2306 } 2307 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2308 2309 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2310 const struct ath9k_beacon_state *bs) 2311 { 2312 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2313 struct ath9k_hw_capabilities *pCap = &ah->caps; 2314 struct ath_common *common = ath9k_hw_common(ah); 2315 2316 ENABLE_REGWRITE_BUFFER(ah); 2317 2318 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); 2319 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); 2320 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); 2321 2322 REGWRITE_BUFFER_FLUSH(ah); 2323 2324 REG_RMW_FIELD(ah, AR_RSSI_THR, 2325 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2326 2327 beaconintval = bs->bs_intval; 2328 2329 if (bs->bs_sleepduration > beaconintval) 2330 beaconintval = bs->bs_sleepduration; 2331 2332 dtimperiod = bs->bs_dtimperiod; 2333 if (bs->bs_sleepduration > dtimperiod) 2334 dtimperiod = bs->bs_sleepduration; 2335 2336 if (beaconintval == dtimperiod) 2337 nextTbtt = bs->bs_nextdtim; 2338 else 2339 nextTbtt = bs->bs_nexttbtt; 2340 2341 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); 2342 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt); 2343 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval); 2344 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod); 2345 2346 ENABLE_REGWRITE_BUFFER(ah); 2347 2348 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); 2349 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); 2350 2351 REG_WRITE(ah, AR_SLEEP1, 2352 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2353 | AR_SLEEP1_ASSUME_DTIM); 2354 2355 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2356 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2357 else 2358 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2359 2360 REG_WRITE(ah, AR_SLEEP2, 2361 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2362 2363 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); 2364 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); 2365 2366 REGWRITE_BUFFER_FLUSH(ah); 2367 2368 REG_SET_BIT(ah, AR_TIMER_MODE, 2369 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2370 AR_DTIM_TIMER_EN); 2371 2372 /* TSF Out of Range Threshold */ 2373 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2374 } 2375 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2376 2377 /*******************/ 2378 /* HW Capabilities */ 2379 /*******************/ 2380 2381 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2382 { 2383 eeprom_chainmask &= chip_chainmask; 2384 if (eeprom_chainmask) 2385 return eeprom_chainmask; 2386 else 2387 return chip_chainmask; 2388 } 2389 2390 /** 2391 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2392 * @ah: the atheros hardware data structure 2393 * 2394 * We enable DFS support upstream on chipsets which have passed a series 2395 * of tests. The testing requirements are going to be documented. Desired 2396 * test requirements are documented at: 2397 * 2398 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2399 * 2400 * Once a new chipset gets properly tested an individual commit can be used 2401 * to document the testing for DFS for that chipset. 2402 */ 2403 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2404 { 2405 2406 switch (ah->hw_version.macVersion) { 2407 /* for temporary testing DFS with 9280 */ 2408 case AR_SREV_VERSION_9280: 2409 /* AR9580 will likely be our first target to get testing on */ 2410 case AR_SREV_VERSION_9580: 2411 return true; 2412 default: 2413 return false; 2414 } 2415 } 2416 2417 static void ath9k_gpio_cap_init(struct ath_hw *ah) 2418 { 2419 struct ath9k_hw_capabilities *pCap = &ah->caps; 2420 2421 if (AR_SREV_9271(ah)) { 2422 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2423 pCap->gpio_mask = AR9271_GPIO_MASK; 2424 } else if (AR_DEVID_7010(ah)) { 2425 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2426 pCap->gpio_mask = AR7010_GPIO_MASK; 2427 } else if (AR_SREV_9287(ah)) { 2428 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2429 pCap->gpio_mask = AR9287_GPIO_MASK; 2430 } else if (AR_SREV_9285(ah)) { 2431 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2432 pCap->gpio_mask = AR9285_GPIO_MASK; 2433 } else if (AR_SREV_9280(ah)) { 2434 pCap->num_gpio_pins = AR9280_NUM_GPIO; 2435 pCap->gpio_mask = AR9280_GPIO_MASK; 2436 } else if (AR_SREV_9300(ah)) { 2437 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2438 pCap->gpio_mask = AR9300_GPIO_MASK; 2439 } else if (AR_SREV_9330(ah)) { 2440 pCap->num_gpio_pins = AR9330_NUM_GPIO; 2441 pCap->gpio_mask = AR9330_GPIO_MASK; 2442 } else if (AR_SREV_9340(ah)) { 2443 pCap->num_gpio_pins = AR9340_NUM_GPIO; 2444 pCap->gpio_mask = AR9340_GPIO_MASK; 2445 } else if (AR_SREV_9462(ah)) { 2446 pCap->num_gpio_pins = AR9462_NUM_GPIO; 2447 pCap->gpio_mask = AR9462_GPIO_MASK; 2448 } else if (AR_SREV_9485(ah)) { 2449 pCap->num_gpio_pins = AR9485_NUM_GPIO; 2450 pCap->gpio_mask = AR9485_GPIO_MASK; 2451 } else if (AR_SREV_9531(ah)) { 2452 pCap->num_gpio_pins = AR9531_NUM_GPIO; 2453 pCap->gpio_mask = AR9531_GPIO_MASK; 2454 } else if (AR_SREV_9550(ah)) { 2455 pCap->num_gpio_pins = AR9550_NUM_GPIO; 2456 pCap->gpio_mask = AR9550_GPIO_MASK; 2457 } else if (AR_SREV_9561(ah)) { 2458 pCap->num_gpio_pins = AR9561_NUM_GPIO; 2459 pCap->gpio_mask = AR9561_GPIO_MASK; 2460 } else if (AR_SREV_9565(ah)) { 2461 pCap->num_gpio_pins = AR9565_NUM_GPIO; 2462 pCap->gpio_mask = AR9565_GPIO_MASK; 2463 } else if (AR_SREV_9580(ah)) { 2464 pCap->num_gpio_pins = AR9580_NUM_GPIO; 2465 pCap->gpio_mask = AR9580_GPIO_MASK; 2466 } else { 2467 pCap->num_gpio_pins = AR_NUM_GPIO; 2468 pCap->gpio_mask = AR_GPIO_MASK; 2469 } 2470 } 2471 2472 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2473 { 2474 struct ath9k_hw_capabilities *pCap = &ah->caps; 2475 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2476 struct ath_common *common = ath9k_hw_common(ah); 2477 2478 u16 eeval; 2479 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2480 2481 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2482 regulatory->current_rd = eeval; 2483 2484 if (ah->opmode != NL80211_IFTYPE_AP && 2485 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2486 if (regulatory->current_rd == 0x64 || 2487 regulatory->current_rd == 0x65) 2488 regulatory->current_rd += 5; 2489 else if (regulatory->current_rd == 0x41) 2490 regulatory->current_rd = 0x43; 2491 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2492 regulatory->current_rd); 2493 } 2494 2495 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2496 2497 if (eeval & AR5416_OPFLAGS_11A) { 2498 if (ah->disable_5ghz) 2499 ath_warn(common, "disabling 5GHz band\n"); 2500 else 2501 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2502 } 2503 2504 if (eeval & AR5416_OPFLAGS_11G) { 2505 if (ah->disable_2ghz) 2506 ath_warn(common, "disabling 2GHz band\n"); 2507 else 2508 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2509 } 2510 2511 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { 2512 ath_err(common, "both bands are disabled\n"); 2513 return -EINVAL; 2514 } 2515 2516 ath9k_gpio_cap_init(ah); 2517 2518 if (AR_SREV_9485(ah) || 2519 AR_SREV_9285(ah) || 2520 AR_SREV_9330(ah) || 2521 AR_SREV_9565(ah)) 2522 pCap->chip_chainmask = 1; 2523 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2524 pCap->chip_chainmask = 7; 2525 else if (!AR_SREV_9300_20_OR_LATER(ah) || 2526 AR_SREV_9340(ah) || 2527 AR_SREV_9462(ah) || 2528 AR_SREV_9531(ah)) 2529 pCap->chip_chainmask = 3; 2530 else 2531 pCap->chip_chainmask = 7; 2532 2533 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2534 /* 2535 * For AR9271 we will temporarilly uses the rx chainmax as read from 2536 * the EEPROM. 2537 */ 2538 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2539 !(eeval & AR5416_OPFLAGS_11A) && 2540 !(AR_SREV_9271(ah))) 2541 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2542 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2543 else if (AR_SREV_9100(ah)) 2544 pCap->rx_chainmask = 0x7; 2545 else 2546 /* Use rx_chainmask from EEPROM. */ 2547 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2548 2549 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); 2550 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); 2551 ah->txchainmask = pCap->tx_chainmask; 2552 ah->rxchainmask = pCap->rx_chainmask; 2553 2554 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2555 2556 /* enable key search for every frame in an aggregate */ 2557 if (AR_SREV_9300_20_OR_LATER(ah)) 2558 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2559 2560 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2561 2562 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2563 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2564 else 2565 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2566 2567 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2568 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2569 else 2570 pCap->rts_aggr_limit = (8 * 1024); 2571 2572 #ifdef CONFIG_ATH9K_RFKILL 2573 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2574 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2575 ah->rfkill_gpio = 2576 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2577 ah->rfkill_polarity = 2578 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2579 2580 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2581 } 2582 #endif 2583 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2584 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2585 else 2586 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2587 2588 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2589 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2590 else 2591 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2592 2593 if (AR_SREV_9300_20_OR_LATER(ah)) { 2594 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2595 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && 2596 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) 2597 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2598 2599 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2600 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2601 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2602 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2603 pCap->txs_len = sizeof(struct ar9003_txs); 2604 } else { 2605 pCap->tx_desc_len = sizeof(struct ath_desc); 2606 if (AR_SREV_9280_20(ah)) 2607 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2608 } 2609 2610 if (AR_SREV_9300_20_OR_LATER(ah)) 2611 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2612 2613 if (AR_SREV_9561(ah)) 2614 ah->ent_mode = 0x3BDA000; 2615 else if (AR_SREV_9300_20_OR_LATER(ah)) 2616 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2617 2618 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2619 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2620 2621 if (AR_SREV_9285(ah)) { 2622 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2623 ant_div_ctl1 = 2624 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2625 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2626 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2627 ath_info(common, "Enable LNA combining\n"); 2628 } 2629 } 2630 } 2631 2632 if (AR_SREV_9300_20_OR_LATER(ah)) { 2633 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2634 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2635 } 2636 2637 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2638 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2639 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2640 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2641 ath_info(common, "Enable LNA combining\n"); 2642 } 2643 } 2644 2645 if (ath9k_hw_dfs_tested(ah)) 2646 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2647 2648 tx_chainmask = pCap->tx_chainmask; 2649 rx_chainmask = pCap->rx_chainmask; 2650 while (tx_chainmask || rx_chainmask) { 2651 if (tx_chainmask & BIT(0)) 2652 pCap->max_txchains++; 2653 if (rx_chainmask & BIT(0)) 2654 pCap->max_rxchains++; 2655 2656 tx_chainmask >>= 1; 2657 rx_chainmask >>= 1; 2658 } 2659 2660 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2661 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2662 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2663 2664 if (AR_SREV_9462_20_OR_LATER(ah)) 2665 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2666 } 2667 2668 if (AR_SREV_9300_20_OR_LATER(ah) && 2669 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2670 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2671 2672 #ifdef CONFIG_ATH9K_WOW 2673 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) 2674 ah->wow.max_patterns = MAX_NUM_PATTERN; 2675 else 2676 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; 2677 #endif 2678 2679 return 0; 2680 } 2681 2682 /****************************/ 2683 /* GPIO / RFKILL / Antennae */ 2684 /****************************/ 2685 2686 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) 2687 { 2688 int addr; 2689 u32 gpio_shift, tmp; 2690 2691 if (gpio > 11) 2692 addr = AR_GPIO_OUTPUT_MUX3; 2693 else if (gpio > 5) 2694 addr = AR_GPIO_OUTPUT_MUX2; 2695 else 2696 addr = AR_GPIO_OUTPUT_MUX1; 2697 2698 gpio_shift = (gpio % 6) * 5; 2699 2700 if (AR_SREV_9280_20_OR_LATER(ah) || 2701 (addr != AR_GPIO_OUTPUT_MUX1)) { 2702 REG_RMW(ah, addr, (type << gpio_shift), 2703 (0x1f << gpio_shift)); 2704 } else { 2705 tmp = REG_READ(ah, addr); 2706 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2707 tmp &= ~(0x1f << gpio_shift); 2708 tmp |= (type << gpio_shift); 2709 REG_WRITE(ah, addr, tmp); 2710 } 2711 } 2712 2713 /* BSP should set the corresponding MUX register correctly. 2714 */ 2715 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, 2716 const char *label) 2717 { 2718 if (ah->caps.gpio_requested & BIT(gpio)) 2719 return; 2720 2721 /* may be requested by BSP, free anyway */ 2722 gpio_free(gpio); 2723 2724 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label)) 2725 return; 2726 2727 ah->caps.gpio_requested |= BIT(gpio); 2728 } 2729 2730 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, 2731 u32 ah_signal_type) 2732 { 2733 u32 gpio_set, gpio_shift = gpio; 2734 2735 if (AR_DEVID_7010(ah)) { 2736 gpio_set = out ? 2737 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT; 2738 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, 2739 AR7010_GPIO_OE_MASK << gpio_shift); 2740 } else if (AR_SREV_SOC(ah)) { 2741 gpio_set = out ? 1 : 0; 2742 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2743 gpio_set << gpio_shift); 2744 } else { 2745 gpio_shift = gpio << 1; 2746 gpio_set = out ? 2747 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO; 2748 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, 2749 AR_GPIO_OE_OUT_DRV << gpio_shift); 2750 2751 if (out) 2752 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2753 } 2754 } 2755 2756 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, 2757 const char *label, u32 ah_signal_type) 2758 { 2759 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2760 2761 if (BIT(gpio) & ah->caps.gpio_mask) 2762 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); 2763 else if (AR_SREV_SOC(ah)) 2764 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); 2765 else 2766 WARN_ON(1); 2767 } 2768 2769 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) 2770 { 2771 ath9k_hw_gpio_request(ah, gpio, false, label, 0); 2772 } 2773 EXPORT_SYMBOL(ath9k_hw_gpio_request_in); 2774 2775 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, 2776 u32 ah_signal_type) 2777 { 2778 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); 2779 } 2780 EXPORT_SYMBOL(ath9k_hw_gpio_request_out); 2781 2782 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) 2783 { 2784 if (!AR_SREV_SOC(ah)) 2785 return; 2786 2787 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2788 2789 if (ah->caps.gpio_requested & BIT(gpio)) { 2790 gpio_free(gpio); 2791 ah->caps.gpio_requested &= ~BIT(gpio); 2792 } 2793 } 2794 EXPORT_SYMBOL(ath9k_hw_gpio_free); 2795 2796 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2797 { 2798 u32 val = 0xffffffff; 2799 2800 #define MS_REG_READ(x, y) \ 2801 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) 2802 2803 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2804 2805 if (BIT(gpio) & ah->caps.gpio_mask) { 2806 if (AR_SREV_9271(ah)) 2807 val = MS_REG_READ(AR9271, gpio); 2808 else if (AR_SREV_9287(ah)) 2809 val = MS_REG_READ(AR9287, gpio); 2810 else if (AR_SREV_9285(ah)) 2811 val = MS_REG_READ(AR9285, gpio); 2812 else if (AR_SREV_9280(ah)) 2813 val = MS_REG_READ(AR928X, gpio); 2814 else if (AR_DEVID_7010(ah)) 2815 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); 2816 else if (AR_SREV_9300_20_OR_LATER(ah)) 2817 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); 2818 else 2819 val = MS_REG_READ(AR, gpio); 2820 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2821 val = gpio_get_value(gpio) & BIT(gpio); 2822 } else { 2823 WARN_ON(1); 2824 } 2825 2826 return !!val; 2827 } 2828 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2829 2830 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2831 { 2832 WARN_ON(gpio >= ah->caps.num_gpio_pins); 2833 2834 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) 2835 val = !val; 2836 else 2837 val = !!val; 2838 2839 if (BIT(gpio) & ah->caps.gpio_mask) { 2840 u32 out_addr = AR_DEVID_7010(ah) ? 2841 AR7010_GPIO_OUT : AR_GPIO_IN_OUT; 2842 2843 REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); 2844 } else if (BIT(gpio) & ah->caps.gpio_requested) { 2845 gpio_set_value(gpio, val); 2846 } else { 2847 WARN_ON(1); 2848 } 2849 } 2850 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2851 2852 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2853 { 2854 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2855 } 2856 EXPORT_SYMBOL(ath9k_hw_setantenna); 2857 2858 /*********************/ 2859 /* General Operation */ 2860 /*********************/ 2861 2862 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2863 { 2864 u32 bits = REG_READ(ah, AR_RX_FILTER); 2865 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2866 2867 if (phybits & AR_PHY_ERR_RADAR) 2868 bits |= ATH9K_RX_FILTER_PHYRADAR; 2869 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2870 bits |= ATH9K_RX_FILTER_PHYERR; 2871 2872 return bits; 2873 } 2874 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2875 2876 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2877 { 2878 u32 phybits; 2879 2880 ENABLE_REGWRITE_BUFFER(ah); 2881 2882 REG_WRITE(ah, AR_RX_FILTER, bits); 2883 2884 phybits = 0; 2885 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2886 phybits |= AR_PHY_ERR_RADAR; 2887 if (bits & ATH9K_RX_FILTER_PHYERR) 2888 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2889 REG_WRITE(ah, AR_PHY_ERR, phybits); 2890 2891 if (phybits) 2892 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2893 else 2894 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2895 2896 REGWRITE_BUFFER_FLUSH(ah); 2897 } 2898 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2899 2900 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2901 { 2902 if (ath9k_hw_mci_is_enabled(ah)) 2903 ar9003_mci_bt_gain_ctrl(ah); 2904 2905 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2906 return false; 2907 2908 ath9k_hw_init_pll(ah, NULL); 2909 ah->htc_reset_init = true; 2910 return true; 2911 } 2912 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2913 2914 bool ath9k_hw_disable(struct ath_hw *ah) 2915 { 2916 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2917 return false; 2918 2919 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2920 return false; 2921 2922 ath9k_hw_init_pll(ah, NULL); 2923 return true; 2924 } 2925 EXPORT_SYMBOL(ath9k_hw_disable); 2926 2927 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2928 { 2929 enum eeprom_param gain_param; 2930 2931 if (IS_CHAN_2GHZ(chan)) 2932 gain_param = EEP_ANTENNA_GAIN_2G; 2933 else 2934 gain_param = EEP_ANTENNA_GAIN_5G; 2935 2936 return ah->eep_ops->get_eeprom(ah, gain_param); 2937 } 2938 2939 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2940 bool test) 2941 { 2942 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2943 struct ieee80211_channel *channel; 2944 int chan_pwr, new_pwr; 2945 2946 if (!chan) 2947 return; 2948 2949 channel = chan->chan; 2950 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2951 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2952 2953 ah->eep_ops->set_txpower(ah, chan, 2954 ath9k_regd_get_ctl(reg, chan), 2955 get_antenna_gain(ah, chan), new_pwr, test); 2956 } 2957 2958 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2959 { 2960 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2961 struct ath9k_channel *chan = ah->curchan; 2962 struct ieee80211_channel *channel = chan->chan; 2963 2964 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2965 if (test) 2966 channel->max_power = MAX_RATE_POWER / 2; 2967 2968 ath9k_hw_apply_txpower(ah, chan, test); 2969 2970 if (test) 2971 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2972 } 2973 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2974 2975 void ath9k_hw_setopmode(struct ath_hw *ah) 2976 { 2977 ath9k_hw_set_operating_mode(ah, ah->opmode); 2978 } 2979 EXPORT_SYMBOL(ath9k_hw_setopmode); 2980 2981 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2982 { 2983 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2984 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2985 } 2986 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2987 2988 void ath9k_hw_write_associd(struct ath_hw *ah) 2989 { 2990 struct ath_common *common = ath9k_hw_common(ah); 2991 2992 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2993 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2994 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2995 } 2996 EXPORT_SYMBOL(ath9k_hw_write_associd); 2997 2998 #define ATH9K_MAX_TSF_READ 10 2999 3000 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 3001 { 3002 u32 tsf_lower, tsf_upper1, tsf_upper2; 3003 int i; 3004 3005 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 3006 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 3007 tsf_lower = REG_READ(ah, AR_TSF_L32); 3008 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 3009 if (tsf_upper2 == tsf_upper1) 3010 break; 3011 tsf_upper1 = tsf_upper2; 3012 } 3013 3014 WARN_ON( i == ATH9K_MAX_TSF_READ ); 3015 3016 return (((u64)tsf_upper1 << 32) | tsf_lower); 3017 } 3018 EXPORT_SYMBOL(ath9k_hw_gettsf64); 3019 3020 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 3021 { 3022 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 3023 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 3024 } 3025 EXPORT_SYMBOL(ath9k_hw_settsf64); 3026 3027 void ath9k_hw_reset_tsf(struct ath_hw *ah) 3028 { 3029 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 3030 AH_TSF_WRITE_TIMEOUT)) 3031 ath_dbg(ath9k_hw_common(ah), RESET, 3032 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 3033 3034 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 3035 } 3036 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 3037 3038 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 3039 { 3040 if (set) 3041 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 3042 else 3043 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 3044 } 3045 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 3046 3047 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) 3048 { 3049 u32 macmode; 3050 3051 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) 3052 macmode = AR_2040_JOINED_RX_CLEAR; 3053 else 3054 macmode = 0; 3055 3056 REG_WRITE(ah, AR_2040_MODE, macmode); 3057 } 3058 3059 /* HW Generic timers configuration */ 3060 3061 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 3062 { 3063 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3064 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3065 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3066 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3067 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3068 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3069 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3070 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 3071 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 3072 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 3073 AR_NDP2_TIMER_MODE, 0x0002}, 3074 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3075 AR_NDP2_TIMER_MODE, 0x0004}, 3076 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3077 AR_NDP2_TIMER_MODE, 0x0008}, 3078 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3079 AR_NDP2_TIMER_MODE, 0x0010}, 3080 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3081 AR_NDP2_TIMER_MODE, 0x0020}, 3082 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3083 AR_NDP2_TIMER_MODE, 0x0040}, 3084 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3085 AR_NDP2_TIMER_MODE, 0x0080} 3086 }; 3087 3088 /* HW generic timer primitives */ 3089 3090 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3091 { 3092 return REG_READ(ah, AR_TSF_L32); 3093 } 3094 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3095 3096 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) 3097 { 3098 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3099 3100 if (timer_table->tsf2_enabled) { 3101 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 3102 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 3103 } 3104 } 3105 3106 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3107 void (*trigger)(void *), 3108 void (*overflow)(void *), 3109 void *arg, 3110 u8 timer_index) 3111 { 3112 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3113 struct ath_gen_timer *timer; 3114 3115 if ((timer_index < AR_FIRST_NDP_TIMER) || 3116 (timer_index >= ATH_MAX_GEN_TIMER)) 3117 return NULL; 3118 3119 if ((timer_index > AR_FIRST_NDP_TIMER) && 3120 !AR_SREV_9300_20_OR_LATER(ah)) 3121 return NULL; 3122 3123 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3124 if (timer == NULL) 3125 return NULL; 3126 3127 /* allocate a hardware generic timer slot */ 3128 timer_table->timers[timer_index] = timer; 3129 timer->index = timer_index; 3130 timer->trigger = trigger; 3131 timer->overflow = overflow; 3132 timer->arg = arg; 3133 3134 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { 3135 timer_table->tsf2_enabled = true; 3136 ath9k_hw_gen_timer_start_tsf2(ah); 3137 } 3138 3139 return timer; 3140 } 3141 EXPORT_SYMBOL(ath_gen_timer_alloc); 3142 3143 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3144 struct ath_gen_timer *timer, 3145 u32 timer_next, 3146 u32 timer_period) 3147 { 3148 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3149 u32 mask = 0; 3150 3151 timer_table->timer_mask |= BIT(timer->index); 3152 3153 /* 3154 * Program generic timer registers 3155 */ 3156 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3157 timer_next); 3158 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3159 timer_period); 3160 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3161 gen_tmr_configuration[timer->index].mode_mask); 3162 3163 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3164 /* 3165 * Starting from AR9462, each generic timer can select which tsf 3166 * to use. But we still follow the old rule, 0 - 7 use tsf and 3167 * 8 - 15 use tsf2. 3168 */ 3169 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3170 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3171 (1 << timer->index)); 3172 else 3173 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3174 (1 << timer->index)); 3175 } 3176 3177 if (timer->trigger) 3178 mask |= SM(AR_GENTMR_BIT(timer->index), 3179 AR_IMR_S5_GENTIMER_TRIG); 3180 if (timer->overflow) 3181 mask |= SM(AR_GENTMR_BIT(timer->index), 3182 AR_IMR_S5_GENTIMER_THRESH); 3183 3184 REG_SET_BIT(ah, AR_IMR_S5, mask); 3185 3186 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { 3187 ah->imask |= ATH9K_INT_GENTIMER; 3188 ath9k_hw_set_interrupts(ah); 3189 } 3190 } 3191 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3192 3193 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3194 { 3195 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3196 3197 /* Clear generic timer enable bits. */ 3198 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3199 gen_tmr_configuration[timer->index].mode_mask); 3200 3201 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3202 /* 3203 * Need to switch back to TSF if it was using TSF2. 3204 */ 3205 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3206 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3207 (1 << timer->index)); 3208 } 3209 } 3210 3211 /* Disable both trigger and thresh interrupt masks */ 3212 REG_CLR_BIT(ah, AR_IMR_S5, 3213 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3214 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3215 3216 timer_table->timer_mask &= ~BIT(timer->index); 3217 3218 if (timer_table->timer_mask == 0) { 3219 ah->imask &= ~ATH9K_INT_GENTIMER; 3220 ath9k_hw_set_interrupts(ah); 3221 } 3222 } 3223 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3224 3225 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3226 { 3227 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3228 3229 /* free the hardware generic timer slot */ 3230 timer_table->timers[timer->index] = NULL; 3231 kfree(timer); 3232 } 3233 EXPORT_SYMBOL(ath_gen_timer_free); 3234 3235 /* 3236 * Generic Timer Interrupts handling 3237 */ 3238 void ath_gen_timer_isr(struct ath_hw *ah) 3239 { 3240 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3241 struct ath_gen_timer *timer; 3242 unsigned long trigger_mask, thresh_mask; 3243 unsigned int index; 3244 3245 /* get hardware generic timer interrupt status */ 3246 trigger_mask = ah->intr_gen_timer_trigger; 3247 thresh_mask = ah->intr_gen_timer_thresh; 3248 trigger_mask &= timer_table->timer_mask; 3249 thresh_mask &= timer_table->timer_mask; 3250 3251 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { 3252 timer = timer_table->timers[index]; 3253 if (!timer) 3254 continue; 3255 if (!timer->overflow) 3256 continue; 3257 3258 trigger_mask &= ~BIT(index); 3259 timer->overflow(timer->arg); 3260 } 3261 3262 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { 3263 timer = timer_table->timers[index]; 3264 if (!timer) 3265 continue; 3266 if (!timer->trigger) 3267 continue; 3268 timer->trigger(timer->arg); 3269 } 3270 } 3271 EXPORT_SYMBOL(ath_gen_timer_isr); 3272 3273 /********/ 3274 /* HTC */ 3275 /********/ 3276 3277 static struct { 3278 u32 version; 3279 const char * name; 3280 } ath_mac_bb_names[] = { 3281 /* Devices with external radios */ 3282 { AR_SREV_VERSION_5416_PCI, "5416" }, 3283 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3284 { AR_SREV_VERSION_9100, "9100" }, 3285 { AR_SREV_VERSION_9160, "9160" }, 3286 /* Single-chip solutions */ 3287 { AR_SREV_VERSION_9280, "9280" }, 3288 { AR_SREV_VERSION_9285, "9285" }, 3289 { AR_SREV_VERSION_9287, "9287" }, 3290 { AR_SREV_VERSION_9271, "9271" }, 3291 { AR_SREV_VERSION_9300, "9300" }, 3292 { AR_SREV_VERSION_9330, "9330" }, 3293 { AR_SREV_VERSION_9340, "9340" }, 3294 { AR_SREV_VERSION_9485, "9485" }, 3295 { AR_SREV_VERSION_9462, "9462" }, 3296 { AR_SREV_VERSION_9550, "9550" }, 3297 { AR_SREV_VERSION_9565, "9565" }, 3298 { AR_SREV_VERSION_9531, "9531" }, 3299 { AR_SREV_VERSION_9561, "9561" }, 3300 }; 3301 3302 /* For devices with external radios */ 3303 static struct { 3304 u16 version; 3305 const char * name; 3306 } ath_rf_names[] = { 3307 { 0, "5133" }, 3308 { AR_RAD5133_SREV_MAJOR, "5133" }, 3309 { AR_RAD5122_SREV_MAJOR, "5122" }, 3310 { AR_RAD2133_SREV_MAJOR, "2133" }, 3311 { AR_RAD2122_SREV_MAJOR, "2122" } 3312 }; 3313 3314 /* 3315 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3316 */ 3317 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3318 { 3319 int i; 3320 3321 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3322 if (ath_mac_bb_names[i].version == mac_bb_version) { 3323 return ath_mac_bb_names[i].name; 3324 } 3325 } 3326 3327 return "????"; 3328 } 3329 3330 /* 3331 * Return the RF name. "????" is returned if the RF is unknown. 3332 * Used for devices with external radios. 3333 */ 3334 static const char *ath9k_hw_rf_name(u16 rf_version) 3335 { 3336 int i; 3337 3338 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3339 if (ath_rf_names[i].version == rf_version) { 3340 return ath_rf_names[i].name; 3341 } 3342 } 3343 3344 return "????"; 3345 } 3346 3347 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3348 { 3349 int used; 3350 3351 /* chipsets >= AR9280 are single-chip */ 3352 if (AR_SREV_9280_20_OR_LATER(ah)) { 3353 used = scnprintf(hw_name, len, 3354 "Atheros AR%s Rev:%x", 3355 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3356 ah->hw_version.macRev); 3357 } 3358 else { 3359 used = scnprintf(hw_name, len, 3360 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3361 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3362 ah->hw_version.macRev, 3363 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3364 & AR_RADIO_SREV_MAJOR)), 3365 ah->hw_version.phyRev); 3366 } 3367 3368 hw_name[used] = '\0'; 3369 } 3370 EXPORT_SYMBOL(ath9k_hw_name); 3371