1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "hal_rx.h" 11 #include "hw.h" 12 13 #define MAX_RXDMA_PER_PDEV 2 14 15 struct ath12k_base; 16 struct ath12k_peer; 17 struct ath12k_dp; 18 struct ath12k_vif; 19 struct hal_tcl_status_ring; 20 struct ath12k_ext_irq_grp; 21 22 #define DP_MON_PURGE_TIMEOUT_MS 100 23 #define DP_MON_SERVICE_BUDGET 128 24 25 struct dp_srng { 26 u32 *vaddr_unaligned; 27 u32 *vaddr; 28 dma_addr_t paddr_unaligned; 29 dma_addr_t paddr; 30 int size; 31 u32 ring_id; 32 }; 33 34 struct dp_rxdma_mon_ring { 35 struct dp_srng refill_buf_ring; 36 struct idr bufs_idr; 37 /* Protects bufs_idr */ 38 spinlock_t idr_lock; 39 int bufs_max; 40 }; 41 42 struct dp_rxdma_ring { 43 struct dp_srng refill_buf_ring; 44 int bufs_max; 45 }; 46 47 #define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 48 49 struct dp_tx_ring { 50 u8 tcl_data_ring_id; 51 struct dp_srng tcl_data_ring; 52 struct dp_srng tcl_comp_ring; 53 struct hal_wbm_completion_ring_tx *tx_status; 54 int tx_status_head; 55 int tx_status_tail; 56 }; 57 58 struct ath12k_pdev_mon_stats { 59 u32 status_ppdu_state; 60 u32 status_ppdu_start; 61 u32 status_ppdu_end; 62 u32 status_ppdu_compl; 63 u32 status_ppdu_start_mis; 64 u32 status_ppdu_end_mis; 65 u32 status_ppdu_done; 66 u32 dest_ppdu_done; 67 u32 dest_mpdu_done; 68 u32 dest_mpdu_drop; 69 u32 dup_mon_linkdesc_cnt; 70 u32 dup_mon_buf_cnt; 71 }; 72 73 struct dp_link_desc_bank { 74 void *vaddr_unaligned; 75 void *vaddr; 76 dma_addr_t paddr_unaligned; 77 dma_addr_t paddr; 78 u32 size; 79 }; 80 81 /* Size to enforce scatter idle list mode */ 82 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 83 #define DP_LINK_DESC_BANKS_MAX 8 84 85 #define DP_LINK_DESC_START 0x4000 86 #define DP_LINK_DESC_SHIFT 3 87 88 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 89 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 90 91 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 92 93 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 94 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 95 #define DP_RX_DESC_COOKIE_MAX \ 96 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 97 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 98 99 enum ath12k_dp_ppdu_state { 100 DP_PPDU_STATUS_START, 101 DP_PPDU_STATUS_DONE, 102 }; 103 104 struct dp_mon_mpdu { 105 struct list_head list; 106 struct sk_buff *head; 107 struct sk_buff *tail; 108 }; 109 110 #define DP_MON_MAX_STATUS_BUF 32 111 112 struct ath12k_mon_data { 113 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 114 struct hal_rx_mon_ppdu_info mon_ppdu_info; 115 116 u32 mon_ppdu_status; 117 u32 mon_last_buf_cookie; 118 u64 mon_last_linkdesc_paddr; 119 u16 chan_noise_floor; 120 121 struct ath12k_pdev_mon_stats rx_mon_stats; 122 /* lock for monitor data */ 123 spinlock_t mon_lock; 124 struct sk_buff_head rx_status_q; 125 struct dp_mon_mpdu *mon_mpdu; 126 struct list_head dp_rx_mon_mpdu_list; 127 struct sk_buff *dest_skb_q[DP_MON_MAX_STATUS_BUF]; 128 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 129 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 130 }; 131 132 struct ath12k_pdev_dp { 133 u32 mac_id; 134 atomic_t num_tx_pending; 135 wait_queue_head_t tx_empty_waitq; 136 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 137 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 138 139 struct ieee80211_rx_status rx_status; 140 struct ath12k_mon_data mon_data; 141 }; 142 143 #define DP_NUM_CLIENTS_MAX 64 144 #define DP_AVG_TIDS_PER_CLIENT 2 145 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 146 #define DP_AVG_MSDUS_PER_FLOW 128 147 #define DP_AVG_FLOWS_PER_TID 2 148 #define DP_AVG_MPDUS_PER_TID_MAX 128 149 #define DP_AVG_MSDUS_PER_MPDU 4 150 151 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 152 153 #define DP_BA_WIN_SZ_MAX 256 154 155 #define DP_TCL_NUM_RING_MAX 4 156 157 #define DP_IDLE_SCATTER_BUFS_MAX 16 158 159 #define DP_WBM_RELEASE_RING_SIZE 64 160 #define DP_TCL_DATA_RING_SIZE 512 161 #define DP_TX_COMP_RING_SIZE 32768 162 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 163 #define DP_TCL_CMD_RING_SIZE 32 164 #define DP_TCL_STATUS_RING_SIZE 32 165 #define DP_REO_DST_RING_MAX 8 166 #define DP_REO_DST_RING_SIZE 2048 167 #define DP_REO_REINJECT_RING_SIZE 32 168 #define DP_RX_RELEASE_RING_SIZE 1024 169 #define DP_REO_EXCEPTION_RING_SIZE 128 170 #define DP_REO_CMD_RING_SIZE 128 171 #define DP_REO_STATUS_RING_SIZE 2048 172 #define DP_RXDMA_BUF_RING_SIZE 4096 173 #define DP_RXDMA_REFILL_RING_SIZE 2048 174 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 175 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 176 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 177 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 178 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 179 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 180 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 181 182 #define DP_TX_MONITOR_BUF_SIZE 2048 183 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 184 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 185 186 #define DP_RX_BUFFER_SIZE 2048 187 #define DP_RX_BUFFER_SIZE_LITE 1024 188 #define DP_RX_BUFFER_ALIGN_SIZE 128 189 190 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 191 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 192 193 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 194 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 195 196 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 197 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 198 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 199 200 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 201 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 202 203 #define ATH12K_NUM_POOL_TX_DESC 32768 204 205 /* TODO: revisit this count during testing */ 206 #define ATH12K_RX_DESC_COUNT (12288) 207 208 #define ATH12K_PAGE_SIZE PAGE_SIZE 209 210 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 211 * SPT pages which makes lower 12bits 0 212 */ 213 #define ATH12K_MAX_PPT_ENTRIES 1024 214 215 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 216 #define ATH12K_MAX_SPT_ENTRIES 512 217 218 #define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES) 219 220 #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ 221 ATH12K_MAX_SPT_ENTRIES) 222 #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) 223 #define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) 224 225 /* The SPT pages are divided for RX and TX, first block for RX 226 * and remaining for TX 227 */ 228 #define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES 229 230 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 231 232 /* 4K aligned address have last 12 bits set to 0, this check is done 233 * so that two spt pages address can be stored per 8bytes 234 * of CMEM (PPT) 235 */ 236 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 237 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 238 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 239 240 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 241 #define ATH12K_CMEM_ADDR_MSB 0x10 242 243 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 244 #define ATH12K_CC_SPT_MSB 8 245 #define ATH12K_CC_PPT_MSB 19 246 #define ATH12K_CC_PPT_SHIFT 9 247 #define ATH12k_DP_CC_COOKIE_SPT GENMASK(8, 0) 248 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 249 250 #define DP_REO_QREF_NUM GENMASK(31, 16) 251 #define DP_MAX_PEER_ID 2047 252 253 /* Total size of the LUT is based on 2K peers, each having reference 254 * for 17tids, note each entry is of type ath12k_reo_queue_ref 255 * hence total size is 2048 * 17 * 8 = 278528 256 */ 257 #define DP_REOQ_LUT_SIZE 278528 258 259 /* Invalid TX Bank ID value */ 260 #define DP_INVALID_BANK_ID -1 261 262 struct ath12k_dp_tx_bank_profile { 263 u8 is_configured; 264 u32 num_users; 265 u32 bank_config; 266 }; 267 268 struct ath12k_hp_update_timer { 269 struct timer_list timer; 270 bool started; 271 bool init; 272 u32 tx_num; 273 u32 timer_tx_num; 274 u32 ring_id; 275 u32 interval; 276 struct ath12k_base *ab; 277 }; 278 279 struct ath12k_rx_desc_info { 280 struct list_head list; 281 struct sk_buff *skb; 282 u32 cookie; 283 u32 magic; 284 }; 285 286 struct ath12k_tx_desc_info { 287 struct list_head list; 288 struct sk_buff *skb; 289 u32 desc_id; /* Cookie */ 290 u8 mac_id; 291 u8 pool_id; 292 }; 293 294 struct ath12k_spt_info { 295 dma_addr_t paddr; 296 u64 *vaddr; 297 struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; 298 struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; 299 }; 300 301 struct ath12k_reo_queue_ref { 302 u32 info0; 303 u32 info1; 304 } __packed; 305 306 struct ath12k_reo_q_addr_lut { 307 dma_addr_t paddr; 308 u32 *vaddr; 309 }; 310 311 struct ath12k_dp { 312 struct ath12k_base *ab; 313 u8 num_bank_profiles; 314 /* protects the access and update of bank_profiles */ 315 spinlock_t tx_bank_lock; 316 struct ath12k_dp_tx_bank_profile *bank_profiles; 317 enum ath12k_htc_ep_id eid; 318 struct completion htt_tgt_version_received; 319 u8 htt_tgt_ver_major; 320 u8 htt_tgt_ver_minor; 321 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 322 struct dp_srng wbm_idle_ring; 323 struct dp_srng wbm_desc_rel_ring; 324 struct dp_srng tcl_cmd_ring; 325 struct dp_srng tcl_status_ring; 326 struct dp_srng reo_reinject_ring; 327 struct dp_srng rx_rel_ring; 328 struct dp_srng reo_except_ring; 329 struct dp_srng reo_cmd_ring; 330 struct dp_srng reo_status_ring; 331 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 332 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 333 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 334 struct list_head reo_cmd_list; 335 struct list_head reo_cmd_cache_flush_list; 336 u32 reo_cmd_cache_flush_count; 337 338 /* protects access to below fields, 339 * - reo_cmd_list 340 * - reo_cmd_cache_flush_list 341 * - reo_cmd_cache_flush_count 342 */ 343 spinlock_t reo_cmd_lock; 344 struct ath12k_hp_update_timer reo_cmd_timer; 345 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 346 struct ath12k_spt_info *spt_info; 347 u32 num_spt_pages; 348 struct list_head rx_desc_free_list; 349 struct list_head rx_desc_used_list; 350 /* protects the free and used desc list */ 351 spinlock_t rx_desc_lock; 352 353 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 354 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 355 /* protects the free and used desc lists */ 356 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 357 358 struct dp_rxdma_ring rx_refill_buf_ring; 359 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 360 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 361 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 362 struct dp_rxdma_mon_ring tx_mon_buf_ring; 363 struct ath12k_reo_q_addr_lut reoq_lut; 364 }; 365 366 /* HTT definitions */ 367 368 #define HTT_TCL_META_DATA_TYPE BIT(0) 369 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 370 371 /* vdev meta data */ 372 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 373 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 374 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 375 376 /* peer meta data */ 377 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 378 379 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 380 381 /* HTT tx completion is overlaid in wbm_release_ring */ 382 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 383 #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 384 #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 385 386 #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 387 388 struct htt_tx_wbm_completion { 389 __le32 rsvd0[2]; 390 __le32 info0; 391 __le32 info1; 392 __le32 info2; 393 __le32 info3; 394 __le32 info4; 395 __le32 rsvd1; 396 397 } __packed; 398 399 enum htt_h2t_msg_type { 400 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 401 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 402 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 403 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 404 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 405 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 406 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 407 }; 408 409 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 410 411 struct htt_ver_req_cmd { 412 __le32 ver_reg_info; 413 } __packed; 414 415 enum htt_srng_ring_type { 416 HTT_HW_TO_SW_RING, 417 HTT_SW_TO_HW_RING, 418 HTT_SW_TO_SW_RING, 419 }; 420 421 enum htt_srng_ring_id { 422 HTT_RXDMA_HOST_BUF_RING, 423 HTT_RXDMA_MONITOR_STATUS_RING, 424 HTT_RXDMA_MONITOR_BUF_RING, 425 HTT_RXDMA_MONITOR_DESC_RING, 426 HTT_RXDMA_MONITOR_DEST_RING, 427 HTT_HOST1_TO_FW_RXBUF_RING, 428 HTT_HOST2_TO_FW_RXBUF_RING, 429 HTT_RXDMA_NON_MONITOR_DEST_RING, 430 HTT_TX_MON_HOST2MON_BUF_RING, 431 HTT_TX_MON_MON2HOST_DEST_RING, 432 }; 433 434 /* host -> target HTT_SRING_SETUP message 435 * 436 * After target is booted up, Host can send SRING setup message for 437 * each host facing LMAC SRING. Target setups up HW registers based 438 * on setup message and confirms back to Host if response_required is set. 439 * Host should wait for confirmation message before sending new SRING 440 * setup message 441 * 442 * The message would appear as follows: 443 * 444 * |31 24|23 20|19|18 16|15|14 8|7 0| 445 * |--------------- +-----------------+----------------+------------------| 446 * | ring_type | ring_id | pdev_id | msg_type | 447 * |----------------------------------------------------------------------| 448 * | ring_base_addr_lo | 449 * |----------------------------------------------------------------------| 450 * | ring_base_addr_hi | 451 * |----------------------------------------------------------------------| 452 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 453 * |----------------------------------------------------------------------| 454 * | ring_head_offset32_remote_addr_lo | 455 * |----------------------------------------------------------------------| 456 * | ring_head_offset32_remote_addr_hi | 457 * |----------------------------------------------------------------------| 458 * | ring_tail_offset32_remote_addr_lo | 459 * |----------------------------------------------------------------------| 460 * | ring_tail_offset32_remote_addr_hi | 461 * |----------------------------------------------------------------------| 462 * | ring_msi_addr_lo | 463 * |----------------------------------------------------------------------| 464 * | ring_msi_addr_hi | 465 * |----------------------------------------------------------------------| 466 * | ring_msi_data | 467 * |----------------------------------------------------------------------| 468 * | intr_timer_th |IM| intr_batch_counter_th | 469 * |----------------------------------------------------------------------| 470 * | reserved |RR|PTCF| intr_low_threshold | 471 * |----------------------------------------------------------------------| 472 * Where 473 * IM = sw_intr_mode 474 * RR = response_required 475 * PTCF = prefetch_timer_cfg 476 * 477 * The message is interpreted as follows: 478 * dword0 - b'0:7 - msg_type: This will be set to 479 * HTT_H2T_MSG_TYPE_SRING_SETUP 480 * b'8:15 - pdev_id: 481 * 0 (for rings at SOC/UMAC level), 482 * 1/2/3 mac id (for rings at LMAC level) 483 * b'16:23 - ring_id: identify which ring is to setup, 484 * more details can be got from enum htt_srng_ring_id 485 * b'24:31 - ring_type: identify type of host rings, 486 * more details can be got from enum htt_srng_ring_type 487 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 488 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 489 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 490 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 491 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 492 * SW_TO_HW_RING. 493 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 494 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 495 * Lower 32 bits of memory address of the remote variable 496 * storing the 4-byte word offset that identifies the head 497 * element within the ring. 498 * (The head offset variable has type u32.) 499 * Valid for HW_TO_SW and SW_TO_SW rings. 500 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 501 * Upper 32 bits of memory address of the remote variable 502 * storing the 4-byte word offset that identifies the head 503 * element within the ring. 504 * (The head offset variable has type u32.) 505 * Valid for HW_TO_SW and SW_TO_SW rings. 506 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 507 * Lower 32 bits of memory address of the remote variable 508 * storing the 4-byte word offset that identifies the tail 509 * element within the ring. 510 * (The tail offset variable has type u32.) 511 * Valid for HW_TO_SW and SW_TO_SW rings. 512 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 513 * Upper 32 bits of memory address of the remote variable 514 * storing the 4-byte word offset that identifies the tail 515 * element within the ring. 516 * (The tail offset variable has type u32.) 517 * Valid for HW_TO_SW and SW_TO_SW rings. 518 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 519 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 520 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 521 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 522 * dword10 - b'0:31 - ring_msi_data: MSI data 523 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 524 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 525 * dword11 - b'0:14 - intr_batch_counter_th: 526 * batch counter threshold is in units of 4-byte words. 527 * HW internally maintains and increments batch count. 528 * (see SRING spec for detail description). 529 * When batch count reaches threshold value, an interrupt 530 * is generated by HW. 531 * b'15 - sw_intr_mode: 532 * This configuration shall be static. 533 * Only programmed at power up. 534 * 0: generate pulse style sw interrupts 535 * 1: generate level style sw interrupts 536 * b'16:31 - intr_timer_th: 537 * The timer init value when timer is idle or is 538 * initialized to start downcounting. 539 * In 8us units (to cover a range of 0 to 524 ms) 540 * dword12 - b'0:15 - intr_low_threshold: 541 * Used only by Consumer ring to generate ring_sw_int_p. 542 * Ring entries low threshold water mark, that is used 543 * in combination with the interrupt timer as well as 544 * the clearing of the level interrupt. 545 * b'16:18 - prefetch_timer_cfg: 546 * Used only by Consumer ring to set timer mode to 547 * support Application prefetch handling. 548 * The external tail offset/pointer will be updated 549 * at following intervals: 550 * 3'b000: (Prefetch feature disabled; used only for debug) 551 * 3'b001: 1 usec 552 * 3'b010: 4 usec 553 * 3'b011: 8 usec (default) 554 * 3'b100: 16 usec 555 * Others: Reserved 556 * b'19 - response_required: 557 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 558 * b'20:31 - reserved: reserved for future use 559 */ 560 561 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 562 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 563 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 564 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 565 566 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 567 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 568 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 569 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 570 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 571 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 572 573 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 574 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 575 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 576 577 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 578 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 579 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 580 581 struct htt_srng_setup_cmd { 582 __le32 info0; 583 __le32 ring_base_addr_lo; 584 __le32 ring_base_addr_hi; 585 __le32 info1; 586 __le32 ring_head_off32_remote_addr_lo; 587 __le32 ring_head_off32_remote_addr_hi; 588 __le32 ring_tail_off32_remote_addr_lo; 589 __le32 ring_tail_off32_remote_addr_hi; 590 __le32 ring_msi_addr_lo; 591 __le32 ring_msi_addr_hi; 592 __le32 msi_data; 593 __le32 intr_info; 594 __le32 info2; 595 } __packed; 596 597 /* host -> target FW PPDU_STATS config message 598 * 599 * @details 600 * The following field definitions describe the format of the HTT host 601 * to target FW for PPDU_STATS_CFG msg. 602 * The message allows the host to configure the PPDU_STATS_IND messages 603 * produced by the target. 604 * 605 * |31 24|23 16|15 8|7 0| 606 * |-----------------------------------------------------------| 607 * | REQ bit mask | pdev_mask | msg type | 608 * |-----------------------------------------------------------| 609 * Header fields: 610 * - MSG_TYPE 611 * Bits 7:0 612 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 613 * Value: 0x11 614 * - PDEV_MASK 615 * Bits 8:15 616 * Purpose: identifies which pdevs this PPDU stats configuration applies to 617 * Value: This is a overloaded field, refer to usage and interpretation of 618 * PDEV in interface document. 619 * Bit 8 : Reserved for SOC stats 620 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 621 * Indicates MACID_MASK in DBS 622 * - REQ_TLV_BIT_MASK 623 * Bits 16:31 624 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 625 * needs to be included in the target's PPDU_STATS_IND messages. 626 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 627 * 628 */ 629 630 struct htt_ppdu_stats_cfg_cmd { 631 __le32 msg; 632 } __packed; 633 634 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 635 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 636 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 637 638 enum htt_ppdu_stats_tag_type { 639 HTT_PPDU_STATS_TAG_COMMON, 640 HTT_PPDU_STATS_TAG_USR_COMMON, 641 HTT_PPDU_STATS_TAG_USR_RATE, 642 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 643 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 644 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 645 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 646 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 647 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 648 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 649 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 650 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 651 HTT_PPDU_STATS_TAG_INFO, 652 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 653 654 /* New TLV's are added above to this line */ 655 HTT_PPDU_STATS_TAG_MAX, 656 }; 657 658 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 659 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 660 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 661 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 662 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 663 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 664 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 665 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 666 667 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 668 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 669 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 670 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 671 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 672 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 673 HTT_PPDU_STATS_TAG_DEFAULT) 674 675 enum htt_stats_internal_ppdu_frametype { 676 HTT_STATS_PPDU_FTYPE_CTRL, 677 HTT_STATS_PPDU_FTYPE_DATA, 678 HTT_STATS_PPDU_FTYPE_BAR, 679 HTT_STATS_PPDU_FTYPE_MAX 680 }; 681 682 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 683 * 684 * details: 685 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 686 * configure RXDMA rings. 687 * The configuration is per ring based and includes both packet subtypes 688 * and PPDU/MPDU TLVs. 689 * 690 * The message would appear as follows: 691 * 692 * |31 26|25|24|23 16|15 8|7 0| 693 * |-----------------+----------------+----------------+---------------| 694 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 695 * |-------------------------------------------------------------------| 696 * | rsvd2 | ring_buffer_size | 697 * |-------------------------------------------------------------------| 698 * | packet_type_enable_flags_0 | 699 * |-------------------------------------------------------------------| 700 * | packet_type_enable_flags_1 | 701 * |-------------------------------------------------------------------| 702 * | packet_type_enable_flags_2 | 703 * |-------------------------------------------------------------------| 704 * | packet_type_enable_flags_3 | 705 * |-------------------------------------------------------------------| 706 * | tlv_filter_in_flags | 707 * |-------------------------------------------------------------------| 708 * Where: 709 * PS = pkt_swap 710 * SS = status_swap 711 * The message is interpreted as follows: 712 * dword0 - b'0:7 - msg_type: This will be set to 713 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 714 * b'8:15 - pdev_id: 715 * 0 (for rings at SOC/UMAC level), 716 * 1/2/3 mac id (for rings at LMAC level) 717 * b'16:23 - ring_id : Identify the ring to configure. 718 * More details can be got from enum htt_srng_ring_id 719 * b'24 - status_swap: 1 is to swap status TLV 720 * b'25 - pkt_swap: 1 is to swap packet TLV 721 * b'26:31 - rsvd1: reserved for future use 722 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 723 * in byte units. 724 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 725 * - b'16:31 - rsvd2: Reserved for future use 726 * dword2 - b'0:31 - packet_type_enable_flags_0: 727 * Enable MGMT packet from 0b0000 to 0b1001 728 * bits from low to high: FP, MD, MO - 3 bits 729 * FP: Filter_Pass 730 * MD: Monitor_Direct 731 * MO: Monitor_Other 732 * 10 mgmt subtypes * 3 bits -> 30 bits 733 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 734 * dword3 - b'0:31 - packet_type_enable_flags_1: 735 * Enable MGMT packet from 0b1010 to 0b1111 736 * bits from low to high: FP, MD, MO - 3 bits 737 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 738 * dword4 - b'0:31 - packet_type_enable_flags_2: 739 * Enable CTRL packet from 0b0000 to 0b1001 740 * bits from low to high: FP, MD, MO - 3 bits 741 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 742 * dword5 - b'0:31 - packet_type_enable_flags_3: 743 * Enable CTRL packet from 0b1010 to 0b1111, 744 * MCAST_DATA, UCAST_DATA, NULL_DATA 745 * bits from low to high: FP, MD, MO - 3 bits 746 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 747 * dword6 - b'0:31 - tlv_filter_in_flags: 748 * Filter in Attention/MPDU/PPDU/Header/User tlvs 749 * Refer to CFG_TLV_FILTER_IN_FLAG defs 750 */ 751 752 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 753 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 754 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 755 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 756 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 757 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 758 #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26) 759 760 #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 761 #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 762 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 763 #define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 764 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 765 #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 766 #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 767 768 enum htt_rx_filter_tlv_flags { 769 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 770 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 771 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 772 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 773 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 774 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 775 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 776 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 777 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 778 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 779 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 780 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 781 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 782 }; 783 784 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 785 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 786 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 787 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 788 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 789 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 790 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 791 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 792 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 793 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 794 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 795 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 796 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 797 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 798 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 799 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 800 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 801 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 802 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 803 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 804 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 805 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 806 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 807 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 808 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 809 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 810 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 811 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 812 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 813 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 814 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 815 }; 816 817 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 818 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 819 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 820 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 821 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 822 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 823 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 824 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 825 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 826 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 827 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 828 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 829 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 830 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 831 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 832 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 833 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 834 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 835 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 836 }; 837 838 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 839 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 840 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 841 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 842 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 843 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 844 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 845 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 846 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 847 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 848 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 849 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 850 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 851 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 852 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 853 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 854 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 855 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 856 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 857 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 858 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 859 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 860 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 861 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 862 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 863 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 864 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 865 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 866 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 867 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 868 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 869 }; 870 871 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 872 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 873 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 874 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 875 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 876 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 877 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 878 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 879 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 880 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 881 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 882 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 883 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 884 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 885 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 886 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 888 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 889 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 890 }; 891 892 enum htt_rx_data_pkt_filter_tlv_flasg3 { 893 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 894 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 895 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 896 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 897 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 898 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 899 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 900 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 901 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 902 }; 903 904 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 905 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 906 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 907 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 908 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 909 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 910 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 911 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 912 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 913 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 914 915 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 916 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 917 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 918 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 919 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 920 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 921 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 922 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 923 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 924 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 925 926 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 927 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 928 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 929 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 930 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 931 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 932 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 933 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 934 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 935 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 936 937 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 938 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 939 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 940 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 941 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 942 943 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 944 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 945 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 946 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 947 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 948 949 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 950 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 951 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 952 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 953 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 954 955 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 956 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 957 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 958 959 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 960 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 961 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 962 963 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 964 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 965 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 966 967 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 968 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 969 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 970 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 971 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 972 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 973 974 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 975 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 976 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 977 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 978 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 979 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 980 981 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 982 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 983 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 984 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 985 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 986 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 987 988 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 989 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 990 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 991 992 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 993 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 994 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 995 996 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 997 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 998 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 999 1000 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1001 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1002 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1003 1004 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1005 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1006 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1007 1008 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1009 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1010 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1011 1012 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1013 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1014 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1015 1016 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1017 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1018 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1019 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1020 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1021 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1022 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1023 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1024 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1025 1026 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1027 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1028 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1029 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1030 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1031 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1032 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1033 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1034 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1035 1036 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1037 1038 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1039 1040 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1041 1042 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1043 1044 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 1045 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1046 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1047 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1048 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1049 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1050 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1051 1052 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1053 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1054 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1055 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1056 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1057 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1058 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1059 1060 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1061 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1062 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1063 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1064 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1065 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1066 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1067 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1068 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1069 1070 /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1071 #define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1072 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1073 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1074 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1075 1076 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1077 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1078 1079 struct htt_rx_ring_selection_cfg_cmd { 1080 __le32 info0; 1081 __le32 info1; 1082 __le32 pkt_type_en_flags0; 1083 __le32 pkt_type_en_flags1; 1084 __le32 pkt_type_en_flags2; 1085 __le32 pkt_type_en_flags3; 1086 __le32 rx_filter_tlv; 1087 __le32 rx_packet_offset; 1088 __le32 rx_mpdu_offset; 1089 __le32 rx_msdu_offset; 1090 __le32 rx_attn_offset; 1091 } __packed; 1092 1093 struct htt_rx_ring_tlv_filter { 1094 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1095 u32 pkt_filter_flags0; /* MGMT */ 1096 u32 pkt_filter_flags1; /* MGMT */ 1097 u32 pkt_filter_flags2; /* CTRL */ 1098 u32 pkt_filter_flags3; /* DATA */ 1099 bool offset_valid; 1100 u16 rx_packet_offset; 1101 u16 rx_header_offset; 1102 u16 rx_mpdu_end_offset; 1103 u16 rx_mpdu_start_offset; 1104 u16 rx_msdu_end_offset; 1105 u16 rx_msdu_start_offset; 1106 u16 rx_attn_offset; 1107 }; 1108 1109 #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1110 #define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1111 #define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1112 #define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1113 1114 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1115 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1116 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1117 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1118 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1119 1120 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1121 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1122 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1123 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1124 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1125 1126 #define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1127 1128 struct htt_tx_ring_selection_cfg_cmd { 1129 __le32 info0; 1130 __le32 info1; 1131 __le32 info2; 1132 __le32 tlv_filter_mask_in0; 1133 __le32 tlv_filter_mask_in1; 1134 __le32 tlv_filter_mask_in2; 1135 __le32 tlv_filter_mask_in3; 1136 __le32 reserved[3]; 1137 } __packed; 1138 1139 #define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1140 #define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1141 #define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1142 1143 #define HTT_TX_MON_FILTER_HYBRID_MODE \ 1144 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1145 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1146 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1147 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1148 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1149 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1150 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1151 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1152 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1153 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1154 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1155 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1156 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1157 1158 struct htt_tx_ring_tlv_filter { 1159 u32 tx_mon_downstream_tlv_flags; 1160 u32 tx_mon_upstream_tlv_flags0; 1161 u32 tx_mon_upstream_tlv_flags1; 1162 u32 tx_mon_upstream_tlv_flags2; 1163 bool tx_mon_mgmt_filter; 1164 bool tx_mon_data_filter; 1165 bool tx_mon_ctrl_filter; 1166 u16 tx_mon_pkt_dma_len; 1167 } __packed; 1168 1169 enum htt_tx_mon_upstream_tlv_flags0 { 1170 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1171 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1172 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1173 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1174 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1175 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1176 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1177 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1178 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1179 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1180 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1181 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1182 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1183 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1184 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1185 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1186 }; 1187 1188 #define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1189 1190 /* HTT message target->host */ 1191 1192 enum htt_t2h_msg_type { 1193 HTT_T2H_MSG_TYPE_VERSION_CONF, 1194 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1195 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1196 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1197 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1198 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1199 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1200 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1201 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1202 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1203 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1204 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1205 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1206 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1207 }; 1208 1209 #define HTT_TARGET_VERSION_MAJOR 3 1210 1211 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1212 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1213 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1214 1215 struct htt_t2h_version_conf_msg { 1216 __le32 version; 1217 } __packed; 1218 1219 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1220 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1221 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1222 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1223 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1224 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1225 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1226 1227 struct htt_t2h_peer_map_event { 1228 __le32 info; 1229 __le32 mac_addr_l32; 1230 __le32 info1; 1231 __le32 info2; 1232 } __packed; 1233 1234 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1235 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1236 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1237 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1238 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1239 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1240 1241 struct htt_t2h_peer_unmap_event { 1242 __le32 info; 1243 __le32 mac_addr_l32; 1244 __le32 info1; 1245 } __packed; 1246 1247 struct htt_resp_msg { 1248 union { 1249 struct htt_t2h_version_conf_msg version_msg; 1250 struct htt_t2h_peer_map_event peer_map_ev; 1251 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1252 }; 1253 } __packed; 1254 1255 #define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1256 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1257 #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1258 #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1259 #define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1260 #define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1261 #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1262 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1263 1264 struct htt_t2h_vdev_txrx_stats_ind { 1265 __le32 vdev_id; 1266 __le32 rx_msdu_byte_cnt_lo; 1267 __le32 rx_msdu_byte_cnt_hi; 1268 __le32 rx_msdu_cnt_lo; 1269 __le32 rx_msdu_cnt_hi; 1270 __le32 tx_msdu_byte_cnt_lo; 1271 __le32 tx_msdu_byte_cnt_hi; 1272 __le32 tx_msdu_cnt_lo; 1273 __le32 tx_msdu_cnt_hi; 1274 __le32 tx_retry_cnt_lo; 1275 __le32 tx_retry_cnt_hi; 1276 __le32 tx_retry_byte_cnt_lo; 1277 __le32 tx_retry_byte_cnt_hi; 1278 __le32 tx_drop_cnt_lo; 1279 __le32 tx_drop_cnt_hi; 1280 __le32 tx_drop_byte_cnt_lo; 1281 __le32 tx_drop_byte_cnt_hi; 1282 __le32 msdu_ttl_cnt_lo; 1283 __le32 msdu_ttl_cnt_hi; 1284 __le32 msdu_ttl_byte_cnt_lo; 1285 __le32 msdu_ttl_byte_cnt_hi; 1286 } __packed; 1287 1288 struct htt_t2h_vdev_common_stats_tlv { 1289 __le32 soc_drop_count_lo; 1290 __le32 soc_drop_count_hi; 1291 } __packed; 1292 1293 /* ppdu stats 1294 * 1295 * @details 1296 * The following field definitions describe the format of the HTT target 1297 * to host ppdu stats indication message. 1298 * 1299 * 1300 * |31 16|15 12|11 10|9 8|7 0 | 1301 * |----------------------------------------------------------------------| 1302 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1303 * |----------------------------------------------------------------------| 1304 * | ppdu_id | 1305 * |----------------------------------------------------------------------| 1306 * | Timestamp in us | 1307 * |----------------------------------------------------------------------| 1308 * | reserved | 1309 * |----------------------------------------------------------------------| 1310 * | type-specific stats info | 1311 * | (see htt_ppdu_stats.h) | 1312 * |----------------------------------------------------------------------| 1313 * Header fields: 1314 * - MSG_TYPE 1315 * Bits 7:0 1316 * Purpose: Identifies this is a PPDU STATS indication 1317 * message. 1318 * Value: 0x1d 1319 * - mac_id 1320 * Bits 9:8 1321 * Purpose: mac_id of this ppdu_id 1322 * Value: 0-3 1323 * - pdev_id 1324 * Bits 11:10 1325 * Purpose: pdev_id of this ppdu_id 1326 * Value: 0-3 1327 * 0 (for rings at SOC level), 1328 * 1/2/3 PDEV -> 0/1/2 1329 * - payload_size 1330 * Bits 31:16 1331 * Purpose: total tlv size 1332 * Value: payload_size in bytes 1333 */ 1334 1335 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1336 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1337 1338 struct ath12k_htt_ppdu_stats_msg { 1339 __le32 info; 1340 __le32 ppdu_id; 1341 __le32 timestamp; 1342 __le32 rsvd; 1343 u8 data[]; 1344 } __packed; 1345 1346 struct htt_tlv { 1347 __le32 header; 1348 u8 value[]; 1349 } __packed; 1350 1351 #define HTT_TLV_TAG GENMASK(11, 0) 1352 #define HTT_TLV_LEN GENMASK(23, 12) 1353 1354 enum HTT_PPDU_STATS_BW { 1355 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1356 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1357 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1358 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1359 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1360 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1361 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1362 }; 1363 1364 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1365 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1366 /* bw - HTT_PPDU_STATS_BW */ 1367 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1368 1369 struct htt_ppdu_stats_common { 1370 __le32 ppdu_id; 1371 __le16 sched_cmdid; 1372 u8 ring_id; 1373 u8 num_users; 1374 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1375 __le32 chain_mask; 1376 __le32 fes_duration_us; /* frame exchange sequence */ 1377 __le32 ppdu_sch_eval_start_tstmp_us; 1378 __le32 ppdu_sch_end_tstmp_us; 1379 __le32 ppdu_start_tstmp_us; 1380 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1381 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1382 */ 1383 __le16 phy_mode; 1384 __le16 bw_mhz; 1385 } __packed; 1386 1387 enum htt_ppdu_stats_gi { 1388 HTT_PPDU_STATS_SGI_0_8_US, 1389 HTT_PPDU_STATS_SGI_0_4_US, 1390 HTT_PPDU_STATS_SGI_1_6_US, 1391 HTT_PPDU_STATS_SGI_3_2_US, 1392 }; 1393 1394 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1395 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1396 1397 enum HTT_PPDU_STATS_PPDU_TYPE { 1398 HTT_PPDU_STATS_PPDU_TYPE_SU, 1399 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1400 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1401 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1402 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1403 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1404 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1405 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1406 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1407 HTT_PPDU_STATS_PPDU_TYPE_MAX 1408 }; 1409 1410 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1411 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1412 1413 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1414 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1415 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1416 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1417 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1418 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1419 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1420 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1421 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1422 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1423 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1424 1425 #define HTT_USR_RATE_PREAMBLE(_val) \ 1426 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1427 #define HTT_USR_RATE_BW(_val) \ 1428 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1429 #define HTT_USR_RATE_NSS(_val) \ 1430 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1431 #define HTT_USR_RATE_MCS(_val) \ 1432 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1433 #define HTT_USR_RATE_GI(_val) \ 1434 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1435 #define HTT_USR_RATE_DCM(_val) \ 1436 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1437 1438 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1439 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1440 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1441 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1442 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1443 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1444 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1445 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1446 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1447 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1448 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1449 1450 struct htt_ppdu_stats_user_rate { 1451 u8 tid_num; 1452 u8 reserved0; 1453 __le16 sw_peer_id; 1454 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1455 __le16 ru_end; 1456 __le16 ru_start; 1457 __le16 resp_ru_end; 1458 __le16 resp_ru_start; 1459 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1460 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1461 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1462 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1463 } __packed; 1464 1465 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1466 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1467 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1468 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1469 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1470 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1471 1472 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1473 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1474 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1475 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1476 #define HTT_TX_INFO_RATECODE(_flags) \ 1477 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1478 #define HTT_TX_INFO_PEERID(_flags) \ 1479 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1480 1481 struct htt_tx_ppdu_stats_info { 1482 struct htt_tlv tlv_hdr; 1483 __le32 tx_success_bytes; 1484 __le32 tx_retry_bytes; 1485 __le32 tx_failed_bytes; 1486 __le32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1487 __le16 tx_success_msdus; 1488 __le16 tx_retry_msdus; 1489 __le16 tx_failed_msdus; 1490 __le16 tx_duration; /* united in us */ 1491 } __packed; 1492 1493 enum htt_ppdu_stats_usr_compln_status { 1494 HTT_PPDU_STATS_USER_STATUS_OK, 1495 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1496 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1497 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1498 HTT_PPDU_STATS_USER_STATUS_ABORT, 1499 }; 1500 1501 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1502 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1503 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1504 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1505 1506 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1507 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1508 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1509 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1510 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1511 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1512 1513 struct htt_ppdu_stats_usr_cmpltn_cmn { 1514 u8 status; 1515 u8 tid_num; 1516 __le16 sw_peer_id; 1517 /* RSSI value of last ack packet (units = dB above noise floor) */ 1518 __le32 ack_rssi; 1519 __le16 mpdu_tried; 1520 __le16 mpdu_success; 1521 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1522 } __packed; 1523 1524 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1525 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1526 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1527 1528 #define HTT_PPDU_STATS_NON_QOS_TID 16 1529 1530 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1531 __le32 ppdu_id; 1532 __le16 sw_peer_id; 1533 __le16 reserved0; 1534 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1535 __le16 current_seq; 1536 __le16 start_seq; 1537 __le32 success_bytes; 1538 } __packed; 1539 1540 struct htt_ppdu_user_stats { 1541 u16 peer_id; 1542 u16 delay_ba; 1543 u32 tlv_flags; 1544 bool is_valid_peer_id; 1545 struct htt_ppdu_stats_user_rate rate; 1546 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1547 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1548 }; 1549 1550 #define HTT_PPDU_STATS_MAX_USERS 8 1551 #define HTT_PPDU_DESC_MAX_DEPTH 16 1552 1553 struct htt_ppdu_stats { 1554 struct htt_ppdu_stats_common common; 1555 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1556 }; 1557 1558 struct htt_ppdu_stats_info { 1559 u32 tlv_bitmap; 1560 u32 ppdu_id; 1561 u32 frame_type; 1562 u32 frame_ctrl; 1563 u32 delay_ba; 1564 u32 bar_num_users; 1565 struct htt_ppdu_stats ppdu_stats; 1566 struct list_head list; 1567 }; 1568 1569 /* @brief target -> host MLO offset indiciation message 1570 * 1571 * @details 1572 * The following field definitions describe the format of the HTT target 1573 * to host mlo offset indication message. 1574 * 1575 * 1576 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1577 * |---------------------------------------------------------------------| 1578 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1579 * |---------------------------------------------------------------------| 1580 * | sync_timestamp_lo_us | 1581 * |---------------------------------------------------------------------| 1582 * | sync_timestamp_hi_us | 1583 * |---------------------------------------------------------------------| 1584 * | mlo_offset_lo | 1585 * |---------------------------------------------------------------------| 1586 * | mlo_offset_hi | 1587 * |---------------------------------------------------------------------| 1588 * | mlo_offset_clcks | 1589 * |---------------------------------------------------------------------| 1590 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1591 * |---------------------------------------------------------------------| 1592 * | rsvd3 |mlo_comp_timer | 1593 * |---------------------------------------------------------------------| 1594 * Header fields 1595 * - MSG_TYPE 1596 * Bits 7:0 1597 * Purpose: Identifies this is a MLO offset indication msg 1598 * - PDEV_ID 1599 * Bits 9:8 1600 * Purpose: Pdev of this MLO offset 1601 * - CHIP_ID 1602 * Bits 12:10 1603 * Purpose: chip_id of this MLO offset 1604 * - MAC_FREQ 1605 * Bits 28:13 1606 * - SYNC_TIMESTAMP_LO_US 1607 * Purpose: clock frequency of the mac HW block in MHz 1608 * Bits: 31:0 1609 * Purpose: lower 32 bits of the WLAN global time stamp at which 1610 * last sync interrupt was received 1611 * - SYNC_TIMESTAMP_HI_US 1612 * Bits: 31:0 1613 * Purpose: upper 32 bits of WLAN global time stamp at which 1614 * last sync interrupt was received 1615 * - MLO_OFFSET_LO 1616 * Bits: 31:0 1617 * Purpose: lower 32 bits of the MLO offset in us 1618 * - MLO_OFFSET_HI 1619 * Bits: 31:0 1620 * Purpose: upper 32 bits of the MLO offset in us 1621 * - MLO_COMP_US 1622 * Bits: 15:0 1623 * Purpose: MLO time stamp compensation applied in us 1624 * - MLO_COMP_CLCKS 1625 * Bits: 25:16 1626 * Purpose: MLO time stamp compensation applied in clock ticks 1627 * - MLO_COMP_TIMER 1628 * Bits: 21:0 1629 * Purpose: Periodic timer at which compensation is applied 1630 */ 1631 1632 #define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1633 #define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1634 1635 struct ath12k_htt_mlo_offset_msg { 1636 __le32 info; 1637 __le32 sync_timestamp_lo_us; 1638 __le32 sync_timestamp_hi_us; 1639 __le32 mlo_offset_hi; 1640 __le32 mlo_offset_lo; 1641 __le32 mlo_offset_clks; 1642 __le32 mlo_comp_clks; 1643 __le32 mlo_comp_timer; 1644 } __packed; 1645 1646 /* @brief host -> target FW extended statistics retrieve 1647 * 1648 * @details 1649 * The following field definitions describe the format of the HTT host 1650 * to target FW extended stats retrieve message. 1651 * The message specifies the type of stats the host wants to retrieve. 1652 * 1653 * |31 24|23 16|15 8|7 0| 1654 * |-----------------------------------------------------------| 1655 * | reserved | stats type | pdev_mask | msg type | 1656 * |-----------------------------------------------------------| 1657 * | config param [0] | 1658 * |-----------------------------------------------------------| 1659 * | config param [1] | 1660 * |-----------------------------------------------------------| 1661 * | config param [2] | 1662 * |-----------------------------------------------------------| 1663 * | config param [3] | 1664 * |-----------------------------------------------------------| 1665 * | reserved | 1666 * |-----------------------------------------------------------| 1667 * | cookie LSBs | 1668 * |-----------------------------------------------------------| 1669 * | cookie MSBs | 1670 * |-----------------------------------------------------------| 1671 * Header fields: 1672 * - MSG_TYPE 1673 * Bits 7:0 1674 * Purpose: identifies this is a extended stats upload request message 1675 * Value: 0x10 1676 * - PDEV_MASK 1677 * Bits 8:15 1678 * Purpose: identifies the mask of PDEVs to retrieve stats from 1679 * Value: This is a overloaded field, refer to usage and interpretation of 1680 * PDEV in interface document. 1681 * Bit 8 : Reserved for SOC stats 1682 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1683 * Indicates MACID_MASK in DBS 1684 * - STATS_TYPE 1685 * Bits 23:16 1686 * Purpose: identifies which FW statistics to upload 1687 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1688 * - Reserved 1689 * Bits 31:24 1690 * - CONFIG_PARAM [0] 1691 * Bits 31:0 1692 * Purpose: give an opaque configuration value to the specified stats type 1693 * Value: stats-type specific configuration value 1694 * Refer to htt_stats.h for interpretation for each stats sub_type 1695 * - CONFIG_PARAM [1] 1696 * Bits 31:0 1697 * Purpose: give an opaque configuration value to the specified stats type 1698 * Value: stats-type specific configuration value 1699 * Refer to htt_stats.h for interpretation for each stats sub_type 1700 * - CONFIG_PARAM [2] 1701 * Bits 31:0 1702 * Purpose: give an opaque configuration value to the specified stats type 1703 * Value: stats-type specific configuration value 1704 * Refer to htt_stats.h for interpretation for each stats sub_type 1705 * - CONFIG_PARAM [3] 1706 * Bits 31:0 1707 * Purpose: give an opaque configuration value to the specified stats type 1708 * Value: stats-type specific configuration value 1709 * Refer to htt_stats.h for interpretation for each stats sub_type 1710 * - Reserved [31:0] for future use. 1711 * - COOKIE_LSBS 1712 * Bits 31:0 1713 * Purpose: Provide a mechanism to match a target->host stats confirmation 1714 * message with its preceding host->target stats request message. 1715 * Value: LSBs of the opaque cookie specified by the host-side requestor 1716 * - COOKIE_MSBS 1717 * Bits 31:0 1718 * Purpose: Provide a mechanism to match a target->host stats confirmation 1719 * message with its preceding host->target stats request message. 1720 * Value: MSBs of the opaque cookie specified by the host-side requestor 1721 */ 1722 1723 struct htt_ext_stats_cfg_hdr { 1724 u8 msg_type; 1725 u8 pdev_mask; 1726 u8 stats_type; 1727 u8 reserved; 1728 } __packed; 1729 1730 struct htt_ext_stats_cfg_cmd { 1731 struct htt_ext_stats_cfg_hdr hdr; 1732 __le32 cfg_param0; 1733 __le32 cfg_param1; 1734 __le32 cfg_param2; 1735 __le32 cfg_param3; 1736 __le32 reserved; 1737 __le32 cookie_lsb; 1738 __le32 cookie_msb; 1739 } __packed; 1740 1741 /* htt stats config default params */ 1742 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1743 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1744 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1745 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1746 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1747 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1748 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1749 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1750 1751 /* HTT_DBG_EXT_STATS_PEER_INFO 1752 * PARAMS: 1753 * @config_param0: 1754 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1755 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1756 * [Bit31 : Bit16] sw_peer_id 1757 * @config_param1: 1758 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1759 * 0 bit htt_peer_stats_cmn_tlv 1760 * 1 bit htt_peer_details_tlv 1761 * 2 bit htt_tx_peer_rate_stats_tlv 1762 * 3 bit htt_rx_peer_rate_stats_tlv 1763 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1764 * 5 bit htt_rx_tid_stats_tlv 1765 * 6 bit htt_msdu_flow_stats_tlv 1766 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1767 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1768 * [Bit31 : Bit16] reserved 1769 */ 1770 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1771 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1772 1773 /* Used to set different configs to the specified stats type.*/ 1774 struct htt_ext_stats_cfg_params { 1775 u32 cfg0; 1776 u32 cfg1; 1777 u32 cfg2; 1778 u32 cfg3; 1779 }; 1780 1781 enum vdev_stats_offload_timer_duration { 1782 ATH12K_STATS_TIMER_DUR_500MS = 1, 1783 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1784 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1785 }; 1786 1787 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1788 { 1789 memcpy(addr, &addr_l32, 4); 1790 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1791 } 1792 1793 int ath12k_dp_service_srng(struct ath12k_base *ab, 1794 struct ath12k_ext_irq_grp *irq_grp, 1795 int budget); 1796 int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1797 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif); 1798 void ath12k_dp_free(struct ath12k_base *ab); 1799 int ath12k_dp_alloc(struct ath12k_base *ab); 1800 void ath12k_dp_cc_config(struct ath12k_base *ab); 1801 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1802 void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab); 1803 void ath12k_dp_pdev_free(struct ath12k_base *ab); 1804 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1805 int mac_id, enum hal_ring_type ring_type); 1806 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1807 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1808 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1809 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1810 enum hal_ring_type type, int ring_num, 1811 int mac_id, int num_entries); 1812 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1813 struct dp_link_desc_bank *desc_bank, 1814 u32 ring_type, struct dp_srng *ring); 1815 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1816 struct dp_link_desc_bank *link_desc_banks, 1817 u32 ring_type, struct hal_srng *srng, 1818 u32 n_link_desc); 1819 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1820 u32 cookie); 1821 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1822 u32 desc_id); 1823 #endif 1824