1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/etherdevice.h> 19 #include "htt.h" 20 #include "mac.h" 21 #include "hif.h" 22 #include "txrx.h" 23 #include "debug.h" 24 25 static u8 ath10k_htt_tx_txq_calc_size(size_t count) 26 { 27 int exp; 28 int factor; 29 30 exp = 0; 31 factor = count >> 7; 32 33 while (factor >= 64 && exp < 4) { 34 factor >>= 3; 35 exp++; 36 } 37 38 if (exp == 4) 39 return 0xff; 40 41 if (count > 0) 42 factor = max(1, factor); 43 44 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | 45 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); 46 } 47 48 static void __ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 49 struct ieee80211_txq *txq) 50 { 51 struct ath10k *ar = hw->priv; 52 struct ath10k_sta *arsta; 53 struct ath10k_vif *arvif = (void *)txq->vif->drv_priv; 54 unsigned long frame_cnt; 55 unsigned long byte_cnt; 56 int idx; 57 u32 bit; 58 u16 peer_id; 59 u8 tid; 60 u8 count; 61 62 lockdep_assert_held(&ar->htt.tx_lock); 63 64 if (!ar->htt.tx_q_state.enabled) 65 return; 66 67 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 68 return; 69 70 if (txq->sta) { 71 arsta = (void *)txq->sta->drv_priv; 72 peer_id = arsta->peer_id; 73 } else { 74 peer_id = arvif->peer_id; 75 } 76 77 tid = txq->tid; 78 bit = BIT(peer_id % 32); 79 idx = peer_id / 32; 80 81 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 82 count = ath10k_htt_tx_txq_calc_size(byte_cnt); 83 84 if (unlikely(peer_id >= ar->htt.tx_q_state.num_peers) || 85 unlikely(tid >= ar->htt.tx_q_state.num_tids)) { 86 ath10k_warn(ar, "refusing to update txq for peer_id %hu tid %hhu due to out of bounds\n", 87 peer_id, tid); 88 return; 89 } 90 91 ar->htt.tx_q_state.vaddr->count[tid][peer_id] = count; 92 ar->htt.tx_q_state.vaddr->map[tid][idx] &= ~bit; 93 ar->htt.tx_q_state.vaddr->map[tid][idx] |= count ? bit : 0; 94 95 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update peer_id %hu tid %hhu count %hhu\n", 96 peer_id, tid, count); 97 } 98 99 static void __ath10k_htt_tx_txq_sync(struct ath10k *ar) 100 { 101 u32 seq; 102 size_t size; 103 104 lockdep_assert_held(&ar->htt.tx_lock); 105 106 if (!ar->htt.tx_q_state.enabled) 107 return; 108 109 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH_PULL) 110 return; 111 112 seq = le32_to_cpu(ar->htt.tx_q_state.vaddr->seq); 113 seq++; 114 ar->htt.tx_q_state.vaddr->seq = cpu_to_le32(seq); 115 116 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx txq state update commit seq %u\n", 117 seq); 118 119 size = sizeof(*ar->htt.tx_q_state.vaddr); 120 dma_sync_single_for_device(ar->dev, 121 ar->htt.tx_q_state.paddr, 122 size, 123 DMA_TO_DEVICE); 124 } 125 126 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw, 127 struct ieee80211_txq *txq) 128 { 129 struct ath10k *ar = hw->priv; 130 131 spin_lock_bh(&ar->htt.tx_lock); 132 __ath10k_htt_tx_txq_recalc(hw, txq); 133 spin_unlock_bh(&ar->htt.tx_lock); 134 } 135 136 void ath10k_htt_tx_txq_sync(struct ath10k *ar) 137 { 138 spin_lock_bh(&ar->htt.tx_lock); 139 __ath10k_htt_tx_txq_sync(ar); 140 spin_unlock_bh(&ar->htt.tx_lock); 141 } 142 143 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw, 144 struct ieee80211_txq *txq) 145 { 146 struct ath10k *ar = hw->priv; 147 148 spin_lock_bh(&ar->htt.tx_lock); 149 __ath10k_htt_tx_txq_recalc(hw, txq); 150 __ath10k_htt_tx_txq_sync(ar); 151 spin_unlock_bh(&ar->htt.tx_lock); 152 } 153 154 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt) 155 { 156 lockdep_assert_held(&htt->tx_lock); 157 158 htt->num_pending_tx--; 159 if (htt->num_pending_tx == htt->max_num_pending_tx - 1) 160 ath10k_mac_tx_unlock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 161 } 162 163 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt) 164 { 165 lockdep_assert_held(&htt->tx_lock); 166 167 if (htt->num_pending_tx >= htt->max_num_pending_tx) 168 return -EBUSY; 169 170 htt->num_pending_tx++; 171 if (htt->num_pending_tx == htt->max_num_pending_tx) 172 ath10k_mac_tx_lock(htt->ar, ATH10K_TX_PAUSE_Q_FULL); 173 174 return 0; 175 } 176 177 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt, 178 bool is_presp) 179 { 180 struct ath10k *ar = htt->ar; 181 182 lockdep_assert_held(&htt->tx_lock); 183 184 if (!is_mgmt || !ar->hw_params.max_probe_resp_desc_thres) 185 return 0; 186 187 if (is_presp && 188 ar->hw_params.max_probe_resp_desc_thres < htt->num_pending_mgmt_tx) 189 return -EBUSY; 190 191 htt->num_pending_mgmt_tx++; 192 193 return 0; 194 } 195 196 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt) 197 { 198 lockdep_assert_held(&htt->tx_lock); 199 200 if (!htt->ar->hw_params.max_probe_resp_desc_thres) 201 return; 202 203 htt->num_pending_mgmt_tx--; 204 } 205 206 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb) 207 { 208 struct ath10k *ar = htt->ar; 209 int ret; 210 211 lockdep_assert_held(&htt->tx_lock); 212 213 ret = idr_alloc(&htt->pending_tx, skb, 0, 214 htt->max_num_pending_tx, GFP_ATOMIC); 215 216 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", ret); 217 218 return ret; 219 } 220 221 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id) 222 { 223 struct ath10k *ar = htt->ar; 224 225 lockdep_assert_held(&htt->tx_lock); 226 227 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id); 228 229 idr_remove(&htt->pending_tx, msdu_id); 230 } 231 232 static void ath10k_htt_tx_free_cont_txbuf_32(struct ath10k_htt *htt) 233 { 234 struct ath10k *ar = htt->ar; 235 size_t size; 236 237 if (!htt->txbuf.vaddr_txbuff_32) 238 return; 239 240 size = htt->txbuf.size; 241 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_32, 242 htt->txbuf.paddr); 243 htt->txbuf.vaddr_txbuff_32 = NULL; 244 } 245 246 static int ath10k_htt_tx_alloc_cont_txbuf_32(struct ath10k_htt *htt) 247 { 248 struct ath10k *ar = htt->ar; 249 size_t size; 250 251 size = htt->max_num_pending_tx * 252 sizeof(struct ath10k_htt_txbuf_32); 253 254 htt->txbuf.vaddr_txbuff_32 = dma_alloc_coherent(ar->dev, size, 255 &htt->txbuf.paddr, 256 GFP_KERNEL); 257 if (!htt->txbuf.vaddr_txbuff_32) 258 return -ENOMEM; 259 260 htt->txbuf.size = size; 261 262 return 0; 263 } 264 265 static void ath10k_htt_tx_free_cont_txbuf_64(struct ath10k_htt *htt) 266 { 267 struct ath10k *ar = htt->ar; 268 size_t size; 269 270 if (!htt->txbuf.vaddr_txbuff_64) 271 return; 272 273 size = htt->txbuf.size; 274 dma_free_coherent(ar->dev, size, htt->txbuf.vaddr_txbuff_64, 275 htt->txbuf.paddr); 276 htt->txbuf.vaddr_txbuff_64 = NULL; 277 } 278 279 static int ath10k_htt_tx_alloc_cont_txbuf_64(struct ath10k_htt *htt) 280 { 281 struct ath10k *ar = htt->ar; 282 size_t size; 283 284 size = htt->max_num_pending_tx * 285 sizeof(struct ath10k_htt_txbuf_64); 286 287 htt->txbuf.vaddr_txbuff_64 = dma_alloc_coherent(ar->dev, size, 288 &htt->txbuf.paddr, 289 GFP_KERNEL); 290 if (!htt->txbuf.vaddr_txbuff_64) 291 return -ENOMEM; 292 293 htt->txbuf.size = size; 294 295 return 0; 296 } 297 298 static void ath10k_htt_tx_free_cont_frag_desc_32(struct ath10k_htt *htt) 299 { 300 size_t size; 301 302 if (!htt->frag_desc.vaddr_desc_32) 303 return; 304 305 size = htt->max_num_pending_tx * 306 sizeof(struct htt_msdu_ext_desc); 307 308 dma_free_coherent(htt->ar->dev, 309 size, 310 htt->frag_desc.vaddr_desc_32, 311 htt->frag_desc.paddr); 312 313 htt->frag_desc.vaddr_desc_32 = NULL; 314 } 315 316 static int ath10k_htt_tx_alloc_cont_frag_desc_32(struct ath10k_htt *htt) 317 { 318 struct ath10k *ar = htt->ar; 319 size_t size; 320 321 if (!ar->hw_params.continuous_frag_desc) 322 return 0; 323 324 size = htt->max_num_pending_tx * 325 sizeof(struct htt_msdu_ext_desc); 326 htt->frag_desc.vaddr_desc_32 = dma_alloc_coherent(ar->dev, size, 327 &htt->frag_desc.paddr, 328 GFP_KERNEL); 329 if (!htt->frag_desc.vaddr_desc_32) { 330 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 331 return -ENOMEM; 332 } 333 htt->frag_desc.size = size; 334 335 return 0; 336 } 337 338 static void ath10k_htt_tx_free_cont_frag_desc_64(struct ath10k_htt *htt) 339 { 340 size_t size; 341 342 if (!htt->frag_desc.vaddr_desc_64) 343 return; 344 345 size = htt->max_num_pending_tx * 346 sizeof(struct htt_msdu_ext_desc_64); 347 348 dma_free_coherent(htt->ar->dev, 349 size, 350 htt->frag_desc.vaddr_desc_64, 351 htt->frag_desc.paddr); 352 353 htt->frag_desc.vaddr_desc_64 = NULL; 354 } 355 356 static int ath10k_htt_tx_alloc_cont_frag_desc_64(struct ath10k_htt *htt) 357 { 358 struct ath10k *ar = htt->ar; 359 size_t size; 360 361 if (!ar->hw_params.continuous_frag_desc) 362 return 0; 363 364 size = htt->max_num_pending_tx * 365 sizeof(struct htt_msdu_ext_desc_64); 366 367 htt->frag_desc.vaddr_desc_64 = dma_alloc_coherent(ar->dev, size, 368 &htt->frag_desc.paddr, 369 GFP_KERNEL); 370 if (!htt->frag_desc.vaddr_desc_64) { 371 ath10k_err(ar, "failed to alloc fragment desc memory\n"); 372 return -ENOMEM; 373 } 374 htt->frag_desc.size = size; 375 376 return 0; 377 } 378 379 static void ath10k_htt_tx_free_txq(struct ath10k_htt *htt) 380 { 381 struct ath10k *ar = htt->ar; 382 size_t size; 383 384 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 385 ar->running_fw->fw_file.fw_features)) 386 return; 387 388 size = sizeof(*htt->tx_q_state.vaddr); 389 390 dma_unmap_single(ar->dev, htt->tx_q_state.paddr, size, DMA_TO_DEVICE); 391 kfree(htt->tx_q_state.vaddr); 392 } 393 394 static int ath10k_htt_tx_alloc_txq(struct ath10k_htt *htt) 395 { 396 struct ath10k *ar = htt->ar; 397 size_t size; 398 int ret; 399 400 if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 401 ar->running_fw->fw_file.fw_features)) 402 return 0; 403 404 htt->tx_q_state.num_peers = HTT_TX_Q_STATE_NUM_PEERS; 405 htt->tx_q_state.num_tids = HTT_TX_Q_STATE_NUM_TIDS; 406 htt->tx_q_state.type = HTT_Q_DEPTH_TYPE_BYTES; 407 408 size = sizeof(*htt->tx_q_state.vaddr); 409 htt->tx_q_state.vaddr = kzalloc(size, GFP_KERNEL); 410 if (!htt->tx_q_state.vaddr) 411 return -ENOMEM; 412 413 htt->tx_q_state.paddr = dma_map_single(ar->dev, htt->tx_q_state.vaddr, 414 size, DMA_TO_DEVICE); 415 ret = dma_mapping_error(ar->dev, htt->tx_q_state.paddr); 416 if (ret) { 417 ath10k_warn(ar, "failed to dma map tx_q_state: %d\n", ret); 418 kfree(htt->tx_q_state.vaddr); 419 return -EIO; 420 } 421 422 return 0; 423 } 424 425 static void ath10k_htt_tx_free_txdone_fifo(struct ath10k_htt *htt) 426 { 427 WARN_ON(!kfifo_is_empty(&htt->txdone_fifo)); 428 kfifo_free(&htt->txdone_fifo); 429 } 430 431 static int ath10k_htt_tx_alloc_txdone_fifo(struct ath10k_htt *htt) 432 { 433 int ret; 434 size_t size; 435 436 size = roundup_pow_of_two(htt->max_num_pending_tx); 437 ret = kfifo_alloc(&htt->txdone_fifo, size, GFP_KERNEL); 438 return ret; 439 } 440 441 static int ath10k_htt_tx_alloc_buf(struct ath10k_htt *htt) 442 { 443 struct ath10k *ar = htt->ar; 444 int ret; 445 446 ret = ath10k_htt_alloc_txbuff(htt); 447 if (ret) { 448 ath10k_err(ar, "failed to alloc cont tx buffer: %d\n", ret); 449 return ret; 450 } 451 452 ret = ath10k_htt_alloc_frag_desc(htt); 453 if (ret) { 454 ath10k_err(ar, "failed to alloc cont frag desc: %d\n", ret); 455 goto free_txbuf; 456 } 457 458 ret = ath10k_htt_tx_alloc_txq(htt); 459 if (ret) { 460 ath10k_err(ar, "failed to alloc txq: %d\n", ret); 461 goto free_frag_desc; 462 } 463 464 ret = ath10k_htt_tx_alloc_txdone_fifo(htt); 465 if (ret) { 466 ath10k_err(ar, "failed to alloc txdone fifo: %d\n", ret); 467 goto free_txq; 468 } 469 470 return 0; 471 472 free_txq: 473 ath10k_htt_tx_free_txq(htt); 474 475 free_frag_desc: 476 ath10k_htt_free_frag_desc(htt); 477 478 free_txbuf: 479 ath10k_htt_free_txbuff(htt); 480 481 return ret; 482 } 483 484 int ath10k_htt_tx_start(struct ath10k_htt *htt) 485 { 486 struct ath10k *ar = htt->ar; 487 int ret; 488 489 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n", 490 htt->max_num_pending_tx); 491 492 spin_lock_init(&htt->tx_lock); 493 idr_init(&htt->pending_tx); 494 495 if (htt->tx_mem_allocated) 496 return 0; 497 498 ret = ath10k_htt_tx_alloc_buf(htt); 499 if (ret) 500 goto free_idr_pending_tx; 501 502 htt->tx_mem_allocated = true; 503 504 return 0; 505 506 free_idr_pending_tx: 507 idr_destroy(&htt->pending_tx); 508 509 return ret; 510 } 511 512 static int ath10k_htt_tx_clean_up_pending(int msdu_id, void *skb, void *ctx) 513 { 514 struct ath10k *ar = ctx; 515 struct ath10k_htt *htt = &ar->htt; 516 struct htt_tx_done tx_done = {0}; 517 518 ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n", msdu_id); 519 520 tx_done.msdu_id = msdu_id; 521 tx_done.status = HTT_TX_COMPL_STATE_DISCARD; 522 523 ath10k_txrx_tx_unref(htt, &tx_done); 524 525 return 0; 526 } 527 528 void ath10k_htt_tx_destroy(struct ath10k_htt *htt) 529 { 530 if (!htt->tx_mem_allocated) 531 return; 532 533 ath10k_htt_free_txbuff(htt); 534 ath10k_htt_tx_free_txq(htt); 535 ath10k_htt_free_frag_desc(htt); 536 ath10k_htt_tx_free_txdone_fifo(htt); 537 htt->tx_mem_allocated = false; 538 } 539 540 void ath10k_htt_tx_stop(struct ath10k_htt *htt) 541 { 542 idr_for_each(&htt->pending_tx, ath10k_htt_tx_clean_up_pending, htt->ar); 543 idr_destroy(&htt->pending_tx); 544 } 545 546 void ath10k_htt_tx_free(struct ath10k_htt *htt) 547 { 548 ath10k_htt_tx_stop(htt); 549 ath10k_htt_tx_destroy(htt); 550 } 551 552 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb) 553 { 554 dev_kfree_skb_any(skb); 555 } 556 557 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb) 558 { 559 dev_kfree_skb_any(skb); 560 } 561 EXPORT_SYMBOL(ath10k_htt_hif_tx_complete); 562 563 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt) 564 { 565 struct ath10k *ar = htt->ar; 566 struct sk_buff *skb; 567 struct htt_cmd *cmd; 568 int len = 0; 569 int ret; 570 571 len += sizeof(cmd->hdr); 572 len += sizeof(cmd->ver_req); 573 574 skb = ath10k_htc_alloc_skb(ar, len); 575 if (!skb) 576 return -ENOMEM; 577 578 skb_put(skb, len); 579 cmd = (struct htt_cmd *)skb->data; 580 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ; 581 582 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 583 if (ret) { 584 dev_kfree_skb_any(skb); 585 return ret; 586 } 587 588 return 0; 589 } 590 591 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie) 592 { 593 struct ath10k *ar = htt->ar; 594 struct htt_stats_req *req; 595 struct sk_buff *skb; 596 struct htt_cmd *cmd; 597 int len = 0, ret; 598 599 len += sizeof(cmd->hdr); 600 len += sizeof(cmd->stats_req); 601 602 skb = ath10k_htc_alloc_skb(ar, len); 603 if (!skb) 604 return -ENOMEM; 605 606 skb_put(skb, len); 607 cmd = (struct htt_cmd *)skb->data; 608 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ; 609 610 req = &cmd->stats_req; 611 612 memset(req, 0, sizeof(*req)); 613 614 /* currently we support only max 8 bit masks so no need to worry 615 * about endian support 616 */ 617 req->upload_types[0] = mask; 618 req->reset_types[0] = mask; 619 req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID; 620 req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff); 621 req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32); 622 623 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 624 if (ret) { 625 ath10k_warn(ar, "failed to send htt type stats request: %d", 626 ret); 627 dev_kfree_skb_any(skb); 628 return ret; 629 } 630 631 return 0; 632 } 633 634 static int ath10k_htt_send_frag_desc_bank_cfg_32(struct ath10k_htt *htt) 635 { 636 struct ath10k *ar = htt->ar; 637 struct sk_buff *skb; 638 struct htt_cmd *cmd; 639 struct htt_frag_desc_bank_cfg32 *cfg; 640 int ret, size; 641 u8 info; 642 643 if (!ar->hw_params.continuous_frag_desc) 644 return 0; 645 646 if (!htt->frag_desc.paddr) { 647 ath10k_warn(ar, "invalid frag desc memory\n"); 648 return -EINVAL; 649 } 650 651 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg32); 652 skb = ath10k_htc_alloc_skb(ar, size); 653 if (!skb) 654 return -ENOMEM; 655 656 skb_put(skb, size); 657 cmd = (struct htt_cmd *)skb->data; 658 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 659 660 info = 0; 661 info |= SM(htt->tx_q_state.type, 662 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 663 664 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 665 ar->running_fw->fw_file.fw_features)) 666 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 667 668 cfg = &cmd->frag_desc_bank_cfg32; 669 cfg->info = info; 670 cfg->num_banks = 1; 671 cfg->desc_size = sizeof(struct htt_msdu_ext_desc); 672 cfg->bank_base_addrs[0] = __cpu_to_le32(htt->frag_desc.paddr); 673 cfg->bank_id[0].bank_min_id = 0; 674 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 675 1); 676 677 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 678 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 679 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 680 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 681 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 682 683 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 684 685 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 686 if (ret) { 687 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 688 ret); 689 dev_kfree_skb_any(skb); 690 return ret; 691 } 692 693 return 0; 694 } 695 696 static int ath10k_htt_send_frag_desc_bank_cfg_64(struct ath10k_htt *htt) 697 { 698 struct ath10k *ar = htt->ar; 699 struct sk_buff *skb; 700 struct htt_cmd *cmd; 701 struct htt_frag_desc_bank_cfg64 *cfg; 702 int ret, size; 703 u8 info; 704 705 if (!ar->hw_params.continuous_frag_desc) 706 return 0; 707 708 if (!htt->frag_desc.paddr) { 709 ath10k_warn(ar, "invalid frag desc memory\n"); 710 return -EINVAL; 711 } 712 713 size = sizeof(cmd->hdr) + sizeof(cmd->frag_desc_bank_cfg64); 714 skb = ath10k_htc_alloc_skb(ar, size); 715 if (!skb) 716 return -ENOMEM; 717 718 skb_put(skb, size); 719 cmd = (struct htt_cmd *)skb->data; 720 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG; 721 722 info = 0; 723 info |= SM(htt->tx_q_state.type, 724 HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE); 725 726 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, 727 ar->running_fw->fw_file.fw_features)) 728 info |= HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID; 729 730 cfg = &cmd->frag_desc_bank_cfg64; 731 cfg->info = info; 732 cfg->num_banks = 1; 733 cfg->desc_size = sizeof(struct htt_msdu_ext_desc_64); 734 cfg->bank_base_addrs[0] = __cpu_to_le64(htt->frag_desc.paddr); 735 cfg->bank_id[0].bank_min_id = 0; 736 cfg->bank_id[0].bank_max_id = __cpu_to_le16(htt->max_num_pending_tx - 737 1); 738 739 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); 740 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); 741 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); 742 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; 743 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; 744 745 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt frag desc bank cmd\n"); 746 747 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 748 if (ret) { 749 ath10k_warn(ar, "failed to send frag desc bank cfg request: %d\n", 750 ret); 751 dev_kfree_skb_any(skb); 752 return ret; 753 } 754 755 return 0; 756 } 757 758 static void ath10k_htt_fill_rx_desc_offset_32(void *rx_ring) 759 { 760 struct htt_rx_ring_setup_ring32 *ring = 761 (struct htt_rx_ring_setup_ring32 *)rx_ring; 762 763 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 764 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 765 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 766 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 767 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 768 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 769 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 770 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 771 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 772 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 773 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 774 #undef desc_offset 775 } 776 777 static void ath10k_htt_fill_rx_desc_offset_64(void *rx_ring) 778 { 779 struct htt_rx_ring_setup_ring64 *ring = 780 (struct htt_rx_ring_setup_ring64 *)rx_ring; 781 782 #define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4) 783 ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status)); 784 ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload)); 785 ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start)); 786 ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end)); 787 ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start)); 788 ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end)); 789 ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start)); 790 ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end)); 791 ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention)); 792 ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info)); 793 #undef desc_offset 794 } 795 796 static int ath10k_htt_send_rx_ring_cfg_32(struct ath10k_htt *htt) 797 { 798 struct ath10k *ar = htt->ar; 799 struct sk_buff *skb; 800 struct htt_cmd *cmd; 801 struct htt_rx_ring_setup_ring32 *ring; 802 const int num_rx_ring = 1; 803 u16 flags; 804 u32 fw_idx; 805 int len; 806 int ret; 807 808 /* 809 * the HW expects the buffer to be an integral number of 4-byte 810 * "words" 811 */ 812 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 813 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 814 815 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_32.hdr) 816 + (sizeof(*ring) * num_rx_ring); 817 skb = ath10k_htc_alloc_skb(ar, len); 818 if (!skb) 819 return -ENOMEM; 820 821 skb_put(skb, len); 822 823 cmd = (struct htt_cmd *)skb->data; 824 ring = &cmd->rx_setup_32.rings[0]; 825 826 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 827 cmd->rx_setup_32.hdr.num_rings = 1; 828 829 /* FIXME: do we need all of this? */ 830 flags = 0; 831 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 832 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 833 flags |= HTT_RX_RING_FLAGS_PPDU_START; 834 flags |= HTT_RX_RING_FLAGS_PPDU_END; 835 flags |= HTT_RX_RING_FLAGS_MPDU_START; 836 flags |= HTT_RX_RING_FLAGS_MPDU_END; 837 flags |= HTT_RX_RING_FLAGS_MSDU_START; 838 flags |= HTT_RX_RING_FLAGS_MSDU_END; 839 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 840 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 841 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 842 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 843 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 844 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 845 flags |= HTT_RX_RING_FLAGS_NULL_RX; 846 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 847 848 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 849 850 ring->fw_idx_shadow_reg_paddr = 851 __cpu_to_le32(htt->rx_ring.alloc_idx.paddr); 852 ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr); 853 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 854 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 855 ring->flags = __cpu_to_le16(flags); 856 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 857 858 ath10k_htt_fill_rx_desc_offset_32(ring); 859 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 860 if (ret) { 861 dev_kfree_skb_any(skb); 862 return ret; 863 } 864 865 return 0; 866 } 867 868 static int ath10k_htt_send_rx_ring_cfg_64(struct ath10k_htt *htt) 869 { 870 struct ath10k *ar = htt->ar; 871 struct sk_buff *skb; 872 struct htt_cmd *cmd; 873 struct htt_rx_ring_setup_ring64 *ring; 874 const int num_rx_ring = 1; 875 u16 flags; 876 u32 fw_idx; 877 int len; 878 int ret; 879 880 /* HW expects the buffer to be an integral number of 4-byte 881 * "words" 882 */ 883 BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4)); 884 BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0); 885 886 len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup_64.hdr) 887 + (sizeof(*ring) * num_rx_ring); 888 skb = ath10k_htc_alloc_skb(ar, len); 889 if (!skb) 890 return -ENOMEM; 891 892 skb_put(skb, len); 893 894 cmd = (struct htt_cmd *)skb->data; 895 ring = &cmd->rx_setup_64.rings[0]; 896 897 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG; 898 cmd->rx_setup_64.hdr.num_rings = 1; 899 900 flags = 0; 901 flags |= HTT_RX_RING_FLAGS_MAC80211_HDR; 902 flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD; 903 flags |= HTT_RX_RING_FLAGS_PPDU_START; 904 flags |= HTT_RX_RING_FLAGS_PPDU_END; 905 flags |= HTT_RX_RING_FLAGS_MPDU_START; 906 flags |= HTT_RX_RING_FLAGS_MPDU_END; 907 flags |= HTT_RX_RING_FLAGS_MSDU_START; 908 flags |= HTT_RX_RING_FLAGS_MSDU_END; 909 flags |= HTT_RX_RING_FLAGS_RX_ATTENTION; 910 flags |= HTT_RX_RING_FLAGS_FRAG_INFO; 911 flags |= HTT_RX_RING_FLAGS_UNICAST_RX; 912 flags |= HTT_RX_RING_FLAGS_MULTICAST_RX; 913 flags |= HTT_RX_RING_FLAGS_CTRL_RX; 914 flags |= HTT_RX_RING_FLAGS_MGMT_RX; 915 flags |= HTT_RX_RING_FLAGS_NULL_RX; 916 flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX; 917 918 fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr); 919 920 ring->fw_idx_shadow_reg_paddr = __cpu_to_le64(htt->rx_ring.alloc_idx.paddr); 921 ring->rx_ring_base_paddr = __cpu_to_le64(htt->rx_ring.base_paddr); 922 ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size); 923 ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE); 924 ring->flags = __cpu_to_le16(flags); 925 ring->fw_idx_init_val = __cpu_to_le16(fw_idx); 926 927 ath10k_htt_fill_rx_desc_offset_64(ring); 928 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 929 if (ret) { 930 dev_kfree_skb_any(skb); 931 return ret; 932 } 933 934 return 0; 935 } 936 937 int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt, 938 u8 max_subfrms_ampdu, 939 u8 max_subfrms_amsdu) 940 { 941 struct ath10k *ar = htt->ar; 942 struct htt_aggr_conf *aggr_conf; 943 struct sk_buff *skb; 944 struct htt_cmd *cmd; 945 int len; 946 int ret; 947 948 /* Firmware defaults are: amsdu = 3 and ampdu = 64 */ 949 950 if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64) 951 return -EINVAL; 952 953 if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31) 954 return -EINVAL; 955 956 len = sizeof(cmd->hdr); 957 len += sizeof(cmd->aggr_conf); 958 959 skb = ath10k_htc_alloc_skb(ar, len); 960 if (!skb) 961 return -ENOMEM; 962 963 skb_put(skb, len); 964 cmd = (struct htt_cmd *)skb->data; 965 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG; 966 967 aggr_conf = &cmd->aggr_conf; 968 aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu; 969 aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu; 970 971 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d", 972 aggr_conf->max_num_amsdu_subframes, 973 aggr_conf->max_num_ampdu_subframes); 974 975 ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb); 976 if (ret) { 977 dev_kfree_skb_any(skb); 978 return ret; 979 } 980 981 return 0; 982 } 983 984 int ath10k_htt_tx_fetch_resp(struct ath10k *ar, 985 __le32 token, 986 __le16 fetch_seq_num, 987 struct htt_tx_fetch_record *records, 988 size_t num_records) 989 { 990 struct sk_buff *skb; 991 struct htt_cmd *cmd; 992 const u16 resp_id = 0; 993 int len = 0; 994 int ret; 995 996 /* Response IDs are echo-ed back only for host driver convienence 997 * purposes. They aren't used for anything in the driver yet so use 0. 998 */ 999 1000 len += sizeof(cmd->hdr); 1001 len += sizeof(cmd->tx_fetch_resp); 1002 len += sizeof(cmd->tx_fetch_resp.records[0]) * num_records; 1003 1004 skb = ath10k_htc_alloc_skb(ar, len); 1005 if (!skb) 1006 return -ENOMEM; 1007 1008 skb_put(skb, len); 1009 cmd = (struct htt_cmd *)skb->data; 1010 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FETCH_RESP; 1011 cmd->tx_fetch_resp.resp_id = cpu_to_le16(resp_id); 1012 cmd->tx_fetch_resp.fetch_seq_num = fetch_seq_num; 1013 cmd->tx_fetch_resp.num_records = cpu_to_le16(num_records); 1014 cmd->tx_fetch_resp.token = token; 1015 1016 memcpy(cmd->tx_fetch_resp.records, records, 1017 sizeof(records[0]) * num_records); 1018 1019 ret = ath10k_htc_send(&ar->htc, ar->htt.eid, skb); 1020 if (ret) { 1021 ath10k_warn(ar, "failed to submit htc command: %d\n", ret); 1022 goto err_free_skb; 1023 } 1024 1025 return 0; 1026 1027 err_free_skb: 1028 dev_kfree_skb_any(skb); 1029 1030 return ret; 1031 } 1032 1033 static u8 ath10k_htt_tx_get_vdev_id(struct ath10k *ar, struct sk_buff *skb) 1034 { 1035 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1036 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1037 struct ath10k_vif *arvif; 1038 1039 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { 1040 return ar->scan.vdev_id; 1041 } else if (cb->vif) { 1042 arvif = (void *)cb->vif->drv_priv; 1043 return arvif->vdev_id; 1044 } else if (ar->monitor_started) { 1045 return ar->monitor_vdev_id; 1046 } else { 1047 return 0; 1048 } 1049 } 1050 1051 static u8 ath10k_htt_tx_get_tid(struct sk_buff *skb, bool is_eth) 1052 { 1053 struct ieee80211_hdr *hdr = (void *)skb->data; 1054 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb); 1055 1056 if (!is_eth && ieee80211_is_mgmt(hdr->frame_control)) 1057 return HTT_DATA_TX_EXT_TID_MGMT; 1058 else if (cb->flags & ATH10K_SKB_F_QOS) 1059 return skb->priority % IEEE80211_QOS_CTL_TID_MASK; 1060 else 1061 return HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST; 1062 } 1063 1064 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu) 1065 { 1066 struct ath10k *ar = htt->ar; 1067 struct device *dev = ar->dev; 1068 struct sk_buff *txdesc = NULL; 1069 struct htt_cmd *cmd; 1070 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1071 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1072 int len = 0; 1073 int msdu_id = -1; 1074 int res; 1075 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1076 1077 len += sizeof(cmd->hdr); 1078 len += sizeof(cmd->mgmt_tx); 1079 1080 spin_lock_bh(&htt->tx_lock); 1081 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1082 spin_unlock_bh(&htt->tx_lock); 1083 if (res < 0) 1084 goto err; 1085 1086 msdu_id = res; 1087 1088 if ((ieee80211_is_action(hdr->frame_control) || 1089 ieee80211_is_deauth(hdr->frame_control) || 1090 ieee80211_is_disassoc(hdr->frame_control)) && 1091 ieee80211_has_protected(hdr->frame_control)) { 1092 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1093 } 1094 1095 txdesc = ath10k_htc_alloc_skb(ar, len); 1096 if (!txdesc) { 1097 res = -ENOMEM; 1098 goto err_free_msdu_id; 1099 } 1100 1101 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1102 DMA_TO_DEVICE); 1103 res = dma_mapping_error(dev, skb_cb->paddr); 1104 if (res) { 1105 res = -EIO; 1106 goto err_free_txdesc; 1107 } 1108 1109 skb_put(txdesc, len); 1110 cmd = (struct htt_cmd *)txdesc->data; 1111 memset(cmd, 0, len); 1112 1113 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX; 1114 cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr); 1115 cmd->mgmt_tx.len = __cpu_to_le32(msdu->len); 1116 cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id); 1117 cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id); 1118 memcpy(cmd->mgmt_tx.hdr, msdu->data, 1119 min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN)); 1120 1121 res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc); 1122 if (res) 1123 goto err_unmap_msdu; 1124 1125 return 0; 1126 1127 err_unmap_msdu: 1128 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1129 err_free_txdesc: 1130 dev_kfree_skb_any(txdesc); 1131 err_free_msdu_id: 1132 spin_lock_bh(&htt->tx_lock); 1133 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1134 spin_unlock_bh(&htt->tx_lock); 1135 err: 1136 return res; 1137 } 1138 1139 static int ath10k_htt_tx_32(struct ath10k_htt *htt, 1140 enum ath10k_hw_txrx_mode txmode, 1141 struct sk_buff *msdu) 1142 { 1143 struct ath10k *ar = htt->ar; 1144 struct device *dev = ar->dev; 1145 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1146 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1147 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1148 struct ath10k_hif_sg_item sg_items[2]; 1149 struct ath10k_htt_txbuf_32 *txbuf; 1150 struct htt_data_tx_desc_frag *frags; 1151 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1152 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1153 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1154 int prefetch_len; 1155 int res; 1156 u8 flags0 = 0; 1157 u16 msdu_id, flags1 = 0; 1158 u16 freq = 0; 1159 u32 frags_paddr = 0; 1160 u32 txbuf_paddr; 1161 struct htt_msdu_ext_desc *ext_desc = NULL; 1162 struct htt_msdu_ext_desc *ext_desc_t = NULL; 1163 1164 spin_lock_bh(&htt->tx_lock); 1165 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1166 spin_unlock_bh(&htt->tx_lock); 1167 if (res < 0) 1168 goto err; 1169 1170 msdu_id = res; 1171 1172 prefetch_len = min(htt->prefetch_len, msdu->len); 1173 prefetch_len = roundup(prefetch_len, 4); 1174 1175 txbuf = htt->txbuf.vaddr_txbuff_32 + msdu_id; 1176 txbuf_paddr = htt->txbuf.paddr + 1177 (sizeof(struct ath10k_htt_txbuf_32) * msdu_id); 1178 1179 if ((ieee80211_is_action(hdr->frame_control) || 1180 ieee80211_is_deauth(hdr->frame_control) || 1181 ieee80211_is_disassoc(hdr->frame_control)) && 1182 ieee80211_has_protected(hdr->frame_control)) { 1183 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1184 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1185 txmode == ATH10K_HW_TXRX_RAW && 1186 ieee80211_has_protected(hdr->frame_control)) { 1187 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1188 } 1189 1190 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1191 DMA_TO_DEVICE); 1192 res = dma_mapping_error(dev, skb_cb->paddr); 1193 if (res) { 1194 res = -EIO; 1195 goto err_free_msdu_id; 1196 } 1197 1198 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1199 freq = ar->scan.roc_freq; 1200 1201 switch (txmode) { 1202 case ATH10K_HW_TXRX_RAW: 1203 case ATH10K_HW_TXRX_NATIVE_WIFI: 1204 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1205 /* pass through */ 1206 case ATH10K_HW_TXRX_ETHERNET: 1207 if (ar->hw_params.continuous_frag_desc) { 1208 ext_desc_t = htt->frag_desc.vaddr_desc_32; 1209 memset(&ext_desc_t[msdu_id], 0, 1210 sizeof(struct htt_msdu_ext_desc)); 1211 frags = (struct htt_data_tx_desc_frag *) 1212 &ext_desc_t[msdu_id].frags; 1213 ext_desc = &ext_desc_t[msdu_id]; 1214 frags[0].tword_addr.paddr_lo = 1215 __cpu_to_le32(skb_cb->paddr); 1216 frags[0].tword_addr.paddr_hi = 0; 1217 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1218 1219 frags_paddr = htt->frag_desc.paddr + 1220 (sizeof(struct htt_msdu_ext_desc) * msdu_id); 1221 } else { 1222 frags = txbuf->frags; 1223 frags[0].dword_addr.paddr = 1224 __cpu_to_le32(skb_cb->paddr); 1225 frags[0].dword_addr.len = __cpu_to_le32(msdu->len); 1226 frags[1].dword_addr.paddr = 0; 1227 frags[1].dword_addr.len = 0; 1228 1229 frags_paddr = txbuf_paddr; 1230 } 1231 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1232 break; 1233 case ATH10K_HW_TXRX_MGMT: 1234 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1235 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1236 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1237 1238 frags_paddr = skb_cb->paddr; 1239 break; 1240 } 1241 1242 /* Normally all commands go through HTC which manages tx credits for 1243 * each endpoint and notifies when tx is completed. 1244 * 1245 * HTT endpoint is creditless so there's no need to care about HTC 1246 * flags. In that case it is trivial to fill the HTC header here. 1247 * 1248 * MSDU transmission is considered completed upon HTT event. This 1249 * implies no relevant resources can be freed until after the event is 1250 * received. That's why HTC tx completion handler itself is ignored by 1251 * setting NULL to transfer_context for all sg items. 1252 * 1253 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1254 * as it's a waste of resources. By bypassing HTC it is possible to 1255 * avoid extra memory allocations, compress data structures and thus 1256 * improve performance. 1257 */ 1258 1259 txbuf->htc_hdr.eid = htt->eid; 1260 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1261 sizeof(txbuf->cmd_tx) + 1262 prefetch_len); 1263 txbuf->htc_hdr.flags = 0; 1264 1265 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1266 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1267 1268 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1269 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1270 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1271 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1272 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1273 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1274 if (ar->hw_params.continuous_frag_desc) 1275 ext_desc->flags |= HTT_MSDU_CHECKSUM_ENABLE; 1276 } 1277 1278 /* Prevent firmware from sending up tx inspection requests. There's 1279 * nothing ath10k can do with frames requested for inspection so force 1280 * it to simply rely a regular tx completion with discard status. 1281 */ 1282 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1283 1284 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1285 txbuf->cmd_tx.flags0 = flags0; 1286 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1287 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1288 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1289 txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr); 1290 if (ath10k_mac_tx_frm_has_freq(ar)) { 1291 txbuf->cmd_tx.offchan_tx.peerid = 1292 __cpu_to_le16(HTT_INVALID_PEERID); 1293 txbuf->cmd_tx.offchan_tx.freq = 1294 __cpu_to_le16(freq); 1295 } else { 1296 txbuf->cmd_tx.peerid = 1297 __cpu_to_le32(HTT_INVALID_PEERID); 1298 } 1299 1300 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1301 ath10k_dbg(ar, ATH10K_DBG_HTT, 1302 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1303 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1304 &skb_cb->paddr, vdev_id, tid, freq); 1305 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1306 msdu->data, msdu->len); 1307 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1308 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1309 1310 sg_items[0].transfer_id = 0; 1311 sg_items[0].transfer_context = NULL; 1312 sg_items[0].vaddr = &txbuf->htc_hdr; 1313 sg_items[0].paddr = txbuf_paddr + 1314 sizeof(txbuf->frags); 1315 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1316 sizeof(txbuf->cmd_hdr) + 1317 sizeof(txbuf->cmd_tx); 1318 1319 sg_items[1].transfer_id = 0; 1320 sg_items[1].transfer_context = NULL; 1321 sg_items[1].vaddr = msdu->data; 1322 sg_items[1].paddr = skb_cb->paddr; 1323 sg_items[1].len = prefetch_len; 1324 1325 res = ath10k_hif_tx_sg(htt->ar, 1326 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1327 sg_items, ARRAY_SIZE(sg_items)); 1328 if (res) 1329 goto err_unmap_msdu; 1330 1331 return 0; 1332 1333 err_unmap_msdu: 1334 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1335 err_free_msdu_id: 1336 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1337 err: 1338 return res; 1339 } 1340 1341 static int ath10k_htt_tx_64(struct ath10k_htt *htt, 1342 enum ath10k_hw_txrx_mode txmode, 1343 struct sk_buff *msdu) 1344 { 1345 struct ath10k *ar = htt->ar; 1346 struct device *dev = ar->dev; 1347 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 1348 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(msdu); 1349 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu); 1350 struct ath10k_hif_sg_item sg_items[2]; 1351 struct ath10k_htt_txbuf_64 *txbuf; 1352 struct htt_data_tx_desc_frag *frags; 1353 bool is_eth = (txmode == ATH10K_HW_TXRX_ETHERNET); 1354 u8 vdev_id = ath10k_htt_tx_get_vdev_id(ar, msdu); 1355 u8 tid = ath10k_htt_tx_get_tid(msdu, is_eth); 1356 int prefetch_len; 1357 int res; 1358 u8 flags0 = 0; 1359 u16 msdu_id, flags1 = 0; 1360 u16 freq = 0; 1361 dma_addr_t frags_paddr = 0; 1362 u32 txbuf_paddr; 1363 struct htt_msdu_ext_desc_64 *ext_desc = NULL; 1364 struct htt_msdu_ext_desc_64 *ext_desc_t = NULL; 1365 1366 spin_lock_bh(&htt->tx_lock); 1367 res = ath10k_htt_tx_alloc_msdu_id(htt, msdu); 1368 spin_unlock_bh(&htt->tx_lock); 1369 if (res < 0) 1370 goto err; 1371 1372 msdu_id = res; 1373 1374 prefetch_len = min(htt->prefetch_len, msdu->len); 1375 prefetch_len = roundup(prefetch_len, 4); 1376 1377 txbuf = htt->txbuf.vaddr_txbuff_64 + msdu_id; 1378 txbuf_paddr = htt->txbuf.paddr + 1379 (sizeof(struct ath10k_htt_txbuf_64) * msdu_id); 1380 1381 if ((ieee80211_is_action(hdr->frame_control) || 1382 ieee80211_is_deauth(hdr->frame_control) || 1383 ieee80211_is_disassoc(hdr->frame_control)) && 1384 ieee80211_has_protected(hdr->frame_control)) { 1385 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1386 } else if (!(skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) && 1387 txmode == ATH10K_HW_TXRX_RAW && 1388 ieee80211_has_protected(hdr->frame_control)) { 1389 skb_put(msdu, IEEE80211_CCMP_MIC_LEN); 1390 } 1391 1392 skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len, 1393 DMA_TO_DEVICE); 1394 res = dma_mapping_error(dev, skb_cb->paddr); 1395 if (res) { 1396 res = -EIO; 1397 goto err_free_msdu_id; 1398 } 1399 1400 if (unlikely(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) 1401 freq = ar->scan.roc_freq; 1402 1403 switch (txmode) { 1404 case ATH10K_HW_TXRX_RAW: 1405 case ATH10K_HW_TXRX_NATIVE_WIFI: 1406 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1407 /* pass through */ 1408 case ATH10K_HW_TXRX_ETHERNET: 1409 if (ar->hw_params.continuous_frag_desc) { 1410 ext_desc_t = htt->frag_desc.vaddr_desc_64; 1411 memset(&ext_desc_t[msdu_id], 0, 1412 sizeof(struct htt_msdu_ext_desc_64)); 1413 frags = (struct htt_data_tx_desc_frag *) 1414 &ext_desc_t[msdu_id].frags; 1415 ext_desc = &ext_desc_t[msdu_id]; 1416 frags[0].tword_addr.paddr_lo = 1417 __cpu_to_le32(skb_cb->paddr); 1418 frags[0].tword_addr.paddr_hi = 1419 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1420 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1421 1422 frags_paddr = htt->frag_desc.paddr + 1423 (sizeof(struct htt_msdu_ext_desc_64) * msdu_id); 1424 } else { 1425 frags = txbuf->frags; 1426 frags[0].tword_addr.paddr_lo = 1427 __cpu_to_le32(skb_cb->paddr); 1428 frags[0].tword_addr.paddr_hi = 1429 __cpu_to_le16(upper_32_bits(skb_cb->paddr)); 1430 frags[0].tword_addr.len_16 = __cpu_to_le16(msdu->len); 1431 frags[1].tword_addr.paddr_lo = 0; 1432 frags[1].tword_addr.paddr_hi = 0; 1433 frags[1].tword_addr.len_16 = 0; 1434 } 1435 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1436 break; 1437 case ATH10K_HW_TXRX_MGMT: 1438 flags0 |= SM(ATH10K_HW_TXRX_MGMT, 1439 HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); 1440 flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; 1441 1442 frags_paddr = skb_cb->paddr; 1443 break; 1444 } 1445 1446 /* Normally all commands go through HTC which manages tx credits for 1447 * each endpoint and notifies when tx is completed. 1448 * 1449 * HTT endpoint is creditless so there's no need to care about HTC 1450 * flags. In that case it is trivial to fill the HTC header here. 1451 * 1452 * MSDU transmission is considered completed upon HTT event. This 1453 * implies no relevant resources can be freed until after the event is 1454 * received. That's why HTC tx completion handler itself is ignored by 1455 * setting NULL to transfer_context for all sg items. 1456 * 1457 * There is simply no point in pushing HTT TX_FRM through HTC tx path 1458 * as it's a waste of resources. By bypassing HTC it is possible to 1459 * avoid extra memory allocations, compress data structures and thus 1460 * improve performance. 1461 */ 1462 1463 txbuf->htc_hdr.eid = htt->eid; 1464 txbuf->htc_hdr.len = __cpu_to_le16(sizeof(txbuf->cmd_hdr) + 1465 sizeof(txbuf->cmd_tx) + 1466 prefetch_len); 1467 txbuf->htc_hdr.flags = 0; 1468 1469 if (skb_cb->flags & ATH10K_SKB_F_NO_HWCRYPT) 1470 flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT; 1471 1472 flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID); 1473 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); 1474 if (msdu->ip_summed == CHECKSUM_PARTIAL && 1475 !test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { 1476 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD; 1477 flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD; 1478 if (ar->hw_params.continuous_frag_desc) { 1479 memset(ext_desc->tso_flag, 0, sizeof(ext_desc->tso_flag)); 1480 ext_desc->tso_flag[3] |= 1481 __cpu_to_le32(HTT_MSDU_CHECKSUM_ENABLE_64); 1482 } 1483 } 1484 1485 /* Prevent firmware from sending up tx inspection requests. There's 1486 * nothing ath10k can do with frames requested for inspection so force 1487 * it to simply rely a regular tx completion with discard status. 1488 */ 1489 flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED; 1490 1491 txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM; 1492 txbuf->cmd_tx.flags0 = flags0; 1493 txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1); 1494 txbuf->cmd_tx.len = __cpu_to_le16(msdu->len); 1495 txbuf->cmd_tx.id = __cpu_to_le16(msdu_id); 1496 1497 /* fill fragment descriptor */ 1498 txbuf->cmd_tx.frags_paddr = __cpu_to_le64(frags_paddr); 1499 if (ath10k_mac_tx_frm_has_freq(ar)) { 1500 txbuf->cmd_tx.offchan_tx.peerid = 1501 __cpu_to_le16(HTT_INVALID_PEERID); 1502 txbuf->cmd_tx.offchan_tx.freq = 1503 __cpu_to_le16(freq); 1504 } else { 1505 txbuf->cmd_tx.peerid = 1506 __cpu_to_le32(HTT_INVALID_PEERID); 1507 } 1508 1509 trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid); 1510 ath10k_dbg(ar, ATH10K_DBG_HTT, 1511 "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %pad, msdu_paddr %pad vdev %hhu tid %hhu freq %hu\n", 1512 flags0, flags1, msdu->len, msdu_id, &frags_paddr, 1513 &skb_cb->paddr, vdev_id, tid, freq); 1514 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ", 1515 msdu->data, msdu->len); 1516 trace_ath10k_tx_hdr(ar, msdu->data, msdu->len); 1517 trace_ath10k_tx_payload(ar, msdu->data, msdu->len); 1518 1519 sg_items[0].transfer_id = 0; 1520 sg_items[0].transfer_context = NULL; 1521 sg_items[0].vaddr = &txbuf->htc_hdr; 1522 sg_items[0].paddr = txbuf_paddr + 1523 sizeof(txbuf->frags); 1524 sg_items[0].len = sizeof(txbuf->htc_hdr) + 1525 sizeof(txbuf->cmd_hdr) + 1526 sizeof(txbuf->cmd_tx); 1527 1528 sg_items[1].transfer_id = 0; 1529 sg_items[1].transfer_context = NULL; 1530 sg_items[1].vaddr = msdu->data; 1531 sg_items[1].paddr = skb_cb->paddr; 1532 sg_items[1].len = prefetch_len; 1533 1534 res = ath10k_hif_tx_sg(htt->ar, 1535 htt->ar->htc.endpoint[htt->eid].ul_pipe_id, 1536 sg_items, ARRAY_SIZE(sg_items)); 1537 if (res) 1538 goto err_unmap_msdu; 1539 1540 return 0; 1541 1542 err_unmap_msdu: 1543 dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 1544 err_free_msdu_id: 1545 ath10k_htt_tx_free_msdu_id(htt, msdu_id); 1546 err: 1547 return res; 1548 } 1549 1550 static const struct ath10k_htt_tx_ops htt_tx_ops_32 = { 1551 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_32, 1552 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_32, 1553 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_32, 1554 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_32, 1555 .htt_tx = ath10k_htt_tx_32, 1556 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_32, 1557 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_32, 1558 }; 1559 1560 static const struct ath10k_htt_tx_ops htt_tx_ops_64 = { 1561 .htt_send_rx_ring_cfg = ath10k_htt_send_rx_ring_cfg_64, 1562 .htt_send_frag_desc_bank_cfg = ath10k_htt_send_frag_desc_bank_cfg_64, 1563 .htt_alloc_frag_desc = ath10k_htt_tx_alloc_cont_frag_desc_64, 1564 .htt_free_frag_desc = ath10k_htt_tx_free_cont_frag_desc_64, 1565 .htt_tx = ath10k_htt_tx_64, 1566 .htt_alloc_txbuff = ath10k_htt_tx_alloc_cont_txbuf_64, 1567 .htt_free_txbuff = ath10k_htt_tx_free_cont_txbuf_64, 1568 }; 1569 1570 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt) 1571 { 1572 struct ath10k *ar = htt->ar; 1573 1574 if (ar->hw_params.target_64bit) 1575 htt->tx_ops = &htt_tx_ops_64; 1576 else 1577 htt->tx_ops = &htt_tx_ops_32; 1578 } 1579