1 /* 2 * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices 3 * 4 * Copyright (C) 2011-2013 ASIX 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/etherdevice.h> 22 #include <linux/mii.h> 23 #include <linux/usb.h> 24 #include <linux/crc32.h> 25 #include <linux/usb/usbnet.h> 26 #include <uapi/linux/mdio.h> 27 #include <linux/mdio.h> 28 29 #define AX88179_PHY_ID 0x03 30 #define AX_EEPROM_LEN 0x100 31 #define AX88179_EEPROM_MAGIC 0x17900b95 32 #define AX_MCAST_FLTSIZE 8 33 #define AX_MAX_MCAST 64 34 #define AX_INT_PPLS_LINK ((u32)BIT(16)) 35 #define AX_RXHDR_L4_TYPE_MASK 0x1c 36 #define AX_RXHDR_L4_TYPE_UDP 4 37 #define AX_RXHDR_L4_TYPE_TCP 16 38 #define AX_RXHDR_L3CSUM_ERR 2 39 #define AX_RXHDR_L4CSUM_ERR 1 40 #define AX_RXHDR_CRC_ERR ((u32)BIT(29)) 41 #define AX_RXHDR_DROP_ERR ((u32)BIT(31)) 42 #define AX_ACCESS_MAC 0x01 43 #define AX_ACCESS_PHY 0x02 44 #define AX_ACCESS_EEPROM 0x04 45 #define AX_ACCESS_EFUS 0x05 46 #define AX_PAUSE_WATERLVL_HIGH 0x54 47 #define AX_PAUSE_WATERLVL_LOW 0x55 48 49 #define PHYSICAL_LINK_STATUS 0x02 50 #define AX_USB_SS 0x04 51 #define AX_USB_HS 0x02 52 53 #define GENERAL_STATUS 0x03 54 /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */ 55 #define AX_SECLD 0x04 56 57 #define AX_SROM_ADDR 0x07 58 #define AX_SROM_CMD 0x0a 59 #define EEP_RD 0x04 60 #define EEP_BUSY 0x10 61 62 #define AX_SROM_DATA_LOW 0x08 63 #define AX_SROM_DATA_HIGH 0x09 64 65 #define AX_RX_CTL 0x0b 66 #define AX_RX_CTL_DROPCRCERR 0x0100 67 #define AX_RX_CTL_IPE 0x0200 68 #define AX_RX_CTL_START 0x0080 69 #define AX_RX_CTL_AP 0x0020 70 #define AX_RX_CTL_AM 0x0010 71 #define AX_RX_CTL_AB 0x0008 72 #define AX_RX_CTL_AMALL 0x0002 73 #define AX_RX_CTL_PRO 0x0001 74 #define AX_RX_CTL_STOP 0x0000 75 76 #define AX_NODE_ID 0x10 77 #define AX_MULFLTARY 0x16 78 79 #define AX_MEDIUM_STATUS_MODE 0x22 80 #define AX_MEDIUM_GIGAMODE 0x01 81 #define AX_MEDIUM_FULL_DUPLEX 0x02 82 #define AX_MEDIUM_EN_125MHZ 0x08 83 #define AX_MEDIUM_RXFLOW_CTRLEN 0x10 84 #define AX_MEDIUM_TXFLOW_CTRLEN 0x20 85 #define AX_MEDIUM_RECEIVE_EN 0x100 86 #define AX_MEDIUM_PS 0x200 87 #define AX_MEDIUM_JUMBO_EN 0x8040 88 89 #define AX_MONITOR_MOD 0x24 90 #define AX_MONITOR_MODE_RWLC 0x02 91 #define AX_MONITOR_MODE_RWMP 0x04 92 #define AX_MONITOR_MODE_PMEPOL 0x20 93 #define AX_MONITOR_MODE_PMETYPE 0x40 94 95 #define AX_GPIO_CTRL 0x25 96 #define AX_GPIO_CTRL_GPIO3EN 0x80 97 #define AX_GPIO_CTRL_GPIO2EN 0x40 98 #define AX_GPIO_CTRL_GPIO1EN 0x20 99 100 #define AX_PHYPWR_RSTCTL 0x26 101 #define AX_PHYPWR_RSTCTL_BZ 0x0010 102 #define AX_PHYPWR_RSTCTL_IPRL 0x0020 103 #define AX_PHYPWR_RSTCTL_AT 0x1000 104 105 #define AX_RX_BULKIN_QCTRL 0x2e 106 #define AX_CLK_SELECT 0x33 107 #define AX_CLK_SELECT_BCS 0x01 108 #define AX_CLK_SELECT_ACS 0x02 109 #define AX_CLK_SELECT_ULR 0x08 110 111 #define AX_RXCOE_CTL 0x34 112 #define AX_RXCOE_IP 0x01 113 #define AX_RXCOE_TCP 0x02 114 #define AX_RXCOE_UDP 0x04 115 #define AX_RXCOE_TCPV6 0x20 116 #define AX_RXCOE_UDPV6 0x40 117 118 #define AX_TXCOE_CTL 0x35 119 #define AX_TXCOE_IP 0x01 120 #define AX_TXCOE_TCP 0x02 121 #define AX_TXCOE_UDP 0x04 122 #define AX_TXCOE_TCPV6 0x20 123 #define AX_TXCOE_UDPV6 0x40 124 125 #define AX_LEDCTRL 0x73 126 127 #define GMII_PHY_PHYSR 0x11 128 #define GMII_PHY_PHYSR_SMASK 0xc000 129 #define GMII_PHY_PHYSR_GIGA 0x8000 130 #define GMII_PHY_PHYSR_100 0x4000 131 #define GMII_PHY_PHYSR_FULL 0x2000 132 #define GMII_PHY_PHYSR_LINK 0x400 133 134 #define GMII_LED_ACT 0x1a 135 #define GMII_LED_ACTIVE_MASK 0xff8f 136 #define GMII_LED0_ACTIVE BIT(4) 137 #define GMII_LED1_ACTIVE BIT(5) 138 #define GMII_LED2_ACTIVE BIT(6) 139 140 #define GMII_LED_LINK 0x1c 141 #define GMII_LED_LINK_MASK 0xf888 142 #define GMII_LED0_LINK_10 BIT(0) 143 #define GMII_LED0_LINK_100 BIT(1) 144 #define GMII_LED0_LINK_1000 BIT(2) 145 #define GMII_LED1_LINK_10 BIT(4) 146 #define GMII_LED1_LINK_100 BIT(5) 147 #define GMII_LED1_LINK_1000 BIT(6) 148 #define GMII_LED2_LINK_10 BIT(8) 149 #define GMII_LED2_LINK_100 BIT(9) 150 #define GMII_LED2_LINK_1000 BIT(10) 151 #define LED0_ACTIVE BIT(0) 152 #define LED0_LINK_10 BIT(1) 153 #define LED0_LINK_100 BIT(2) 154 #define LED0_LINK_1000 BIT(3) 155 #define LED0_FD BIT(4) 156 #define LED0_USB3_MASK 0x001f 157 #define LED1_ACTIVE BIT(5) 158 #define LED1_LINK_10 BIT(6) 159 #define LED1_LINK_100 BIT(7) 160 #define LED1_LINK_1000 BIT(8) 161 #define LED1_FD BIT(9) 162 #define LED1_USB3_MASK 0x03e0 163 #define LED2_ACTIVE BIT(10) 164 #define LED2_LINK_1000 BIT(13) 165 #define LED2_LINK_100 BIT(12) 166 #define LED2_LINK_10 BIT(11) 167 #define LED2_FD BIT(14) 168 #define LED_VALID BIT(15) 169 #define LED2_USB3_MASK 0x7c00 170 171 #define GMII_PHYPAGE 0x1e 172 #define GMII_PHY_PAGE_SELECT 0x1f 173 #define GMII_PHY_PGSEL_EXT 0x0007 174 #define GMII_PHY_PGSEL_PAGE0 0x0000 175 #define GMII_PHY_PGSEL_PAGE3 0x0003 176 #define GMII_PHY_PGSEL_PAGE5 0x0005 177 178 struct ax88179_data { 179 u8 eee_enabled; 180 u8 eee_active; 181 u16 rxctl; 182 u16 reserved; 183 }; 184 185 struct ax88179_int_data { 186 __le32 intdata1; 187 __le32 intdata2; 188 }; 189 190 static const struct { 191 unsigned char ctrl, timer_l, timer_h, size, ifg; 192 } AX88179_BULKIN_SIZE[] = { 193 {7, 0x4f, 0, 0x12, 0xff}, 194 {7, 0x20, 3, 0x16, 0xff}, 195 {7, 0xae, 7, 0x18, 0xff}, 196 {7, 0xcc, 0x4c, 0x18, 8}, 197 }; 198 199 static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 200 u16 size, void *data, int in_pm) 201 { 202 int ret; 203 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16); 204 205 BUG_ON(!dev); 206 207 if (!in_pm) 208 fn = usbnet_read_cmd; 209 else 210 fn = usbnet_read_cmd_nopm; 211 212 ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 213 value, index, data, size); 214 215 if (unlikely(ret < 0)) 216 netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n", 217 index, ret); 218 219 return ret; 220 } 221 222 static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 223 u16 size, void *data, int in_pm) 224 { 225 int ret; 226 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16); 227 228 BUG_ON(!dev); 229 230 if (!in_pm) 231 fn = usbnet_write_cmd; 232 else 233 fn = usbnet_write_cmd_nopm; 234 235 ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 236 value, index, data, size); 237 238 if (unlikely(ret < 0)) 239 netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n", 240 index, ret); 241 242 return ret; 243 } 244 245 static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, 246 u16 index, u16 size, void *data) 247 { 248 u16 buf; 249 250 if (2 == size) { 251 buf = *((u16 *)data); 252 cpu_to_le16s(&buf); 253 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 254 USB_RECIP_DEVICE, value, index, &buf, 255 size); 256 } else { 257 usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | 258 USB_RECIP_DEVICE, value, index, data, 259 size); 260 } 261 } 262 263 static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 264 u16 index, u16 size, void *data) 265 { 266 int ret; 267 268 if (2 == size) { 269 u16 buf; 270 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 271 le16_to_cpus(&buf); 272 *((u16 *)data) = buf; 273 } else if (4 == size) { 274 u32 buf; 275 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1); 276 le32_to_cpus(&buf); 277 *((u32 *)data) = buf; 278 } else { 279 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1); 280 } 281 282 return ret; 283 } 284 285 static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value, 286 u16 index, u16 size, void *data) 287 { 288 int ret; 289 290 if (2 == size) { 291 u16 buf; 292 buf = *((u16 *)data); 293 cpu_to_le16s(&buf); 294 ret = __ax88179_write_cmd(dev, cmd, value, index, 295 size, &buf, 1); 296 } else { 297 ret = __ax88179_write_cmd(dev, cmd, value, index, 298 size, data, 1); 299 } 300 301 return ret; 302 } 303 304 static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 305 u16 size, void *data) 306 { 307 int ret; 308 309 if (2 == size) { 310 u16 buf; 311 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 312 le16_to_cpus(&buf); 313 *((u16 *)data) = buf; 314 } else if (4 == size) { 315 u32 buf; 316 ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0); 317 le32_to_cpus(&buf); 318 *((u32 *)data) = buf; 319 } else { 320 ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0); 321 } 322 323 return ret; 324 } 325 326 static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 327 u16 size, void *data) 328 { 329 int ret; 330 331 if (2 == size) { 332 u16 buf; 333 buf = *((u16 *)data); 334 cpu_to_le16s(&buf); 335 ret = __ax88179_write_cmd(dev, cmd, value, index, 336 size, &buf, 0); 337 } else { 338 ret = __ax88179_write_cmd(dev, cmd, value, index, 339 size, data, 0); 340 } 341 342 return ret; 343 } 344 345 static void ax88179_status(struct usbnet *dev, struct urb *urb) 346 { 347 struct ax88179_int_data *event; 348 u32 link; 349 350 if (urb->actual_length < 8) 351 return; 352 353 event = urb->transfer_buffer; 354 le32_to_cpus((void *)&event->intdata1); 355 356 link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16; 357 358 if (netif_carrier_ok(dev->net) != link) { 359 usbnet_link_change(dev, link, 1); 360 netdev_info(dev->net, "ax88179 - Link status is: %d\n", link); 361 } 362 } 363 364 static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc) 365 { 366 struct usbnet *dev = netdev_priv(netdev); 367 u16 res; 368 369 ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 370 return res; 371 } 372 373 static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc, 374 int val) 375 { 376 struct usbnet *dev = netdev_priv(netdev); 377 u16 res = (u16) val; 378 379 ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res); 380 } 381 382 static inline int ax88179_phy_mmd_indirect(struct usbnet *dev, u16 prtad, 383 u16 devad) 384 { 385 u16 tmp16; 386 int ret; 387 388 tmp16 = devad; 389 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 390 MII_MMD_CTRL, 2, &tmp16); 391 392 tmp16 = prtad; 393 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 394 MII_MMD_DATA, 2, &tmp16); 395 396 tmp16 = devad | MII_MMD_CTRL_NOINCR; 397 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 398 MII_MMD_CTRL, 2, &tmp16); 399 400 return ret; 401 } 402 403 static int 404 ax88179_phy_read_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad) 405 { 406 int ret; 407 u16 tmp16; 408 409 ax88179_phy_mmd_indirect(dev, prtad, devad); 410 411 ret = ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 412 MII_MMD_DATA, 2, &tmp16); 413 if (ret < 0) 414 return ret; 415 416 return tmp16; 417 } 418 419 static int 420 ax88179_phy_write_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad, 421 u16 data) 422 { 423 int ret; 424 425 ax88179_phy_mmd_indirect(dev, prtad, devad); 426 427 ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 428 MII_MMD_DATA, 2, &data); 429 430 if (ret < 0) 431 return ret; 432 433 return 0; 434 } 435 436 static int ax88179_suspend(struct usb_interface *intf, pm_message_t message) 437 { 438 struct usbnet *dev = usb_get_intfdata(intf); 439 u16 tmp16; 440 u8 tmp8; 441 442 usbnet_suspend(intf, message); 443 444 /* Disable RX path */ 445 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 446 2, 2, &tmp16); 447 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 448 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 449 2, 2, &tmp16); 450 451 /* Force bulk-in zero length */ 452 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 453 2, 2, &tmp16); 454 455 tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL; 456 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 457 2, 2, &tmp16); 458 459 /* change clock */ 460 tmp8 = 0; 461 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 462 463 /* Configure RX control register => stop operation */ 464 tmp16 = AX_RX_CTL_STOP; 465 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 466 467 return 0; 468 } 469 470 /* This function is used to enable the autodetach function. */ 471 /* This function is determined by offset 0x43 of EEPROM */ 472 static int ax88179_auto_detach(struct usbnet *dev, int in_pm) 473 { 474 u16 tmp16; 475 u8 tmp8; 476 int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *); 477 int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *); 478 479 if (!in_pm) { 480 fnr = ax88179_read_cmd; 481 fnw = ax88179_write_cmd; 482 } else { 483 fnr = ax88179_read_cmd_nopm; 484 fnw = ax88179_write_cmd_nopm; 485 } 486 487 if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0) 488 return 0; 489 490 if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100))) 491 return 0; 492 493 /* Enable Auto Detach bit */ 494 tmp8 = 0; 495 fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 496 tmp8 |= AX_CLK_SELECT_ULR; 497 fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 498 499 fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 500 tmp16 |= AX_PHYPWR_RSTCTL_AT; 501 fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 502 503 return 0; 504 } 505 506 static int ax88179_resume(struct usb_interface *intf) 507 { 508 struct usbnet *dev = usb_get_intfdata(intf); 509 u16 tmp16; 510 u8 tmp8; 511 512 usbnet_link_change(dev, 0, 0); 513 514 /* Power up ethernet PHY */ 515 tmp16 = 0; 516 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 517 2, 2, &tmp16); 518 udelay(1000); 519 520 tmp16 = AX_PHYPWR_RSTCTL_IPRL; 521 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 522 2, 2, &tmp16); 523 msleep(200); 524 525 /* Ethernet PHY Auto Detach*/ 526 ax88179_auto_detach(dev, 1); 527 528 /* Enable clock */ 529 ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 530 tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 531 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8); 532 msleep(100); 533 534 /* Configure RX control register => start operation */ 535 tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 536 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 537 ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 538 539 return usbnet_resume(intf); 540 } 541 542 static void 543 ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 544 { 545 struct usbnet *dev = netdev_priv(net); 546 u8 opt; 547 548 if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 549 1, 1, &opt) < 0) { 550 wolinfo->supported = 0; 551 wolinfo->wolopts = 0; 552 return; 553 } 554 555 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 556 wolinfo->wolopts = 0; 557 if (opt & AX_MONITOR_MODE_RWLC) 558 wolinfo->wolopts |= WAKE_PHY; 559 if (opt & AX_MONITOR_MODE_RWMP) 560 wolinfo->wolopts |= WAKE_MAGIC; 561 } 562 563 static int 564 ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 565 { 566 struct usbnet *dev = netdev_priv(net); 567 u8 opt = 0; 568 569 if (wolinfo->wolopts & WAKE_PHY) 570 opt |= AX_MONITOR_MODE_RWLC; 571 if (wolinfo->wolopts & WAKE_MAGIC) 572 opt |= AX_MONITOR_MODE_RWMP; 573 574 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 575 1, 1, &opt) < 0) 576 return -EINVAL; 577 578 return 0; 579 } 580 581 static int ax88179_get_eeprom_len(struct net_device *net) 582 { 583 return AX_EEPROM_LEN; 584 } 585 586 static int 587 ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, 588 u8 *data) 589 { 590 struct usbnet *dev = netdev_priv(net); 591 u16 *eeprom_buff; 592 int first_word, last_word; 593 int i, ret; 594 595 if (eeprom->len == 0) 596 return -EINVAL; 597 598 eeprom->magic = AX88179_EEPROM_MAGIC; 599 600 first_word = eeprom->offset >> 1; 601 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 602 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16), 603 GFP_KERNEL); 604 if (!eeprom_buff) 605 return -ENOMEM; 606 607 /* ax88179/178A returns 2 bytes from eeprom on read */ 608 for (i = first_word; i <= last_word; i++) { 609 ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2, 610 &eeprom_buff[i - first_word], 611 0); 612 if (ret < 0) { 613 kfree(eeprom_buff); 614 return -EIO; 615 } 616 } 617 618 memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len); 619 kfree(eeprom_buff); 620 return 0; 621 } 622 623 static int ax88179_get_link_ksettings(struct net_device *net, 624 struct ethtool_link_ksettings *cmd) 625 { 626 struct usbnet *dev = netdev_priv(net); 627 628 mii_ethtool_get_link_ksettings(&dev->mii, cmd); 629 630 return 0; 631 } 632 633 static int ax88179_set_link_ksettings(struct net_device *net, 634 const struct ethtool_link_ksettings *cmd) 635 { 636 struct usbnet *dev = netdev_priv(net); 637 return mii_ethtool_set_link_ksettings(&dev->mii, cmd); 638 } 639 640 static int 641 ax88179_ethtool_get_eee(struct usbnet *dev, struct ethtool_eee *data) 642 { 643 int val; 644 645 /* Get Supported EEE */ 646 val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE, 647 MDIO_MMD_PCS); 648 if (val < 0) 649 return val; 650 data->supported = mmd_eee_cap_to_ethtool_sup_t(val); 651 652 /* Get advertisement EEE */ 653 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV, 654 MDIO_MMD_AN); 655 if (val < 0) 656 return val; 657 data->advertised = mmd_eee_adv_to_ethtool_adv_t(val); 658 659 /* Get LP advertisement EEE */ 660 val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE, 661 MDIO_MMD_AN); 662 if (val < 0) 663 return val; 664 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); 665 666 return 0; 667 } 668 669 static int 670 ax88179_ethtool_set_eee(struct usbnet *dev, struct ethtool_eee *data) 671 { 672 u16 tmp16 = ethtool_adv_to_mmd_eee_adv_t(data->advertised); 673 674 return ax88179_phy_write_mmd_indirect(dev, MDIO_AN_EEE_ADV, 675 MDIO_MMD_AN, tmp16); 676 } 677 678 static int ax88179_chk_eee(struct usbnet *dev) 679 { 680 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 681 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 682 683 mii_ethtool_gset(&dev->mii, &ecmd); 684 685 if (ecmd.duplex & DUPLEX_FULL) { 686 int eee_lp, eee_cap, eee_adv; 687 u32 lp, cap, adv, supported = 0; 688 689 eee_cap = ax88179_phy_read_mmd_indirect(dev, 690 MDIO_PCS_EEE_ABLE, 691 MDIO_MMD_PCS); 692 if (eee_cap < 0) { 693 priv->eee_active = 0; 694 return false; 695 } 696 697 cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap); 698 if (!cap) { 699 priv->eee_active = 0; 700 return false; 701 } 702 703 eee_lp = ax88179_phy_read_mmd_indirect(dev, 704 MDIO_AN_EEE_LPABLE, 705 MDIO_MMD_AN); 706 if (eee_lp < 0) { 707 priv->eee_active = 0; 708 return false; 709 } 710 711 eee_adv = ax88179_phy_read_mmd_indirect(dev, 712 MDIO_AN_EEE_ADV, 713 MDIO_MMD_AN); 714 715 if (eee_adv < 0) { 716 priv->eee_active = 0; 717 return false; 718 } 719 720 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv); 721 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp); 722 supported = (ecmd.speed == SPEED_1000) ? 723 SUPPORTED_1000baseT_Full : 724 SUPPORTED_100baseT_Full; 725 726 if (!(lp & adv & supported)) { 727 priv->eee_active = 0; 728 return false; 729 } 730 731 priv->eee_active = 1; 732 return true; 733 } 734 735 priv->eee_active = 0; 736 return false; 737 } 738 739 static void ax88179_disable_eee(struct usbnet *dev) 740 { 741 u16 tmp16; 742 743 tmp16 = GMII_PHY_PGSEL_PAGE3; 744 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 745 GMII_PHY_PAGE_SELECT, 2, &tmp16); 746 747 tmp16 = 0x3246; 748 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 749 MII_PHYADDR, 2, &tmp16); 750 751 tmp16 = GMII_PHY_PGSEL_PAGE0; 752 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 753 GMII_PHY_PAGE_SELECT, 2, &tmp16); 754 } 755 756 static void ax88179_enable_eee(struct usbnet *dev) 757 { 758 u16 tmp16; 759 760 tmp16 = GMII_PHY_PGSEL_PAGE3; 761 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 762 GMII_PHY_PAGE_SELECT, 2, &tmp16); 763 764 tmp16 = 0x3247; 765 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 766 MII_PHYADDR, 2, &tmp16); 767 768 tmp16 = GMII_PHY_PGSEL_PAGE5; 769 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 770 GMII_PHY_PAGE_SELECT, 2, &tmp16); 771 772 tmp16 = 0x0680; 773 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 774 MII_BMSR, 2, &tmp16); 775 776 tmp16 = GMII_PHY_PGSEL_PAGE0; 777 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 778 GMII_PHY_PAGE_SELECT, 2, &tmp16); 779 } 780 781 static int ax88179_get_eee(struct net_device *net, struct ethtool_eee *edata) 782 { 783 struct usbnet *dev = netdev_priv(net); 784 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 785 786 edata->eee_enabled = priv->eee_enabled; 787 edata->eee_active = priv->eee_active; 788 789 return ax88179_ethtool_get_eee(dev, edata); 790 } 791 792 static int ax88179_set_eee(struct net_device *net, struct ethtool_eee *edata) 793 { 794 struct usbnet *dev = netdev_priv(net); 795 struct ax88179_data *priv = (struct ax88179_data *)dev->data; 796 int ret = -EOPNOTSUPP; 797 798 priv->eee_enabled = edata->eee_enabled; 799 if (!priv->eee_enabled) { 800 ax88179_disable_eee(dev); 801 } else { 802 priv->eee_enabled = ax88179_chk_eee(dev); 803 if (!priv->eee_enabled) 804 return -EOPNOTSUPP; 805 806 ax88179_enable_eee(dev); 807 } 808 809 ret = ax88179_ethtool_set_eee(dev, edata); 810 if (ret) 811 return ret; 812 813 mii_nway_restart(&dev->mii); 814 815 usbnet_link_change(dev, 0, 0); 816 817 return ret; 818 } 819 820 static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd) 821 { 822 struct usbnet *dev = netdev_priv(net); 823 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); 824 } 825 826 static const struct ethtool_ops ax88179_ethtool_ops = { 827 .get_link = ethtool_op_get_link, 828 .get_msglevel = usbnet_get_msglevel, 829 .set_msglevel = usbnet_set_msglevel, 830 .get_wol = ax88179_get_wol, 831 .set_wol = ax88179_set_wol, 832 .get_eeprom_len = ax88179_get_eeprom_len, 833 .get_eeprom = ax88179_get_eeprom, 834 .get_eee = ax88179_get_eee, 835 .set_eee = ax88179_set_eee, 836 .nway_reset = usbnet_nway_reset, 837 .get_link_ksettings = ax88179_get_link_ksettings, 838 .set_link_ksettings = ax88179_set_link_ksettings, 839 }; 840 841 static void ax88179_set_multicast(struct net_device *net) 842 { 843 struct usbnet *dev = netdev_priv(net); 844 struct ax88179_data *data = (struct ax88179_data *)dev->data; 845 u8 *m_filter = ((u8 *)dev->data) + 12; 846 847 data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE); 848 849 if (net->flags & IFF_PROMISC) { 850 data->rxctl |= AX_RX_CTL_PRO; 851 } else if (net->flags & IFF_ALLMULTI || 852 netdev_mc_count(net) > AX_MAX_MCAST) { 853 data->rxctl |= AX_RX_CTL_AMALL; 854 } else if (netdev_mc_empty(net)) { 855 /* just broadcast and directed */ 856 } else { 857 /* We use the 20 byte dev->data for our 8 byte filter buffer 858 * to avoid allocating memory that is tricky to free later 859 */ 860 u32 crc_bits; 861 struct netdev_hw_addr *ha; 862 863 memset(m_filter, 0, AX_MCAST_FLTSIZE); 864 865 netdev_for_each_mc_addr(ha, net) { 866 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 867 *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7)); 868 } 869 870 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY, 871 AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE, 872 m_filter); 873 874 data->rxctl |= AX_RX_CTL_AM; 875 } 876 877 ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL, 878 2, 2, &data->rxctl); 879 } 880 881 static int 882 ax88179_set_features(struct net_device *net, netdev_features_t features) 883 { 884 u8 tmp; 885 struct usbnet *dev = netdev_priv(net); 886 netdev_features_t changed = net->features ^ features; 887 888 if (changed & NETIF_F_IP_CSUM) { 889 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 890 tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP; 891 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 892 } 893 894 if (changed & NETIF_F_IPV6_CSUM) { 895 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 896 tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 897 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp); 898 } 899 900 if (changed & NETIF_F_RXCSUM) { 901 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 902 tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 903 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 904 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp); 905 } 906 907 return 0; 908 } 909 910 static int ax88179_change_mtu(struct net_device *net, int new_mtu) 911 { 912 struct usbnet *dev = netdev_priv(net); 913 u16 tmp16; 914 915 net->mtu = new_mtu; 916 dev->hard_mtu = net->mtu + net->hard_header_len; 917 918 if (net->mtu > 1500) { 919 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 920 2, 2, &tmp16); 921 tmp16 |= AX_MEDIUM_JUMBO_EN; 922 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 923 2, 2, &tmp16); 924 } else { 925 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 926 2, 2, &tmp16); 927 tmp16 &= ~AX_MEDIUM_JUMBO_EN; 928 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 929 2, 2, &tmp16); 930 } 931 932 /* max qlen depend on hard_mtu and rx_urb_size */ 933 usbnet_update_max_qlen(dev); 934 935 return 0; 936 } 937 938 static int ax88179_set_mac_addr(struct net_device *net, void *p) 939 { 940 struct usbnet *dev = netdev_priv(net); 941 struct sockaddr *addr = p; 942 int ret; 943 944 if (netif_running(net)) 945 return -EBUSY; 946 if (!is_valid_ether_addr(addr->sa_data)) 947 return -EADDRNOTAVAIL; 948 949 memcpy(net->dev_addr, addr->sa_data, ETH_ALEN); 950 951 /* Set the MAC address */ 952 ret = ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 953 ETH_ALEN, net->dev_addr); 954 if (ret < 0) 955 return ret; 956 957 return 0; 958 } 959 960 static const struct net_device_ops ax88179_netdev_ops = { 961 .ndo_open = usbnet_open, 962 .ndo_stop = usbnet_stop, 963 .ndo_start_xmit = usbnet_start_xmit, 964 .ndo_tx_timeout = usbnet_tx_timeout, 965 .ndo_get_stats64 = usbnet_get_stats64, 966 .ndo_change_mtu = ax88179_change_mtu, 967 .ndo_set_mac_address = ax88179_set_mac_addr, 968 .ndo_validate_addr = eth_validate_addr, 969 .ndo_do_ioctl = ax88179_ioctl, 970 .ndo_set_rx_mode = ax88179_set_multicast, 971 .ndo_set_features = ax88179_set_features, 972 }; 973 974 static int ax88179_check_eeprom(struct usbnet *dev) 975 { 976 u8 i, buf, eeprom[20]; 977 u16 csum, delay = HZ / 10; 978 unsigned long jtimeout; 979 980 /* Read EEPROM content */ 981 for (i = 0; i < 6; i++) { 982 buf = i; 983 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 984 1, 1, &buf) < 0) 985 return -EINVAL; 986 987 buf = EEP_RD; 988 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 989 1, 1, &buf) < 0) 990 return -EINVAL; 991 992 jtimeout = jiffies + delay; 993 do { 994 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 995 1, 1, &buf); 996 997 if (time_after(jiffies, jtimeout)) 998 return -EINVAL; 999 1000 } while (buf & EEP_BUSY); 1001 1002 __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 1003 2, 2, &eeprom[i * 2], 0); 1004 1005 if ((i == 0) && (eeprom[0] == 0xFF)) 1006 return -EINVAL; 1007 } 1008 1009 csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9]; 1010 csum = (csum >> 8) + (csum & 0xff); 1011 if ((csum + eeprom[10]) != 0xff) 1012 return -EINVAL; 1013 1014 return 0; 1015 } 1016 1017 static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode) 1018 { 1019 u8 i; 1020 u8 efuse[64]; 1021 u16 csum = 0; 1022 1023 if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0) 1024 return -EINVAL; 1025 1026 if (*efuse == 0xFF) 1027 return -EINVAL; 1028 1029 for (i = 0; i < 64; i++) 1030 csum = csum + efuse[i]; 1031 1032 while (csum > 255) 1033 csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF); 1034 1035 if (csum != 0xFF) 1036 return -EINVAL; 1037 1038 *ledmode = (efuse[51] << 8) | efuse[52]; 1039 1040 return 0; 1041 } 1042 1043 static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue) 1044 { 1045 u16 led; 1046 1047 /* Loaded the old eFuse LED Mode */ 1048 if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0) 1049 return -EINVAL; 1050 1051 led >>= 8; 1052 switch (led) { 1053 case 0xFF: 1054 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1055 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1056 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1057 break; 1058 case 0xFE: 1059 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID; 1060 break; 1061 case 0xFD: 1062 led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | 1063 LED2_LINK_10 | LED_VALID; 1064 break; 1065 case 0xFC: 1066 led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE | 1067 LED2_LINK_100 | LED2_LINK_10 | LED_VALID; 1068 break; 1069 default: 1070 led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 | 1071 LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 | 1072 LED2_LINK_100 | LED2_LINK_1000 | LED_VALID; 1073 break; 1074 } 1075 1076 *ledvalue = led; 1077 1078 return 0; 1079 } 1080 1081 static int ax88179_led_setting(struct usbnet *dev) 1082 { 1083 u8 ledfd, value = 0; 1084 u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10; 1085 unsigned long jtimeout; 1086 1087 /* Check AX88179 version. UA1 or UA2*/ 1088 ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value); 1089 1090 if (!(value & AX_SECLD)) { /* UA1 */ 1091 value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN | 1092 AX_GPIO_CTRL_GPIO1EN; 1093 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL, 1094 1, 1, &value) < 0) 1095 return -EINVAL; 1096 } 1097 1098 /* Check EEPROM */ 1099 if (!ax88179_check_eeprom(dev)) { 1100 value = 0x42; 1101 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR, 1102 1, 1, &value) < 0) 1103 return -EINVAL; 1104 1105 value = EEP_RD; 1106 if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1107 1, 1, &value) < 0) 1108 return -EINVAL; 1109 1110 jtimeout = jiffies + delay; 1111 do { 1112 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD, 1113 1, 1, &value); 1114 1115 if (time_after(jiffies, jtimeout)) 1116 return -EINVAL; 1117 1118 } while (value & EEP_BUSY); 1119 1120 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH, 1121 1, 1, &value); 1122 ledvalue = (value << 8); 1123 1124 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW, 1125 1, 1, &value); 1126 ledvalue |= value; 1127 1128 /* load internal ROM for defaule setting */ 1129 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1130 ax88179_convert_old_led(dev, &ledvalue); 1131 1132 } else if (!ax88179_check_efuse(dev, &ledvalue)) { 1133 if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0)) 1134 ax88179_convert_old_led(dev, &ledvalue); 1135 } else { 1136 ax88179_convert_old_led(dev, &ledvalue); 1137 } 1138 1139 tmp = GMII_PHY_PGSEL_EXT; 1140 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1141 GMII_PHY_PAGE_SELECT, 2, &tmp); 1142 1143 tmp = 0x2c; 1144 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1145 GMII_PHYPAGE, 2, &tmp); 1146 1147 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1148 GMII_LED_ACT, 2, &ledact); 1149 1150 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1151 GMII_LED_LINK, 2, &ledlink); 1152 1153 ledact &= GMII_LED_ACTIVE_MASK; 1154 ledlink &= GMII_LED_LINK_MASK; 1155 1156 if (ledvalue & LED0_ACTIVE) 1157 ledact |= GMII_LED0_ACTIVE; 1158 1159 if (ledvalue & LED1_ACTIVE) 1160 ledact |= GMII_LED1_ACTIVE; 1161 1162 if (ledvalue & LED2_ACTIVE) 1163 ledact |= GMII_LED2_ACTIVE; 1164 1165 if (ledvalue & LED0_LINK_10) 1166 ledlink |= GMII_LED0_LINK_10; 1167 1168 if (ledvalue & LED1_LINK_10) 1169 ledlink |= GMII_LED1_LINK_10; 1170 1171 if (ledvalue & LED2_LINK_10) 1172 ledlink |= GMII_LED2_LINK_10; 1173 1174 if (ledvalue & LED0_LINK_100) 1175 ledlink |= GMII_LED0_LINK_100; 1176 1177 if (ledvalue & LED1_LINK_100) 1178 ledlink |= GMII_LED1_LINK_100; 1179 1180 if (ledvalue & LED2_LINK_100) 1181 ledlink |= GMII_LED2_LINK_100; 1182 1183 if (ledvalue & LED0_LINK_1000) 1184 ledlink |= GMII_LED0_LINK_1000; 1185 1186 if (ledvalue & LED1_LINK_1000) 1187 ledlink |= GMII_LED1_LINK_1000; 1188 1189 if (ledvalue & LED2_LINK_1000) 1190 ledlink |= GMII_LED2_LINK_1000; 1191 1192 tmp = ledact; 1193 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1194 GMII_LED_ACT, 2, &tmp); 1195 1196 tmp = ledlink; 1197 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1198 GMII_LED_LINK, 2, &tmp); 1199 1200 tmp = GMII_PHY_PGSEL_PAGE0; 1201 ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1202 GMII_PHY_PAGE_SELECT, 2, &tmp); 1203 1204 /* LED full duplex setting */ 1205 ledfd = 0; 1206 if (ledvalue & LED0_FD) 1207 ledfd |= 0x01; 1208 else if ((ledvalue & LED0_USB3_MASK) == 0) 1209 ledfd |= 0x02; 1210 1211 if (ledvalue & LED1_FD) 1212 ledfd |= 0x04; 1213 else if ((ledvalue & LED1_USB3_MASK) == 0) 1214 ledfd |= 0x08; 1215 1216 if (ledvalue & LED2_FD) 1217 ledfd |= 0x10; 1218 else if ((ledvalue & LED2_USB3_MASK) == 0) 1219 ledfd |= 0x20; 1220 1221 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd); 1222 1223 return 0; 1224 } 1225 1226 static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf) 1227 { 1228 u8 buf[5]; 1229 u16 *tmp16; 1230 u8 *tmp; 1231 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1232 struct ethtool_eee eee_data; 1233 1234 usbnet_get_endpoints(dev, intf); 1235 1236 tmp16 = (u16 *)buf; 1237 tmp = (u8 *)buf; 1238 1239 memset(ax179_data, 0, sizeof(*ax179_data)); 1240 1241 /* Power up ethernet PHY */ 1242 *tmp16 = 0; 1243 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1244 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1245 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1246 msleep(200); 1247 1248 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1249 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1250 msleep(100); 1251 1252 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 1253 ETH_ALEN, dev->net->dev_addr); 1254 memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN); 1255 1256 /* RX bulk configuration */ 1257 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1258 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1259 1260 dev->rx_urb_size = 1024 * 20; 1261 1262 *tmp = 0x34; 1263 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1264 1265 *tmp = 0x52; 1266 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1267 1, 1, tmp); 1268 1269 dev->net->netdev_ops = &ax88179_netdev_ops; 1270 dev->net->ethtool_ops = &ax88179_ethtool_ops; 1271 dev->net->needed_headroom = 8; 1272 dev->net->max_mtu = 4088; 1273 1274 /* Initialize MII structure */ 1275 dev->mii.dev = dev->net; 1276 dev->mii.mdio_read = ax88179_mdio_read; 1277 dev->mii.mdio_write = ax88179_mdio_write; 1278 dev->mii.phy_id_mask = 0xff; 1279 dev->mii.reg_num_mask = 0xff; 1280 dev->mii.phy_id = 0x03; 1281 dev->mii.supports_gmii = 1; 1282 1283 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1284 NETIF_F_RXCSUM; 1285 1286 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1287 NETIF_F_RXCSUM; 1288 1289 /* Enable checksum offload */ 1290 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1291 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1292 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1293 1294 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1295 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1296 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1297 1298 /* Configure RX control register => start operation */ 1299 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1300 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1301 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1302 1303 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1304 AX_MONITOR_MODE_RWMP; 1305 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1306 1307 /* Configure default medium type => giga */ 1308 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1309 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1310 AX_MEDIUM_GIGAMODE; 1311 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1312 2, 2, tmp16); 1313 1314 ax88179_led_setting(dev); 1315 1316 ax179_data->eee_enabled = 0; 1317 ax179_data->eee_active = 0; 1318 1319 ax88179_disable_eee(dev); 1320 1321 ax88179_ethtool_get_eee(dev, &eee_data); 1322 eee_data.advertised = 0; 1323 ax88179_ethtool_set_eee(dev, &eee_data); 1324 1325 /* Restart autoneg */ 1326 mii_nway_restart(&dev->mii); 1327 1328 usbnet_link_change(dev, 0, 0); 1329 1330 return 0; 1331 } 1332 1333 static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf) 1334 { 1335 u16 tmp16; 1336 1337 /* Configure RX control register => stop operation */ 1338 tmp16 = AX_RX_CTL_STOP; 1339 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16); 1340 1341 tmp16 = 0; 1342 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16); 1343 1344 /* Power down ethernet PHY */ 1345 tmp16 = 0; 1346 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16); 1347 } 1348 1349 static void 1350 ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr) 1351 { 1352 skb->ip_summed = CHECKSUM_NONE; 1353 1354 /* checksum error bit is set */ 1355 if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) || 1356 (*pkt_hdr & AX_RXHDR_L4CSUM_ERR)) 1357 return; 1358 1359 /* It must be a TCP or UDP packet with a valid checksum */ 1360 if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) || 1361 ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP)) 1362 skb->ip_summed = CHECKSUM_UNNECESSARY; 1363 } 1364 1365 static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 1366 { 1367 struct sk_buff *ax_skb; 1368 int pkt_cnt; 1369 u32 rx_hdr; 1370 u16 hdr_off; 1371 u32 *pkt_hdr; 1372 1373 /* This check is no longer done by usbnet */ 1374 if (skb->len < dev->net->hard_header_len) 1375 return 0; 1376 1377 skb_trim(skb, skb->len - 4); 1378 memcpy(&rx_hdr, skb_tail_pointer(skb), 4); 1379 le32_to_cpus(&rx_hdr); 1380 1381 pkt_cnt = (u16)rx_hdr; 1382 hdr_off = (u16)(rx_hdr >> 16); 1383 pkt_hdr = (u32 *)(skb->data + hdr_off); 1384 1385 while (pkt_cnt--) { 1386 u16 pkt_len; 1387 1388 le32_to_cpus(pkt_hdr); 1389 pkt_len = (*pkt_hdr >> 16) & 0x1fff; 1390 1391 /* Check CRC or runt packet */ 1392 if ((*pkt_hdr & AX_RXHDR_CRC_ERR) || 1393 (*pkt_hdr & AX_RXHDR_DROP_ERR)) { 1394 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1395 pkt_hdr++; 1396 continue; 1397 } 1398 1399 if (pkt_cnt == 0) { 1400 /* Skip IP alignment psudo header */ 1401 skb_pull(skb, 2); 1402 skb->len = pkt_len; 1403 skb_set_tail_pointer(skb, pkt_len); 1404 skb->truesize = pkt_len + sizeof(struct sk_buff); 1405 ax88179_rx_checksum(skb, pkt_hdr); 1406 return 1; 1407 } 1408 1409 ax_skb = skb_clone(skb, GFP_ATOMIC); 1410 if (ax_skb) { 1411 ax_skb->len = pkt_len; 1412 ax_skb->data = skb->data + 2; 1413 skb_set_tail_pointer(ax_skb, pkt_len); 1414 ax_skb->truesize = pkt_len + sizeof(struct sk_buff); 1415 ax88179_rx_checksum(ax_skb, pkt_hdr); 1416 usbnet_skb_return(dev, ax_skb); 1417 } else { 1418 return 0; 1419 } 1420 1421 skb_pull(skb, (pkt_len + 7) & 0xFFF8); 1422 pkt_hdr++; 1423 } 1424 return 1; 1425 } 1426 1427 static struct sk_buff * 1428 ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) 1429 { 1430 u32 tx_hdr1, tx_hdr2; 1431 int frame_size = dev->maxpacket; 1432 int mss = skb_shinfo(skb)->gso_size; 1433 int headroom; 1434 1435 tx_hdr1 = skb->len; 1436 tx_hdr2 = mss; 1437 if (((skb->len + 8) % frame_size) == 0) 1438 tx_hdr2 |= 0x80008000; /* Enable padding */ 1439 1440 headroom = skb_headroom(skb) - 8; 1441 1442 if ((skb_header_cloned(skb) || headroom < 0) && 1443 pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) { 1444 dev_kfree_skb_any(skb); 1445 return NULL; 1446 } 1447 1448 skb_push(skb, 4); 1449 cpu_to_le32s(&tx_hdr2); 1450 skb_copy_to_linear_data(skb, &tx_hdr2, 4); 1451 1452 skb_push(skb, 4); 1453 cpu_to_le32s(&tx_hdr1); 1454 skb_copy_to_linear_data(skb, &tx_hdr1, 4); 1455 1456 return skb; 1457 } 1458 1459 static int ax88179_link_reset(struct usbnet *dev) 1460 { 1461 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1462 u8 tmp[5], link_sts; 1463 u16 mode, tmp16, delay = HZ / 10; 1464 u32 tmp32 = 0x40000000; 1465 unsigned long jtimeout; 1466 1467 jtimeout = jiffies + delay; 1468 while (tmp32 & 0x40000000) { 1469 mode = 0; 1470 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode); 1471 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, 1472 &ax179_data->rxctl); 1473 1474 /*link up, check the usb device control TX FIFO full or empty*/ 1475 ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32); 1476 1477 if (time_after(jiffies, jtimeout)) 1478 return 0; 1479 } 1480 1481 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1482 AX_MEDIUM_RXFLOW_CTRLEN; 1483 1484 ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 1485 1, 1, &link_sts); 1486 1487 ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 1488 GMII_PHY_PHYSR, 2, &tmp16); 1489 1490 if (!(tmp16 & GMII_PHY_PHYSR_LINK)) { 1491 return 0; 1492 } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1493 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ; 1494 if (dev->net->mtu > 1500) 1495 mode |= AX_MEDIUM_JUMBO_EN; 1496 1497 if (link_sts & AX_USB_SS) 1498 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1499 else if (link_sts & AX_USB_HS) 1500 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 1501 else 1502 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1503 } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) { 1504 mode |= AX_MEDIUM_PS; 1505 1506 if (link_sts & (AX_USB_SS | AX_USB_HS)) 1507 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 1508 else 1509 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1510 } else { 1511 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 1512 } 1513 1514 /* RX bulk configuration */ 1515 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1516 1517 dev->rx_urb_size = (1024 * (tmp[3] + 2)); 1518 1519 if (tmp16 & GMII_PHY_PHYSR_FULL) 1520 mode |= AX_MEDIUM_FULL_DUPLEX; 1521 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1522 2, 2, &mode); 1523 1524 ax179_data->eee_enabled = ax88179_chk_eee(dev); 1525 1526 netif_carrier_on(dev->net); 1527 1528 return 0; 1529 } 1530 1531 static int ax88179_reset(struct usbnet *dev) 1532 { 1533 u8 buf[5]; 1534 u16 *tmp16; 1535 u8 *tmp; 1536 struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data; 1537 struct ethtool_eee eee_data; 1538 1539 tmp16 = (u16 *)buf; 1540 tmp = (u8 *)buf; 1541 1542 /* Power up ethernet PHY */ 1543 *tmp16 = 0; 1544 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1545 1546 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 1547 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 1548 msleep(200); 1549 1550 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 1551 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 1552 msleep(100); 1553 1554 /* Ethernet PHY Auto Detach*/ 1555 ax88179_auto_detach(dev, 0); 1556 1557 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN, 1558 dev->net->dev_addr); 1559 1560 /* RX bulk configuration */ 1561 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 1562 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 1563 1564 dev->rx_urb_size = 1024 * 20; 1565 1566 *tmp = 0x34; 1567 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 1568 1569 *tmp = 0x52; 1570 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1571 1, 1, tmp); 1572 1573 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1574 NETIF_F_RXCSUM; 1575 1576 dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1577 NETIF_F_RXCSUM; 1578 1579 /* Enable checksum offload */ 1580 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 1581 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 1582 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 1583 1584 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 1585 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 1586 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 1587 1588 /* Configure RX control register => start operation */ 1589 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 1590 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 1591 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 1592 1593 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 1594 AX_MONITOR_MODE_RWMP; 1595 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 1596 1597 /* Configure default medium type => giga */ 1598 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 1599 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 1600 AX_MEDIUM_GIGAMODE; 1601 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1602 2, 2, tmp16); 1603 1604 ax88179_led_setting(dev); 1605 1606 ax179_data->eee_enabled = 0; 1607 ax179_data->eee_active = 0; 1608 1609 ax88179_disable_eee(dev); 1610 1611 ax88179_ethtool_get_eee(dev, &eee_data); 1612 eee_data.advertised = 0; 1613 ax88179_ethtool_set_eee(dev, &eee_data); 1614 1615 /* Restart autoneg */ 1616 mii_nway_restart(&dev->mii); 1617 1618 usbnet_link_change(dev, 0, 0); 1619 1620 return 0; 1621 } 1622 1623 static int ax88179_stop(struct usbnet *dev) 1624 { 1625 u16 tmp16; 1626 1627 ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1628 2, 2, &tmp16); 1629 tmp16 &= ~AX_MEDIUM_RECEIVE_EN; 1630 ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 1631 2, 2, &tmp16); 1632 1633 return 0; 1634 } 1635 1636 static const struct driver_info ax88179_info = { 1637 .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet", 1638 .bind = ax88179_bind, 1639 .unbind = ax88179_unbind, 1640 .status = ax88179_status, 1641 .link_reset = ax88179_link_reset, 1642 .reset = ax88179_reset, 1643 .stop = ax88179_stop, 1644 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1645 .rx_fixup = ax88179_rx_fixup, 1646 .tx_fixup = ax88179_tx_fixup, 1647 }; 1648 1649 static const struct driver_info ax88178a_info = { 1650 .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet", 1651 .bind = ax88179_bind, 1652 .unbind = ax88179_unbind, 1653 .status = ax88179_status, 1654 .link_reset = ax88179_link_reset, 1655 .reset = ax88179_reset, 1656 .stop = ax88179_stop, 1657 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1658 .rx_fixup = ax88179_rx_fixup, 1659 .tx_fixup = ax88179_tx_fixup, 1660 }; 1661 1662 static const struct driver_info cypress_GX3_info = { 1663 .description = "Cypress GX3 SuperSpeed to Gigabit Ethernet Controller", 1664 .bind = ax88179_bind, 1665 .unbind = ax88179_unbind, 1666 .status = ax88179_status, 1667 .link_reset = ax88179_link_reset, 1668 .reset = ax88179_reset, 1669 .stop = ax88179_stop, 1670 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1671 .rx_fixup = ax88179_rx_fixup, 1672 .tx_fixup = ax88179_tx_fixup, 1673 }; 1674 1675 static const struct driver_info dlink_dub1312_info = { 1676 .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter", 1677 .bind = ax88179_bind, 1678 .unbind = ax88179_unbind, 1679 .status = ax88179_status, 1680 .link_reset = ax88179_link_reset, 1681 .reset = ax88179_reset, 1682 .stop = ax88179_stop, 1683 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1684 .rx_fixup = ax88179_rx_fixup, 1685 .tx_fixup = ax88179_tx_fixup, 1686 }; 1687 1688 static const struct driver_info sitecom_info = { 1689 .description = "Sitecom USB 3.0 to Gigabit Adapter", 1690 .bind = ax88179_bind, 1691 .unbind = ax88179_unbind, 1692 .status = ax88179_status, 1693 .link_reset = ax88179_link_reset, 1694 .reset = ax88179_reset, 1695 .stop = ax88179_stop, 1696 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1697 .rx_fixup = ax88179_rx_fixup, 1698 .tx_fixup = ax88179_tx_fixup, 1699 }; 1700 1701 static const struct driver_info samsung_info = { 1702 .description = "Samsung USB Ethernet Adapter", 1703 .bind = ax88179_bind, 1704 .unbind = ax88179_unbind, 1705 .status = ax88179_status, 1706 .link_reset = ax88179_link_reset, 1707 .reset = ax88179_reset, 1708 .stop = ax88179_stop, 1709 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1710 .rx_fixup = ax88179_rx_fixup, 1711 .tx_fixup = ax88179_tx_fixup, 1712 }; 1713 1714 static const struct driver_info lenovo_info = { 1715 .description = "Lenovo OneLinkDock Gigabit LAN", 1716 .bind = ax88179_bind, 1717 .unbind = ax88179_unbind, 1718 .status = ax88179_status, 1719 .link_reset = ax88179_link_reset, 1720 .reset = ax88179_reset, 1721 .stop = ax88179_stop, 1722 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1723 .rx_fixup = ax88179_rx_fixup, 1724 .tx_fixup = ax88179_tx_fixup, 1725 }; 1726 1727 static const struct driver_info belkin_info = { 1728 .description = "Belkin USB Ethernet Adapter", 1729 .bind = ax88179_bind, 1730 .unbind = ax88179_unbind, 1731 .status = ax88179_status, 1732 .link_reset = ax88179_link_reset, 1733 .reset = ax88179_reset, 1734 .flags = FLAG_ETHER | FLAG_FRAMING_AX, 1735 .rx_fixup = ax88179_rx_fixup, 1736 .tx_fixup = ax88179_tx_fixup, 1737 }; 1738 1739 static const struct usb_device_id products[] = { 1740 { 1741 /* ASIX AX88179 10/100/1000 */ 1742 USB_DEVICE(0x0b95, 0x1790), 1743 .driver_info = (unsigned long)&ax88179_info, 1744 }, { 1745 /* ASIX AX88178A 10/100/1000 */ 1746 USB_DEVICE(0x0b95, 0x178a), 1747 .driver_info = (unsigned long)&ax88178a_info, 1748 }, { 1749 /* Cypress GX3 SuperSpeed to Gigabit Ethernet Bridge Controller */ 1750 USB_DEVICE(0x04b4, 0x3610), 1751 .driver_info = (unsigned long)&cypress_GX3_info, 1752 }, { 1753 /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */ 1754 USB_DEVICE(0x2001, 0x4a00), 1755 .driver_info = (unsigned long)&dlink_dub1312_info, 1756 }, { 1757 /* Sitecom USB 3.0 to Gigabit Adapter */ 1758 USB_DEVICE(0x0df6, 0x0072), 1759 .driver_info = (unsigned long)&sitecom_info, 1760 }, { 1761 /* Samsung USB Ethernet Adapter */ 1762 USB_DEVICE(0x04e8, 0xa100), 1763 .driver_info = (unsigned long)&samsung_info, 1764 }, { 1765 /* Lenovo OneLinkDock Gigabit LAN */ 1766 USB_DEVICE(0x17ef, 0x304b), 1767 .driver_info = (unsigned long)&lenovo_info, 1768 }, { 1769 /* Belkin B2B128 USB 3.0 Hub + Gigabit Ethernet Adapter */ 1770 USB_DEVICE(0x050d, 0x0128), 1771 .driver_info = (unsigned long)&belkin_info, 1772 }, 1773 { }, 1774 }; 1775 MODULE_DEVICE_TABLE(usb, products); 1776 1777 static struct usb_driver ax88179_178a_driver = { 1778 .name = "ax88179_178a", 1779 .id_table = products, 1780 .probe = usbnet_probe, 1781 .suspend = ax88179_suspend, 1782 .resume = ax88179_resume, 1783 .reset_resume = ax88179_resume, 1784 .disconnect = usbnet_disconnect, 1785 .supports_autosuspend = 1, 1786 .disable_hub_initiated_lpm = 1, 1787 }; 1788 1789 module_usb_driver(ax88179_178a_driver); 1790 1791 MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices"); 1792 MODULE_LICENSE("GPL"); 1793