1 /******************************************************************************* 2 Copyright (C) 2007-2009 STMicroelectronics Ltd 3 4 This program is free software; you can redistribute it and/or modify it 5 under the terms and conditions of the GNU General Public License, 6 version 2, as published by the Free Software Foundation. 7 8 This program is distributed in the hope it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 more details. 12 13 You should have received a copy of the GNU General Public License along with 14 this program; if not, write to the Free Software Foundation, Inc., 15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 17 The full GNU General Public License is included in this distribution in 18 the file called "COPYING". 19 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 21 *******************************************************************************/ 22 23 #include <linux/io.h> 24 #include "common.h" 25 #include "dwmac_dma.h" 26 27 #undef DWMAC_DMA_DEBUG 28 #ifdef DWMAC_DMA_DEBUG 29 #define DWMAC_LIB_DBG(fmt, args...) printk(fmt, ## args) 30 #else 31 #define DWMAC_LIB_DBG(fmt, args...) do { } while (0) 32 #endif 33 34 #define GMAC_HI_REG_AE 0x80000000 35 36 /* CSR1 enables the transmit DMA to check for new descriptor */ 37 void dwmac_enable_dma_transmission(void __iomem *ioaddr) 38 { 39 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); 40 } 41 42 void dwmac_enable_dma_irq(void __iomem *ioaddr) 43 { 44 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); 45 } 46 47 void dwmac_disable_dma_irq(void __iomem *ioaddr) 48 { 49 writel(0, ioaddr + DMA_INTR_ENA); 50 } 51 52 void dwmac_dma_start_tx(void __iomem *ioaddr) 53 { 54 u32 value = readl(ioaddr + DMA_CONTROL); 55 value |= DMA_CONTROL_ST; 56 writel(value, ioaddr + DMA_CONTROL); 57 } 58 59 void dwmac_dma_stop_tx(void __iomem *ioaddr) 60 { 61 u32 value = readl(ioaddr + DMA_CONTROL); 62 value &= ~DMA_CONTROL_ST; 63 writel(value, ioaddr + DMA_CONTROL); 64 } 65 66 void dwmac_dma_start_rx(void __iomem *ioaddr) 67 { 68 u32 value = readl(ioaddr + DMA_CONTROL); 69 value |= DMA_CONTROL_SR; 70 writel(value, ioaddr + DMA_CONTROL); 71 } 72 73 void dwmac_dma_stop_rx(void __iomem *ioaddr) 74 { 75 u32 value = readl(ioaddr + DMA_CONTROL); 76 value &= ~DMA_CONTROL_SR; 77 writel(value, ioaddr + DMA_CONTROL); 78 } 79 80 #ifdef DWMAC_DMA_DEBUG 81 static void show_tx_process_state(unsigned int status) 82 { 83 unsigned int state; 84 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT; 85 86 switch (state) { 87 case 0: 88 pr_info("- TX (Stopped): Reset or Stop command\n"); 89 break; 90 case 1: 91 pr_info("- TX (Running):Fetching the Tx desc\n"); 92 break; 93 case 2: 94 pr_info("- TX (Running): Waiting for end of tx\n"); 95 break; 96 case 3: 97 pr_info("- TX (Running): Reading the data " 98 "and queuing the data into the Tx buf\n"); 99 break; 100 case 6: 101 pr_info("- TX (Suspended): Tx Buff Underflow " 102 "or an unavailable Transmit descriptor\n"); 103 break; 104 case 7: 105 pr_info("- TX (Running): Closing Tx descriptor\n"); 106 break; 107 default: 108 break; 109 } 110 } 111 112 static void show_rx_process_state(unsigned int status) 113 { 114 unsigned int state; 115 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT; 116 117 switch (state) { 118 case 0: 119 pr_info("- RX (Stopped): Reset or Stop command\n"); 120 break; 121 case 1: 122 pr_info("- RX (Running): Fetching the Rx desc\n"); 123 break; 124 case 2: 125 pr_info("- RX (Running):Checking for end of pkt\n"); 126 break; 127 case 3: 128 pr_info("- RX (Running): Waiting for Rx pkt\n"); 129 break; 130 case 4: 131 pr_info("- RX (Suspended): Unavailable Rx buf\n"); 132 break; 133 case 5: 134 pr_info("- RX (Running): Closing Rx descriptor\n"); 135 break; 136 case 6: 137 pr_info("- RX(Running): Flushing the current frame" 138 " from the Rx buf\n"); 139 break; 140 case 7: 141 pr_info("- RX (Running): Queuing the Rx frame" 142 " from the Rx buf into memory\n"); 143 break; 144 default: 145 break; 146 } 147 } 148 #endif 149 150 int dwmac_dma_interrupt(void __iomem *ioaddr, 151 struct stmmac_extra_stats *x) 152 { 153 int ret = 0; 154 /* read the status register (CSR5) */ 155 u32 intr_status = readl(ioaddr + DMA_STATUS); 156 157 DWMAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status); 158 #ifdef DWMAC_DMA_DEBUG 159 /* It displays the DMA process states (CSR5 register) */ 160 show_tx_process_state(intr_status); 161 show_rx_process_state(intr_status); 162 #endif 163 /* ABNORMAL interrupts */ 164 if (unlikely(intr_status & DMA_STATUS_AIS)) { 165 DWMAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: "); 166 if (unlikely(intr_status & DMA_STATUS_UNF)) { 167 DWMAC_LIB_DBG(KERN_INFO "transmit underflow\n"); 168 ret = tx_hard_error_bump_tc; 169 x->tx_undeflow_irq++; 170 } 171 if (unlikely(intr_status & DMA_STATUS_TJT)) { 172 DWMAC_LIB_DBG(KERN_INFO "transmit jabber\n"); 173 x->tx_jabber_irq++; 174 } 175 if (unlikely(intr_status & DMA_STATUS_OVF)) { 176 DWMAC_LIB_DBG(KERN_INFO "recv overflow\n"); 177 x->rx_overflow_irq++; 178 } 179 if (unlikely(intr_status & DMA_STATUS_RU)) { 180 DWMAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n"); 181 x->rx_buf_unav_irq++; 182 } 183 if (unlikely(intr_status & DMA_STATUS_RPS)) { 184 DWMAC_LIB_DBG(KERN_INFO "receive process stopped\n"); 185 x->rx_process_stopped_irq++; 186 } 187 if (unlikely(intr_status & DMA_STATUS_RWT)) { 188 DWMAC_LIB_DBG(KERN_INFO "receive watchdog\n"); 189 x->rx_watchdog_irq++; 190 } 191 if (unlikely(intr_status & DMA_STATUS_ETI)) { 192 DWMAC_LIB_DBG(KERN_INFO "transmit early interrupt\n"); 193 x->tx_early_irq++; 194 } 195 if (unlikely(intr_status & DMA_STATUS_TPS)) { 196 DWMAC_LIB_DBG(KERN_INFO "transmit process stopped\n"); 197 x->tx_process_stopped_irq++; 198 ret = tx_hard_error; 199 } 200 if (unlikely(intr_status & DMA_STATUS_FBI)) { 201 DWMAC_LIB_DBG(KERN_INFO "fatal bus error\n"); 202 x->fatal_bus_error_irq++; 203 ret = tx_hard_error; 204 } 205 } 206 /* TX/RX NORMAL interrupts */ 207 if (intr_status & DMA_STATUS_NIS) { 208 x->normal_irq_n++; 209 if (likely((intr_status & DMA_STATUS_RI) || 210 (intr_status & (DMA_STATUS_TI)))) 211 ret = handle_tx_rx; 212 } 213 /* Optional hardware blocks, interrupts should be disabled */ 214 if (unlikely(intr_status & 215 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI))) 216 pr_info("%s: unexpected status %08x\n", __func__, intr_status); 217 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */ 218 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); 219 220 DWMAC_LIB_DBG(KERN_INFO "\n\n"); 221 return ret; 222 } 223 224 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) 225 { 226 u32 csr6 = readl(ioaddr + DMA_CONTROL); 227 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 228 229 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 230 } 231 232 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], 233 unsigned int high, unsigned int low) 234 { 235 unsigned long data; 236 237 data = (addr[5] << 8) | addr[4]; 238 /* For MAC Addr registers se have to set the Address Enable (AE) 239 * bit that has no effect on the High Reg 0 where the bit 31 (MO) 240 * is RO. 241 */ 242 writel(data | GMAC_HI_REG_AE, ioaddr + high); 243 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 244 writel(data, ioaddr + low); 245 } 246 247 /* Enable disable MAC RX/TX */ 248 void stmmac_set_mac(void __iomem *ioaddr, bool enable) 249 { 250 u32 value = readl(ioaddr + MAC_CTRL_REG); 251 252 if (enable) 253 value |= MAC_RNABLE_RX | MAC_ENABLE_TX; 254 else 255 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX); 256 257 writel(value, ioaddr + MAC_CTRL_REG); 258 } 259 260 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 261 unsigned int high, unsigned int low) 262 { 263 unsigned int hi_addr, lo_addr; 264 265 /* Read the MAC address from the hardware */ 266 hi_addr = readl(ioaddr + high); 267 lo_addr = readl(ioaddr + low); 268 269 /* Extract the MAC address from the high and low words */ 270 addr[0] = lo_addr & 0xff; 271 addr[1] = (lo_addr >> 8) & 0xff; 272 addr[2] = (lo_addr >> 16) & 0xff; 273 addr[3] = (lo_addr >> 24) & 0xff; 274 addr[4] = hi_addr & 0xff; 275 addr[5] = (hi_addr >> 8) & 0xff; 276 } 277 278