1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef REG_ADDR_H 34 #define REG_ADDR_H 35 36 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 37 0 38 39 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 40 0xfff << 0) 41 42 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 43 12 44 45 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 46 0xfff << 12) 47 48 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 49 24 50 51 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 52 0xff << 24) 53 54 #define CDU_REG_SEGMENT0_PARAMS \ 55 0x580904UL 56 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 57 (0xfff << 0) 58 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 59 0 60 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 61 (0xff << 16) 62 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 63 16 64 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 65 (0xff << 24) 66 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 67 24 68 #define CDU_REG_SEGMENT1_PARAMS \ 69 0x580908UL 70 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 71 (0xfff << 0) 72 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 73 0 74 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 75 (0xff << 16) 76 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 77 16 78 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 79 (0xff << 24) 80 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 81 24 82 83 #define XSDM_REG_OPERATION_GEN \ 84 0xf80408UL 85 #define NIG_REG_RX_BRB_OUT_EN \ 86 0x500e18UL 87 #define NIG_REG_STORM_OUT_EN \ 88 0x500e08UL 89 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 90 0x240c50UL 91 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 92 0x2aae04UL 93 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 94 0x2aa16cUL 95 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 96 0x2aa118UL 97 #define PSWHST_REG_ZONE_PERMISSION_TABLE \ 98 0x2a0800UL 99 #define BAR0_MAP_REG_MSDM_RAM \ 100 0x1d00000UL 101 #define BAR0_MAP_REG_USDM_RAM \ 102 0x1d80000UL 103 #define BAR0_MAP_REG_PSDM_RAM \ 104 0x1f00000UL 105 #define BAR0_MAP_REG_TSDM_RAM \ 106 0x1c80000UL 107 #define BAR0_MAP_REG_XSDM_RAM \ 108 0x1e00000UL 109 #define BAR0_MAP_REG_YSDM_RAM \ 110 0x1e80000UL 111 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 112 0x5011f4UL 113 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ 114 0x1f0164UL 115 #define PRS_REG_SEARCH_TCP \ 116 0x1f0400UL 117 #define PRS_REG_SEARCH_UDP \ 118 0x1f0404UL 119 #define PRS_REG_SEARCH_FCOE \ 120 0x1f0408UL 121 #define PRS_REG_SEARCH_ROCE \ 122 0x1f040cUL 123 #define PRS_REG_SEARCH_OPENFLOW \ 124 0x1f0434UL 125 #define PRS_REG_SEARCH_TAG1 \ 126 0x1f0444UL 127 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ 128 0x1f0a0cUL 129 #define PRS_REG_SEARCH_TCP_FIRST_FRAG \ 130 0x1f0410UL 131 #define TM_REG_PF_ENABLE_CONN \ 132 0x2c043cUL 133 #define TM_REG_PF_ENABLE_TASK \ 134 0x2c0444UL 135 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 136 0x2c04fcUL 137 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 138 0x2c0500UL 139 #define IGU_REG_LEADING_EDGE_LATCH \ 140 0x18082cUL 141 #define IGU_REG_TRAILING_EDGE_LATCH \ 142 0x180830UL 143 #define QM_REG_USG_CNT_PF_TX \ 144 0x2f2eacUL 145 #define QM_REG_USG_CNT_PF_OTHER \ 146 0x2f2eb0UL 147 #define DORQ_REG_PF_DB_ENABLE \ 148 0x100508UL 149 #define DORQ_REG_VF_USAGE_CNT \ 150 0x1009c4UL 151 #define QM_REG_PF_EN \ 152 0x2f2ea4UL 153 #define TCFC_REG_WEAK_ENABLE_VF \ 154 0x2d0704UL 155 #define TCFC_REG_STRONG_ENABLE_PF \ 156 0x2d0708UL 157 #define TCFC_REG_STRONG_ENABLE_VF \ 158 0x2d070cUL 159 #define CCFC_REG_WEAK_ENABLE_VF \ 160 0x2e0704UL 161 #define CCFC_REG_STRONG_ENABLE_PF \ 162 0x2e0708UL 163 #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ 164 0x2aa404UL 165 #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ 166 0x2aa408UL 167 #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ 168 0x2aa40cUL 169 #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ 170 0x2aa410UL 171 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 172 0x2aa138UL 173 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 174 0x2aa174UL 175 #define MISC_REG_GEN_PURP_CR0 \ 176 0x008c80UL 177 #define MCP_REG_SCRATCH \ 178 0xe20000UL 179 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 180 0x218200UL 181 #define MISCS_REG_CHIP_NUM \ 182 0x00976cUL 183 #define MISCS_REG_CHIP_REV \ 184 0x009770UL 185 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 186 0x00971cUL 187 #define MISCS_REG_CHIP_TEST_REG \ 188 0x009778UL 189 #define MISCS_REG_CHIP_METAL \ 190 0x009774UL 191 #define MISCS_REG_FUNCTION_HIDE \ 192 0x0096f0UL 193 #define BRB_REG_HEADER_SIZE \ 194 0x340804UL 195 #define BTB_REG_HEADER_SIZE \ 196 0xdb0804UL 197 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 198 0x1c0708UL 199 #define CCFC_REG_ACTIVITY_COUNTER \ 200 0x2e8800UL 201 #define CCFC_REG_STRONG_ENABLE_VF \ 202 0x2e070cUL 203 #define CDU_REG_CID_ADDR_PARAMS \ 204 0x580900UL 205 #define DBG_REG_CLIENT_ENABLE \ 206 0x010004UL 207 #define DMAE_REG_INIT \ 208 0x00c000UL 209 #define DORQ_REG_IFEN \ 210 0x100040UL 211 #define DORQ_REG_DB_DROP_REASON \ 212 0x100a2cUL 213 #define DORQ_REG_DB_DROP_DETAILS \ 214 0x100a24UL 215 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 216 0x100a1cUL 217 #define GRC_REG_TIMEOUT_EN \ 218 0x050404UL 219 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 220 0x050054UL 221 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 222 0x05004cUL 223 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 224 0x050050UL 225 #define IGU_REG_BLOCK_CONFIGURATION \ 226 0x180040UL 227 #define MCM_REG_INIT \ 228 0x1200000UL 229 #define MCP2_REG_DBG_DWORD_ENABLE \ 230 0x052404UL 231 #define MISC_REG_PORT_MODE \ 232 0x008c00UL 233 #define MISCS_REG_CLK_100G_MODE \ 234 0x009070UL 235 #define MSDM_REG_ENABLE_IN1 \ 236 0xfc0004UL 237 #define MSEM_REG_ENABLE_IN \ 238 0x1800004UL 239 #define NIG_REG_CM_HDR \ 240 0x500840UL 241 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 242 0x50196cUL 243 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 244 0x501964UL 245 #define NIG_REG_LLH_FUNC_FILTER_VALUE \ 246 0x501a00UL 247 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 248 32 249 #define NIG_REG_LLH_FUNC_FILTER_EN \ 250 0x501a80UL 251 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 252 16 253 #define NIG_REG_LLH_FUNC_FILTER_MODE \ 254 0x501ac0UL 255 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 256 16 257 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 258 0x501b00UL 259 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 260 16 261 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 262 0x501b40UL 263 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 264 16 265 #define NCSI_REG_CONFIG \ 266 0x040200UL 267 #define PBF_REG_INIT \ 268 0xd80000UL 269 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 270 0xd806c8UL 271 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 272 0xd806ccUL 273 #define PTU_REG_ATC_INIT_ARRAY \ 274 0x560000UL 275 #define PCM_REG_INIT \ 276 0x1100000UL 277 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 278 0x2a9000UL 279 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 280 0x2aa150UL 281 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 282 0x2aa144UL 283 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 284 0x2aa148UL 285 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 286 0x2aa14cUL 287 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 288 0x2aa154UL 289 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 290 0x2aa158UL 291 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 292 0x2aa15cUL 293 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 294 0x2aa160UL 295 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 296 0x2aa164UL 297 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 298 0x2aa54cUL 299 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 300 0x2aa544UL 301 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 302 0x2aa548UL 303 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 304 0x2aae74UL 305 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 306 0x2aae78UL 307 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 308 0x2aae7cUL 309 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 310 0x2aae80UL 311 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 312 0x2aa3bcUL 313 #define PRM_REG_DISABLE_PRM \ 314 0x230000UL 315 #define PRS_REG_SOFT_RST \ 316 0x1f0000UL 317 #define PRS_REG_MSG_INFO \ 318 0x1f0a1cUL 319 #define PRS_REG_ROCE_DEST_QP_MAX_PF \ 320 0x1f0430UL 321 #define PRS_REG_USE_LIGHT_L2 \ 322 0x1f096cUL 323 #define PSDM_REG_ENABLE_IN1 \ 324 0xfa0004UL 325 #define PSEM_REG_ENABLE_IN \ 326 0x1600004UL 327 #define PSWRQ_REG_DBG_SELECT \ 328 0x280020UL 329 #define PSWRQ2_REG_CDUT_P_SIZE \ 330 0x24000cUL 331 #define PSWRQ2_REG_ILT_MEMORY \ 332 0x260000UL 333 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 334 0x2a0040UL 335 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 336 0x29e050UL 337 #define PSWHST_REG_INCORRECT_ACCESS_VALID \ 338 0x2a0070UL 339 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 340 0x2a0074UL 341 #define PSWHST_REG_INCORRECT_ACCESS_DATA \ 342 0x2a0068UL 343 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 344 0x2a006cUL 345 #define PSWRD_REG_DBG_SELECT \ 346 0x29c040UL 347 #define PSWRD2_REG_CONF11 \ 348 0x29d064UL 349 #define PSWWR_REG_USDM_FULL_TH \ 350 0x29a040UL 351 #define PSWWR2_REG_CDU_FULL_TH2 \ 352 0x29b040UL 353 #define QM_REG_MAXPQSIZE_0 \ 354 0x2f0434UL 355 #define RSS_REG_RSS_INIT_EN \ 356 0x238804UL 357 #define RDIF_REG_STOP_ON_ERROR \ 358 0x300040UL 359 #define RDIF_REG_DEBUG_ERROR_INFO \ 360 0x300400UL 361 #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ 362 64 363 #define SRC_REG_SOFT_RST \ 364 0x23874cUL 365 #define TCFC_REG_ACTIVITY_COUNTER \ 366 0x2d8800UL 367 #define TCM_REG_INIT \ 368 0x1180000UL 369 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 370 0x2c0014UL 371 #define TSDM_REG_ENABLE_IN1 \ 372 0xfb0004UL 373 #define TSEM_REG_ENABLE_IN \ 374 0x1700004UL 375 #define TDIF_REG_STOP_ON_ERROR \ 376 0x310040UL 377 #define TDIF_REG_DEBUG_ERROR_INFO \ 378 0x310400UL 379 #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ 380 64 381 #define UCM_REG_INIT \ 382 0x1280000UL 383 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 384 0x051004UL 385 #define USDM_REG_ENABLE_IN1 \ 386 0xfd0004UL 387 #define USEM_REG_ENABLE_IN \ 388 0x1900004UL 389 #define XCM_REG_INIT \ 390 0x1000000UL 391 #define XSDM_REG_ENABLE_IN1 \ 392 0xf80004UL 393 #define XSEM_REG_ENABLE_IN \ 394 0x1400004UL 395 #define YCM_REG_INIT \ 396 0x1080000UL 397 #define YSDM_REG_ENABLE_IN1 \ 398 0xf90004UL 399 #define YSEM_REG_ENABLE_IN \ 400 0x1500004UL 401 #define XYLD_REG_SCBD_STRICT_PRIO \ 402 0x4c0000UL 403 #define TMLD_REG_SCBD_STRICT_PRIO \ 404 0x4d0000UL 405 #define MULD_REG_SCBD_STRICT_PRIO \ 406 0x4e0000UL 407 #define YULD_REG_SCBD_STRICT_PRIO \ 408 0x4c8000UL 409 #define MISC_REG_SHARED_MEM_ADDR \ 410 0x008c20UL 411 #define DMAE_REG_GO_C0 \ 412 0x00c048UL 413 #define DMAE_REG_GO_C1 \ 414 0x00c04cUL 415 #define DMAE_REG_GO_C2 \ 416 0x00c050UL 417 #define DMAE_REG_GO_C3 \ 418 0x00c054UL 419 #define DMAE_REG_GO_C4 \ 420 0x00c058UL 421 #define DMAE_REG_GO_C5 \ 422 0x00c05cUL 423 #define DMAE_REG_GO_C6 \ 424 0x00c060UL 425 #define DMAE_REG_GO_C7 \ 426 0x00c064UL 427 #define DMAE_REG_GO_C8 \ 428 0x00c068UL 429 #define DMAE_REG_GO_C9 \ 430 0x00c06cUL 431 #define DMAE_REG_GO_C10 \ 432 0x00c070UL 433 #define DMAE_REG_GO_C11 \ 434 0x00c074UL 435 #define DMAE_REG_GO_C12 \ 436 0x00c078UL 437 #define DMAE_REG_GO_C13 \ 438 0x00c07cUL 439 #define DMAE_REG_GO_C14 \ 440 0x00c080UL 441 #define DMAE_REG_GO_C15 \ 442 0x00c084UL 443 #define DMAE_REG_GO_C16 \ 444 0x00c088UL 445 #define DMAE_REG_GO_C17 \ 446 0x00c08cUL 447 #define DMAE_REG_GO_C18 \ 448 0x00c090UL 449 #define DMAE_REG_GO_C19 \ 450 0x00c094UL 451 #define DMAE_REG_GO_C20 \ 452 0x00c098UL 453 #define DMAE_REG_GO_C21 \ 454 0x00c09cUL 455 #define DMAE_REG_GO_C22 \ 456 0x00c0a0UL 457 #define DMAE_REG_GO_C23 \ 458 0x00c0a4UL 459 #define DMAE_REG_GO_C24 \ 460 0x00c0a8UL 461 #define DMAE_REG_GO_C25 \ 462 0x00c0acUL 463 #define DMAE_REG_GO_C26 \ 464 0x00c0b0UL 465 #define DMAE_REG_GO_C27 \ 466 0x00c0b4UL 467 #define DMAE_REG_GO_C28 \ 468 0x00c0b8UL 469 #define DMAE_REG_GO_C29 \ 470 0x00c0bcUL 471 #define DMAE_REG_GO_C30 \ 472 0x00c0c0UL 473 #define DMAE_REG_GO_C31 \ 474 0x00c0c4UL 475 #define DMAE_REG_CMD_MEM \ 476 0x00c800UL 477 #define QM_REG_MAXPQSIZETXSEL_0 \ 478 0x2f0440UL 479 #define QM_REG_SDMCMDREADY \ 480 0x2f1e10UL 481 #define QM_REG_SDMCMDADDR \ 482 0x2f1e04UL 483 #define QM_REG_SDMCMDDATALSB \ 484 0x2f1e08UL 485 #define QM_REG_SDMCMDDATAMSB \ 486 0x2f1e0cUL 487 #define QM_REG_SDMCMDGO \ 488 0x2f1e14UL 489 #define QM_REG_RLPFCRD \ 490 0x2f4d80UL 491 #define QM_REG_RLPFINCVAL \ 492 0x2f4c80UL 493 #define QM_REG_RLGLBLCRD \ 494 0x2f4400UL 495 #define QM_REG_RLGLBLINCVAL \ 496 0x2f3400UL 497 #define IGU_REG_ATTENTION_ENABLE \ 498 0x18083cUL 499 #define IGU_REG_ATTN_MSG_ADDR_L \ 500 0x180820UL 501 #define IGU_REG_ATTN_MSG_ADDR_H \ 502 0x180824UL 503 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 504 0x008400UL 505 #define CAU_REG_SB_ADDR_MEMORY \ 506 0x1c8000UL 507 #define CAU_REG_SB_VAR_MEMORY \ 508 0x1c6000UL 509 #define CAU_REG_PI_MEMORY \ 510 0x1d0000UL 511 #define IGU_REG_PF_CONFIGURATION \ 512 0x180800UL 513 #define IGU_REG_VF_CONFIGURATION \ 514 0x180804UL 515 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 516 0x00849cUL 517 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 518 0x0087b4UL 519 #define MISC_REG_AEU_MASK_ATTN_IGU \ 520 0x008494UL 521 #define IGU_REG_CLEANUP_STATUS_0 \ 522 0x180980UL 523 #define IGU_REG_CLEANUP_STATUS_1 \ 524 0x180a00UL 525 #define IGU_REG_CLEANUP_STATUS_2 \ 526 0x180a80UL 527 #define IGU_REG_CLEANUP_STATUS_3 \ 528 0x180b00UL 529 #define IGU_REG_CLEANUP_STATUS_4 \ 530 0x180b80UL 531 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 532 0x180840UL 533 #define IGU_REG_COMMAND_REG_CTRL \ 534 0x180848UL 535 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 536 0x1 << 1) 537 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 538 0x1 << 0) 539 #define IGU_REG_MAPPING_MEMORY \ 540 0x184000UL 541 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 542 0x180408UL 543 #define IGU_REG_WRITE_DONE_PENDING \ 544 0x180900UL 545 #define MISCS_REG_GENERIC_POR_0 \ 546 0x0096d4UL 547 #define MCP_REG_NVM_CFG4 \ 548 0xe0642cUL 549 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 550 0x7 << 0) 551 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 552 0 553 #define MCP_REG_CPU_STATE \ 554 0xe05004UL 555 #define MCP_REG_CPU_EVENT_MASK \ 556 0xe05008UL 557 #define PGLUE_B_REG_PF_BAR0_SIZE \ 558 0x2aae60UL 559 #define PGLUE_B_REG_PF_BAR1_SIZE \ 560 0x2aae64UL 561 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 562 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL 563 #define PRS_REG_VXLAN_PORT 0x1f0738UL 564 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 565 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 566 567 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 568 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 569 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 570 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 571 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 572 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 573 574 #define NIG_REG_VXLAN_CTRL 0x50105cUL 575 #define PBF_REG_VXLAN_PORT 0xd80518UL 576 #define PBF_REG_NGE_PORT 0xd8051cUL 577 #define PRS_REG_NGE_PORT 0x1f086cUL 578 #define NIG_REG_NGE_PORT 0x508b38UL 579 580 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 581 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 582 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 583 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 584 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 585 586 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 587 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 588 #define NIG_REG_NGE_COMP_VER 0x508b30UL 589 #define PBF_REG_NGE_COMP_VER 0xd80524UL 590 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 591 592 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 593 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 594 595 #define PGLCS_REG_DBG_SELECT \ 596 0x001d14UL 597 #define PGLCS_REG_DBG_DWORD_ENABLE \ 598 0x001d18UL 599 #define PGLCS_REG_DBG_SHIFT \ 600 0x001d1cUL 601 #define PGLCS_REG_DBG_FORCE_VALID \ 602 0x001d20UL 603 #define PGLCS_REG_DBG_FORCE_FRAME \ 604 0x001d24UL 605 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 606 0x008070UL 607 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 608 0x008080UL 609 #define MISC_REG_RESET_PL_PDA_VAUX \ 610 0x008090UL 611 #define MISCS_REG_RESET_PL_UA \ 612 0x009050UL 613 #define MISCS_REG_RESET_PL_HV \ 614 0x009060UL 615 #define MISCS_REG_RESET_PL_HV_2 \ 616 0x009150UL 617 #define DMAE_REG_DBG_SELECT \ 618 0x00c510UL 619 #define DMAE_REG_DBG_DWORD_ENABLE \ 620 0x00c514UL 621 #define DMAE_REG_DBG_SHIFT \ 622 0x00c518UL 623 #define DMAE_REG_DBG_FORCE_VALID \ 624 0x00c51cUL 625 #define DMAE_REG_DBG_FORCE_FRAME \ 626 0x00c520UL 627 #define NCSI_REG_DBG_SELECT \ 628 0x040474UL 629 #define NCSI_REG_DBG_DWORD_ENABLE \ 630 0x040478UL 631 #define NCSI_REG_DBG_SHIFT \ 632 0x04047cUL 633 #define NCSI_REG_DBG_FORCE_VALID \ 634 0x040480UL 635 #define NCSI_REG_DBG_FORCE_FRAME \ 636 0x040484UL 637 #define GRC_REG_DBG_SELECT \ 638 0x0500a4UL 639 #define GRC_REG_DBG_DWORD_ENABLE \ 640 0x0500a8UL 641 #define GRC_REG_DBG_SHIFT \ 642 0x0500acUL 643 #define GRC_REG_DBG_FORCE_VALID \ 644 0x0500b0UL 645 #define GRC_REG_DBG_FORCE_FRAME \ 646 0x0500b4UL 647 #define UMAC_REG_DBG_SELECT \ 648 0x051094UL 649 #define UMAC_REG_DBG_DWORD_ENABLE \ 650 0x051098UL 651 #define UMAC_REG_DBG_SHIFT \ 652 0x05109cUL 653 #define UMAC_REG_DBG_FORCE_VALID \ 654 0x0510a0UL 655 #define UMAC_REG_DBG_FORCE_FRAME \ 656 0x0510a4UL 657 #define MCP2_REG_DBG_SELECT \ 658 0x052400UL 659 #define MCP2_REG_DBG_DWORD_ENABLE \ 660 0x052404UL 661 #define MCP2_REG_DBG_SHIFT \ 662 0x052408UL 663 #define MCP2_REG_DBG_FORCE_VALID \ 664 0x052440UL 665 #define MCP2_REG_DBG_FORCE_FRAME \ 666 0x052444UL 667 #define PCIE_REG_DBG_SELECT \ 668 0x0547e8UL 669 #define PCIE_REG_DBG_DWORD_ENABLE \ 670 0x0547ecUL 671 #define PCIE_REG_DBG_SHIFT \ 672 0x0547f0UL 673 #define PCIE_REG_DBG_FORCE_VALID \ 674 0x0547f4UL 675 #define PCIE_REG_DBG_FORCE_FRAME \ 676 0x0547f8UL 677 #define DORQ_REG_DBG_SELECT \ 678 0x100ad0UL 679 #define DORQ_REG_DBG_DWORD_ENABLE \ 680 0x100ad4UL 681 #define DORQ_REG_DBG_SHIFT \ 682 0x100ad8UL 683 #define DORQ_REG_DBG_FORCE_VALID \ 684 0x100adcUL 685 #define DORQ_REG_DBG_FORCE_FRAME \ 686 0x100ae0UL 687 #define IGU_REG_DBG_SELECT \ 688 0x181578UL 689 #define IGU_REG_DBG_DWORD_ENABLE \ 690 0x18157cUL 691 #define IGU_REG_DBG_SHIFT \ 692 0x181580UL 693 #define IGU_REG_DBG_FORCE_VALID \ 694 0x181584UL 695 #define IGU_REG_DBG_FORCE_FRAME \ 696 0x181588UL 697 #define CAU_REG_DBG_SELECT \ 698 0x1c0ea8UL 699 #define CAU_REG_DBG_DWORD_ENABLE \ 700 0x1c0eacUL 701 #define CAU_REG_DBG_SHIFT \ 702 0x1c0eb0UL 703 #define CAU_REG_DBG_FORCE_VALID \ 704 0x1c0eb4UL 705 #define CAU_REG_DBG_FORCE_FRAME \ 706 0x1c0eb8UL 707 #define PRS_REG_DBG_SELECT \ 708 0x1f0b6cUL 709 #define PRS_REG_DBG_DWORD_ENABLE \ 710 0x1f0b70UL 711 #define PRS_REG_DBG_SHIFT \ 712 0x1f0b74UL 713 #define PRS_REG_DBG_FORCE_VALID \ 714 0x1f0ba0UL 715 #define PRS_REG_DBG_FORCE_FRAME \ 716 0x1f0ba4UL 717 #define CNIG_REG_DBG_SELECT_K2 \ 718 0x218254UL 719 #define CNIG_REG_DBG_DWORD_ENABLE_K2 \ 720 0x218258UL 721 #define CNIG_REG_DBG_SHIFT_K2 \ 722 0x21825cUL 723 #define CNIG_REG_DBG_FORCE_VALID_K2 \ 724 0x218260UL 725 #define CNIG_REG_DBG_FORCE_FRAME_K2 \ 726 0x218264UL 727 #define PRM_REG_DBG_SELECT \ 728 0x2306a8UL 729 #define PRM_REG_DBG_DWORD_ENABLE \ 730 0x2306acUL 731 #define PRM_REG_DBG_SHIFT \ 732 0x2306b0UL 733 #define PRM_REG_DBG_FORCE_VALID \ 734 0x2306b4UL 735 #define PRM_REG_DBG_FORCE_FRAME \ 736 0x2306b8UL 737 #define SRC_REG_DBG_SELECT \ 738 0x238700UL 739 #define SRC_REG_DBG_DWORD_ENABLE \ 740 0x238704UL 741 #define SRC_REG_DBG_SHIFT \ 742 0x238708UL 743 #define SRC_REG_DBG_FORCE_VALID \ 744 0x23870cUL 745 #define SRC_REG_DBG_FORCE_FRAME \ 746 0x238710UL 747 #define RSS_REG_DBG_SELECT \ 748 0x238c4cUL 749 #define RSS_REG_DBG_DWORD_ENABLE \ 750 0x238c50UL 751 #define RSS_REG_DBG_SHIFT \ 752 0x238c54UL 753 #define RSS_REG_DBG_FORCE_VALID \ 754 0x238c58UL 755 #define RSS_REG_DBG_FORCE_FRAME \ 756 0x238c5cUL 757 #define RPB_REG_DBG_SELECT \ 758 0x23c728UL 759 #define RPB_REG_DBG_DWORD_ENABLE \ 760 0x23c72cUL 761 #define RPB_REG_DBG_SHIFT \ 762 0x23c730UL 763 #define RPB_REG_DBG_FORCE_VALID \ 764 0x23c734UL 765 #define RPB_REG_DBG_FORCE_FRAME \ 766 0x23c738UL 767 #define PSWRQ2_REG_DBG_SELECT \ 768 0x240100UL 769 #define PSWRQ2_REG_DBG_DWORD_ENABLE \ 770 0x240104UL 771 #define PSWRQ2_REG_DBG_SHIFT \ 772 0x240108UL 773 #define PSWRQ2_REG_DBG_FORCE_VALID \ 774 0x24010cUL 775 #define PSWRQ2_REG_DBG_FORCE_FRAME \ 776 0x240110UL 777 #define PSWRQ_REG_DBG_SELECT \ 778 0x280020UL 779 #define PSWRQ_REG_DBG_DWORD_ENABLE \ 780 0x280024UL 781 #define PSWRQ_REG_DBG_SHIFT \ 782 0x280028UL 783 #define PSWRQ_REG_DBG_FORCE_VALID \ 784 0x28002cUL 785 #define PSWRQ_REG_DBG_FORCE_FRAME \ 786 0x280030UL 787 #define PSWWR_REG_DBG_SELECT \ 788 0x29a084UL 789 #define PSWWR_REG_DBG_DWORD_ENABLE \ 790 0x29a088UL 791 #define PSWWR_REG_DBG_SHIFT \ 792 0x29a08cUL 793 #define PSWWR_REG_DBG_FORCE_VALID \ 794 0x29a090UL 795 #define PSWWR_REG_DBG_FORCE_FRAME \ 796 0x29a094UL 797 #define PSWRD_REG_DBG_SELECT \ 798 0x29c040UL 799 #define PSWRD_REG_DBG_DWORD_ENABLE \ 800 0x29c044UL 801 #define PSWRD_REG_DBG_SHIFT \ 802 0x29c048UL 803 #define PSWRD_REG_DBG_FORCE_VALID \ 804 0x29c04cUL 805 #define PSWRD_REG_DBG_FORCE_FRAME \ 806 0x29c050UL 807 #define PSWRD2_REG_DBG_SELECT \ 808 0x29d400UL 809 #define PSWRD2_REG_DBG_DWORD_ENABLE \ 810 0x29d404UL 811 #define PSWRD2_REG_DBG_SHIFT \ 812 0x29d408UL 813 #define PSWRD2_REG_DBG_FORCE_VALID \ 814 0x29d40cUL 815 #define PSWRD2_REG_DBG_FORCE_FRAME \ 816 0x29d410UL 817 #define PSWHST2_REG_DBG_SELECT \ 818 0x29e058UL 819 #define PSWHST2_REG_DBG_DWORD_ENABLE \ 820 0x29e05cUL 821 #define PSWHST2_REG_DBG_SHIFT \ 822 0x29e060UL 823 #define PSWHST2_REG_DBG_FORCE_VALID \ 824 0x29e064UL 825 #define PSWHST2_REG_DBG_FORCE_FRAME \ 826 0x29e068UL 827 #define PSWHST_REG_DBG_SELECT \ 828 0x2a0100UL 829 #define PSWHST_REG_DBG_DWORD_ENABLE \ 830 0x2a0104UL 831 #define PSWHST_REG_DBG_SHIFT \ 832 0x2a0108UL 833 #define PSWHST_REG_DBG_FORCE_VALID \ 834 0x2a010cUL 835 #define PSWHST_REG_DBG_FORCE_FRAME \ 836 0x2a0110UL 837 #define PGLUE_B_REG_DBG_SELECT \ 838 0x2a8400UL 839 #define PGLUE_B_REG_DBG_DWORD_ENABLE \ 840 0x2a8404UL 841 #define PGLUE_B_REG_DBG_SHIFT \ 842 0x2a8408UL 843 #define PGLUE_B_REG_DBG_FORCE_VALID \ 844 0x2a840cUL 845 #define PGLUE_B_REG_DBG_FORCE_FRAME \ 846 0x2a8410UL 847 #define TM_REG_DBG_SELECT \ 848 0x2c07a8UL 849 #define TM_REG_DBG_DWORD_ENABLE \ 850 0x2c07acUL 851 #define TM_REG_DBG_SHIFT \ 852 0x2c07b0UL 853 #define TM_REG_DBG_FORCE_VALID \ 854 0x2c07b4UL 855 #define TM_REG_DBG_FORCE_FRAME \ 856 0x2c07b8UL 857 #define TCFC_REG_DBG_SELECT \ 858 0x2d0500UL 859 #define TCFC_REG_DBG_DWORD_ENABLE \ 860 0x2d0504UL 861 #define TCFC_REG_DBG_SHIFT \ 862 0x2d0508UL 863 #define TCFC_REG_DBG_FORCE_VALID \ 864 0x2d050cUL 865 #define TCFC_REG_DBG_FORCE_FRAME \ 866 0x2d0510UL 867 #define CCFC_REG_DBG_SELECT \ 868 0x2e0500UL 869 #define CCFC_REG_DBG_DWORD_ENABLE \ 870 0x2e0504UL 871 #define CCFC_REG_DBG_SHIFT \ 872 0x2e0508UL 873 #define CCFC_REG_DBG_FORCE_VALID \ 874 0x2e050cUL 875 #define CCFC_REG_DBG_FORCE_FRAME \ 876 0x2e0510UL 877 #define QM_REG_DBG_SELECT \ 878 0x2f2e74UL 879 #define QM_REG_DBG_DWORD_ENABLE \ 880 0x2f2e78UL 881 #define QM_REG_DBG_SHIFT \ 882 0x2f2e7cUL 883 #define QM_REG_DBG_FORCE_VALID \ 884 0x2f2e80UL 885 #define QM_REG_DBG_FORCE_FRAME \ 886 0x2f2e84UL 887 #define RDIF_REG_DBG_SELECT \ 888 0x300500UL 889 #define RDIF_REG_DBG_DWORD_ENABLE \ 890 0x300504UL 891 #define RDIF_REG_DBG_SHIFT \ 892 0x300508UL 893 #define RDIF_REG_DBG_FORCE_VALID \ 894 0x30050cUL 895 #define RDIF_REG_DBG_FORCE_FRAME \ 896 0x300510UL 897 #define TDIF_REG_DBG_SELECT \ 898 0x310500UL 899 #define TDIF_REG_DBG_DWORD_ENABLE \ 900 0x310504UL 901 #define TDIF_REG_DBG_SHIFT \ 902 0x310508UL 903 #define TDIF_REG_DBG_FORCE_VALID \ 904 0x31050cUL 905 #define TDIF_REG_DBG_FORCE_FRAME \ 906 0x310510UL 907 #define BRB_REG_DBG_SELECT \ 908 0x340ed0UL 909 #define BRB_REG_DBG_DWORD_ENABLE \ 910 0x340ed4UL 911 #define BRB_REG_DBG_SHIFT \ 912 0x340ed8UL 913 #define BRB_REG_DBG_FORCE_VALID \ 914 0x340edcUL 915 #define BRB_REG_DBG_FORCE_FRAME \ 916 0x340ee0UL 917 #define XYLD_REG_DBG_SELECT \ 918 0x4c1600UL 919 #define XYLD_REG_DBG_DWORD_ENABLE \ 920 0x4c1604UL 921 #define XYLD_REG_DBG_SHIFT \ 922 0x4c1608UL 923 #define XYLD_REG_DBG_FORCE_VALID \ 924 0x4c160cUL 925 #define XYLD_REG_DBG_FORCE_FRAME \ 926 0x4c1610UL 927 #define YULD_REG_DBG_SELECT \ 928 0x4c9600UL 929 #define YULD_REG_DBG_DWORD_ENABLE \ 930 0x4c9604UL 931 #define YULD_REG_DBG_SHIFT \ 932 0x4c9608UL 933 #define YULD_REG_DBG_FORCE_VALID \ 934 0x4c960cUL 935 #define YULD_REG_DBG_FORCE_FRAME \ 936 0x4c9610UL 937 #define TMLD_REG_DBG_SELECT \ 938 0x4d1600UL 939 #define TMLD_REG_DBG_DWORD_ENABLE \ 940 0x4d1604UL 941 #define TMLD_REG_DBG_SHIFT \ 942 0x4d1608UL 943 #define TMLD_REG_DBG_FORCE_VALID \ 944 0x4d160cUL 945 #define TMLD_REG_DBG_FORCE_FRAME \ 946 0x4d1610UL 947 #define MULD_REG_DBG_SELECT \ 948 0x4e1600UL 949 #define MULD_REG_DBG_DWORD_ENABLE \ 950 0x4e1604UL 951 #define MULD_REG_DBG_SHIFT \ 952 0x4e1608UL 953 #define MULD_REG_DBG_FORCE_VALID \ 954 0x4e160cUL 955 #define MULD_REG_DBG_FORCE_FRAME \ 956 0x4e1610UL 957 #define NIG_REG_DBG_SELECT \ 958 0x502140UL 959 #define NIG_REG_DBG_DWORD_ENABLE \ 960 0x502144UL 961 #define NIG_REG_DBG_SHIFT \ 962 0x502148UL 963 #define NIG_REG_DBG_FORCE_VALID \ 964 0x50214cUL 965 #define NIG_REG_DBG_FORCE_FRAME \ 966 0x502150UL 967 #define BMB_REG_DBG_SELECT \ 968 0x540a7cUL 969 #define BMB_REG_DBG_DWORD_ENABLE \ 970 0x540a80UL 971 #define BMB_REG_DBG_SHIFT \ 972 0x540a84UL 973 #define BMB_REG_DBG_FORCE_VALID \ 974 0x540a88UL 975 #define BMB_REG_DBG_FORCE_FRAME \ 976 0x540a8cUL 977 #define PTU_REG_DBG_SELECT \ 978 0x560100UL 979 #define PTU_REG_DBG_DWORD_ENABLE \ 980 0x560104UL 981 #define PTU_REG_DBG_SHIFT \ 982 0x560108UL 983 #define PTU_REG_DBG_FORCE_VALID \ 984 0x56010cUL 985 #define PTU_REG_DBG_FORCE_FRAME \ 986 0x560110UL 987 #define CDU_REG_DBG_SELECT \ 988 0x580704UL 989 #define CDU_REG_DBG_DWORD_ENABLE \ 990 0x580708UL 991 #define CDU_REG_DBG_SHIFT \ 992 0x58070cUL 993 #define CDU_REG_DBG_FORCE_VALID \ 994 0x580710UL 995 #define CDU_REG_DBG_FORCE_FRAME \ 996 0x580714UL 997 #define WOL_REG_DBG_SELECT \ 998 0x600140UL 999 #define WOL_REG_DBG_DWORD_ENABLE \ 1000 0x600144UL 1001 #define WOL_REG_DBG_SHIFT \ 1002 0x600148UL 1003 #define WOL_REG_DBG_FORCE_VALID \ 1004 0x60014cUL 1005 #define WOL_REG_DBG_FORCE_FRAME \ 1006 0x600150UL 1007 #define BMBN_REG_DBG_SELECT \ 1008 0x610140UL 1009 #define BMBN_REG_DBG_DWORD_ENABLE \ 1010 0x610144UL 1011 #define BMBN_REG_DBG_SHIFT \ 1012 0x610148UL 1013 #define BMBN_REG_DBG_FORCE_VALID \ 1014 0x61014cUL 1015 #define BMBN_REG_DBG_FORCE_FRAME \ 1016 0x610150UL 1017 #define NWM_REG_DBG_SELECT \ 1018 0x8000ecUL 1019 #define NWM_REG_DBG_DWORD_ENABLE \ 1020 0x8000f0UL 1021 #define NWM_REG_DBG_SHIFT \ 1022 0x8000f4UL 1023 #define NWM_REG_DBG_FORCE_VALID \ 1024 0x8000f8UL 1025 #define NWM_REG_DBG_FORCE_FRAME \ 1026 0x8000fcUL 1027 #define PBF_REG_DBG_SELECT \ 1028 0xd80060UL 1029 #define PBF_REG_DBG_DWORD_ENABLE \ 1030 0xd80064UL 1031 #define PBF_REG_DBG_SHIFT \ 1032 0xd80068UL 1033 #define PBF_REG_DBG_FORCE_VALID \ 1034 0xd8006cUL 1035 #define PBF_REG_DBG_FORCE_FRAME \ 1036 0xd80070UL 1037 #define PBF_PB1_REG_DBG_SELECT \ 1038 0xda0728UL 1039 #define PBF_PB1_REG_DBG_DWORD_ENABLE \ 1040 0xda072cUL 1041 #define PBF_PB1_REG_DBG_SHIFT \ 1042 0xda0730UL 1043 #define PBF_PB1_REG_DBG_FORCE_VALID \ 1044 0xda0734UL 1045 #define PBF_PB1_REG_DBG_FORCE_FRAME \ 1046 0xda0738UL 1047 #define PBF_PB2_REG_DBG_SELECT \ 1048 0xda4728UL 1049 #define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1050 0xda472cUL 1051 #define PBF_PB2_REG_DBG_SHIFT \ 1052 0xda4730UL 1053 #define PBF_PB2_REG_DBG_FORCE_VALID \ 1054 0xda4734UL 1055 #define PBF_PB2_REG_DBG_FORCE_FRAME \ 1056 0xda4738UL 1057 #define BTB_REG_DBG_SELECT \ 1058 0xdb08c8UL 1059 #define BTB_REG_DBG_DWORD_ENABLE \ 1060 0xdb08ccUL 1061 #define BTB_REG_DBG_SHIFT \ 1062 0xdb08d0UL 1063 #define BTB_REG_DBG_FORCE_VALID \ 1064 0xdb08d4UL 1065 #define BTB_REG_DBG_FORCE_FRAME \ 1066 0xdb08d8UL 1067 #define XSDM_REG_DBG_SELECT \ 1068 0xf80e28UL 1069 #define XSDM_REG_DBG_DWORD_ENABLE \ 1070 0xf80e2cUL 1071 #define XSDM_REG_DBG_SHIFT \ 1072 0xf80e30UL 1073 #define XSDM_REG_DBG_FORCE_VALID \ 1074 0xf80e34UL 1075 #define XSDM_REG_DBG_FORCE_FRAME \ 1076 0xf80e38UL 1077 #define YSDM_REG_DBG_SELECT \ 1078 0xf90e28UL 1079 #define YSDM_REG_DBG_DWORD_ENABLE \ 1080 0xf90e2cUL 1081 #define YSDM_REG_DBG_SHIFT \ 1082 0xf90e30UL 1083 #define YSDM_REG_DBG_FORCE_VALID \ 1084 0xf90e34UL 1085 #define YSDM_REG_DBG_FORCE_FRAME \ 1086 0xf90e38UL 1087 #define PSDM_REG_DBG_SELECT \ 1088 0xfa0e28UL 1089 #define PSDM_REG_DBG_DWORD_ENABLE \ 1090 0xfa0e2cUL 1091 #define PSDM_REG_DBG_SHIFT \ 1092 0xfa0e30UL 1093 #define PSDM_REG_DBG_FORCE_VALID \ 1094 0xfa0e34UL 1095 #define PSDM_REG_DBG_FORCE_FRAME \ 1096 0xfa0e38UL 1097 #define TSDM_REG_DBG_SELECT \ 1098 0xfb0e28UL 1099 #define TSDM_REG_DBG_DWORD_ENABLE \ 1100 0xfb0e2cUL 1101 #define TSDM_REG_DBG_SHIFT \ 1102 0xfb0e30UL 1103 #define TSDM_REG_DBG_FORCE_VALID \ 1104 0xfb0e34UL 1105 #define TSDM_REG_DBG_FORCE_FRAME \ 1106 0xfb0e38UL 1107 #define MSDM_REG_DBG_SELECT \ 1108 0xfc0e28UL 1109 #define MSDM_REG_DBG_DWORD_ENABLE \ 1110 0xfc0e2cUL 1111 #define MSDM_REG_DBG_SHIFT \ 1112 0xfc0e30UL 1113 #define MSDM_REG_DBG_FORCE_VALID \ 1114 0xfc0e34UL 1115 #define MSDM_REG_DBG_FORCE_FRAME \ 1116 0xfc0e38UL 1117 #define USDM_REG_DBG_SELECT \ 1118 0xfd0e28UL 1119 #define USDM_REG_DBG_DWORD_ENABLE \ 1120 0xfd0e2cUL 1121 #define USDM_REG_DBG_SHIFT \ 1122 0xfd0e30UL 1123 #define USDM_REG_DBG_FORCE_VALID \ 1124 0xfd0e34UL 1125 #define USDM_REG_DBG_FORCE_FRAME \ 1126 0xfd0e38UL 1127 #define XCM_REG_DBG_SELECT \ 1128 0x1000040UL 1129 #define XCM_REG_DBG_DWORD_ENABLE \ 1130 0x1000044UL 1131 #define XCM_REG_DBG_SHIFT \ 1132 0x1000048UL 1133 #define XCM_REG_DBG_FORCE_VALID \ 1134 0x100004cUL 1135 #define XCM_REG_DBG_FORCE_FRAME \ 1136 0x1000050UL 1137 #define YCM_REG_DBG_SELECT \ 1138 0x1080040UL 1139 #define YCM_REG_DBG_DWORD_ENABLE \ 1140 0x1080044UL 1141 #define YCM_REG_DBG_SHIFT \ 1142 0x1080048UL 1143 #define YCM_REG_DBG_FORCE_VALID \ 1144 0x108004cUL 1145 #define YCM_REG_DBG_FORCE_FRAME \ 1146 0x1080050UL 1147 #define PCM_REG_DBG_SELECT \ 1148 0x1100040UL 1149 #define PCM_REG_DBG_DWORD_ENABLE \ 1150 0x1100044UL 1151 #define PCM_REG_DBG_SHIFT \ 1152 0x1100048UL 1153 #define PCM_REG_DBG_FORCE_VALID \ 1154 0x110004cUL 1155 #define PCM_REG_DBG_FORCE_FRAME \ 1156 0x1100050UL 1157 #define TCM_REG_DBG_SELECT \ 1158 0x1180040UL 1159 #define TCM_REG_DBG_DWORD_ENABLE \ 1160 0x1180044UL 1161 #define TCM_REG_DBG_SHIFT \ 1162 0x1180048UL 1163 #define TCM_REG_DBG_FORCE_VALID \ 1164 0x118004cUL 1165 #define TCM_REG_DBG_FORCE_FRAME \ 1166 0x1180050UL 1167 #define MCM_REG_DBG_SELECT \ 1168 0x1200040UL 1169 #define MCM_REG_DBG_DWORD_ENABLE \ 1170 0x1200044UL 1171 #define MCM_REG_DBG_SHIFT \ 1172 0x1200048UL 1173 #define MCM_REG_DBG_FORCE_VALID \ 1174 0x120004cUL 1175 #define MCM_REG_DBG_FORCE_FRAME \ 1176 0x1200050UL 1177 #define UCM_REG_DBG_SELECT \ 1178 0x1280050UL 1179 #define UCM_REG_DBG_DWORD_ENABLE \ 1180 0x1280054UL 1181 #define UCM_REG_DBG_SHIFT \ 1182 0x1280058UL 1183 #define UCM_REG_DBG_FORCE_VALID \ 1184 0x128005cUL 1185 #define UCM_REG_DBG_FORCE_FRAME \ 1186 0x1280060UL 1187 #define XSEM_REG_DBG_SELECT \ 1188 0x1401528UL 1189 #define XSEM_REG_DBG_DWORD_ENABLE \ 1190 0x140152cUL 1191 #define XSEM_REG_DBG_SHIFT \ 1192 0x1401530UL 1193 #define XSEM_REG_DBG_FORCE_VALID \ 1194 0x1401534UL 1195 #define XSEM_REG_DBG_FORCE_FRAME \ 1196 0x1401538UL 1197 #define YSEM_REG_DBG_SELECT \ 1198 0x1501528UL 1199 #define YSEM_REG_DBG_DWORD_ENABLE \ 1200 0x150152cUL 1201 #define YSEM_REG_DBG_SHIFT \ 1202 0x1501530UL 1203 #define YSEM_REG_DBG_FORCE_VALID \ 1204 0x1501534UL 1205 #define YSEM_REG_DBG_FORCE_FRAME \ 1206 0x1501538UL 1207 #define PSEM_REG_DBG_SELECT \ 1208 0x1601528UL 1209 #define PSEM_REG_DBG_DWORD_ENABLE \ 1210 0x160152cUL 1211 #define PSEM_REG_DBG_SHIFT \ 1212 0x1601530UL 1213 #define PSEM_REG_DBG_FORCE_VALID \ 1214 0x1601534UL 1215 #define PSEM_REG_DBG_FORCE_FRAME \ 1216 0x1601538UL 1217 #define TSEM_REG_DBG_SELECT \ 1218 0x1701528UL 1219 #define TSEM_REG_DBG_DWORD_ENABLE \ 1220 0x170152cUL 1221 #define TSEM_REG_DBG_SHIFT \ 1222 0x1701530UL 1223 #define TSEM_REG_DBG_FORCE_VALID \ 1224 0x1701534UL 1225 #define TSEM_REG_DBG_FORCE_FRAME \ 1226 0x1701538UL 1227 #define MSEM_REG_DBG_SELECT \ 1228 0x1801528UL 1229 #define MSEM_REG_DBG_DWORD_ENABLE \ 1230 0x180152cUL 1231 #define MSEM_REG_DBG_SHIFT \ 1232 0x1801530UL 1233 #define MSEM_REG_DBG_FORCE_VALID \ 1234 0x1801534UL 1235 #define MSEM_REG_DBG_FORCE_FRAME \ 1236 0x1801538UL 1237 #define USEM_REG_DBG_SELECT \ 1238 0x1901528UL 1239 #define USEM_REG_DBG_DWORD_ENABLE \ 1240 0x190152cUL 1241 #define USEM_REG_DBG_SHIFT \ 1242 0x1901530UL 1243 #define USEM_REG_DBG_FORCE_VALID \ 1244 0x1901534UL 1245 #define USEM_REG_DBG_FORCE_FRAME \ 1246 0x1901538UL 1247 #define NWS_REG_DBG_SELECT \ 1248 0x700128UL 1249 #define NWS_REG_DBG_DWORD_ENABLE \ 1250 0x70012cUL 1251 #define NWS_REG_DBG_SHIFT \ 1252 0x700130UL 1253 #define NWS_REG_DBG_FORCE_VALID \ 1254 0x700134UL 1255 #define NWS_REG_DBG_FORCE_FRAME \ 1256 0x700138UL 1257 #define MS_REG_DBG_SELECT \ 1258 0x6a0228UL 1259 #define MS_REG_DBG_DWORD_ENABLE \ 1260 0x6a022cUL 1261 #define MS_REG_DBG_SHIFT \ 1262 0x6a0230UL 1263 #define MS_REG_DBG_FORCE_VALID \ 1264 0x6a0234UL 1265 #define MS_REG_DBG_FORCE_FRAME \ 1266 0x6a0238UL 1267 #define PCIE_REG_DBG_COMMON_SELECT \ 1268 0x054398UL 1269 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE \ 1270 0x05439cUL 1271 #define PCIE_REG_DBG_COMMON_SHIFT \ 1272 0x0543a0UL 1273 #define PCIE_REG_DBG_COMMON_FORCE_VALID \ 1274 0x0543a4UL 1275 #define PCIE_REG_DBG_COMMON_FORCE_FRAME \ 1276 0x0543a8UL 1277 #define MISC_REG_RESET_PL_UA \ 1278 0x008050UL 1279 #define MISC_REG_RESET_PL_HV \ 1280 0x008060UL 1281 #define XCM_REG_CTX_RBC_ACCS \ 1282 0x1001800UL 1283 #define XCM_REG_AGG_CON_CTX \ 1284 0x1001804UL 1285 #define XCM_REG_SM_CON_CTX \ 1286 0x1001808UL 1287 #define YCM_REG_CTX_RBC_ACCS \ 1288 0x1081800UL 1289 #define YCM_REG_AGG_CON_CTX \ 1290 0x1081804UL 1291 #define YCM_REG_AGG_TASK_CTX \ 1292 0x1081808UL 1293 #define YCM_REG_SM_CON_CTX \ 1294 0x108180cUL 1295 #define YCM_REG_SM_TASK_CTX \ 1296 0x1081810UL 1297 #define PCM_REG_CTX_RBC_ACCS \ 1298 0x1101440UL 1299 #define PCM_REG_SM_CON_CTX \ 1300 0x1101444UL 1301 #define TCM_REG_CTX_RBC_ACCS \ 1302 0x11814c0UL 1303 #define TCM_REG_AGG_CON_CTX \ 1304 0x11814c4UL 1305 #define TCM_REG_AGG_TASK_CTX \ 1306 0x11814c8UL 1307 #define TCM_REG_SM_CON_CTX \ 1308 0x11814ccUL 1309 #define TCM_REG_SM_TASK_CTX \ 1310 0x11814d0UL 1311 #define MCM_REG_CTX_RBC_ACCS \ 1312 0x1201800UL 1313 #define MCM_REG_AGG_CON_CTX \ 1314 0x1201804UL 1315 #define MCM_REG_AGG_TASK_CTX \ 1316 0x1201808UL 1317 #define MCM_REG_SM_CON_CTX \ 1318 0x120180cUL 1319 #define MCM_REG_SM_TASK_CTX \ 1320 0x1201810UL 1321 #define UCM_REG_CTX_RBC_ACCS \ 1322 0x1281700UL 1323 #define UCM_REG_AGG_CON_CTX \ 1324 0x1281704UL 1325 #define UCM_REG_AGG_TASK_CTX \ 1326 0x1281708UL 1327 #define UCM_REG_SM_CON_CTX \ 1328 0x128170cUL 1329 #define UCM_REG_SM_TASK_CTX \ 1330 0x1281710UL 1331 #define XSEM_REG_SLOW_DBG_EMPTY \ 1332 0x1401140UL 1333 #define XSEM_REG_SYNC_DBG_EMPTY \ 1334 0x1401160UL 1335 #define XSEM_REG_SLOW_DBG_ACTIVE \ 1336 0x1401400UL 1337 #define XSEM_REG_SLOW_DBG_MODE \ 1338 0x1401404UL 1339 #define XSEM_REG_DBG_FRAME_MODE \ 1340 0x1401408UL 1341 #define XSEM_REG_DBG_MODE1_CFG \ 1342 0x1401420UL 1343 #define XSEM_REG_FAST_MEMORY \ 1344 0x1440000UL 1345 #define YSEM_REG_SYNC_DBG_EMPTY \ 1346 0x1501160UL 1347 #define YSEM_REG_SLOW_DBG_ACTIVE \ 1348 0x1501400UL 1349 #define YSEM_REG_SLOW_DBG_MODE \ 1350 0x1501404UL 1351 #define YSEM_REG_DBG_FRAME_MODE \ 1352 0x1501408UL 1353 #define YSEM_REG_DBG_MODE1_CFG \ 1354 0x1501420UL 1355 #define YSEM_REG_FAST_MEMORY \ 1356 0x1540000UL 1357 #define PSEM_REG_SLOW_DBG_EMPTY \ 1358 0x1601140UL 1359 #define PSEM_REG_SYNC_DBG_EMPTY \ 1360 0x1601160UL 1361 #define PSEM_REG_SLOW_DBG_ACTIVE \ 1362 0x1601400UL 1363 #define PSEM_REG_SLOW_DBG_MODE \ 1364 0x1601404UL 1365 #define PSEM_REG_DBG_FRAME_MODE \ 1366 0x1601408UL 1367 #define PSEM_REG_DBG_MODE1_CFG \ 1368 0x1601420UL 1369 #define PSEM_REG_FAST_MEMORY \ 1370 0x1640000UL 1371 #define TSEM_REG_SLOW_DBG_EMPTY \ 1372 0x1701140UL 1373 #define TSEM_REG_SYNC_DBG_EMPTY \ 1374 0x1701160UL 1375 #define TSEM_REG_SLOW_DBG_ACTIVE \ 1376 0x1701400UL 1377 #define TSEM_REG_SLOW_DBG_MODE \ 1378 0x1701404UL 1379 #define TSEM_REG_DBG_FRAME_MODE \ 1380 0x1701408UL 1381 #define TSEM_REG_DBG_MODE1_CFG \ 1382 0x1701420UL 1383 #define TSEM_REG_FAST_MEMORY \ 1384 0x1740000UL 1385 #define MSEM_REG_SLOW_DBG_EMPTY \ 1386 0x1801140UL 1387 #define MSEM_REG_SYNC_DBG_EMPTY \ 1388 0x1801160UL 1389 #define MSEM_REG_SLOW_DBG_ACTIVE \ 1390 0x1801400UL 1391 #define MSEM_REG_SLOW_DBG_MODE \ 1392 0x1801404UL 1393 #define MSEM_REG_DBG_FRAME_MODE \ 1394 0x1801408UL 1395 #define MSEM_REG_DBG_MODE1_CFG \ 1396 0x1801420UL 1397 #define MSEM_REG_FAST_MEMORY \ 1398 0x1840000UL 1399 #define USEM_REG_SLOW_DBG_EMPTY \ 1400 0x1901140UL 1401 #define USEM_REG_SYNC_DBG_EMPTY \ 1402 0x1901160UL 1403 #define USEM_REG_SLOW_DBG_ACTIVE \ 1404 0x1901400UL 1405 #define USEM_REG_SLOW_DBG_MODE \ 1406 0x1901404UL 1407 #define USEM_REG_DBG_FRAME_MODE \ 1408 0x1901408UL 1409 #define USEM_REG_DBG_MODE1_CFG \ 1410 0x1901420UL 1411 #define USEM_REG_FAST_MEMORY \ 1412 0x1940000UL 1413 #define SEM_FAST_REG_INT_RAM \ 1414 0x020000UL 1415 #define SEM_FAST_REG_INT_RAM_SIZE \ 1416 20480 1417 #define GRC_REG_TRACE_FIFO_VALID_DATA \ 1418 0x050064UL 1419 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1420 0x05040cUL 1421 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1422 0x050500UL 1423 #define IGU_REG_ERROR_HANDLING_MEMORY \ 1424 0x181520UL 1425 #define MCP_REG_CPU_MODE \ 1426 0xe05000UL 1427 #define MCP_REG_CPU_MODE_SOFT_HALT \ 1428 (0x1 << 10) 1429 #define BRB_REG_BIG_RAM_ADDRESS \ 1430 0x340800UL 1431 #define BRB_REG_BIG_RAM_DATA \ 1432 0x341500UL 1433 #define SEM_FAST_REG_STALL_0 \ 1434 0x000488UL 1435 #define SEM_FAST_REG_STALLED \ 1436 0x000494UL 1437 #define BTB_REG_BIG_RAM_ADDRESS \ 1438 0xdb0800UL 1439 #define BTB_REG_BIG_RAM_DATA \ 1440 0xdb0c00UL 1441 #define BMB_REG_BIG_RAM_ADDRESS \ 1442 0x540800UL 1443 #define BMB_REG_BIG_RAM_DATA \ 1444 0x540f00UL 1445 #define SEM_FAST_REG_STORM_REG_FILE \ 1446 0x008000UL 1447 #define RSS_REG_RSS_RAM_ADDR \ 1448 0x238c30UL 1449 #define MISCS_REG_BLOCK_256B_EN \ 1450 0x009074UL 1451 #define MCP_REG_SCRATCH_SIZE \ 1452 57344 1453 #define MCP_REG_CPU_REG_FILE \ 1454 0xe05200UL 1455 #define MCP_REG_CPU_REG_FILE_SIZE \ 1456 32 1457 #define DBG_REG_DEBUG_TARGET \ 1458 0x01005cUL 1459 #define DBG_REG_FULL_MODE \ 1460 0x010060UL 1461 #define DBG_REG_CALENDAR_OUT_DATA \ 1462 0x010480UL 1463 #define GRC_REG_TRACE_FIFO \ 1464 0x050068UL 1465 #define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1466 0x181530UL 1467 #define DBG_REG_DBG_BLOCK_ON \ 1468 0x010454UL 1469 #define DBG_REG_FRAMING_MODE \ 1470 0x010058UL 1471 #define SEM_FAST_REG_VFC_DATA_WR \ 1472 0x000b40UL 1473 #define SEM_FAST_REG_VFC_ADDR \ 1474 0x000b44UL 1475 #define SEM_FAST_REG_VFC_DATA_RD \ 1476 0x000b48UL 1477 #define RSS_REG_RSS_RAM_DATA \ 1478 0x238c20UL 1479 #define RSS_REG_RSS_RAM_DATA_SIZE \ 1480 4 1481 #define MISC_REG_BLOCK_256B_EN \ 1482 0x008c14UL 1483 #define NWS_REG_NWS_CMU \ 1484 0x720000UL 1485 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0 \ 1486 0x000680UL 1487 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8 \ 1488 0x000684UL 1489 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0 \ 1490 0x0006c0UL 1491 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8 \ 1492 0x0006c4UL 1493 #define MS_REG_MS_CMU \ 1494 0x6a4000UL 1495 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130 \ 1496 0x000208UL 1497 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132 \ 1498 0x000210UL 1499 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131 \ 1500 0x00020cUL 1501 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133 \ 1502 0x000214UL 1503 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130 \ 1504 0x000208UL 1505 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131 \ 1506 0x00020cUL 1507 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132 \ 1508 0x000210UL 1509 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133 \ 1510 0x000214UL 1511 #define PHY_PCIE_REG_PHY0 \ 1512 0x620000UL 1513 #define PHY_PCIE_REG_PHY1 \ 1514 0x624000UL 1515 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1516 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1517 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1518 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1519 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1520 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1521 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1522 #define NIG_REG_RX_PTP_EN 0x501900UL 1523 #define NIG_REG_TX_PTP_EN 0x501904UL 1524 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL 1525 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL 1526 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL 1527 #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL 1528 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL 1529 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL 1530 #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL 1531 #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL 1532 #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL 1533 #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL 1534 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL 1535 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL 1536 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL 1537 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL 1538 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL 1539 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL 1540 #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL 1541 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL 1542 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL 1543 #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL 1544 #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL 1545 #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL 1546 #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL 1547 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL 1548 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL 1549 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL 1550 #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL 1551 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL 1552 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL 1553 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL 1554 #define PSWRQ2_REG_WR_MBS0 0x240400UL 1555 1556 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL 1557 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL 1558 #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL 1559 #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL 1560 #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL 1561 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL 1562 1563 #define PRS_REG_SEARCH_GFT 0x1f11bcUL 1564 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL 1565 #define PRS_REG_GFT_CAM 0x1f1100UL 1566 #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL 1567 #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 1568 #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 1569 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL 1570 1571 #endif 1572