1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_GCB = 27, 21 TARGET_ORG = 36, 22 TARGET_QS = 42, 23 TARGET_QSYS = 46, 24 TARGET_REW = 47, 25 TARGET_SYS = 52, 26 NUM_TARGETS = 66 27 }; 28 29 #define __REG(...) __VA_ARGS__ 30 31 /* AFI:PORT_TBL:PORT_FRM_OUT */ 32 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 33 34 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 35 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 36 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 38 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 39 40 /* AFI:PORT_TBL:PORT_CFG */ 41 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 42 43 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 44 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 45 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 47 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 48 49 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 50 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 51 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 52 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 53 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 54 55 /* ANA:ANA:ADVLEARN */ 56 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 57 58 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 59 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 60 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 61 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 62 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 63 64 /* ANA:ANA:VLANMASK */ 65 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 66 67 /* ANA:ANA:ANAINTR */ 68 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 69 70 #define ANA_ANAINTR_INTR BIT(1) 71 #define ANA_ANAINTR_INTR_SET(x)\ 72 FIELD_PREP(ANA_ANAINTR_INTR, x) 73 #define ANA_ANAINTR_INTR_GET(x)\ 74 FIELD_GET(ANA_ANAINTR_INTR, x) 75 76 #define ANA_ANAINTR_INTR_ENA BIT(0) 77 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 78 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 79 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 80 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 81 82 /* ANA:ANA:AUTOAGE */ 83 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 84 85 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 86 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 87 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 88 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 89 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 90 91 /* ANA:ANA:FLOODING */ 92 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 93 94 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 95 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 96 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 97 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 98 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 99 100 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 101 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 102 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 103 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 104 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 105 106 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 107 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 108 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 109 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 110 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 111 112 /* ANA:ANA:FLOODING_IPMC */ 113 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 114 115 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 116 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 117 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 118 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 119 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 120 121 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 122 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 123 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 124 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 125 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 126 127 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 128 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 129 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 130 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 131 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 132 133 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 134 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 135 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 136 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 137 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 138 139 /* ANA:PGID:PGID */ 140 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 141 142 #define ANA_PGID_PGID GENMASK(8, 0) 143 #define ANA_PGID_PGID_SET(x)\ 144 FIELD_PREP(ANA_PGID_PGID, x) 145 #define ANA_PGID_PGID_GET(x)\ 146 FIELD_GET(ANA_PGID_PGID, x) 147 148 /* ANA:PGID:PGID_CFG */ 149 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 150 151 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 152 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 153 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 154 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 155 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 156 157 /* ANA:ANA_TABLES:MACHDATA */ 158 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 159 160 /* ANA:ANA_TABLES:MACLDATA */ 161 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 162 163 /* ANA:ANA_TABLES:MACACCESS */ 164 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 165 166 #define ANA_MACACCESS_CHANGE2SW BIT(17) 167 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 168 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 169 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 170 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 171 172 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 173 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 174 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 175 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 176 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 177 178 #define ANA_MACACCESS_VALID BIT(12) 179 #define ANA_MACACCESS_VALID_SET(x)\ 180 FIELD_PREP(ANA_MACACCESS_VALID, x) 181 #define ANA_MACACCESS_VALID_GET(x)\ 182 FIELD_GET(ANA_MACACCESS_VALID, x) 183 184 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 185 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 186 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 187 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 188 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 189 190 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 191 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 192 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 193 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 194 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 195 196 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 197 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 198 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 199 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 200 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 201 202 /* ANA:ANA_TABLES:MACTINDX */ 203 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 204 205 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 206 #define ANA_MACTINDX_BUCKET_SET(x)\ 207 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 208 #define ANA_MACTINDX_BUCKET_GET(x)\ 209 FIELD_GET(ANA_MACTINDX_BUCKET, x) 210 211 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 212 #define ANA_MACTINDX_M_INDEX_SET(x)\ 213 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 214 #define ANA_MACTINDX_M_INDEX_GET(x)\ 215 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 216 217 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 218 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 219 220 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 221 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 222 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 223 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 224 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 225 226 /* ANA:ANA_TABLES:VLANACCESS */ 227 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 228 229 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 230 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 231 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 232 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 233 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 234 235 /* ANA:ANA_TABLES:VLANTIDX */ 236 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 237 238 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 239 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 240 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 241 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 242 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 243 244 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 245 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 246 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 247 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 248 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 249 250 /* ANA:PORT:VLAN_CFG */ 251 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 252 253 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 254 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 255 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 256 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 257 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 258 259 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 260 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 261 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 262 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 263 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 264 265 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 266 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 267 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 268 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 269 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 270 271 /* ANA:PORT:DROP_CFG */ 272 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 273 274 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 275 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 276 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 277 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 278 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 279 280 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 281 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 282 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 283 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 284 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 285 286 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 287 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 288 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 289 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 290 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 291 292 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 293 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 294 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 295 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 296 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 297 298 /* ANA:PORT:CPU_FWD_CFG */ 299 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 300 301 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 302 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 303 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 304 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 305 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 306 307 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 308 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 309 310 /* ANA:PORT:PORT_CFG */ 311 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 312 313 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 314 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 315 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 316 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 317 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 318 319 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 320 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 321 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 322 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 323 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 324 325 #define ANA_PORT_CFG_RECV_ENA BIT(4) 326 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 327 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 328 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 329 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 330 331 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 332 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 333 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 334 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 335 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 336 337 /* ANA:PFC:PFC_CFG */ 338 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 339 340 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 341 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 342 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 343 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 344 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 345 346 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 347 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 348 349 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 350 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 351 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 352 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 353 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 354 355 /* DEV:PORT_MODE:CLOCK_CFG */ 356 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 357 358 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 359 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 360 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 361 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 362 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 363 364 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 365 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 366 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 367 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 368 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 369 370 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 371 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 372 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 373 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 374 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 375 376 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 377 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 378 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 379 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 380 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 381 382 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 383 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 384 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 385 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 386 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 387 388 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 389 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 390 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 391 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 392 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 393 394 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 395 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 396 397 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 398 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 399 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 400 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 401 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 402 403 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 404 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 405 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 406 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 407 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 408 409 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 410 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 411 412 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 413 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 414 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 415 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 416 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 417 418 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 419 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 420 421 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 422 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 423 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 424 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 425 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 426 427 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 428 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 429 430 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 431 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 432 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 433 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 434 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 435 436 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 437 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 438 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 439 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 440 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 441 442 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 443 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 444 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 445 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 446 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 447 448 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 449 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 450 451 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 452 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 453 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 454 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 455 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 456 457 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 458 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 459 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 460 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 461 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 462 463 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 464 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 465 466 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 467 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 468 469 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 470 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 471 472 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 473 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 474 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 475 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 476 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 477 478 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 479 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 480 481 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 482 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 483 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 484 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 485 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 486 487 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 488 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 489 490 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 491 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 492 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 493 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 494 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 495 496 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 497 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 498 499 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 500 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 501 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 502 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 503 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 504 505 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 506 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 507 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 508 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 509 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 510 511 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 512 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 513 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 514 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 515 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 516 517 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 518 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 519 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 520 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 521 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 522 523 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 524 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 525 526 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 527 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 528 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 529 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 530 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 531 532 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 533 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 534 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 535 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 536 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 537 538 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 539 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 540 541 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 542 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 543 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 544 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 545 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 546 547 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 548 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 549 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 550 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 551 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 552 553 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 554 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 555 556 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 557 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 558 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 559 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 560 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 561 562 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 563 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 564 565 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 566 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 567 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 568 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 569 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 570 571 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 572 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 573 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 574 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 575 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 576 577 /* DEVCPU_QS:XTR:XTR_RD */ 578 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 579 580 /* DEVCPU_QS:XTR:XTR_FLUSH */ 581 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 582 583 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 584 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 585 586 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 587 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 588 589 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 590 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 591 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 592 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 593 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 594 595 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 596 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 597 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 598 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 599 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 600 601 /* DEVCPU_QS:INJ:INJ_WR */ 602 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 603 604 /* DEVCPU_QS:INJ:INJ_CTRL */ 605 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 606 607 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 608 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 609 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 610 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 611 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 612 613 #define QS_INJ_CTRL_EOF BIT(19) 614 #define QS_INJ_CTRL_EOF_SET(x)\ 615 FIELD_PREP(QS_INJ_CTRL_EOF, x) 616 #define QS_INJ_CTRL_EOF_GET(x)\ 617 FIELD_GET(QS_INJ_CTRL_EOF, x) 618 619 #define QS_INJ_CTRL_SOF BIT(18) 620 #define QS_INJ_CTRL_SOF_SET(x)\ 621 FIELD_PREP(QS_INJ_CTRL_SOF, x) 622 #define QS_INJ_CTRL_SOF_GET(x)\ 623 FIELD_GET(QS_INJ_CTRL_SOF, x) 624 625 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 626 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 627 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 628 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 629 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 630 631 /* DEVCPU_QS:INJ:INJ_STATUS */ 632 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 633 634 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 635 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 636 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 637 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 638 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 639 640 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 641 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 642 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 643 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 644 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 645 646 /* QSYS:SYSTEM:PORT_MODE */ 647 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 648 649 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 650 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 651 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 652 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 653 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 654 655 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 656 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 657 658 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 659 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 660 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 661 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 662 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 663 664 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 665 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 666 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 667 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 668 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 669 670 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 671 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 672 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 673 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 674 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 675 676 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 677 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 678 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 679 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 680 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 681 682 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 683 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 684 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 685 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 686 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 687 688 /* QSYS:SYSTEM:SW_STATUS */ 689 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 690 691 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 692 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 693 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 694 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 695 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 696 697 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 698 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 699 700 /* QSYS:RES_CTRL:RES_CFG */ 701 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 702 703 /* REW:PORT:PORT_VLAN_CFG */ 704 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 705 706 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 707 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 708 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 709 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 710 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 711 712 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 713 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 714 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 715 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 716 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 717 718 /* REW:PORT:TAG_CFG */ 719 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 720 721 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 722 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 723 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 724 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 725 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 726 727 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 728 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 729 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 730 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 731 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 732 733 /* REW:PORT:PORT_CFG */ 734 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 735 736 #define REW_PORT_CFG_NO_REWRITE BIT(0) 737 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 738 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 739 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 740 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 741 742 /* SYS:SYSTEM:RESET_CFG */ 743 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 744 745 #define SYS_RESET_CFG_CORE_ENA BIT(0) 746 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 747 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 748 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 749 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 750 751 /* SYS:SYSTEM:PORT_MODE */ 752 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 753 754 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 755 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 756 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 757 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 758 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 759 760 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 761 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 762 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 763 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 764 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 765 766 /* SYS:SYSTEM:FRONT_PORT_MODE */ 767 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 768 769 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 770 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 771 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 772 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 773 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 774 775 /* SYS:SYSTEM:FRM_AGING */ 776 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 777 778 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 779 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 780 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 781 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 782 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 783 784 /* SYS:SYSTEM:STAT_CFG */ 785 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 786 787 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 788 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 789 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 790 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 791 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 792 793 /* SYS:PAUSE_CFG:PAUSE_CFG */ 794 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 795 796 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 797 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 798 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 799 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 800 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 801 802 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 803 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 804 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 805 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 806 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 807 808 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 809 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 810 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 811 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 812 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 813 814 /* SYS:PAUSE_CFG:ATOP */ 815 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 816 817 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 818 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 819 820 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 821 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 822 823 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 824 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 825 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 826 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 827 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 828 829 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 830 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 831 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 832 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 833 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 834 835 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 836 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 837 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 838 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 839 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 840 841 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 842 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 843 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 844 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 845 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 846 847 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 848 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 849 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 850 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 851 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 852 853 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 854 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 855 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 856 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 857 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 858 859 /* SYS:STAT:CNT */ 860 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 861 862 /* SYS:RAM_CTRL:RAM_INIT */ 863 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 864 865 #define SYS_RAM_INIT_RAM_INIT BIT(1) 866 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 867 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 868 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 869 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 870 871 #endif /* _LAN966X_REGS_H_ */ 872