1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_clear_counter 3300 * Clear counters. 3301 * Access: OP 3302 */ 3303 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3304 3305 /* reg_qpcr_color_aware 3306 * Is the policer aware of colors. 3307 * Must be 0 (unaware) for cpu port. 3308 * Access: RW for unbounded policer. RO for bounded policer. 3309 */ 3310 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3311 3312 /* reg_qpcr_bytes 3313 * Is policer limit is for bytes per sec or packets per sec. 3314 * 0 - packets 3315 * 1 - bytes 3316 * Access: RW for unbounded policer. RO for bounded policer. 3317 */ 3318 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3319 3320 enum mlxsw_reg_qpcr_ir_units { 3321 MLXSW_REG_QPCR_IR_UNITS_M, 3322 MLXSW_REG_QPCR_IR_UNITS_K, 3323 }; 3324 3325 /* reg_qpcr_ir_units 3326 * Policer's units for cir and eir fields (for bytes limits only) 3327 * 1 - 10^3 3328 * 0 - 10^6 3329 * Access: OP 3330 */ 3331 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3332 3333 enum mlxsw_reg_qpcr_rate_type { 3334 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3335 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3336 }; 3337 3338 /* reg_qpcr_rate_type 3339 * Policer can have one limit (single rate) or 2 limits with specific operation 3340 * for packets that exceed the lower rate but not the upper one. 3341 * (For cpu port must be single rate) 3342 * Access: RW for unbounded policer. RO for bounded policer. 3343 */ 3344 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3345 3346 /* reg_qpc_cbs 3347 * Policer's committed burst size. 3348 * The policer is working with time slices of 50 nano sec. By default every 3349 * slice is granted the proportionate share of the committed rate. If we want to 3350 * allow a slice to exceed that share (while still keeping the rate per sec) we 3351 * can allow burst. The burst size is between the default proportionate share 3352 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3353 * committed rate will result in exceeding the rate). The burst size must be a 3354 * log of 2 and will be determined by 2^cbs. 3355 * Access: RW 3356 */ 3357 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3358 3359 /* reg_qpcr_cir 3360 * Policer's committed rate. 3361 * The rate used for sungle rate, the lower rate for double rate. 3362 * For bytes limits, the rate will be this value * the unit from ir_units. 3363 * (Resolution error is up to 1%). 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3367 3368 /* reg_qpcr_eir 3369 * Policer's exceed rate. 3370 * The higher rate for double rate, reserved for single rate. 3371 * Lower rate for double rate policer. 3372 * For bytes limits, the rate will be this value * the unit from ir_units. 3373 * (Resolution error is up to 1%). 3374 * Access: RW 3375 */ 3376 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3377 3378 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3379 3380 /* reg_qpcr_exceed_action. 3381 * What to do with packets between the 2 limits for double rate. 3382 * Access: RW for unbounded policer. RO for bounded policer. 3383 */ 3384 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3385 3386 enum mlxsw_reg_qpcr_action { 3387 /* Discard */ 3388 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3389 /* Forward and set color to red. 3390 * If the packet is intended to cpu port, it will be dropped. 3391 */ 3392 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3393 }; 3394 3395 /* reg_qpcr_violate_action 3396 * What to do with packets that cross the cir limit (for single rate) or the eir 3397 * limit (for double rate). 3398 * Access: RW for unbounded policer. RO for bounded policer. 3399 */ 3400 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3401 3402 /* reg_qpcr_violate_count 3403 * Counts the number of times violate_action happened on this PID. 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3407 3408 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3409 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3410 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3411 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3412 3413 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3414 enum mlxsw_reg_qpcr_ir_units ir_units, 3415 bool bytes, u32 cir, u16 cbs) 3416 { 3417 MLXSW_REG_ZERO(qpcr, payload); 3418 mlxsw_reg_qpcr_pid_set(payload, pid); 3419 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3420 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3421 mlxsw_reg_qpcr_violate_action_set(payload, 3422 MLXSW_REG_QPCR_ACTION_DISCARD); 3423 mlxsw_reg_qpcr_cir_set(payload, cir); 3424 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3425 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3426 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3427 } 3428 3429 /* QTCT - QoS Switch Traffic Class Table 3430 * ------------------------------------- 3431 * Configures the mapping between the packet switch priority and the 3432 * traffic class on the transmit port. 3433 */ 3434 #define MLXSW_REG_QTCT_ID 0x400A 3435 #define MLXSW_REG_QTCT_LEN 0x08 3436 3437 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3438 3439 /* reg_qtct_local_port 3440 * Local port number. 3441 * Access: Index 3442 * 3443 * Note: CPU port is not supported. 3444 */ 3445 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3446 3447 /* reg_qtct_sub_port 3448 * Virtual port within the physical port. 3449 * Should be set to 0 when virtual ports are not enabled on the port. 3450 * Access: Index 3451 */ 3452 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3453 3454 /* reg_qtct_switch_prio 3455 * Switch priority. 3456 * Access: Index 3457 */ 3458 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3459 3460 /* reg_qtct_tclass 3461 * Traffic class. 3462 * Default values: 3463 * switch_prio 0 : tclass 1 3464 * switch_prio 1 : tclass 0 3465 * switch_prio i : tclass i, for i > 1 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3469 3470 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3471 u8 switch_prio, u8 tclass) 3472 { 3473 MLXSW_REG_ZERO(qtct, payload); 3474 mlxsw_reg_qtct_local_port_set(payload, local_port); 3475 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3476 mlxsw_reg_qtct_tclass_set(payload, tclass); 3477 } 3478 3479 /* QEEC - QoS ETS Element Configuration Register 3480 * --------------------------------------------- 3481 * Configures the ETS elements. 3482 */ 3483 #define MLXSW_REG_QEEC_ID 0x400D 3484 #define MLXSW_REG_QEEC_LEN 0x20 3485 3486 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3487 3488 /* reg_qeec_local_port 3489 * Local port number. 3490 * Access: Index 3491 * 3492 * Note: CPU port is supported. 3493 */ 3494 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3495 3496 enum mlxsw_reg_qeec_hr { 3497 MLXSW_REG_QEEC_HR_PORT, 3498 MLXSW_REG_QEEC_HR_GROUP, 3499 MLXSW_REG_QEEC_HR_SUBGROUP, 3500 MLXSW_REG_QEEC_HR_TC, 3501 }; 3502 3503 /* reg_qeec_element_hierarchy 3504 * 0 - Port 3505 * 1 - Group 3506 * 2 - Subgroup 3507 * 3 - Traffic Class 3508 * Access: Index 3509 */ 3510 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3511 3512 /* reg_qeec_element_index 3513 * The index of the element in the hierarchy. 3514 * Access: Index 3515 */ 3516 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3517 3518 /* reg_qeec_next_element_index 3519 * The index of the next (lower) element in the hierarchy. 3520 * Access: RW 3521 * 3522 * Note: Reserved for element_hierarchy 0. 3523 */ 3524 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3525 3526 /* reg_qeec_mise 3527 * Min shaper configuration enable. Enables configuration of the min 3528 * shaper on this ETS element 3529 * 0 - Disable 3530 * 1 - Enable 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3534 3535 /* reg_qeec_ptps 3536 * PTP shaper 3537 * 0: regular shaper mode 3538 * 1: PTP oriented shaper 3539 * Allowed only for hierarchy 0 3540 * Not supported for CPU port 3541 * Note that ptps mode may affect the shaper rates of all hierarchies 3542 * Supported only on Spectrum-1 3543 * Access: RW 3544 */ 3545 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3546 3547 enum { 3548 MLXSW_REG_QEEC_BYTES_MODE, 3549 MLXSW_REG_QEEC_PACKETS_MODE, 3550 }; 3551 3552 /* reg_qeec_pb 3553 * Packets or bytes mode. 3554 * 0 - Bytes mode 3555 * 1 - Packets mode 3556 * Access: RW 3557 * 3558 * Note: Used for max shaper configuration. For Spectrum, packets mode 3559 * is supported only for traffic classes of CPU port. 3560 */ 3561 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3562 3563 /* The smallest permitted min shaper rate. */ 3564 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3565 3566 /* reg_qeec_min_shaper_rate 3567 * Min shaper information rate. 3568 * For CPU port, can only be configured for port hierarchy. 3569 * When in bytes mode, value is specified in units of 1000bps. 3570 * Access: RW 3571 */ 3572 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3573 3574 /* reg_qeec_mase 3575 * Max shaper configuration enable. Enables configuration of the max 3576 * shaper on this ETS element. 3577 * 0 - Disable 3578 * 1 - Enable 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3582 3583 /* The largest max shaper value possible to disable the shaper. */ 3584 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3585 3586 /* reg_qeec_max_shaper_rate 3587 * Max shaper information rate. 3588 * For CPU port, can only be configured for port hierarchy. 3589 * When in bytes mode, value is specified in units of 1000bps. 3590 * Access: RW 3591 */ 3592 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3593 3594 /* reg_qeec_de 3595 * DWRR configuration enable. Enables configuration of the dwrr and 3596 * dwrr_weight. 3597 * 0 - Disable 3598 * 1 - Enable 3599 * Access: RW 3600 */ 3601 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3602 3603 /* reg_qeec_dwrr 3604 * Transmission selection algorithm to use on the link going down from 3605 * the ETS element. 3606 * 0 - Strict priority 3607 * 1 - DWRR 3608 * Access: RW 3609 */ 3610 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3611 3612 /* reg_qeec_dwrr_weight 3613 * DWRR weight on the link going down from the ETS element. The 3614 * percentage of bandwidth guaranteed to an ETS element within 3615 * its hierarchy. The sum of all weights across all ETS elements 3616 * within one hierarchy should be equal to 100. Reserved when 3617 * transmission selection algorithm is strict priority. 3618 * Access: RW 3619 */ 3620 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3621 3622 /* reg_qeec_max_shaper_bs 3623 * Max shaper burst size 3624 * Burst size is 2^max_shaper_bs * 512 bits 3625 * For Spectrum-1: Range is: 5..25 3626 * For Spectrum-2: Range is: 11..25 3627 * Reserved when ptps = 1 3628 * Access: RW 3629 */ 3630 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3631 3632 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3633 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3634 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3635 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3636 3637 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3638 enum mlxsw_reg_qeec_hr hr, u8 index, 3639 u8 next_index) 3640 { 3641 MLXSW_REG_ZERO(qeec, payload); 3642 mlxsw_reg_qeec_local_port_set(payload, local_port); 3643 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3644 mlxsw_reg_qeec_element_index_set(payload, index); 3645 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3646 } 3647 3648 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3649 bool ptps) 3650 { 3651 MLXSW_REG_ZERO(qeec, payload); 3652 mlxsw_reg_qeec_local_port_set(payload, local_port); 3653 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3654 mlxsw_reg_qeec_ptps_set(payload, ptps); 3655 } 3656 3657 /* QRWE - QoS ReWrite Enable 3658 * ------------------------- 3659 * This register configures the rewrite enable per receive port. 3660 */ 3661 #define MLXSW_REG_QRWE_ID 0x400F 3662 #define MLXSW_REG_QRWE_LEN 0x08 3663 3664 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3665 3666 /* reg_qrwe_local_port 3667 * Local port number. 3668 * Access: Index 3669 * 3670 * Note: CPU port is supported. No support for router port. 3671 */ 3672 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3673 3674 /* reg_qrwe_dscp 3675 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3676 * Access: RW 3677 */ 3678 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3679 3680 /* reg_qrwe_pcp 3681 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3682 * Access: RW 3683 */ 3684 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3685 3686 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3687 bool rewrite_pcp, bool rewrite_dscp) 3688 { 3689 MLXSW_REG_ZERO(qrwe, payload); 3690 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3691 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3692 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3693 } 3694 3695 /* QPDSM - QoS Priority to DSCP Mapping 3696 * ------------------------------------ 3697 * QoS Priority to DSCP Mapping Register 3698 */ 3699 #define MLXSW_REG_QPDSM_ID 0x4011 3700 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3701 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3702 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3703 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3704 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3705 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3706 3707 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3708 3709 /* reg_qpdsm_local_port 3710 * Local Port. Supported for data packets from CPU port. 3711 * Access: Index 3712 */ 3713 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3714 3715 /* reg_qpdsm_prio_entry_color0_e 3716 * Enable update of the entry for color 0 and a given port. 3717 * Access: WO 3718 */ 3719 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3720 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3721 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3722 3723 /* reg_qpdsm_prio_entry_color0_dscp 3724 * DSCP field in the outer label of the packet for color 0 and a given port. 3725 * Reserved when e=0. 3726 * Access: RW 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3729 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3730 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3731 3732 /* reg_qpdsm_prio_entry_color1_e 3733 * Enable update of the entry for color 1 and a given port. 3734 * Access: WO 3735 */ 3736 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3737 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3738 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3739 3740 /* reg_qpdsm_prio_entry_color1_dscp 3741 * DSCP field in the outer label of the packet for color 1 and a given port. 3742 * Reserved when e=0. 3743 * Access: RW 3744 */ 3745 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3746 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3747 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3748 3749 /* reg_qpdsm_prio_entry_color2_e 3750 * Enable update of the entry for color 2 and a given port. 3751 * Access: WO 3752 */ 3753 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3754 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3755 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3756 3757 /* reg_qpdsm_prio_entry_color2_dscp 3758 * DSCP field in the outer label of the packet for color 2 and a given port. 3759 * Reserved when e=0. 3760 * Access: RW 3761 */ 3762 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3763 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3764 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3765 3766 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3767 { 3768 MLXSW_REG_ZERO(qpdsm, payload); 3769 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3770 } 3771 3772 static inline void 3773 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3774 { 3775 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3776 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3777 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3778 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3779 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3780 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3781 } 3782 3783 /* QPDP - QoS Port DSCP to Priority Mapping Register 3784 * ------------------------------------------------- 3785 * This register controls the port default Switch Priority and Color. The 3786 * default Switch Priority and Color are used for frames where the trust state 3787 * uses default values. All member ports of a LAG should be configured with the 3788 * same default values. 3789 */ 3790 #define MLXSW_REG_QPDP_ID 0x4007 3791 #define MLXSW_REG_QPDP_LEN 0x8 3792 3793 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3794 3795 /* reg_qpdp_local_port 3796 * Local Port. Supported for data packets from CPU port. 3797 * Access: Index 3798 */ 3799 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3800 3801 /* reg_qpdp_switch_prio 3802 * Default port Switch Priority (default 0) 3803 * Access: RW 3804 */ 3805 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3806 3807 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3808 u8 switch_prio) 3809 { 3810 MLXSW_REG_ZERO(qpdp, payload); 3811 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3812 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3813 } 3814 3815 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3816 * -------------------------------------------------- 3817 * This register controls the mapping from DSCP field to 3818 * Switch Priority for IP packets. 3819 */ 3820 #define MLXSW_REG_QPDPM_ID 0x4013 3821 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3822 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3823 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3824 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3825 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3826 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3827 3828 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3829 3830 /* reg_qpdpm_local_port 3831 * Local Port. Supported for data packets from CPU port. 3832 * Access: Index 3833 */ 3834 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3835 3836 /* reg_qpdpm_dscp_e 3837 * Enable update of the specific entry. When cleared, the switch_prio and color 3838 * fields are ignored and the previous switch_prio and color values are 3839 * preserved. 3840 * Access: WO 3841 */ 3842 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3843 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3844 3845 /* reg_qpdpm_dscp_prio 3846 * The new Switch Priority value for the relevant DSCP value. 3847 * Access: RW 3848 */ 3849 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3850 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3851 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3852 3853 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3854 { 3855 MLXSW_REG_ZERO(qpdpm, payload); 3856 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3857 } 3858 3859 static inline void 3860 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3861 { 3862 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3863 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3864 } 3865 3866 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3867 * ------------------------------------------------------------------ 3868 * This register configures if the Switch Priority to Traffic Class mapping is 3869 * based on Multicast packet indication. If so, then multicast packets will get 3870 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3871 * QTCT. 3872 * By default, Switch Priority to Traffic Class mapping is not based on 3873 * Multicast packet indication. 3874 */ 3875 #define MLXSW_REG_QTCTM_ID 0x401A 3876 #define MLXSW_REG_QTCTM_LEN 0x08 3877 3878 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3879 3880 /* reg_qtctm_local_port 3881 * Local port number. 3882 * No support for CPU port. 3883 * Access: Index 3884 */ 3885 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3886 3887 /* reg_qtctm_mc 3888 * Multicast Mode 3889 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3890 * indication (default is 0, not based on Multicast packet indication). 3891 */ 3892 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3893 3894 static inline void 3895 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3896 { 3897 MLXSW_REG_ZERO(qtctm, payload); 3898 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3899 mlxsw_reg_qtctm_mc_set(payload, mc); 3900 } 3901 3902 /* QPSC - QoS PTP Shaper Configuration Register 3903 * -------------------------------------------- 3904 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3905 * Supported only on Spectrum-1. 3906 */ 3907 #define MLXSW_REG_QPSC_ID 0x401B 3908 #define MLXSW_REG_QPSC_LEN 0x28 3909 3910 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3911 3912 enum mlxsw_reg_qpsc_port_speed { 3913 MLXSW_REG_QPSC_PORT_SPEED_100M, 3914 MLXSW_REG_QPSC_PORT_SPEED_1G, 3915 MLXSW_REG_QPSC_PORT_SPEED_10G, 3916 MLXSW_REG_QPSC_PORT_SPEED_25G, 3917 }; 3918 3919 /* reg_qpsc_port_speed 3920 * Port speed. 3921 * Access: Index 3922 */ 3923 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3924 3925 /* reg_qpsc_shaper_time_exp 3926 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3927 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3928 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3929 * Access: RW 3930 */ 3931 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3932 3933 /* reg_qpsc_shaper_time_mantissa 3934 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3935 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3936 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3937 * Access: RW 3938 */ 3939 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3940 3941 /* reg_qpsc_shaper_inc 3942 * Number of tokens added to shaper on each update. 3943 * Units of 8B. 3944 * Access: RW 3945 */ 3946 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3947 3948 /* reg_qpsc_shaper_bs 3949 * Max shaper Burst size. 3950 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3951 * Range is: 5..25 (from 2KB..2GB) 3952 * Access: RW 3953 */ 3954 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3955 3956 /* reg_qpsc_ptsc_we 3957 * Write enable to port_to_shaper_credits. 3958 * Access: WO 3959 */ 3960 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3961 3962 /* reg_qpsc_port_to_shaper_credits 3963 * For split ports: range 1..57 3964 * For non-split ports: range 1..112 3965 * Written only when ptsc_we is set. 3966 * Access: RW 3967 */ 3968 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3969 3970 /* reg_qpsc_ing_timestamp_inc 3971 * Ingress timestamp increment. 3972 * 2's complement. 3973 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3974 * value for all ports. 3975 * Same units as used by MTPPTR. 3976 * Access: RW 3977 */ 3978 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3979 3980 /* reg_qpsc_egr_timestamp_inc 3981 * Egress timestamp increment. 3982 * 2's complement. 3983 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3984 * value for all ports. 3985 * Same units as used by MTPPTR. 3986 * Access: RW 3987 */ 3988 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3989 3990 static inline void 3991 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 3992 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 3993 u8 shaper_bs, u8 port_to_shaper_credits, 3994 int ing_timestamp_inc, int egr_timestamp_inc) 3995 { 3996 MLXSW_REG_ZERO(qpsc, payload); 3997 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 3998 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 3999 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4000 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4001 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4002 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4003 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4004 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4005 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4006 } 4007 4008 /* PMLP - Ports Module to Local Port Register 4009 * ------------------------------------------ 4010 * Configures the assignment of modules to local ports. 4011 */ 4012 #define MLXSW_REG_PMLP_ID 0x5002 4013 #define MLXSW_REG_PMLP_LEN 0x40 4014 4015 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4016 4017 /* reg_pmlp_rxtx 4018 * 0 - Tx value is used for both Tx and Rx. 4019 * 1 - Rx value is taken from a separte field. 4020 * Access: RW 4021 */ 4022 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4023 4024 /* reg_pmlp_local_port 4025 * Local port number. 4026 * Access: Index 4027 */ 4028 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4029 4030 /* reg_pmlp_width 4031 * 0 - Unmap local port. 4032 * 1 - Lane 0 is used. 4033 * 2 - Lanes 0 and 1 are used. 4034 * 4 - Lanes 0, 1, 2 and 3 are used. 4035 * 8 - Lanes 0-7 are used. 4036 * Access: RW 4037 */ 4038 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4039 4040 /* reg_pmlp_module 4041 * Module number. 4042 * Access: RW 4043 */ 4044 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4045 4046 /* reg_pmlp_tx_lane 4047 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4048 * Access: RW 4049 */ 4050 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4051 4052 /* reg_pmlp_rx_lane 4053 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4054 * equal to Tx lane. 4055 * Access: RW 4056 */ 4057 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4058 4059 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4060 { 4061 MLXSW_REG_ZERO(pmlp, payload); 4062 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4063 } 4064 4065 /* PMTU - Port MTU Register 4066 * ------------------------ 4067 * Configures and reports the port MTU. 4068 */ 4069 #define MLXSW_REG_PMTU_ID 0x5003 4070 #define MLXSW_REG_PMTU_LEN 0x10 4071 4072 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4073 4074 /* reg_pmtu_local_port 4075 * Local port number. 4076 * Access: Index 4077 */ 4078 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4079 4080 /* reg_pmtu_max_mtu 4081 * Maximum MTU. 4082 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4083 * reported, otherwise the minimum between the max_mtu of the different 4084 * types is reported. 4085 * Access: RO 4086 */ 4087 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4088 4089 /* reg_pmtu_admin_mtu 4090 * MTU value to set port to. Must be smaller or equal to max_mtu. 4091 * Note: If port type is Infiniband, then port must be disabled, when its 4092 * MTU is set. 4093 * Access: RW 4094 */ 4095 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4096 4097 /* reg_pmtu_oper_mtu 4098 * The actual MTU configured on the port. Packets exceeding this size 4099 * will be dropped. 4100 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4101 * oper_mtu might be smaller than admin_mtu. 4102 * Access: RO 4103 */ 4104 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4105 4106 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4107 u16 new_mtu) 4108 { 4109 MLXSW_REG_ZERO(pmtu, payload); 4110 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4111 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4112 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4113 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4114 } 4115 4116 /* PTYS - Port Type and Speed Register 4117 * ----------------------------------- 4118 * Configures and reports the port speed type. 4119 * 4120 * Note: When set while the link is up, the changes will not take effect 4121 * until the port transitions from down to up state. 4122 */ 4123 #define MLXSW_REG_PTYS_ID 0x5004 4124 #define MLXSW_REG_PTYS_LEN 0x40 4125 4126 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4127 4128 /* an_disable_admin 4129 * Auto negotiation disable administrative configuration 4130 * 0 - Device doesn't support AN disable. 4131 * 1 - Device supports AN disable. 4132 * Access: RW 4133 */ 4134 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4135 4136 /* reg_ptys_local_port 4137 * Local port number. 4138 * Access: Index 4139 */ 4140 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4141 4142 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4143 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4144 4145 /* reg_ptys_proto_mask 4146 * Protocol mask. Indicates which protocol is used. 4147 * 0 - Infiniband. 4148 * 1 - Fibre Channel. 4149 * 2 - Ethernet. 4150 * Access: Index 4151 */ 4152 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4153 4154 enum { 4155 MLXSW_REG_PTYS_AN_STATUS_NA, 4156 MLXSW_REG_PTYS_AN_STATUS_OK, 4157 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4158 }; 4159 4160 /* reg_ptys_an_status 4161 * Autonegotiation status. 4162 * Access: RO 4163 */ 4164 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4165 4166 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4167 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4168 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 4169 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4170 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4171 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4172 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4173 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4174 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4175 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4176 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4177 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4178 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4179 4180 /* reg_ptys_ext_eth_proto_cap 4181 * Extended Ethernet port supported speeds and protocols. 4182 * Access: RO 4183 */ 4184 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4185 4186 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4187 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4188 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4189 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4190 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4191 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 4192 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4193 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4194 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4195 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4196 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4197 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4198 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4199 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4200 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4201 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4202 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4203 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4204 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4205 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4206 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4207 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4208 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4209 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4210 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4211 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4212 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4213 4214 /* reg_ptys_eth_proto_cap 4215 * Ethernet port supported speeds and protocols. 4216 * Access: RO 4217 */ 4218 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4219 4220 /* reg_ptys_ib_link_width_cap 4221 * IB port supported widths. 4222 * Access: RO 4223 */ 4224 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4225 4226 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4227 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4228 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4229 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4230 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4231 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4232 4233 /* reg_ptys_ib_proto_cap 4234 * IB port supported speeds and protocols. 4235 * Access: RO 4236 */ 4237 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4238 4239 /* reg_ptys_ext_eth_proto_admin 4240 * Extended speed and protocol to set port to. 4241 * Access: RW 4242 */ 4243 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4244 4245 /* reg_ptys_eth_proto_admin 4246 * Speed and protocol to set port to. 4247 * Access: RW 4248 */ 4249 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4250 4251 /* reg_ptys_ib_link_width_admin 4252 * IB width to set port to. 4253 * Access: RW 4254 */ 4255 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4256 4257 /* reg_ptys_ib_proto_admin 4258 * IB speeds and protocols to set port to. 4259 * Access: RW 4260 */ 4261 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4262 4263 /* reg_ptys_ext_eth_proto_oper 4264 * The extended current speed and protocol configured for the port. 4265 * Access: RO 4266 */ 4267 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4268 4269 /* reg_ptys_eth_proto_oper 4270 * The current speed and protocol configured for the port. 4271 * Access: RO 4272 */ 4273 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4274 4275 /* reg_ptys_ib_link_width_oper 4276 * The current IB width to set port to. 4277 * Access: RO 4278 */ 4279 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4280 4281 /* reg_ptys_ib_proto_oper 4282 * The current IB speed and protocol. 4283 * Access: RO 4284 */ 4285 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4286 4287 enum mlxsw_reg_ptys_connector_type { 4288 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4289 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4290 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4291 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4292 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4293 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4294 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4295 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4296 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4297 }; 4298 4299 /* reg_ptys_connector_type 4300 * Connector type indication. 4301 * Access: RO 4302 */ 4303 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4304 4305 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4306 u32 proto_admin, bool autoneg) 4307 { 4308 MLXSW_REG_ZERO(ptys, payload); 4309 mlxsw_reg_ptys_local_port_set(payload, local_port); 4310 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4311 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4312 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4313 } 4314 4315 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4316 u32 proto_admin, bool autoneg) 4317 { 4318 MLXSW_REG_ZERO(ptys, payload); 4319 mlxsw_reg_ptys_local_port_set(payload, local_port); 4320 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4321 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4322 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4323 } 4324 4325 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4326 u32 *p_eth_proto_cap, 4327 u32 *p_eth_proto_admin, 4328 u32 *p_eth_proto_oper) 4329 { 4330 if (p_eth_proto_cap) 4331 *p_eth_proto_cap = 4332 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4333 if (p_eth_proto_admin) 4334 *p_eth_proto_admin = 4335 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4336 if (p_eth_proto_oper) 4337 *p_eth_proto_oper = 4338 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4339 } 4340 4341 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4342 u32 *p_eth_proto_cap, 4343 u32 *p_eth_proto_admin, 4344 u32 *p_eth_proto_oper) 4345 { 4346 if (p_eth_proto_cap) 4347 *p_eth_proto_cap = 4348 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4349 if (p_eth_proto_admin) 4350 *p_eth_proto_admin = 4351 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4352 if (p_eth_proto_oper) 4353 *p_eth_proto_oper = 4354 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4355 } 4356 4357 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4358 u16 proto_admin, u16 link_width) 4359 { 4360 MLXSW_REG_ZERO(ptys, payload); 4361 mlxsw_reg_ptys_local_port_set(payload, local_port); 4362 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4363 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4364 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4365 } 4366 4367 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4368 u16 *p_ib_link_width_cap, 4369 u16 *p_ib_proto_oper, 4370 u16 *p_ib_link_width_oper) 4371 { 4372 if (p_ib_proto_cap) 4373 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4374 if (p_ib_link_width_cap) 4375 *p_ib_link_width_cap = 4376 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4377 if (p_ib_proto_oper) 4378 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4379 if (p_ib_link_width_oper) 4380 *p_ib_link_width_oper = 4381 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4382 } 4383 4384 /* PPAD - Port Physical Address Register 4385 * ------------------------------------- 4386 * The PPAD register configures the per port physical MAC address. 4387 */ 4388 #define MLXSW_REG_PPAD_ID 0x5005 4389 #define MLXSW_REG_PPAD_LEN 0x10 4390 4391 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4392 4393 /* reg_ppad_single_base_mac 4394 * 0: base_mac, local port should be 0 and mac[7:0] is 4395 * reserved. HW will set incremental 4396 * 1: single_mac - mac of the local_port 4397 * Access: RW 4398 */ 4399 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4400 4401 /* reg_ppad_local_port 4402 * port number, if single_base_mac = 0 then local_port is reserved 4403 * Access: RW 4404 */ 4405 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4406 4407 /* reg_ppad_mac 4408 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4409 * If single_base_mac = 1 - the per port MAC address 4410 * Access: RW 4411 */ 4412 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4413 4414 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4415 u8 local_port) 4416 { 4417 MLXSW_REG_ZERO(ppad, payload); 4418 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4419 mlxsw_reg_ppad_local_port_set(payload, local_port); 4420 } 4421 4422 /* PAOS - Ports Administrative and Operational Status Register 4423 * ----------------------------------------------------------- 4424 * Configures and retrieves per port administrative and operational status. 4425 */ 4426 #define MLXSW_REG_PAOS_ID 0x5006 4427 #define MLXSW_REG_PAOS_LEN 0x10 4428 4429 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4430 4431 /* reg_paos_swid 4432 * Switch partition ID with which to associate the port. 4433 * Note: while external ports uses unique local port numbers (and thus swid is 4434 * redundant), router ports use the same local port number where swid is the 4435 * only indication for the relevant port. 4436 * Access: Index 4437 */ 4438 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4439 4440 /* reg_paos_local_port 4441 * Local port number. 4442 * Access: Index 4443 */ 4444 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4445 4446 /* reg_paos_admin_status 4447 * Port administrative state (the desired state of the port): 4448 * 1 - Up. 4449 * 2 - Down. 4450 * 3 - Up once. This means that in case of link failure, the port won't go 4451 * into polling mode, but will wait to be re-enabled by software. 4452 * 4 - Disabled by system. Can only be set by hardware. 4453 * Access: RW 4454 */ 4455 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4456 4457 /* reg_paos_oper_status 4458 * Port operational state (the current state): 4459 * 1 - Up. 4460 * 2 - Down. 4461 * 3 - Down by port failure. This means that the device will not let the 4462 * port up again until explicitly specified by software. 4463 * Access: RO 4464 */ 4465 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4466 4467 /* reg_paos_ase 4468 * Admin state update enabled. 4469 * Access: WO 4470 */ 4471 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4472 4473 /* reg_paos_ee 4474 * Event update enable. If this bit is set, event generation will be 4475 * updated based on the e field. 4476 * Access: WO 4477 */ 4478 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4479 4480 /* reg_paos_e 4481 * Event generation on operational state change: 4482 * 0 - Do not generate event. 4483 * 1 - Generate Event. 4484 * 2 - Generate Single Event. 4485 * Access: RW 4486 */ 4487 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4488 4489 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4490 enum mlxsw_port_admin_status status) 4491 { 4492 MLXSW_REG_ZERO(paos, payload); 4493 mlxsw_reg_paos_swid_set(payload, 0); 4494 mlxsw_reg_paos_local_port_set(payload, local_port); 4495 mlxsw_reg_paos_admin_status_set(payload, status); 4496 mlxsw_reg_paos_oper_status_set(payload, 0); 4497 mlxsw_reg_paos_ase_set(payload, 1); 4498 mlxsw_reg_paos_ee_set(payload, 1); 4499 mlxsw_reg_paos_e_set(payload, 1); 4500 } 4501 4502 /* PFCC - Ports Flow Control Configuration Register 4503 * ------------------------------------------------ 4504 * Configures and retrieves the per port flow control configuration. 4505 */ 4506 #define MLXSW_REG_PFCC_ID 0x5007 4507 #define MLXSW_REG_PFCC_LEN 0x20 4508 4509 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4510 4511 /* reg_pfcc_local_port 4512 * Local port number. 4513 * Access: Index 4514 */ 4515 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4516 4517 /* reg_pfcc_pnat 4518 * Port number access type. Determines the way local_port is interpreted: 4519 * 0 - Local port number. 4520 * 1 - IB / label port number. 4521 * Access: Index 4522 */ 4523 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4524 4525 /* reg_pfcc_shl_cap 4526 * Send to higher layers capabilities: 4527 * 0 - No capability of sending Pause and PFC frames to higher layers. 4528 * 1 - Device has capability of sending Pause and PFC frames to higher 4529 * layers. 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4533 4534 /* reg_pfcc_shl_opr 4535 * Send to higher layers operation: 4536 * 0 - Pause and PFC frames are handled by the port (default). 4537 * 1 - Pause and PFC frames are handled by the port and also sent to 4538 * higher layers. Only valid if shl_cap = 1. 4539 * Access: RW 4540 */ 4541 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4542 4543 /* reg_pfcc_ppan 4544 * Pause policy auto negotiation. 4545 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4546 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4547 * based on the auto-negotiation resolution. 4548 * Access: RW 4549 * 4550 * Note: The auto-negotiation advertisement is set according to pptx and 4551 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4552 */ 4553 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4554 4555 /* reg_pfcc_prio_mask_tx 4556 * Bit per priority indicating if Tx flow control policy should be 4557 * updated based on bit pfctx. 4558 * Access: WO 4559 */ 4560 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4561 4562 /* reg_pfcc_prio_mask_rx 4563 * Bit per priority indicating if Rx flow control policy should be 4564 * updated based on bit pfcrx. 4565 * Access: WO 4566 */ 4567 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4568 4569 /* reg_pfcc_pptx 4570 * Admin Pause policy on Tx. 4571 * 0 - Never generate Pause frames (default). 4572 * 1 - Generate Pause frames according to Rx buffer threshold. 4573 * Access: RW 4574 */ 4575 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4576 4577 /* reg_pfcc_aptx 4578 * Active (operational) Pause policy on Tx. 4579 * 0 - Never generate Pause frames. 4580 * 1 - Generate Pause frames according to Rx buffer threshold. 4581 * Access: RO 4582 */ 4583 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4584 4585 /* reg_pfcc_pfctx 4586 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4587 * 0 - Never generate priority Pause frames on the specified priority 4588 * (default). 4589 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4590 * the specified priority. 4591 * Access: RW 4592 * 4593 * Note: pfctx and pptx must be mutually exclusive. 4594 */ 4595 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4596 4597 /* reg_pfcc_pprx 4598 * Admin Pause policy on Rx. 4599 * 0 - Ignore received Pause frames (default). 4600 * 1 - Respect received Pause frames. 4601 * Access: RW 4602 */ 4603 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4604 4605 /* reg_pfcc_aprx 4606 * Active (operational) Pause policy on Rx. 4607 * 0 - Ignore received Pause frames. 4608 * 1 - Respect received Pause frames. 4609 * Access: RO 4610 */ 4611 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4612 4613 /* reg_pfcc_pfcrx 4614 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4615 * 0 - Ignore incoming priority Pause frames on the specified priority 4616 * (default). 4617 * 1 - Respect incoming priority Pause frames on the specified priority. 4618 * Access: RW 4619 */ 4620 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4621 4622 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4623 4624 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4625 { 4626 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4627 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4628 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4629 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4630 } 4631 4632 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4633 { 4634 MLXSW_REG_ZERO(pfcc, payload); 4635 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4636 } 4637 4638 /* PPCNT - Ports Performance Counters Register 4639 * ------------------------------------------- 4640 * The PPCNT register retrieves per port performance counters. 4641 */ 4642 #define MLXSW_REG_PPCNT_ID 0x5008 4643 #define MLXSW_REG_PPCNT_LEN 0x100 4644 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4645 4646 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4647 4648 /* reg_ppcnt_swid 4649 * For HCA: must be always 0. 4650 * Switch partition ID to associate port with. 4651 * Switch partitions are numbered from 0 to 7 inclusively. 4652 * Switch partition 254 indicates stacking ports. 4653 * Switch partition 255 indicates all switch partitions. 4654 * Only valid on Set() operation with local_port=255. 4655 * Access: Index 4656 */ 4657 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4658 4659 /* reg_ppcnt_local_port 4660 * Local port number. 4661 * 255 indicates all ports on the device, and is only allowed 4662 * for Set() operation. 4663 * Access: Index 4664 */ 4665 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4666 4667 /* reg_ppcnt_pnat 4668 * Port number access type: 4669 * 0 - Local port number 4670 * 1 - IB port number 4671 * Access: Index 4672 */ 4673 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4674 4675 enum mlxsw_reg_ppcnt_grp { 4676 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4677 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4678 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4679 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4680 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4681 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4682 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4683 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4684 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4685 }; 4686 4687 /* reg_ppcnt_grp 4688 * Performance counter group. 4689 * Group 63 indicates all groups. Only valid on Set() operation with 4690 * clr bit set. 4691 * 0x0: IEEE 802.3 Counters 4692 * 0x1: RFC 2863 Counters 4693 * 0x2: RFC 2819 Counters 4694 * 0x3: RFC 3635 Counters 4695 * 0x5: Ethernet Extended Counters 4696 * 0x6: Ethernet Discard Counters 4697 * 0x8: Link Level Retransmission Counters 4698 * 0x10: Per Priority Counters 4699 * 0x11: Per Traffic Class Counters 4700 * 0x12: Physical Layer Counters 4701 * 0x13: Per Traffic Class Congestion Counters 4702 * Access: Index 4703 */ 4704 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4705 4706 /* reg_ppcnt_clr 4707 * Clear counters. Setting the clr bit will reset the counter value 4708 * for all counters in the counter group. This bit can be set 4709 * for both Set() and Get() operation. 4710 * Access: OP 4711 */ 4712 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4713 4714 /* reg_ppcnt_prio_tc 4715 * Priority for counter set that support per priority, valid values: 0-7. 4716 * Traffic class for counter set that support per traffic class, 4717 * valid values: 0- cap_max_tclass-1 . 4718 * For HCA: cap_max_tclass is always 8. 4719 * Otherwise must be 0. 4720 * Access: Index 4721 */ 4722 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4723 4724 /* Ethernet IEEE 802.3 Counter Group */ 4725 4726 /* reg_ppcnt_a_frames_transmitted_ok 4727 * Access: RO 4728 */ 4729 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4730 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4731 4732 /* reg_ppcnt_a_frames_received_ok 4733 * Access: RO 4734 */ 4735 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4736 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4737 4738 /* reg_ppcnt_a_frame_check_sequence_errors 4739 * Access: RO 4740 */ 4741 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4742 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4743 4744 /* reg_ppcnt_a_alignment_errors 4745 * Access: RO 4746 */ 4747 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4748 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4749 4750 /* reg_ppcnt_a_octets_transmitted_ok 4751 * Access: RO 4752 */ 4753 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4754 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4755 4756 /* reg_ppcnt_a_octets_received_ok 4757 * Access: RO 4758 */ 4759 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4760 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4761 4762 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4763 * Access: RO 4764 */ 4765 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4766 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4767 4768 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4769 * Access: RO 4770 */ 4771 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4772 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4773 4774 /* reg_ppcnt_a_multicast_frames_received_ok 4775 * Access: RO 4776 */ 4777 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4778 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4779 4780 /* reg_ppcnt_a_broadcast_frames_received_ok 4781 * Access: RO 4782 */ 4783 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4784 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4785 4786 /* reg_ppcnt_a_in_range_length_errors 4787 * Access: RO 4788 */ 4789 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4790 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4791 4792 /* reg_ppcnt_a_out_of_range_length_field 4793 * Access: RO 4794 */ 4795 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4796 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4797 4798 /* reg_ppcnt_a_frame_too_long_errors 4799 * Access: RO 4800 */ 4801 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4802 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4803 4804 /* reg_ppcnt_a_symbol_error_during_carrier 4805 * Access: RO 4806 */ 4807 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4808 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4809 4810 /* reg_ppcnt_a_mac_control_frames_transmitted 4811 * Access: RO 4812 */ 4813 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4814 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4815 4816 /* reg_ppcnt_a_mac_control_frames_received 4817 * Access: RO 4818 */ 4819 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4820 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4821 4822 /* reg_ppcnt_a_unsupported_opcodes_received 4823 * Access: RO 4824 */ 4825 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4826 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4827 4828 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4829 * Access: RO 4830 */ 4831 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4832 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4833 4834 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4835 * Access: RO 4836 */ 4837 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4838 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4839 4840 /* Ethernet RFC 2863 Counter Group */ 4841 4842 /* reg_ppcnt_if_in_discards 4843 * Access: RO 4844 */ 4845 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4846 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4847 4848 /* reg_ppcnt_if_out_discards 4849 * Access: RO 4850 */ 4851 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4852 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4853 4854 /* reg_ppcnt_if_out_errors 4855 * Access: RO 4856 */ 4857 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4858 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4859 4860 /* Ethernet RFC 2819 Counter Group */ 4861 4862 /* reg_ppcnt_ether_stats_undersize_pkts 4863 * Access: RO 4864 */ 4865 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4866 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4867 4868 /* reg_ppcnt_ether_stats_oversize_pkts 4869 * Access: RO 4870 */ 4871 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4872 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4873 4874 /* reg_ppcnt_ether_stats_fragments 4875 * Access: RO 4876 */ 4877 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4878 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4879 4880 /* reg_ppcnt_ether_stats_pkts64octets 4881 * Access: RO 4882 */ 4883 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4884 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4885 4886 /* reg_ppcnt_ether_stats_pkts65to127octets 4887 * Access: RO 4888 */ 4889 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4890 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4891 4892 /* reg_ppcnt_ether_stats_pkts128to255octets 4893 * Access: RO 4894 */ 4895 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4896 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4897 4898 /* reg_ppcnt_ether_stats_pkts256to511octets 4899 * Access: RO 4900 */ 4901 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4902 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4903 4904 /* reg_ppcnt_ether_stats_pkts512to1023octets 4905 * Access: RO 4906 */ 4907 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4908 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4909 4910 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4911 * Access: RO 4912 */ 4913 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4914 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4915 4916 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4917 * Access: RO 4918 */ 4919 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4920 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4921 4922 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4923 * Access: RO 4924 */ 4925 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4926 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4927 4928 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4929 * Access: RO 4930 */ 4931 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4932 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4933 4934 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4935 * Access: RO 4936 */ 4937 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4938 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4939 4940 /* Ethernet RFC 3635 Counter Group */ 4941 4942 /* reg_ppcnt_dot3stats_fcs_errors 4943 * Access: RO 4944 */ 4945 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4947 4948 /* reg_ppcnt_dot3stats_symbol_errors 4949 * Access: RO 4950 */ 4951 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4953 4954 /* reg_ppcnt_dot3control_in_unknown_opcodes 4955 * Access: RO 4956 */ 4957 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4958 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4959 4960 /* reg_ppcnt_dot3in_pause_frames 4961 * Access: RO 4962 */ 4963 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4964 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4965 4966 /* Ethernet Extended Counter Group Counters */ 4967 4968 /* reg_ppcnt_ecn_marked 4969 * Access: RO 4970 */ 4971 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4972 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4973 4974 /* Ethernet Discard Counter Group Counters */ 4975 4976 /* reg_ppcnt_ingress_general 4977 * Access: RO 4978 */ 4979 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4980 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4981 4982 /* reg_ppcnt_ingress_policy_engine 4983 * Access: RO 4984 */ 4985 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4986 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4987 4988 /* reg_ppcnt_ingress_vlan_membership 4989 * Access: RO 4990 */ 4991 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4992 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4993 4994 /* reg_ppcnt_ingress_tag_frame_type 4995 * Access: RO 4996 */ 4997 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4998 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4999 5000 /* reg_ppcnt_egress_vlan_membership 5001 * Access: RO 5002 */ 5003 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5004 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5005 5006 /* reg_ppcnt_loopback_filter 5007 * Access: RO 5008 */ 5009 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5010 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5011 5012 /* reg_ppcnt_egress_general 5013 * Access: RO 5014 */ 5015 MLXSW_ITEM64(reg, ppcnt, egress_general, 5016 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5017 5018 /* reg_ppcnt_egress_hoq 5019 * Access: RO 5020 */ 5021 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5022 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5023 5024 /* reg_ppcnt_egress_policy_engine 5025 * Access: RO 5026 */ 5027 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5028 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5029 5030 /* reg_ppcnt_ingress_tx_link_down 5031 * Access: RO 5032 */ 5033 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5034 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5035 5036 /* reg_ppcnt_egress_stp_filter 5037 * Access: RO 5038 */ 5039 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5040 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5041 5042 /* reg_ppcnt_egress_sll 5043 * Access: RO 5044 */ 5045 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5046 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5047 5048 /* Ethernet Per Priority Group Counters */ 5049 5050 /* reg_ppcnt_rx_octets 5051 * Access: RO 5052 */ 5053 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5054 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5055 5056 /* reg_ppcnt_rx_frames 5057 * Access: RO 5058 */ 5059 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5061 5062 /* reg_ppcnt_tx_octets 5063 * Access: RO 5064 */ 5065 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5067 5068 /* reg_ppcnt_tx_frames 5069 * Access: RO 5070 */ 5071 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5073 5074 /* reg_ppcnt_rx_pause 5075 * Access: RO 5076 */ 5077 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5079 5080 /* reg_ppcnt_rx_pause_duration 5081 * Access: RO 5082 */ 5083 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5085 5086 /* reg_ppcnt_tx_pause 5087 * Access: RO 5088 */ 5089 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5090 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5091 5092 /* reg_ppcnt_tx_pause_duration 5093 * Access: RO 5094 */ 5095 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5097 5098 /* reg_ppcnt_rx_pause_transition 5099 * Access: RO 5100 */ 5101 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5102 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5103 5104 /* Ethernet Per Traffic Group Counters */ 5105 5106 /* reg_ppcnt_tc_transmit_queue 5107 * Contains the transmit queue depth in cells of traffic class 5108 * selected by prio_tc and the port selected by local_port. 5109 * The field cannot be cleared. 5110 * Access: RO 5111 */ 5112 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5113 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5114 5115 /* reg_ppcnt_tc_no_buffer_discard_uc 5116 * The number of unicast packets dropped due to lack of shared 5117 * buffer resources. 5118 * Access: RO 5119 */ 5120 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5121 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5122 5123 /* Ethernet Per Traffic Class Congestion Group Counters */ 5124 5125 /* reg_ppcnt_wred_discard 5126 * Access: RO 5127 */ 5128 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5129 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5130 5131 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5132 enum mlxsw_reg_ppcnt_grp grp, 5133 u8 prio_tc) 5134 { 5135 MLXSW_REG_ZERO(ppcnt, payload); 5136 mlxsw_reg_ppcnt_swid_set(payload, 0); 5137 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5138 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5139 mlxsw_reg_ppcnt_grp_set(payload, grp); 5140 mlxsw_reg_ppcnt_clr_set(payload, 0); 5141 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5142 } 5143 5144 /* PLIB - Port Local to InfiniBand Port 5145 * ------------------------------------ 5146 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5147 */ 5148 #define MLXSW_REG_PLIB_ID 0x500A 5149 #define MLXSW_REG_PLIB_LEN 0x10 5150 5151 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5152 5153 /* reg_plib_local_port 5154 * Local port number. 5155 * Access: Index 5156 */ 5157 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5158 5159 /* reg_plib_ib_port 5160 * InfiniBand port remapping for local_port. 5161 * Access: RW 5162 */ 5163 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5164 5165 /* PPTB - Port Prio To Buffer Register 5166 * ----------------------------------- 5167 * Configures the switch priority to buffer table. 5168 */ 5169 #define MLXSW_REG_PPTB_ID 0x500B 5170 #define MLXSW_REG_PPTB_LEN 0x10 5171 5172 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5173 5174 enum { 5175 MLXSW_REG_PPTB_MM_UM, 5176 MLXSW_REG_PPTB_MM_UNICAST, 5177 MLXSW_REG_PPTB_MM_MULTICAST, 5178 }; 5179 5180 /* reg_pptb_mm 5181 * Mapping mode. 5182 * 0 - Map both unicast and multicast packets to the same buffer. 5183 * 1 - Map only unicast packets. 5184 * 2 - Map only multicast packets. 5185 * Access: Index 5186 * 5187 * Note: SwitchX-2 only supports the first option. 5188 */ 5189 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5190 5191 /* reg_pptb_local_port 5192 * Local port number. 5193 * Access: Index 5194 */ 5195 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5196 5197 /* reg_pptb_um 5198 * Enables the update of the untagged_buf field. 5199 * Access: RW 5200 */ 5201 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5202 5203 /* reg_pptb_pm 5204 * Enables the update of the prio_to_buff field. 5205 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5206 * Access: RW 5207 */ 5208 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5209 5210 /* reg_pptb_prio_to_buff 5211 * Mapping of switch priority <i> to one of the allocated receive port 5212 * buffers. 5213 * Access: RW 5214 */ 5215 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5216 5217 /* reg_pptb_pm_msb 5218 * Enables the update of the prio_to_buff field. 5219 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5220 * Access: RW 5221 */ 5222 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5223 5224 /* reg_pptb_untagged_buff 5225 * Mapping of untagged frames to one of the allocated receive port buffers. 5226 * Access: RW 5227 * 5228 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5229 * Spectrum, as it maps untagged packets based on the default switch priority. 5230 */ 5231 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5232 5233 /* reg_pptb_prio_to_buff_msb 5234 * Mapping of switch priority <i+8> to one of the allocated receive port 5235 * buffers. 5236 * Access: RW 5237 */ 5238 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5239 5240 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5241 5242 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5243 { 5244 MLXSW_REG_ZERO(pptb, payload); 5245 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5246 mlxsw_reg_pptb_local_port_set(payload, local_port); 5247 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5248 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5249 } 5250 5251 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5252 u8 buff) 5253 { 5254 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5255 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5256 } 5257 5258 /* PBMC - Port Buffer Management Control Register 5259 * ---------------------------------------------- 5260 * The PBMC register configures and retrieves the port packet buffer 5261 * allocation for different Prios, and the Pause threshold management. 5262 */ 5263 #define MLXSW_REG_PBMC_ID 0x500C 5264 #define MLXSW_REG_PBMC_LEN 0x6C 5265 5266 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5267 5268 /* reg_pbmc_local_port 5269 * Local port number. 5270 * Access: Index 5271 */ 5272 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5273 5274 /* reg_pbmc_xoff_timer_value 5275 * When device generates a pause frame, it uses this value as the pause 5276 * timer (time for the peer port to pause in quota-512 bit time). 5277 * Access: RW 5278 */ 5279 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5280 5281 /* reg_pbmc_xoff_refresh 5282 * The time before a new pause frame should be sent to refresh the pause RW 5283 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5284 * time). 5285 * Access: RW 5286 */ 5287 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5288 5289 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5290 5291 /* reg_pbmc_buf_lossy 5292 * The field indicates if the buffer is lossy. 5293 * 0 - Lossless 5294 * 1 - Lossy 5295 * Access: RW 5296 */ 5297 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5298 5299 /* reg_pbmc_buf_epsb 5300 * Eligible for Port Shared buffer. 5301 * If epsb is set, packets assigned to buffer are allowed to insert the port 5302 * shared buffer. 5303 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5304 * Access: RW 5305 */ 5306 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5307 5308 /* reg_pbmc_buf_size 5309 * The part of the packet buffer array is allocated for the specific buffer. 5310 * Units are represented in cells. 5311 * Access: RW 5312 */ 5313 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5314 5315 /* reg_pbmc_buf_xoff_threshold 5316 * Once the amount of data in the buffer goes above this value, device 5317 * starts sending PFC frames for all priorities associated with the 5318 * buffer. Units are represented in cells. Reserved in case of lossy 5319 * buffer. 5320 * Access: RW 5321 * 5322 * Note: In Spectrum, reserved for buffer[9]. 5323 */ 5324 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5325 0x08, 0x04, false); 5326 5327 /* reg_pbmc_buf_xon_threshold 5328 * When the amount of data in the buffer goes below this value, device 5329 * stops sending PFC frames for the priorities associated with the 5330 * buffer. Units are represented in cells. Reserved in case of lossy 5331 * buffer. 5332 * Access: RW 5333 * 5334 * Note: In Spectrum, reserved for buffer[9]. 5335 */ 5336 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5337 0x08, 0x04, false); 5338 5339 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5340 u16 xoff_timer_value, u16 xoff_refresh) 5341 { 5342 MLXSW_REG_ZERO(pbmc, payload); 5343 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5344 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5345 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5346 } 5347 5348 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5349 int buf_index, 5350 u16 size) 5351 { 5352 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5353 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5354 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5355 } 5356 5357 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5358 int buf_index, u16 size, 5359 u16 threshold) 5360 { 5361 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5362 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5363 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5364 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5365 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5366 } 5367 5368 /* PSPA - Port Switch Partition Allocation 5369 * --------------------------------------- 5370 * Controls the association of a port with a switch partition and enables 5371 * configuring ports as stacking ports. 5372 */ 5373 #define MLXSW_REG_PSPA_ID 0x500D 5374 #define MLXSW_REG_PSPA_LEN 0x8 5375 5376 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5377 5378 /* reg_pspa_swid 5379 * Switch partition ID. 5380 * Access: RW 5381 */ 5382 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5383 5384 /* reg_pspa_local_port 5385 * Local port number. 5386 * Access: Index 5387 */ 5388 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5389 5390 /* reg_pspa_sub_port 5391 * Virtual port within the local port. Set to 0 when virtual ports are 5392 * disabled on the local port. 5393 * Access: Index 5394 */ 5395 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5396 5397 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5398 { 5399 MLXSW_REG_ZERO(pspa, payload); 5400 mlxsw_reg_pspa_swid_set(payload, swid); 5401 mlxsw_reg_pspa_local_port_set(payload, local_port); 5402 mlxsw_reg_pspa_sub_port_set(payload, 0); 5403 } 5404 5405 /* PPLR - Port Physical Loopback Register 5406 * -------------------------------------- 5407 * This register allows configuration of the port's loopback mode. 5408 */ 5409 #define MLXSW_REG_PPLR_ID 0x5018 5410 #define MLXSW_REG_PPLR_LEN 0x8 5411 5412 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5413 5414 /* reg_pplr_local_port 5415 * Local port number. 5416 * Access: Index 5417 */ 5418 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5419 5420 /* Phy local loopback. When set the port's egress traffic is looped back 5421 * to the receiver and the port transmitter is disabled. 5422 */ 5423 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5424 5425 /* reg_pplr_lb_en 5426 * Loopback enable. 5427 * Access: RW 5428 */ 5429 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5430 5431 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5432 bool phy_local) 5433 { 5434 MLXSW_REG_ZERO(pplr, payload); 5435 mlxsw_reg_pplr_local_port_set(payload, local_port); 5436 mlxsw_reg_pplr_lb_en_set(payload, 5437 phy_local ? 5438 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5439 } 5440 5441 /* PMTM - Port Module Type Mapping Register 5442 * ---------------------------------------- 5443 * The PMTM allows query or configuration of module types. 5444 */ 5445 #define MLXSW_REG_PMTM_ID 0x5067 5446 #define MLXSW_REG_PMTM_LEN 0x10 5447 5448 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5449 5450 /* reg_pmtm_module 5451 * Module number. 5452 * Access: Index 5453 */ 5454 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5455 5456 enum mlxsw_reg_pmtm_module_type { 5457 /* Backplane with 4 lanes */ 5458 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5459 /* QSFP */ 5460 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5461 /* SFP */ 5462 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5463 /* Backplane with single lane */ 5464 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5465 /* Backplane with two lane */ 5466 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5467 /* Chip2Chip4x */ 5468 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5469 /* Chip2Chip2x */ 5470 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5471 /* Chip2Chip1x */ 5472 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5473 /* QSFP-DD */ 5474 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5475 /* OSFP */ 5476 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5477 /* SFP-DD */ 5478 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5479 /* DSFP */ 5480 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5481 /* Chip2Chip8x */ 5482 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5483 }; 5484 5485 /* reg_pmtm_module_type 5486 * Module type. 5487 * Access: RW 5488 */ 5489 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5490 5491 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5492 { 5493 MLXSW_REG_ZERO(pmtm, payload); 5494 mlxsw_reg_pmtm_module_set(payload, module); 5495 } 5496 5497 static inline void 5498 mlxsw_reg_pmtm_unpack(char *payload, 5499 enum mlxsw_reg_pmtm_module_type *module_type) 5500 { 5501 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5502 } 5503 5504 /* HTGT - Host Trap Group Table 5505 * ---------------------------- 5506 * Configures the properties for forwarding to CPU. 5507 */ 5508 #define MLXSW_REG_HTGT_ID 0x7002 5509 #define MLXSW_REG_HTGT_LEN 0x20 5510 5511 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5512 5513 /* reg_htgt_swid 5514 * Switch partition ID. 5515 * Access: Index 5516 */ 5517 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5518 5519 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5520 5521 /* reg_htgt_type 5522 * CPU path type. 5523 * Access: RW 5524 */ 5525 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5526 5527 enum mlxsw_reg_htgt_trap_group { 5528 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5529 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5530 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5531 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5532 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5533 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5534 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5535 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5536 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5537 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5538 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5539 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5540 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5541 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5542 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5543 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5544 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5545 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5546 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5547 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5548 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5549 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5550 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5551 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5552 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5553 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5554 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5555 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5556 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5557 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5558 5559 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5560 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5561 }; 5562 5563 /* reg_htgt_trap_group 5564 * Trap group number. User defined number specifying which trap groups 5565 * should be forwarded to the CPU. The mapping between trap IDs and trap 5566 * groups is configured using HPKT register. 5567 * Access: Index 5568 */ 5569 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5570 5571 enum { 5572 MLXSW_REG_HTGT_POLICER_DISABLE, 5573 MLXSW_REG_HTGT_POLICER_ENABLE, 5574 }; 5575 5576 /* reg_htgt_pide 5577 * Enable policer ID specified using 'pid' field. 5578 * Access: RW 5579 */ 5580 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5581 5582 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5583 5584 /* reg_htgt_pid 5585 * Policer ID for the trap group. 5586 * Access: RW 5587 */ 5588 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5589 5590 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5591 5592 /* reg_htgt_mirror_action 5593 * Mirror action to use. 5594 * 0 - Trap to CPU. 5595 * 1 - Trap to CPU and mirror to a mirroring agent. 5596 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5597 * Access: RW 5598 * 5599 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5600 */ 5601 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5602 5603 /* reg_htgt_mirroring_agent 5604 * Mirroring agent. 5605 * Access: RW 5606 */ 5607 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5608 5609 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5610 5611 /* reg_htgt_priority 5612 * Trap group priority. 5613 * In case a packet matches multiple classification rules, the packet will 5614 * only be trapped once, based on the trap ID associated with the group (via 5615 * register HPKT) with the highest priority. 5616 * Supported values are 0-7, with 7 represnting the highest priority. 5617 * Access: RW 5618 * 5619 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5620 * by the 'trap_group' field. 5621 */ 5622 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5623 5624 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5625 5626 /* reg_htgt_local_path_cpu_tclass 5627 * CPU ingress traffic class for the trap group. 5628 * Access: RW 5629 */ 5630 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5631 5632 enum mlxsw_reg_htgt_local_path_rdq { 5633 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5634 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5635 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5636 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5637 }; 5638 /* reg_htgt_local_path_rdq 5639 * Receive descriptor queue (RDQ) to use for the trap group. 5640 * Access: RW 5641 */ 5642 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5643 5644 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5645 u8 priority, u8 tc) 5646 { 5647 MLXSW_REG_ZERO(htgt, payload); 5648 5649 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5650 mlxsw_reg_htgt_pide_set(payload, 5651 MLXSW_REG_HTGT_POLICER_DISABLE); 5652 } else { 5653 mlxsw_reg_htgt_pide_set(payload, 5654 MLXSW_REG_HTGT_POLICER_ENABLE); 5655 mlxsw_reg_htgt_pid_set(payload, policer_id); 5656 } 5657 5658 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5659 mlxsw_reg_htgt_trap_group_set(payload, group); 5660 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5661 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5662 mlxsw_reg_htgt_priority_set(payload, priority); 5663 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5664 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5665 } 5666 5667 /* HPKT - Host Packet Trap 5668 * ----------------------- 5669 * Configures trap IDs inside trap groups. 5670 */ 5671 #define MLXSW_REG_HPKT_ID 0x7003 5672 #define MLXSW_REG_HPKT_LEN 0x10 5673 5674 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5675 5676 enum { 5677 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5678 MLXSW_REG_HPKT_ACK_REQUIRED, 5679 }; 5680 5681 /* reg_hpkt_ack 5682 * Require acknowledgements from the host for events. 5683 * If set, then the device will wait for the event it sent to be acknowledged 5684 * by the host. This option is only relevant for event trap IDs. 5685 * Access: RW 5686 * 5687 * Note: Currently not supported by firmware. 5688 */ 5689 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5690 5691 enum mlxsw_reg_hpkt_action { 5692 MLXSW_REG_HPKT_ACTION_FORWARD, 5693 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5694 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5695 MLXSW_REG_HPKT_ACTION_DISCARD, 5696 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5697 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5698 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5699 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5700 }; 5701 5702 /* reg_hpkt_action 5703 * Action to perform on packet when trapped. 5704 * 0 - No action. Forward to CPU based on switching rules. 5705 * 1 - Trap to CPU (CPU receives sole copy). 5706 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5707 * 3 - Discard. 5708 * 4 - Soft discard (allow other traps to act on the packet). 5709 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5710 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5711 * 15 - Restore the firmware's default action. 5712 * Access: RW 5713 * 5714 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5715 * addressed to the CPU. 5716 */ 5717 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5718 5719 /* reg_hpkt_trap_group 5720 * Trap group to associate the trap with. 5721 * Access: RW 5722 */ 5723 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5724 5725 /* reg_hpkt_trap_id 5726 * Trap ID. 5727 * Access: Index 5728 * 5729 * Note: A trap ID can only be associated with a single trap group. The device 5730 * will associate the trap ID with the last trap group configured. 5731 */ 5732 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5733 5734 enum { 5735 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5736 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5737 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5738 }; 5739 5740 /* reg_hpkt_ctrl 5741 * Configure dedicated buffer resources for control packets. 5742 * Ignored by SwitchX-2. 5743 * 0 - Keep factory defaults. 5744 * 1 - Do not use control buffer for this trap ID. 5745 * 2 - Use control buffer for this trap ID. 5746 * Access: RW 5747 */ 5748 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5749 5750 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5751 enum mlxsw_reg_htgt_trap_group trap_group, 5752 bool is_ctrl) 5753 { 5754 MLXSW_REG_ZERO(hpkt, payload); 5755 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5756 mlxsw_reg_hpkt_action_set(payload, action); 5757 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5758 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5759 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5760 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5761 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5762 } 5763 5764 /* RGCR - Router General Configuration Register 5765 * -------------------------------------------- 5766 * The register is used for setting up the router configuration. 5767 */ 5768 #define MLXSW_REG_RGCR_ID 0x8001 5769 #define MLXSW_REG_RGCR_LEN 0x28 5770 5771 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5772 5773 /* reg_rgcr_ipv4_en 5774 * IPv4 router enable. 5775 * Access: RW 5776 */ 5777 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5778 5779 /* reg_rgcr_ipv6_en 5780 * IPv6 router enable. 5781 * Access: RW 5782 */ 5783 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5784 5785 /* reg_rgcr_max_router_interfaces 5786 * Defines the maximum number of active router interfaces for all virtual 5787 * routers. 5788 * Access: RW 5789 */ 5790 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5791 5792 /* reg_rgcr_usp 5793 * Update switch priority and packet color. 5794 * 0 - Preserve the value of Switch Priority and packet color. 5795 * 1 - Recalculate the value of Switch Priority and packet color. 5796 * Access: RW 5797 * 5798 * Note: Not supported by SwitchX and SwitchX-2. 5799 */ 5800 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5801 5802 /* reg_rgcr_pcp_rw 5803 * Indicates how to handle the pcp_rewrite_en value: 5804 * 0 - Preserve the value of pcp_rewrite_en. 5805 * 2 - Disable PCP rewrite. 5806 * 3 - Enable PCP rewrite. 5807 * Access: RW 5808 * 5809 * Note: Not supported by SwitchX and SwitchX-2. 5810 */ 5811 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5812 5813 /* reg_rgcr_activity_dis 5814 * Activity disable: 5815 * 0 - Activity will be set when an entry is hit (default). 5816 * 1 - Activity will not be set when an entry is hit. 5817 * 5818 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5819 * (RALUE). 5820 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5821 * Entry (RAUHT). 5822 * Bits 2:7 are reserved. 5823 * Access: RW 5824 * 5825 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5826 */ 5827 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5828 5829 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5830 bool ipv6_en) 5831 { 5832 MLXSW_REG_ZERO(rgcr, payload); 5833 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5834 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5835 } 5836 5837 /* RITR - Router Interface Table Register 5838 * -------------------------------------- 5839 * The register is used to configure the router interface table. 5840 */ 5841 #define MLXSW_REG_RITR_ID 0x8002 5842 #define MLXSW_REG_RITR_LEN 0x40 5843 5844 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5845 5846 /* reg_ritr_enable 5847 * Enables routing on the router interface. 5848 * Access: RW 5849 */ 5850 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5851 5852 /* reg_ritr_ipv4 5853 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5854 * interface. 5855 * Access: RW 5856 */ 5857 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5858 5859 /* reg_ritr_ipv6 5860 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5861 * interface. 5862 * Access: RW 5863 */ 5864 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5865 5866 /* reg_ritr_ipv4_mc 5867 * IPv4 multicast routing enable. 5868 * Access: RW 5869 */ 5870 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5871 5872 /* reg_ritr_ipv6_mc 5873 * IPv6 multicast routing enable. 5874 * Access: RW 5875 */ 5876 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5877 5878 enum mlxsw_reg_ritr_if_type { 5879 /* VLAN interface. */ 5880 MLXSW_REG_RITR_VLAN_IF, 5881 /* FID interface. */ 5882 MLXSW_REG_RITR_FID_IF, 5883 /* Sub-port interface. */ 5884 MLXSW_REG_RITR_SP_IF, 5885 /* Loopback Interface. */ 5886 MLXSW_REG_RITR_LOOPBACK_IF, 5887 }; 5888 5889 /* reg_ritr_type 5890 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5891 * Access: RW 5892 */ 5893 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5894 5895 enum { 5896 MLXSW_REG_RITR_RIF_CREATE, 5897 MLXSW_REG_RITR_RIF_DEL, 5898 }; 5899 5900 /* reg_ritr_op 5901 * Opcode: 5902 * 0 - Create or edit RIF. 5903 * 1 - Delete RIF. 5904 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5905 * is not supported. An interface must be deleted and re-created in order 5906 * to update properties. 5907 * Access: WO 5908 */ 5909 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5910 5911 /* reg_ritr_rif 5912 * Router interface index. A pointer to the Router Interface Table. 5913 * Access: Index 5914 */ 5915 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5916 5917 /* reg_ritr_ipv4_fe 5918 * IPv4 Forwarding Enable. 5919 * Enables routing of IPv4 traffic on the router interface. When disabled, 5920 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5921 * Not supported in SwitchX-2. 5922 * Access: RW 5923 */ 5924 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5925 5926 /* reg_ritr_ipv6_fe 5927 * IPv6 Forwarding Enable. 5928 * Enables routing of IPv6 traffic on the router interface. When disabled, 5929 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5930 * Not supported in SwitchX-2. 5931 * Access: RW 5932 */ 5933 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5934 5935 /* reg_ritr_ipv4_mc_fe 5936 * IPv4 Multicast Forwarding Enable. 5937 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5938 * will be enabled. 5939 * Access: RW 5940 */ 5941 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5942 5943 /* reg_ritr_ipv6_mc_fe 5944 * IPv6 Multicast Forwarding Enable. 5945 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5946 * will be enabled. 5947 * Access: RW 5948 */ 5949 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5950 5951 /* reg_ritr_lb_en 5952 * Loop-back filter enable for unicast packets. 5953 * If the flag is set then loop-back filter for unicast packets is 5954 * implemented on the RIF. Multicast packets are always subject to 5955 * loop-back filtering. 5956 * Access: RW 5957 */ 5958 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5959 5960 /* reg_ritr_virtual_router 5961 * Virtual router ID associated with the router interface. 5962 * Access: RW 5963 */ 5964 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5965 5966 /* reg_ritr_mtu 5967 * Router interface MTU. 5968 * Access: RW 5969 */ 5970 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5971 5972 /* reg_ritr_if_swid 5973 * Switch partition ID. 5974 * Access: RW 5975 */ 5976 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5977 5978 /* reg_ritr_if_mac 5979 * Router interface MAC address. 5980 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5981 * Access: RW 5982 */ 5983 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5984 5985 /* reg_ritr_if_vrrp_id_ipv6 5986 * VRRP ID for IPv6 5987 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5988 * Access: RW 5989 */ 5990 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5991 5992 /* reg_ritr_if_vrrp_id_ipv4 5993 * VRRP ID for IPv4 5994 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5995 * Access: RW 5996 */ 5997 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5998 5999 /* VLAN Interface */ 6000 6001 /* reg_ritr_vlan_if_vid 6002 * VLAN ID. 6003 * Access: RW 6004 */ 6005 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6006 6007 /* FID Interface */ 6008 6009 /* reg_ritr_fid_if_fid 6010 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6011 * the vFID range are supported. 6012 * Access: RW 6013 */ 6014 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6015 6016 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6017 enum mlxsw_reg_ritr_if_type rif_type, 6018 u16 fid) 6019 { 6020 if (rif_type == MLXSW_REG_RITR_FID_IF) 6021 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6022 else 6023 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6024 } 6025 6026 /* Sub-port Interface */ 6027 6028 /* reg_ritr_sp_if_lag 6029 * LAG indication. When this bit is set the system_port field holds the 6030 * LAG identifier. 6031 * Access: RW 6032 */ 6033 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6034 6035 /* reg_ritr_sp_system_port 6036 * Port unique indentifier. When lag bit is set, this field holds the 6037 * lag_id in bits 0:9. 6038 * Access: RW 6039 */ 6040 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6041 6042 /* reg_ritr_sp_if_vid 6043 * VLAN ID. 6044 * Access: RW 6045 */ 6046 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6047 6048 /* Loopback Interface */ 6049 6050 enum mlxsw_reg_ritr_loopback_protocol { 6051 /* IPinIP IPv4 underlay Unicast */ 6052 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6053 /* IPinIP IPv6 underlay Unicast */ 6054 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6055 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6056 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6057 }; 6058 6059 /* reg_ritr_loopback_protocol 6060 * Access: RW 6061 */ 6062 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6063 6064 enum mlxsw_reg_ritr_loopback_ipip_type { 6065 /* Tunnel is IPinIP. */ 6066 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6067 /* Tunnel is GRE, no key. */ 6068 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6069 /* Tunnel is GRE, with a key. */ 6070 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6071 }; 6072 6073 /* reg_ritr_loopback_ipip_type 6074 * Encapsulation type. 6075 * Access: RW 6076 */ 6077 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6078 6079 enum mlxsw_reg_ritr_loopback_ipip_options { 6080 /* The key is defined by gre_key. */ 6081 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6082 }; 6083 6084 /* reg_ritr_loopback_ipip_options 6085 * Access: RW 6086 */ 6087 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6088 6089 /* reg_ritr_loopback_ipip_uvr 6090 * Underlay Virtual Router ID. 6091 * Range is 0..cap_max_virtual_routers-1. 6092 * Reserved for Spectrum-2. 6093 * Access: RW 6094 */ 6095 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6096 6097 /* reg_ritr_loopback_ipip_underlay_rif 6098 * Underlay ingress router interface. 6099 * Reserved for Spectrum. 6100 * Access: RW 6101 */ 6102 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6103 6104 /* reg_ritr_loopback_ipip_usip* 6105 * Encapsulation Underlay source IP. 6106 * Access: RW 6107 */ 6108 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6109 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6110 6111 /* reg_ritr_loopback_ipip_gre_key 6112 * GRE Key. 6113 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6114 * Access: RW 6115 */ 6116 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6117 6118 /* Shared between ingress/egress */ 6119 enum mlxsw_reg_ritr_counter_set_type { 6120 /* No Count. */ 6121 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6122 /* Basic. Used for router interfaces, counting the following: 6123 * - Error and Discard counters. 6124 * - Unicast, Multicast and Broadcast counters. Sharing the 6125 * same set of counters for the different type of traffic 6126 * (IPv4, IPv6 and mpls). 6127 */ 6128 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6129 }; 6130 6131 /* reg_ritr_ingress_counter_index 6132 * Counter Index for flow counter. 6133 * Access: RW 6134 */ 6135 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6136 6137 /* reg_ritr_ingress_counter_set_type 6138 * Igress Counter Set Type for router interface counter. 6139 * Access: RW 6140 */ 6141 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6142 6143 /* reg_ritr_egress_counter_index 6144 * Counter Index for flow counter. 6145 * Access: RW 6146 */ 6147 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6148 6149 /* reg_ritr_egress_counter_set_type 6150 * Egress Counter Set Type for router interface counter. 6151 * Access: RW 6152 */ 6153 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6154 6155 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6156 bool enable, bool egress) 6157 { 6158 enum mlxsw_reg_ritr_counter_set_type set_type; 6159 6160 if (enable) 6161 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6162 else 6163 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6164 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6165 6166 if (egress) 6167 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6168 else 6169 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6170 } 6171 6172 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6173 { 6174 MLXSW_REG_ZERO(ritr, payload); 6175 mlxsw_reg_ritr_rif_set(payload, rif); 6176 } 6177 6178 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6179 u16 system_port, u16 vid) 6180 { 6181 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6182 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6183 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6184 } 6185 6186 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6187 enum mlxsw_reg_ritr_if_type type, 6188 u16 rif, u16 vr_id, u16 mtu) 6189 { 6190 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6191 6192 MLXSW_REG_ZERO(ritr, payload); 6193 mlxsw_reg_ritr_enable_set(payload, enable); 6194 mlxsw_reg_ritr_ipv4_set(payload, 1); 6195 mlxsw_reg_ritr_ipv6_set(payload, 1); 6196 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6197 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6198 mlxsw_reg_ritr_type_set(payload, type); 6199 mlxsw_reg_ritr_op_set(payload, op); 6200 mlxsw_reg_ritr_rif_set(payload, rif); 6201 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6202 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6203 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6204 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6205 mlxsw_reg_ritr_lb_en_set(payload, 1); 6206 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6207 mlxsw_reg_ritr_mtu_set(payload, mtu); 6208 } 6209 6210 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6211 { 6212 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6213 } 6214 6215 static inline void 6216 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6217 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6218 enum mlxsw_reg_ritr_loopback_ipip_options options, 6219 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6220 { 6221 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6222 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6223 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6224 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6225 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6226 } 6227 6228 static inline void 6229 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6230 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6231 enum mlxsw_reg_ritr_loopback_ipip_options options, 6232 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6233 { 6234 mlxsw_reg_ritr_loopback_protocol_set(payload, 6235 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6236 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6237 uvr_id, underlay_rif, gre_key); 6238 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6239 } 6240 6241 /* RTAR - Router TCAM Allocation Register 6242 * -------------------------------------- 6243 * This register is used for allocation of regions in the TCAM table. 6244 */ 6245 #define MLXSW_REG_RTAR_ID 0x8004 6246 #define MLXSW_REG_RTAR_LEN 0x20 6247 6248 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6249 6250 enum mlxsw_reg_rtar_op { 6251 MLXSW_REG_RTAR_OP_ALLOCATE, 6252 MLXSW_REG_RTAR_OP_RESIZE, 6253 MLXSW_REG_RTAR_OP_DEALLOCATE, 6254 }; 6255 6256 /* reg_rtar_op 6257 * Access: WO 6258 */ 6259 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6260 6261 enum mlxsw_reg_rtar_key_type { 6262 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6263 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6264 }; 6265 6266 /* reg_rtar_key_type 6267 * TCAM key type for the region. 6268 * Access: WO 6269 */ 6270 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6271 6272 /* reg_rtar_region_size 6273 * TCAM region size. When allocating/resizing this is the requested 6274 * size, the response is the actual size. 6275 * Note: Actual size may be larger than requested. 6276 * Reserved for op = Deallocate 6277 * Access: WO 6278 */ 6279 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6280 6281 static inline void mlxsw_reg_rtar_pack(char *payload, 6282 enum mlxsw_reg_rtar_op op, 6283 enum mlxsw_reg_rtar_key_type key_type, 6284 u16 region_size) 6285 { 6286 MLXSW_REG_ZERO(rtar, payload); 6287 mlxsw_reg_rtar_op_set(payload, op); 6288 mlxsw_reg_rtar_key_type_set(payload, key_type); 6289 mlxsw_reg_rtar_region_size_set(payload, region_size); 6290 } 6291 6292 /* RATR - Router Adjacency Table Register 6293 * -------------------------------------- 6294 * The RATR register is used to configure the Router Adjacency (next-hop) 6295 * Table. 6296 */ 6297 #define MLXSW_REG_RATR_ID 0x8008 6298 #define MLXSW_REG_RATR_LEN 0x2C 6299 6300 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6301 6302 enum mlxsw_reg_ratr_op { 6303 /* Read */ 6304 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6305 /* Read and clear activity */ 6306 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6307 /* Write Adjacency entry */ 6308 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6309 /* Write Adjacency entry only if the activity is cleared. 6310 * The write may not succeed if the activity is set. There is not 6311 * direct feedback if the write has succeeded or not, however 6312 * the get will reveal the actual entry (SW can compare the get 6313 * response to the set command). 6314 */ 6315 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6316 }; 6317 6318 /* reg_ratr_op 6319 * Note that Write operation may also be used for updating 6320 * counter_set_type and counter_index. In this case all other 6321 * fields must not be updated. 6322 * Access: OP 6323 */ 6324 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6325 6326 /* reg_ratr_v 6327 * Valid bit. Indicates if the adjacency entry is valid. 6328 * Note: the device may need some time before reusing an invalidated 6329 * entry. During this time the entry can not be reused. It is 6330 * recommended to use another entry before reusing an invalidated 6331 * entry (e.g. software can put it at the end of the list for 6332 * reusing). Trying to access an invalidated entry not yet cleared 6333 * by the device results with failure indicating "Try Again" status. 6334 * When valid is '0' then egress_router_interface,trap_action, 6335 * adjacency_parameters and counters are reserved 6336 * Access: RW 6337 */ 6338 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6339 6340 /* reg_ratr_a 6341 * Activity. Set for new entries. Set if a packet lookup has hit on 6342 * the specific entry. To clear the a bit, use "clear activity". 6343 * Access: RO 6344 */ 6345 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6346 6347 enum mlxsw_reg_ratr_type { 6348 /* Ethernet */ 6349 MLXSW_REG_RATR_TYPE_ETHERNET, 6350 /* IPoIB Unicast without GRH. 6351 * Reserved for Spectrum. 6352 */ 6353 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6354 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6355 * adjacency). 6356 * Reserved for Spectrum. 6357 */ 6358 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6359 /* IPoIB Multicast. 6360 * Reserved for Spectrum. 6361 */ 6362 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6363 /* MPLS. 6364 * Reserved for SwitchX/-2. 6365 */ 6366 MLXSW_REG_RATR_TYPE_MPLS, 6367 /* IPinIP Encap. 6368 * Reserved for SwitchX/-2. 6369 */ 6370 MLXSW_REG_RATR_TYPE_IPIP, 6371 }; 6372 6373 /* reg_ratr_type 6374 * Adjacency entry type. 6375 * Access: RW 6376 */ 6377 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6378 6379 /* reg_ratr_adjacency_index_low 6380 * Bits 15:0 of index into the adjacency table. 6381 * For SwitchX and SwitchX-2, the adjacency table is linear and 6382 * used for adjacency entries only. 6383 * For Spectrum, the index is to the KVD linear. 6384 * Access: Index 6385 */ 6386 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6387 6388 /* reg_ratr_egress_router_interface 6389 * Range is 0 .. cap_max_router_interfaces - 1 6390 * Access: RW 6391 */ 6392 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6393 6394 enum mlxsw_reg_ratr_trap_action { 6395 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6396 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6397 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6398 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6399 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6400 }; 6401 6402 /* reg_ratr_trap_action 6403 * see mlxsw_reg_ratr_trap_action 6404 * Access: RW 6405 */ 6406 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6407 6408 /* reg_ratr_adjacency_index_high 6409 * Bits 23:16 of the adjacency_index. 6410 * Access: Index 6411 */ 6412 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6413 6414 enum mlxsw_reg_ratr_trap_id { 6415 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6416 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6417 }; 6418 6419 /* reg_ratr_trap_id 6420 * Trap ID to be reported to CPU. 6421 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6422 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6423 * Access: RW 6424 */ 6425 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6426 6427 /* reg_ratr_eth_destination_mac 6428 * MAC address of the destination next-hop. 6429 * Access: RW 6430 */ 6431 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6432 6433 enum mlxsw_reg_ratr_ipip_type { 6434 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6435 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6436 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6437 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6438 }; 6439 6440 /* reg_ratr_ipip_type 6441 * Underlay destination ip type. 6442 * Note: the type field must match the protocol of the router interface. 6443 * Access: RW 6444 */ 6445 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6446 6447 /* reg_ratr_ipip_ipv4_udip 6448 * Underlay ipv4 dip. 6449 * Reserved when ipip_type is IPv6. 6450 * Access: RW 6451 */ 6452 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6453 6454 /* reg_ratr_ipip_ipv6_ptr 6455 * Pointer to IPv6 underlay destination ip address. 6456 * For Spectrum: Pointer to KVD linear space. 6457 * Access: RW 6458 */ 6459 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6460 6461 enum mlxsw_reg_flow_counter_set_type { 6462 /* No count */ 6463 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6464 /* Count packets and bytes */ 6465 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6466 /* Count only packets */ 6467 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6468 }; 6469 6470 /* reg_ratr_counter_set_type 6471 * Counter set type for flow counters 6472 * Access: RW 6473 */ 6474 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6475 6476 /* reg_ratr_counter_index 6477 * Counter index for flow counters 6478 * Access: RW 6479 */ 6480 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6481 6482 static inline void 6483 mlxsw_reg_ratr_pack(char *payload, 6484 enum mlxsw_reg_ratr_op op, bool valid, 6485 enum mlxsw_reg_ratr_type type, 6486 u32 adjacency_index, u16 egress_rif) 6487 { 6488 MLXSW_REG_ZERO(ratr, payload); 6489 mlxsw_reg_ratr_op_set(payload, op); 6490 mlxsw_reg_ratr_v_set(payload, valid); 6491 mlxsw_reg_ratr_type_set(payload, type); 6492 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6493 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6494 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6495 } 6496 6497 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6498 const char *dest_mac) 6499 { 6500 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6501 } 6502 6503 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6504 { 6505 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6506 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6507 } 6508 6509 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6510 bool counter_enable) 6511 { 6512 enum mlxsw_reg_flow_counter_set_type set_type; 6513 6514 if (counter_enable) 6515 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6516 else 6517 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6518 6519 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6520 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6521 } 6522 6523 /* RDPM - Router DSCP to Priority Mapping 6524 * -------------------------------------- 6525 * Controls the mapping from DSCP field to switch priority on routed packets 6526 */ 6527 #define MLXSW_REG_RDPM_ID 0x8009 6528 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6529 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6530 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6531 #define MLXSW_REG_RDPM_LEN 0x40 6532 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6533 MLXSW_REG_RDPM_LEN - \ 6534 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6535 6536 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6537 6538 /* reg_dscp_entry_e 6539 * Enable update of the specific entry 6540 * Access: Index 6541 */ 6542 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6543 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6544 6545 /* reg_dscp_entry_prio 6546 * Switch Priority 6547 * Access: RW 6548 */ 6549 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6550 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6551 6552 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6553 u8 prio) 6554 { 6555 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6556 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6557 } 6558 6559 /* RICNT - Router Interface Counter Register 6560 * ----------------------------------------- 6561 * The RICNT register retrieves per port performance counters 6562 */ 6563 #define MLXSW_REG_RICNT_ID 0x800B 6564 #define MLXSW_REG_RICNT_LEN 0x100 6565 6566 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6567 6568 /* reg_ricnt_counter_index 6569 * Counter index 6570 * Access: RW 6571 */ 6572 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6573 6574 enum mlxsw_reg_ricnt_counter_set_type { 6575 /* No Count. */ 6576 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6577 /* Basic. Used for router interfaces, counting the following: 6578 * - Error and Discard counters. 6579 * - Unicast, Multicast and Broadcast counters. Sharing the 6580 * same set of counters for the different type of traffic 6581 * (IPv4, IPv6 and mpls). 6582 */ 6583 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6584 }; 6585 6586 /* reg_ricnt_counter_set_type 6587 * Counter Set Type for router interface counter 6588 * Access: RW 6589 */ 6590 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6591 6592 enum mlxsw_reg_ricnt_opcode { 6593 /* Nop. Supported only for read access*/ 6594 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6595 /* Clear. Setting the clr bit will reset the counter value for 6596 * all counters of the specified Router Interface. 6597 */ 6598 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6599 }; 6600 6601 /* reg_ricnt_opcode 6602 * Opcode 6603 * Access: RW 6604 */ 6605 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6606 6607 /* reg_ricnt_good_unicast_packets 6608 * good unicast packets. 6609 * Access: RW 6610 */ 6611 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6612 6613 /* reg_ricnt_good_multicast_packets 6614 * good multicast packets. 6615 * Access: RW 6616 */ 6617 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6618 6619 /* reg_ricnt_good_broadcast_packets 6620 * good broadcast packets 6621 * Access: RW 6622 */ 6623 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6624 6625 /* reg_ricnt_good_unicast_bytes 6626 * A count of L3 data and padding octets not including L2 headers 6627 * for good unicast frames. 6628 * Access: RW 6629 */ 6630 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6631 6632 /* reg_ricnt_good_multicast_bytes 6633 * A count of L3 data and padding octets not including L2 headers 6634 * for good multicast frames. 6635 * Access: RW 6636 */ 6637 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6638 6639 /* reg_ritr_good_broadcast_bytes 6640 * A count of L3 data and padding octets not including L2 headers 6641 * for good broadcast frames. 6642 * Access: RW 6643 */ 6644 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6645 6646 /* reg_ricnt_error_packets 6647 * A count of errored frames that do not pass the router checks. 6648 * Access: RW 6649 */ 6650 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6651 6652 /* reg_ricnt_discrad_packets 6653 * A count of non-errored frames that do not pass the router checks. 6654 * Access: RW 6655 */ 6656 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6657 6658 /* reg_ricnt_error_bytes 6659 * A count of L3 data and padding octets not including L2 headers 6660 * for errored frames. 6661 * Access: RW 6662 */ 6663 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6664 6665 /* reg_ricnt_discard_bytes 6666 * A count of L3 data and padding octets not including L2 headers 6667 * for non-errored frames that do not pass the router checks. 6668 * Access: RW 6669 */ 6670 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6671 6672 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6673 enum mlxsw_reg_ricnt_opcode op) 6674 { 6675 MLXSW_REG_ZERO(ricnt, payload); 6676 mlxsw_reg_ricnt_op_set(payload, op); 6677 mlxsw_reg_ricnt_counter_index_set(payload, index); 6678 mlxsw_reg_ricnt_counter_set_type_set(payload, 6679 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6680 } 6681 6682 /* RRCR - Router Rules Copy Register Layout 6683 * ---------------------------------------- 6684 * This register is used for moving and copying route entry rules. 6685 */ 6686 #define MLXSW_REG_RRCR_ID 0x800F 6687 #define MLXSW_REG_RRCR_LEN 0x24 6688 6689 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6690 6691 enum mlxsw_reg_rrcr_op { 6692 /* Move rules */ 6693 MLXSW_REG_RRCR_OP_MOVE, 6694 /* Copy rules */ 6695 MLXSW_REG_RRCR_OP_COPY, 6696 }; 6697 6698 /* reg_rrcr_op 6699 * Access: WO 6700 */ 6701 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6702 6703 /* reg_rrcr_offset 6704 * Offset within the region from which to copy/move. 6705 * Access: Index 6706 */ 6707 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6708 6709 /* reg_rrcr_size 6710 * The number of rules to copy/move. 6711 * Access: WO 6712 */ 6713 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6714 6715 /* reg_rrcr_table_id 6716 * Identifier of the table on which to perform the operation. Encoding is the 6717 * same as in RTAR.key_type 6718 * Access: Index 6719 */ 6720 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6721 6722 /* reg_rrcr_dest_offset 6723 * Offset within the region to which to copy/move 6724 * Access: Index 6725 */ 6726 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6727 6728 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6729 u16 offset, u16 size, 6730 enum mlxsw_reg_rtar_key_type table_id, 6731 u16 dest_offset) 6732 { 6733 MLXSW_REG_ZERO(rrcr, payload); 6734 mlxsw_reg_rrcr_op_set(payload, op); 6735 mlxsw_reg_rrcr_offset_set(payload, offset); 6736 mlxsw_reg_rrcr_size_set(payload, size); 6737 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6738 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6739 } 6740 6741 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6742 * ------------------------------------------------------- 6743 * RALTA is used to allocate the LPM trees of the SHSPM method. 6744 */ 6745 #define MLXSW_REG_RALTA_ID 0x8010 6746 #define MLXSW_REG_RALTA_LEN 0x04 6747 6748 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6749 6750 /* reg_ralta_op 6751 * opcode (valid for Write, must be 0 on Read) 6752 * 0 - allocate a tree 6753 * 1 - deallocate a tree 6754 * Access: OP 6755 */ 6756 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6757 6758 enum mlxsw_reg_ralxx_protocol { 6759 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6760 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6761 }; 6762 6763 /* reg_ralta_protocol 6764 * Protocol. 6765 * Deallocation opcode: Reserved. 6766 * Access: RW 6767 */ 6768 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6769 6770 /* reg_ralta_tree_id 6771 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6772 * the tree identifier (managed by software). 6773 * Note that tree_id 0 is allocated for a default-route tree. 6774 * Access: Index 6775 */ 6776 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6777 6778 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6779 enum mlxsw_reg_ralxx_protocol protocol, 6780 u8 tree_id) 6781 { 6782 MLXSW_REG_ZERO(ralta, payload); 6783 mlxsw_reg_ralta_op_set(payload, !alloc); 6784 mlxsw_reg_ralta_protocol_set(payload, protocol); 6785 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6786 } 6787 6788 /* RALST - Router Algorithmic LPM Structure Tree Register 6789 * ------------------------------------------------------ 6790 * RALST is used to set and query the structure of an LPM tree. 6791 * The structure of the tree must be sorted as a sorted binary tree, while 6792 * each node is a bin that is tagged as the length of the prefixes the lookup 6793 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6794 * of X bits to match with the destination address. The bin 0 indicates 6795 * the default action, when there is no match of any prefix. 6796 */ 6797 #define MLXSW_REG_RALST_ID 0x8011 6798 #define MLXSW_REG_RALST_LEN 0x104 6799 6800 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6801 6802 /* reg_ralst_root_bin 6803 * The bin number of the root bin. 6804 * 0<root_bin=<(length of IP address) 6805 * For a default-route tree configure 0xff 6806 * Access: RW 6807 */ 6808 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6809 6810 /* reg_ralst_tree_id 6811 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6812 * Access: Index 6813 */ 6814 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6815 6816 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6817 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6818 #define MLXSW_REG_RALST_BIN_COUNT 128 6819 6820 /* reg_ralst_left_child_bin 6821 * Holding the children of the bin according to the stored tree's structure. 6822 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6823 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6824 * Access: RW 6825 */ 6826 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6827 6828 /* reg_ralst_right_child_bin 6829 * Holding the children of the bin according to the stored tree's structure. 6830 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6831 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6832 * Access: RW 6833 */ 6834 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6835 false); 6836 6837 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6838 { 6839 MLXSW_REG_ZERO(ralst, payload); 6840 6841 /* Initialize all bins to have no left or right child */ 6842 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6843 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6844 6845 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6846 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6847 } 6848 6849 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6850 u8 left_child_bin, 6851 u8 right_child_bin) 6852 { 6853 int bin_index = bin_number - 1; 6854 6855 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6856 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6857 right_child_bin); 6858 } 6859 6860 /* RALTB - Router Algorithmic LPM Tree Binding Register 6861 * ---------------------------------------------------- 6862 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6863 */ 6864 #define MLXSW_REG_RALTB_ID 0x8012 6865 #define MLXSW_REG_RALTB_LEN 0x04 6866 6867 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6868 6869 /* reg_raltb_virtual_router 6870 * Virtual Router ID 6871 * Range is 0..cap_max_virtual_routers-1 6872 * Access: Index 6873 */ 6874 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6875 6876 /* reg_raltb_protocol 6877 * Protocol. 6878 * Access: Index 6879 */ 6880 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6881 6882 /* reg_raltb_tree_id 6883 * Tree to be used for the {virtual_router, protocol} 6884 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6885 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6886 * Access: RW 6887 */ 6888 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6889 6890 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6891 enum mlxsw_reg_ralxx_protocol protocol, 6892 u8 tree_id) 6893 { 6894 MLXSW_REG_ZERO(raltb, payload); 6895 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6896 mlxsw_reg_raltb_protocol_set(payload, protocol); 6897 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6898 } 6899 6900 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6901 * ----------------------------------------------------- 6902 * RALUE is used to configure and query LPM entries that serve 6903 * the Unicast protocols. 6904 */ 6905 #define MLXSW_REG_RALUE_ID 0x8013 6906 #define MLXSW_REG_RALUE_LEN 0x38 6907 6908 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6909 6910 /* reg_ralue_protocol 6911 * Protocol. 6912 * Access: Index 6913 */ 6914 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6915 6916 enum mlxsw_reg_ralue_op { 6917 /* Read operation. If entry doesn't exist, the operation fails. */ 6918 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6919 /* Clear on read operation. Used to read entry and 6920 * clear Activity bit. 6921 */ 6922 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6923 /* Write operation. Used to write a new entry to the table. All RW 6924 * fields are written for new entry. Activity bit is set 6925 * for new entries. 6926 */ 6927 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6928 /* Update operation. Used to update an existing route entry and 6929 * only update the RW fields that are detailed in the field 6930 * op_u_mask. If entry doesn't exist, the operation fails. 6931 */ 6932 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6933 /* Clear activity. The Activity bit (the field a) is cleared 6934 * for the entry. 6935 */ 6936 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6937 /* Delete operation. Used to delete an existing entry. If entry 6938 * doesn't exist, the operation fails. 6939 */ 6940 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6941 }; 6942 6943 /* reg_ralue_op 6944 * Operation. 6945 * Access: OP 6946 */ 6947 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6948 6949 /* reg_ralue_a 6950 * Activity. Set for new entries. Set if a packet lookup has hit on the 6951 * specific entry, only if the entry is a route. To clear the a bit, use 6952 * "clear activity" op. 6953 * Enabled by activity_dis in RGCR 6954 * Access: RO 6955 */ 6956 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6957 6958 /* reg_ralue_virtual_router 6959 * Virtual Router ID 6960 * Range is 0..cap_max_virtual_routers-1 6961 * Access: Index 6962 */ 6963 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6964 6965 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6966 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6967 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6968 6969 /* reg_ralue_op_u_mask 6970 * opcode update mask. 6971 * On read operation, this field is reserved. 6972 * This field is valid for update opcode, otherwise - reserved. 6973 * This field is a bitmask of the fields that should be updated. 6974 * Access: WO 6975 */ 6976 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6977 6978 /* reg_ralue_prefix_len 6979 * Number of bits in the prefix of the LPM route. 6980 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6981 * two entries in the physical HW table. 6982 * Access: Index 6983 */ 6984 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6985 6986 /* reg_ralue_dip* 6987 * The prefix of the route or of the marker that the object of the LPM 6988 * is compared with. The most significant bits of the dip are the prefix. 6989 * The least significant bits must be '0' if the prefix_len is smaller 6990 * than 128 for IPv6 or smaller than 32 for IPv4. 6991 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6992 * Access: Index 6993 */ 6994 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6995 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6996 6997 enum mlxsw_reg_ralue_entry_type { 6998 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6999 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7000 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7001 }; 7002 7003 /* reg_ralue_entry_type 7004 * Entry type. 7005 * Note - for Marker entries, the action_type and action fields are reserved. 7006 * Access: RW 7007 */ 7008 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7009 7010 /* reg_ralue_bmp_len 7011 * The best match prefix length in the case that there is no match for 7012 * longer prefixes. 7013 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7014 * Note for any update operation with entry_type modification this 7015 * field must be set. 7016 * Access: RW 7017 */ 7018 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7019 7020 enum mlxsw_reg_ralue_action_type { 7021 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7022 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7023 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7024 }; 7025 7026 /* reg_ralue_action_type 7027 * Action Type 7028 * Indicates how the IP address is connected. 7029 * It can be connected to a local subnet through local_erif or can be 7030 * on a remote subnet connected through a next-hop router, 7031 * or transmitted to the CPU. 7032 * Reserved when entry_type = MARKER_ENTRY 7033 * Access: RW 7034 */ 7035 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7036 7037 enum mlxsw_reg_ralue_trap_action { 7038 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7039 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7040 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7041 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7042 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7043 }; 7044 7045 /* reg_ralue_trap_action 7046 * Trap action. 7047 * For IP2ME action, only NOP and MIRROR are possible. 7048 * Access: RW 7049 */ 7050 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7051 7052 /* reg_ralue_trap_id 7053 * Trap ID to be reported to CPU. 7054 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7055 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7056 * Access: RW 7057 */ 7058 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7059 7060 /* reg_ralue_adjacency_index 7061 * Points to the first entry of the group-based ECMP. 7062 * Only relevant in case of REMOTE action. 7063 * Access: RW 7064 */ 7065 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7066 7067 /* reg_ralue_ecmp_size 7068 * Amount of sequential entries starting 7069 * from the adjacency_index (the number of ECMPs). 7070 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7071 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7072 * Only relevant in case of REMOTE action. 7073 * Access: RW 7074 */ 7075 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7076 7077 /* reg_ralue_local_erif 7078 * Egress Router Interface. 7079 * Only relevant in case of LOCAL action. 7080 * Access: RW 7081 */ 7082 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7083 7084 /* reg_ralue_ip2me_v 7085 * Valid bit for the tunnel_ptr field. 7086 * If valid = 0 then trap to CPU as IP2ME trap ID. 7087 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7088 * decapsulation then tunnel decapsulation is done. 7089 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7090 * decapsulation then trap as IP2ME trap ID. 7091 * Only relevant in case of IP2ME action. 7092 * Access: RW 7093 */ 7094 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7095 7096 /* reg_ralue_ip2me_tunnel_ptr 7097 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7098 * For Spectrum, pointer to KVD Linear. 7099 * Only relevant in case of IP2ME action. 7100 * Access: RW 7101 */ 7102 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7103 7104 static inline void mlxsw_reg_ralue_pack(char *payload, 7105 enum mlxsw_reg_ralxx_protocol protocol, 7106 enum mlxsw_reg_ralue_op op, 7107 u16 virtual_router, u8 prefix_len) 7108 { 7109 MLXSW_REG_ZERO(ralue, payload); 7110 mlxsw_reg_ralue_protocol_set(payload, protocol); 7111 mlxsw_reg_ralue_op_set(payload, op); 7112 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7113 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7114 mlxsw_reg_ralue_entry_type_set(payload, 7115 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7116 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7117 } 7118 7119 static inline void mlxsw_reg_ralue_pack4(char *payload, 7120 enum mlxsw_reg_ralxx_protocol protocol, 7121 enum mlxsw_reg_ralue_op op, 7122 u16 virtual_router, u8 prefix_len, 7123 u32 dip) 7124 { 7125 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7126 mlxsw_reg_ralue_dip4_set(payload, dip); 7127 } 7128 7129 static inline void mlxsw_reg_ralue_pack6(char *payload, 7130 enum mlxsw_reg_ralxx_protocol protocol, 7131 enum mlxsw_reg_ralue_op op, 7132 u16 virtual_router, u8 prefix_len, 7133 const void *dip) 7134 { 7135 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7136 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7137 } 7138 7139 static inline void 7140 mlxsw_reg_ralue_act_remote_pack(char *payload, 7141 enum mlxsw_reg_ralue_trap_action trap_action, 7142 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7143 { 7144 mlxsw_reg_ralue_action_type_set(payload, 7145 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7146 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7147 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7148 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7149 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7150 } 7151 7152 static inline void 7153 mlxsw_reg_ralue_act_local_pack(char *payload, 7154 enum mlxsw_reg_ralue_trap_action trap_action, 7155 u16 trap_id, u16 local_erif) 7156 { 7157 mlxsw_reg_ralue_action_type_set(payload, 7158 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7159 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7160 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7161 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7162 } 7163 7164 static inline void 7165 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7166 { 7167 mlxsw_reg_ralue_action_type_set(payload, 7168 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7169 } 7170 7171 static inline void 7172 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7173 { 7174 mlxsw_reg_ralue_action_type_set(payload, 7175 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7176 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7177 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7178 } 7179 7180 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7181 * ---------------------------------------------------------- 7182 * The RAUHT register is used to configure and query the Unicast Host table in 7183 * devices that implement the Algorithmic LPM. 7184 */ 7185 #define MLXSW_REG_RAUHT_ID 0x8014 7186 #define MLXSW_REG_RAUHT_LEN 0x74 7187 7188 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7189 7190 enum mlxsw_reg_rauht_type { 7191 MLXSW_REG_RAUHT_TYPE_IPV4, 7192 MLXSW_REG_RAUHT_TYPE_IPV6, 7193 }; 7194 7195 /* reg_rauht_type 7196 * Access: Index 7197 */ 7198 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7199 7200 enum mlxsw_reg_rauht_op { 7201 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7202 /* Read operation */ 7203 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7204 /* Clear on read operation. Used to read entry and clear 7205 * activity bit. 7206 */ 7207 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7208 /* Add. Used to write a new entry to the table. All R/W fields are 7209 * relevant for new entry. Activity bit is set for new entries. 7210 */ 7211 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7212 /* Update action. Used to update an existing route entry and 7213 * only update the following fields: 7214 * trap_action, trap_id, mac, counter_set_type, counter_index 7215 */ 7216 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7217 /* Clear activity. A bit is cleared for the entry. */ 7218 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7219 /* Delete entry */ 7220 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7221 /* Delete all host entries on a RIF. In this command, dip 7222 * field is reserved. 7223 */ 7224 }; 7225 7226 /* reg_rauht_op 7227 * Access: OP 7228 */ 7229 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7230 7231 /* reg_rauht_a 7232 * Activity. Set for new entries. Set if a packet lookup has hit on 7233 * the specific entry. 7234 * To clear the a bit, use "clear activity" op. 7235 * Enabled by activity_dis in RGCR 7236 * Access: RO 7237 */ 7238 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7239 7240 /* reg_rauht_rif 7241 * Router Interface 7242 * Access: Index 7243 */ 7244 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7245 7246 /* reg_rauht_dip* 7247 * Destination address. 7248 * Access: Index 7249 */ 7250 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7251 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7252 7253 enum mlxsw_reg_rauht_trap_action { 7254 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7255 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7256 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7257 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7258 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7259 }; 7260 7261 /* reg_rauht_trap_action 7262 * Access: RW 7263 */ 7264 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7265 7266 enum mlxsw_reg_rauht_trap_id { 7267 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7268 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7269 }; 7270 7271 /* reg_rauht_trap_id 7272 * Trap ID to be reported to CPU. 7273 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7274 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7275 * trap_id is reserved. 7276 * Access: RW 7277 */ 7278 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7279 7280 /* reg_rauht_counter_set_type 7281 * Counter set type for flow counters 7282 * Access: RW 7283 */ 7284 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7285 7286 /* reg_rauht_counter_index 7287 * Counter index for flow counters 7288 * Access: RW 7289 */ 7290 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7291 7292 /* reg_rauht_mac 7293 * MAC address. 7294 * Access: RW 7295 */ 7296 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7297 7298 static inline void mlxsw_reg_rauht_pack(char *payload, 7299 enum mlxsw_reg_rauht_op op, u16 rif, 7300 const char *mac) 7301 { 7302 MLXSW_REG_ZERO(rauht, payload); 7303 mlxsw_reg_rauht_op_set(payload, op); 7304 mlxsw_reg_rauht_rif_set(payload, rif); 7305 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7306 } 7307 7308 static inline void mlxsw_reg_rauht_pack4(char *payload, 7309 enum mlxsw_reg_rauht_op op, u16 rif, 7310 const char *mac, u32 dip) 7311 { 7312 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7313 mlxsw_reg_rauht_dip4_set(payload, dip); 7314 } 7315 7316 static inline void mlxsw_reg_rauht_pack6(char *payload, 7317 enum mlxsw_reg_rauht_op op, u16 rif, 7318 const char *mac, const char *dip) 7319 { 7320 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7321 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7322 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7323 } 7324 7325 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7326 u64 counter_index) 7327 { 7328 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7329 mlxsw_reg_rauht_counter_set_type_set(payload, 7330 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7331 } 7332 7333 /* RALEU - Router Algorithmic LPM ECMP Update Register 7334 * --------------------------------------------------- 7335 * The register enables updating the ECMP section in the action for multiple 7336 * LPM Unicast entries in a single operation. The update is executed to 7337 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7338 */ 7339 #define MLXSW_REG_RALEU_ID 0x8015 7340 #define MLXSW_REG_RALEU_LEN 0x28 7341 7342 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7343 7344 /* reg_raleu_protocol 7345 * Protocol. 7346 * Access: Index 7347 */ 7348 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7349 7350 /* reg_raleu_virtual_router 7351 * Virtual Router ID 7352 * Range is 0..cap_max_virtual_routers-1 7353 * Access: Index 7354 */ 7355 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7356 7357 /* reg_raleu_adjacency_index 7358 * Adjacency Index used for matching on the existing entries. 7359 * Access: Index 7360 */ 7361 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7362 7363 /* reg_raleu_ecmp_size 7364 * ECMP Size used for matching on the existing entries. 7365 * Access: Index 7366 */ 7367 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7368 7369 /* reg_raleu_new_adjacency_index 7370 * New Adjacency Index. 7371 * Access: WO 7372 */ 7373 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7374 7375 /* reg_raleu_new_ecmp_size 7376 * New ECMP Size. 7377 * Access: WO 7378 */ 7379 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7380 7381 static inline void mlxsw_reg_raleu_pack(char *payload, 7382 enum mlxsw_reg_ralxx_protocol protocol, 7383 u16 virtual_router, 7384 u32 adjacency_index, u16 ecmp_size, 7385 u32 new_adjacency_index, 7386 u16 new_ecmp_size) 7387 { 7388 MLXSW_REG_ZERO(raleu, payload); 7389 mlxsw_reg_raleu_protocol_set(payload, protocol); 7390 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7391 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7392 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7393 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7394 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7395 } 7396 7397 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7398 * ---------------------------------------------------------------- 7399 * The RAUHTD register allows dumping entries from the Router Unicast Host 7400 * Table. For a given session an entry is dumped no more than one time. The 7401 * first RAUHTD access after reset is a new session. A session ends when the 7402 * num_rec response is smaller than num_rec request or for IPv4 when the 7403 * num_entries is smaller than 4. The clear activity affect the current session 7404 * or the last session if a new session has not started. 7405 */ 7406 #define MLXSW_REG_RAUHTD_ID 0x8018 7407 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7408 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7409 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7410 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7411 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7412 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7413 7414 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7415 7416 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7417 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7418 7419 /* reg_rauhtd_filter_fields 7420 * if a bit is '0' then the relevant field is ignored and dump is done 7421 * regardless of the field value 7422 * Bit0 - filter by activity: entry_a 7423 * Bit3 - filter by entry rip: entry_rif 7424 * Access: Index 7425 */ 7426 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7427 7428 enum mlxsw_reg_rauhtd_op { 7429 MLXSW_REG_RAUHTD_OP_DUMP, 7430 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7431 }; 7432 7433 /* reg_rauhtd_op 7434 * Access: OP 7435 */ 7436 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7437 7438 /* reg_rauhtd_num_rec 7439 * At request: number of records requested 7440 * At response: number of records dumped 7441 * For IPv4, each record has 4 entries at request and up to 4 entries 7442 * at response 7443 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7444 * Access: Index 7445 */ 7446 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7447 7448 /* reg_rauhtd_entry_a 7449 * Dump only if activity has value of entry_a 7450 * Reserved if filter_fields bit0 is '0' 7451 * Access: Index 7452 */ 7453 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7454 7455 enum mlxsw_reg_rauhtd_type { 7456 MLXSW_REG_RAUHTD_TYPE_IPV4, 7457 MLXSW_REG_RAUHTD_TYPE_IPV6, 7458 }; 7459 7460 /* reg_rauhtd_type 7461 * Dump only if record type is: 7462 * 0 - IPv4 7463 * 1 - IPv6 7464 * Access: Index 7465 */ 7466 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7467 7468 /* reg_rauhtd_entry_rif 7469 * Dump only if RIF has value of entry_rif 7470 * Reserved if filter_fields bit3 is '0' 7471 * Access: Index 7472 */ 7473 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7474 7475 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7476 enum mlxsw_reg_rauhtd_type type) 7477 { 7478 MLXSW_REG_ZERO(rauhtd, payload); 7479 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7480 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7481 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7482 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7483 mlxsw_reg_rauhtd_type_set(payload, type); 7484 } 7485 7486 /* reg_rauhtd_ipv4_rec_num_entries 7487 * Number of valid entries in this record: 7488 * 0 - 1 valid entry 7489 * 1 - 2 valid entries 7490 * 2 - 3 valid entries 7491 * 3 - 4 valid entries 7492 * Access: RO 7493 */ 7494 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7495 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7496 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7497 7498 /* reg_rauhtd_rec_type 7499 * Record type. 7500 * 0 - IPv4 7501 * 1 - IPv6 7502 * Access: RO 7503 */ 7504 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7505 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7506 7507 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7508 7509 /* reg_rauhtd_ipv4_ent_a 7510 * Activity. Set for new entries. Set if a packet lookup has hit on the 7511 * specific entry. 7512 * Access: RO 7513 */ 7514 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7515 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7516 7517 /* reg_rauhtd_ipv4_ent_rif 7518 * Router interface. 7519 * Access: RO 7520 */ 7521 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7522 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7523 7524 /* reg_rauhtd_ipv4_ent_dip 7525 * Destination IPv4 address. 7526 * Access: RO 7527 */ 7528 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7529 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7530 7531 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7532 7533 /* reg_rauhtd_ipv6_ent_a 7534 * Activity. Set for new entries. Set if a packet lookup has hit on the 7535 * specific entry. 7536 * Access: RO 7537 */ 7538 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7539 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7540 7541 /* reg_rauhtd_ipv6_ent_rif 7542 * Router interface. 7543 * Access: RO 7544 */ 7545 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7546 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7547 7548 /* reg_rauhtd_ipv6_ent_dip 7549 * Destination IPv6 address. 7550 * Access: RO 7551 */ 7552 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7553 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7554 7555 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7556 int ent_index, u16 *p_rif, 7557 u32 *p_dip) 7558 { 7559 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7560 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7561 } 7562 7563 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7564 int rec_index, u16 *p_rif, 7565 char *p_dip) 7566 { 7567 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7568 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7569 } 7570 7571 /* RTDP - Routing Tunnel Decap Properties Register 7572 * ----------------------------------------------- 7573 * The RTDP register is used for configuring the tunnel decap properties of NVE 7574 * and IPinIP. 7575 */ 7576 #define MLXSW_REG_RTDP_ID 0x8020 7577 #define MLXSW_REG_RTDP_LEN 0x44 7578 7579 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7580 7581 enum mlxsw_reg_rtdp_type { 7582 MLXSW_REG_RTDP_TYPE_NVE, 7583 MLXSW_REG_RTDP_TYPE_IPIP, 7584 }; 7585 7586 /* reg_rtdp_type 7587 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7588 * Access: RW 7589 */ 7590 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7591 7592 /* reg_rtdp_tunnel_index 7593 * Index to the Decap entry. 7594 * For Spectrum, Index to KVD Linear. 7595 * Access: Index 7596 */ 7597 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7598 7599 /* reg_rtdp_egress_router_interface 7600 * Underlay egress router interface. 7601 * Valid range is from 0 to cap_max_router_interfaces - 1 7602 * Access: RW 7603 */ 7604 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7605 7606 /* IPinIP */ 7607 7608 /* reg_rtdp_ipip_irif 7609 * Ingress Router Interface for the overlay router 7610 * Access: RW 7611 */ 7612 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7613 7614 enum mlxsw_reg_rtdp_ipip_sip_check { 7615 /* No sip checks. */ 7616 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7617 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7618 * equal ipv4_usip. 7619 */ 7620 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7621 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7622 * equal ipv6_usip. 7623 */ 7624 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7625 }; 7626 7627 /* reg_rtdp_ipip_sip_check 7628 * SIP check to perform. If decapsulation failed due to these configurations 7629 * then trap_id is IPIP_DECAP_ERROR. 7630 * Access: RW 7631 */ 7632 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7633 7634 /* If set, allow decapsulation of IPinIP (without GRE). */ 7635 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7636 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7637 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7638 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7639 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7640 7641 /* reg_rtdp_ipip_type_check 7642 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7643 * these configurations then trap_id is IPIP_DECAP_ERROR. 7644 * Access: RW 7645 */ 7646 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7647 7648 /* reg_rtdp_ipip_gre_key_check 7649 * Whether GRE key should be checked. When check is enabled: 7650 * - A packet received as IPinIP (without GRE) will always pass. 7651 * - A packet received as IPinGREinIP without a key will not pass the check. 7652 * - A packet received as IPinGREinIP with a key will pass the check only if the 7653 * key in the packet is equal to expected_gre_key. 7654 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7655 * Access: RW 7656 */ 7657 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7658 7659 /* reg_rtdp_ipip_ipv4_usip 7660 * Underlay IPv4 address for ipv4 source address check. 7661 * Reserved when sip_check is not '1'. 7662 * Access: RW 7663 */ 7664 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7665 7666 /* reg_rtdp_ipip_ipv6_usip_ptr 7667 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7668 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7669 * is to the KVD linear. 7670 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7671 * Access: RW 7672 */ 7673 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7674 7675 /* reg_rtdp_ipip_expected_gre_key 7676 * GRE key for checking. 7677 * Reserved when gre_key_check is '0'. 7678 * Access: RW 7679 */ 7680 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7681 7682 static inline void mlxsw_reg_rtdp_pack(char *payload, 7683 enum mlxsw_reg_rtdp_type type, 7684 u32 tunnel_index) 7685 { 7686 MLXSW_REG_ZERO(rtdp, payload); 7687 mlxsw_reg_rtdp_type_set(payload, type); 7688 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7689 } 7690 7691 static inline void 7692 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7693 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7694 unsigned int type_check, bool gre_key_check, 7695 u32 ipv4_usip, u32 expected_gre_key) 7696 { 7697 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7698 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7699 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7700 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7701 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7702 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7703 } 7704 7705 /* RIGR-V2 - Router Interface Group Register Version 2 7706 * --------------------------------------------------- 7707 * The RIGR_V2 register is used to add, remove and query egress interface list 7708 * of a multicast forwarding entry. 7709 */ 7710 #define MLXSW_REG_RIGR2_ID 0x8023 7711 #define MLXSW_REG_RIGR2_LEN 0xB0 7712 7713 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7714 7715 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7716 7717 /* reg_rigr2_rigr_index 7718 * KVD Linear index. 7719 * Access: Index 7720 */ 7721 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7722 7723 /* reg_rigr2_vnext 7724 * Next RIGR Index is valid. 7725 * Access: RW 7726 */ 7727 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7728 7729 /* reg_rigr2_next_rigr_index 7730 * Next RIGR Index. The index is to the KVD linear. 7731 * Reserved when vnxet = '0'. 7732 * Access: RW 7733 */ 7734 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7735 7736 /* reg_rigr2_vrmid 7737 * RMID Index is valid. 7738 * Access: RW 7739 */ 7740 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7741 7742 /* reg_rigr2_rmid_index 7743 * RMID Index. 7744 * Range 0 .. max_mid - 1 7745 * Reserved when vrmid = '0'. 7746 * The index is to the Port Group Table (PGT) 7747 * Access: RW 7748 */ 7749 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7750 7751 /* reg_rigr2_erif_entry_v 7752 * Egress Router Interface is valid. 7753 * Note that low-entries must be set if high-entries are set. For 7754 * example: if erif_entry[2].v is set then erif_entry[1].v and 7755 * erif_entry[0].v must be set. 7756 * Index can be from 0 to cap_mc_erif_list_entries-1 7757 * Access: RW 7758 */ 7759 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7760 7761 /* reg_rigr2_erif_entry_erif 7762 * Egress Router Interface. 7763 * Valid range is from 0 to cap_max_router_interfaces - 1 7764 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7765 * Access: RW 7766 */ 7767 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7768 7769 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7770 bool vnext, u32 next_rigr_index) 7771 { 7772 MLXSW_REG_ZERO(rigr2, payload); 7773 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7774 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7775 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7776 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7777 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7778 } 7779 7780 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7781 bool v, u16 erif) 7782 { 7783 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7784 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7785 } 7786 7787 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7788 * ------------------------------------------------------ 7789 */ 7790 #define MLXSW_REG_RECR2_ID 0x8025 7791 #define MLXSW_REG_RECR2_LEN 0x38 7792 7793 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7794 7795 /* reg_recr2_pp 7796 * Per-port configuration 7797 * Access: Index 7798 */ 7799 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7800 7801 /* reg_recr2_sh 7802 * Symmetric hash 7803 * Access: RW 7804 */ 7805 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7806 7807 /* reg_recr2_seed 7808 * Seed 7809 * Access: RW 7810 */ 7811 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7812 7813 enum { 7814 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7815 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7816 /* Enable IPv4 fields if packet is TCP or UDP */ 7817 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7818 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7819 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7820 /* Enable IPv6 fields if packet is TCP or UDP */ 7821 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7822 /* Enable TCP/UDP header fields if packet is IPv4 */ 7823 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7824 /* Enable TCP/UDP header fields if packet is IPv6 */ 7825 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7826 }; 7827 7828 /* reg_recr2_outer_header_enables 7829 * Bit mask where each bit enables a specific layer to be included in 7830 * the hash calculation. 7831 * Access: RW 7832 */ 7833 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7834 7835 enum { 7836 /* IPv4 Source IP */ 7837 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7838 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7839 /* IPv4 Destination IP */ 7840 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7841 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7842 /* IP Protocol */ 7843 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7844 /* IPv6 Source IP */ 7845 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7846 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7847 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7848 /* IPv6 Destination IP */ 7849 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7850 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7851 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7852 /* IPv6 Next Header */ 7853 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7854 /* IPv6 Flow Label */ 7855 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7856 /* TCP/UDP Source Port */ 7857 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7858 /* TCP/UDP Destination Port */ 7859 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7860 }; 7861 7862 /* reg_recr2_outer_header_fields_enable 7863 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7864 * Access: RW 7865 */ 7866 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7867 7868 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7869 { 7870 int i; 7871 7872 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7873 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7874 true); 7875 } 7876 7877 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7878 { 7879 int i; 7880 7881 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7882 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7883 true); 7884 } 7885 7886 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7887 { 7888 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7889 7890 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7891 7892 i = MLXSW_REG_RECR2_IPV6_SIP8; 7893 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7894 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7895 true); 7896 } 7897 7898 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7899 { 7900 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7901 7902 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7903 7904 i = MLXSW_REG_RECR2_IPV6_DIP8; 7905 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7906 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7907 true); 7908 } 7909 7910 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7911 { 7912 MLXSW_REG_ZERO(recr2, payload); 7913 mlxsw_reg_recr2_pp_set(payload, false); 7914 mlxsw_reg_recr2_sh_set(payload, true); 7915 mlxsw_reg_recr2_seed_set(payload, seed); 7916 } 7917 7918 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7919 * -------------------------------------------------------------- 7920 * The RMFT_V2 register is used to configure and query the multicast table. 7921 */ 7922 #define MLXSW_REG_RMFT2_ID 0x8027 7923 #define MLXSW_REG_RMFT2_LEN 0x174 7924 7925 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7926 7927 /* reg_rmft2_v 7928 * Valid 7929 * Access: RW 7930 */ 7931 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7932 7933 enum mlxsw_reg_rmft2_type { 7934 MLXSW_REG_RMFT2_TYPE_IPV4, 7935 MLXSW_REG_RMFT2_TYPE_IPV6 7936 }; 7937 7938 /* reg_rmft2_type 7939 * Access: Index 7940 */ 7941 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7942 7943 enum mlxsw_sp_reg_rmft2_op { 7944 /* For Write: 7945 * Write operation. Used to write a new entry to the table. All RW 7946 * fields are relevant for new entry. Activity bit is set for new 7947 * entries - Note write with v (Valid) 0 will delete the entry. 7948 * For Query: 7949 * Read operation 7950 */ 7951 MLXSW_REG_RMFT2_OP_READ_WRITE, 7952 }; 7953 7954 /* reg_rmft2_op 7955 * Operation. 7956 * Access: OP 7957 */ 7958 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7959 7960 /* reg_rmft2_a 7961 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7962 * entry. 7963 * Access: RO 7964 */ 7965 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7966 7967 /* reg_rmft2_offset 7968 * Offset within the multicast forwarding table to write to. 7969 * Access: Index 7970 */ 7971 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7972 7973 /* reg_rmft2_virtual_router 7974 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7975 * Access: RW 7976 */ 7977 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7978 7979 enum mlxsw_reg_rmft2_irif_mask { 7980 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7981 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7982 }; 7983 7984 /* reg_rmft2_irif_mask 7985 * Ingress RIF mask. 7986 * Access: RW 7987 */ 7988 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7989 7990 /* reg_rmft2_irif 7991 * Ingress RIF index. 7992 * Access: RW 7993 */ 7994 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7995 7996 /* reg_rmft2_dip{4,6} 7997 * Destination IPv4/6 address 7998 * Access: RW 7999 */ 8000 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8001 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8002 8003 /* reg_rmft2_dip{4,6}_mask 8004 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8005 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8006 * Access: RW 8007 */ 8008 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8009 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8010 8011 /* reg_rmft2_sip{4,6} 8012 * Source IPv4/6 address 8013 * Access: RW 8014 */ 8015 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8016 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8017 8018 /* reg_rmft2_sip{4,6}_mask 8019 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8020 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8021 * Access: RW 8022 */ 8023 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8024 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8025 8026 /* reg_rmft2_flexible_action_set 8027 * ACL action set. The only supported action types in this field and in any 8028 * action-set pointed from here are as follows: 8029 * 00h: ACTION_NULL 8030 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8031 * 03h: ACTION_TRAP 8032 * 06h: ACTION_QOS 8033 * 08h: ACTION_POLICING_MONITORING 8034 * 10h: ACTION_ROUTER_MC 8035 * Access: RW 8036 */ 8037 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8038 MLXSW_REG_FLEX_ACTION_SET_LEN); 8039 8040 static inline void 8041 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8042 u16 virtual_router, 8043 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8044 const char *flex_action_set) 8045 { 8046 MLXSW_REG_ZERO(rmft2, payload); 8047 mlxsw_reg_rmft2_v_set(payload, v); 8048 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8049 mlxsw_reg_rmft2_offset_set(payload, offset); 8050 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8051 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8052 mlxsw_reg_rmft2_irif_set(payload, irif); 8053 if (flex_action_set) 8054 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8055 flex_action_set); 8056 } 8057 8058 static inline void 8059 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8060 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8061 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8062 const char *flexible_action_set) 8063 { 8064 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8065 irif_mask, irif, flexible_action_set); 8066 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8067 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8068 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8069 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8070 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8071 } 8072 8073 static inline void 8074 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8075 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8076 struct in6_addr dip6, struct in6_addr dip6_mask, 8077 struct in6_addr sip6, struct in6_addr sip6_mask, 8078 const char *flexible_action_set) 8079 { 8080 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8081 irif_mask, irif, flexible_action_set); 8082 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8083 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8084 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8085 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8086 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8087 } 8088 8089 /* MFCR - Management Fan Control Register 8090 * -------------------------------------- 8091 * This register controls the settings of the Fan Speed PWM mechanism. 8092 */ 8093 #define MLXSW_REG_MFCR_ID 0x9001 8094 #define MLXSW_REG_MFCR_LEN 0x08 8095 8096 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8097 8098 enum mlxsw_reg_mfcr_pwm_frequency { 8099 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8100 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8101 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8102 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8103 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8104 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8105 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8106 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8107 }; 8108 8109 /* reg_mfcr_pwm_frequency 8110 * Controls the frequency of the PWM signal. 8111 * Access: RW 8112 */ 8113 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8114 8115 #define MLXSW_MFCR_TACHOS_MAX 10 8116 8117 /* reg_mfcr_tacho_active 8118 * Indicates which of the tachometer is active (bit per tachometer). 8119 * Access: RO 8120 */ 8121 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8122 8123 #define MLXSW_MFCR_PWMS_MAX 5 8124 8125 /* reg_mfcr_pwm_active 8126 * Indicates which of the PWM control is active (bit per PWM). 8127 * Access: RO 8128 */ 8129 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8130 8131 static inline void 8132 mlxsw_reg_mfcr_pack(char *payload, 8133 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8134 { 8135 MLXSW_REG_ZERO(mfcr, payload); 8136 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8137 } 8138 8139 static inline void 8140 mlxsw_reg_mfcr_unpack(char *payload, 8141 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8142 u16 *p_tacho_active, u8 *p_pwm_active) 8143 { 8144 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8145 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8146 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8147 } 8148 8149 /* MFSC - Management Fan Speed Control Register 8150 * -------------------------------------------- 8151 * This register controls the settings of the Fan Speed PWM mechanism. 8152 */ 8153 #define MLXSW_REG_MFSC_ID 0x9002 8154 #define MLXSW_REG_MFSC_LEN 0x08 8155 8156 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8157 8158 /* reg_mfsc_pwm 8159 * Fan pwm to control / monitor. 8160 * Access: Index 8161 */ 8162 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8163 8164 /* reg_mfsc_pwm_duty_cycle 8165 * Controls the duty cycle of the PWM. Value range from 0..255 to 8166 * represent duty cycle of 0%...100%. 8167 * Access: RW 8168 */ 8169 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8170 8171 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8172 u8 pwm_duty_cycle) 8173 { 8174 MLXSW_REG_ZERO(mfsc, payload); 8175 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8176 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8177 } 8178 8179 /* MFSM - Management Fan Speed Measurement 8180 * --------------------------------------- 8181 * This register controls the settings of the Tacho measurements and 8182 * enables reading the Tachometer measurements. 8183 */ 8184 #define MLXSW_REG_MFSM_ID 0x9003 8185 #define MLXSW_REG_MFSM_LEN 0x08 8186 8187 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8188 8189 /* reg_mfsm_tacho 8190 * Fan tachometer index. 8191 * Access: Index 8192 */ 8193 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8194 8195 /* reg_mfsm_rpm 8196 * Fan speed (round per minute). 8197 * Access: RO 8198 */ 8199 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8200 8201 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8202 { 8203 MLXSW_REG_ZERO(mfsm, payload); 8204 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8205 } 8206 8207 /* MFSL - Management Fan Speed Limit Register 8208 * ------------------------------------------ 8209 * The Fan Speed Limit register is used to configure the fan speed 8210 * event / interrupt notification mechanism. Fan speed threshold are 8211 * defined for both under-speed and over-speed. 8212 */ 8213 #define MLXSW_REG_MFSL_ID 0x9004 8214 #define MLXSW_REG_MFSL_LEN 0x0C 8215 8216 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8217 8218 /* reg_mfsl_tacho 8219 * Fan tachometer index. 8220 * Access: Index 8221 */ 8222 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8223 8224 /* reg_mfsl_tach_min 8225 * Tachometer minimum value (minimum RPM). 8226 * Access: RW 8227 */ 8228 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8229 8230 /* reg_mfsl_tach_max 8231 * Tachometer maximum value (maximum RPM). 8232 * Access: RW 8233 */ 8234 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8235 8236 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8237 u16 tach_min, u16 tach_max) 8238 { 8239 MLXSW_REG_ZERO(mfsl, payload); 8240 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8241 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8242 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8243 } 8244 8245 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8246 u16 *p_tach_min, u16 *p_tach_max) 8247 { 8248 if (p_tach_min) 8249 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8250 8251 if (p_tach_max) 8252 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8253 } 8254 8255 /* FORE - Fan Out of Range Event Register 8256 * -------------------------------------- 8257 * This register reports the status of the controlled fans compared to the 8258 * range defined by the MFSL register. 8259 */ 8260 #define MLXSW_REG_FORE_ID 0x9007 8261 #define MLXSW_REG_FORE_LEN 0x0C 8262 8263 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8264 8265 /* fan_under_limit 8266 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8267 * to a single tachometer and indicates the specific tachometer reading is 8268 * below the threshold. 8269 * Access: RO 8270 */ 8271 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8272 8273 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8274 bool *fault) 8275 { 8276 u16 limit; 8277 8278 if (fault) { 8279 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8280 *fault = limit & BIT(tacho); 8281 } 8282 } 8283 8284 /* MTCAP - Management Temperature Capabilities 8285 * ------------------------------------------- 8286 * This register exposes the capabilities of the device and 8287 * system temperature sensing. 8288 */ 8289 #define MLXSW_REG_MTCAP_ID 0x9009 8290 #define MLXSW_REG_MTCAP_LEN 0x08 8291 8292 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8293 8294 /* reg_mtcap_sensor_count 8295 * Number of sensors supported by the device. 8296 * This includes the QSFP module sensors (if exists in the QSFP module). 8297 * Access: RO 8298 */ 8299 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8300 8301 /* MTMP - Management Temperature 8302 * ----------------------------- 8303 * This register controls the settings of the temperature measurements 8304 * and enables reading the temperature measurements. Note that temperature 8305 * is in 0.125 degrees Celsius. 8306 */ 8307 #define MLXSW_REG_MTMP_ID 0x900A 8308 #define MLXSW_REG_MTMP_LEN 0x20 8309 8310 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8311 8312 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8313 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8314 /* reg_mtmp_sensor_index 8315 * Sensors index to access. 8316 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8317 * (module 0 is mapped to sensor_index 64). 8318 * Access: Index 8319 */ 8320 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8321 8322 /* Convert to milli degrees Celsius */ 8323 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8324 ((v_) >= 0) ? ((v_) * 125) : \ 8325 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8326 * 125)); }) 8327 8328 /* reg_mtmp_temperature 8329 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8330 * degrees units. 8331 * Access: RO 8332 */ 8333 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8334 8335 /* reg_mtmp_mte 8336 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8337 * Access: RW 8338 */ 8339 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8340 8341 /* reg_mtmp_mtr 8342 * Max Temperature Reset - clears the value of the max temperature register. 8343 * Access: WO 8344 */ 8345 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8346 8347 /* reg_mtmp_max_temperature 8348 * The highest measured temperature from the sensor. 8349 * When the bit mte is cleared, the field max_temperature is reserved. 8350 * Access: RO 8351 */ 8352 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8353 8354 /* reg_mtmp_tee 8355 * Temperature Event Enable. 8356 * 0 - Do not generate event 8357 * 1 - Generate event 8358 * 2 - Generate single event 8359 * Access: RW 8360 */ 8361 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8362 8363 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8364 8365 /* reg_mtmp_temperature_threshold_hi 8366 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8367 * Access: RW 8368 */ 8369 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8370 8371 /* reg_mtmp_temperature_threshold_lo 8372 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8373 * Access: RW 8374 */ 8375 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8376 8377 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8378 8379 /* reg_mtmp_sensor_name 8380 * Sensor Name 8381 * Access: RO 8382 */ 8383 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8384 8385 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8386 bool max_temp_enable, 8387 bool max_temp_reset) 8388 { 8389 MLXSW_REG_ZERO(mtmp, payload); 8390 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8391 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8392 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8393 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8394 MLXSW_REG_MTMP_THRESH_HI); 8395 } 8396 8397 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8398 int *p_max_temp, char *sensor_name) 8399 { 8400 s16 temp; 8401 8402 if (p_temp) { 8403 temp = mlxsw_reg_mtmp_temperature_get(payload); 8404 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8405 } 8406 if (p_max_temp) { 8407 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8408 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8409 } 8410 if (sensor_name) 8411 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8412 } 8413 8414 /* MTBR - Management Temperature Bulk Register 8415 * ------------------------------------------- 8416 * This register is used for bulk temperature reading. 8417 */ 8418 #define MLXSW_REG_MTBR_ID 0x900F 8419 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8420 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8421 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8422 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8423 MLXSW_REG_MTBR_REC_LEN * \ 8424 MLXSW_REG_MTBR_REC_MAX_COUNT) 8425 8426 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8427 8428 /* reg_mtbr_base_sensor_index 8429 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8430 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8431 * Access: Index 8432 */ 8433 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8434 8435 /* reg_mtbr_num_rec 8436 * Request: Number of records to read 8437 * Response: Number of records read 8438 * See above description for more details. 8439 * Range 1..255 8440 * Access: RW 8441 */ 8442 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8443 8444 /* reg_mtbr_rec_max_temp 8445 * The highest measured temperature from the sensor. 8446 * When the bit mte is cleared, the field max_temperature is reserved. 8447 * Access: RO 8448 */ 8449 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8450 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8451 8452 /* reg_mtbr_rec_temp 8453 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8454 * degrees units. 8455 * Access: RO 8456 */ 8457 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8458 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8459 8460 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8461 u8 num_rec) 8462 { 8463 MLXSW_REG_ZERO(mtbr, payload); 8464 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8465 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8466 } 8467 8468 /* Error codes from temperatute reading */ 8469 enum mlxsw_reg_mtbr_temp_status { 8470 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8471 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8472 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8473 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8474 }; 8475 8476 /* Base index for reading modules temperature */ 8477 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8478 8479 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8480 u16 *p_temp, u16 *p_max_temp) 8481 { 8482 if (p_temp) 8483 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8484 if (p_max_temp) 8485 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8486 } 8487 8488 /* MCIA - Management Cable Info Access 8489 * ----------------------------------- 8490 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8491 */ 8492 8493 #define MLXSW_REG_MCIA_ID 0x9014 8494 #define MLXSW_REG_MCIA_LEN 0x40 8495 8496 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8497 8498 /* reg_mcia_l 8499 * Lock bit. Setting this bit will lock the access to the specific 8500 * cable. Used for updating a full page in a cable EPROM. Any access 8501 * other then subsequence writes will fail while the port is locked. 8502 * Access: RW 8503 */ 8504 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8505 8506 /* reg_mcia_module 8507 * Module number. 8508 * Access: Index 8509 */ 8510 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8511 8512 /* reg_mcia_status 8513 * Module status. 8514 * Access: RO 8515 */ 8516 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8517 8518 /* reg_mcia_i2c_device_address 8519 * I2C device address. 8520 * Access: RW 8521 */ 8522 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8523 8524 /* reg_mcia_page_number 8525 * Page number. 8526 * Access: RW 8527 */ 8528 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8529 8530 /* reg_mcia_device_address 8531 * Device address. 8532 * Access: RW 8533 */ 8534 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8535 8536 /* reg_mcia_size 8537 * Number of bytes to read/write (up to 48 bytes). 8538 * Access: RW 8539 */ 8540 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8541 8542 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8543 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8544 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8545 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8546 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8547 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8548 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8549 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8550 #define MLXSW_REG_MCIA_PAGE0_LO 0 8551 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8552 8553 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8554 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8555 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8556 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8557 }; 8558 8559 enum mlxsw_reg_mcia_eeprom_module_info_id { 8560 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8561 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8562 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8563 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8564 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8565 }; 8566 8567 enum mlxsw_reg_mcia_eeprom_module_info { 8568 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8569 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8570 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8571 }; 8572 8573 /* reg_mcia_eeprom 8574 * Bytes to read/write. 8575 * Access: RW 8576 */ 8577 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8578 8579 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8580 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8581 * on offset 384 through 511, page 3 - on offset 512 through 639. 8582 */ 8583 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8584 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8585 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8586 8587 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8588 u8 page_number, u16 device_addr, 8589 u8 size, u8 i2c_device_addr) 8590 { 8591 MLXSW_REG_ZERO(mcia, payload); 8592 mlxsw_reg_mcia_module_set(payload, module); 8593 mlxsw_reg_mcia_l_set(payload, lock); 8594 mlxsw_reg_mcia_page_number_set(payload, page_number); 8595 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8596 mlxsw_reg_mcia_size_set(payload, size); 8597 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8598 } 8599 8600 /* MPAT - Monitoring Port Analyzer Table 8601 * ------------------------------------- 8602 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8603 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8604 */ 8605 #define MLXSW_REG_MPAT_ID 0x901A 8606 #define MLXSW_REG_MPAT_LEN 0x78 8607 8608 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8609 8610 /* reg_mpat_pa_id 8611 * Port Analyzer ID. 8612 * Access: Index 8613 */ 8614 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8615 8616 /* reg_mpat_system_port 8617 * A unique port identifier for the final destination of the packet. 8618 * Access: RW 8619 */ 8620 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8621 8622 /* reg_mpat_e 8623 * Enable. Indicating the Port Analyzer is enabled. 8624 * Access: RW 8625 */ 8626 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8627 8628 /* reg_mpat_qos 8629 * Quality Of Service Mode. 8630 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8631 * PCP, DEI, DSCP or VL) are configured. 8632 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8633 * same as in the original packet that has triggered the mirroring. For 8634 * SPAN also the pcp,dei are maintained. 8635 * Access: RW 8636 */ 8637 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8638 8639 /* reg_mpat_be 8640 * Best effort mode. Indicates mirroring traffic should not cause packet 8641 * drop or back pressure, but will discard the mirrored packets. Mirrored 8642 * packets will be forwarded on a best effort manner. 8643 * 0: Do not discard mirrored packets 8644 * 1: Discard mirrored packets if causing congestion 8645 * Access: RW 8646 */ 8647 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8648 8649 enum mlxsw_reg_mpat_span_type { 8650 /* Local SPAN Ethernet. 8651 * The original packet is not encapsulated. 8652 */ 8653 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8654 8655 /* Remote SPAN Ethernet VLAN. 8656 * The packet is forwarded to the monitoring port on the monitoring 8657 * VLAN. 8658 */ 8659 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8660 8661 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8662 * The packet is encapsulated with GRE header. 8663 */ 8664 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8665 }; 8666 8667 /* reg_mpat_span_type 8668 * SPAN type. 8669 * Access: RW 8670 */ 8671 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8672 8673 /* Remote SPAN - Ethernet VLAN 8674 * - - - - - - - - - - - - - - 8675 */ 8676 8677 /* reg_mpat_eth_rspan_vid 8678 * Encapsulation header VLAN ID. 8679 * Access: RW 8680 */ 8681 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8682 8683 /* Encapsulated Remote SPAN - Ethernet L2 8684 * - - - - - - - - - - - - - - - - - - - 8685 */ 8686 8687 enum mlxsw_reg_mpat_eth_rspan_version { 8688 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8689 }; 8690 8691 /* reg_mpat_eth_rspan_version 8692 * RSPAN mirror header version. 8693 * Access: RW 8694 */ 8695 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8696 8697 /* reg_mpat_eth_rspan_mac 8698 * Destination MAC address. 8699 * Access: RW 8700 */ 8701 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8702 8703 /* reg_mpat_eth_rspan_tp 8704 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8705 * Access: RW 8706 */ 8707 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8708 8709 /* Encapsulated Remote SPAN - Ethernet L3 8710 * - - - - - - - - - - - - - - - - - - - 8711 */ 8712 8713 enum mlxsw_reg_mpat_eth_rspan_protocol { 8714 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8715 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8716 }; 8717 8718 /* reg_mpat_eth_rspan_protocol 8719 * SPAN encapsulation protocol. 8720 * Access: RW 8721 */ 8722 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8723 8724 /* reg_mpat_eth_rspan_ttl 8725 * Encapsulation header Time-to-Live/HopLimit. 8726 * Access: RW 8727 */ 8728 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8729 8730 /* reg_mpat_eth_rspan_smac 8731 * Source MAC address 8732 * Access: RW 8733 */ 8734 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8735 8736 /* reg_mpat_eth_rspan_dip* 8737 * Destination IP address. The IP version is configured by protocol. 8738 * Access: RW 8739 */ 8740 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8741 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8742 8743 /* reg_mpat_eth_rspan_sip* 8744 * Source IP address. The IP version is configured by protocol. 8745 * Access: RW 8746 */ 8747 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8748 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8749 8750 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8751 u16 system_port, bool e, 8752 enum mlxsw_reg_mpat_span_type span_type) 8753 { 8754 MLXSW_REG_ZERO(mpat, payload); 8755 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8756 mlxsw_reg_mpat_system_port_set(payload, system_port); 8757 mlxsw_reg_mpat_e_set(payload, e); 8758 mlxsw_reg_mpat_qos_set(payload, 1); 8759 mlxsw_reg_mpat_be_set(payload, 1); 8760 mlxsw_reg_mpat_span_type_set(payload, span_type); 8761 } 8762 8763 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8764 { 8765 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8766 } 8767 8768 static inline void 8769 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8770 enum mlxsw_reg_mpat_eth_rspan_version version, 8771 const char *mac, 8772 bool tp) 8773 { 8774 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8775 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8776 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8777 } 8778 8779 static inline void 8780 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8781 const char *smac, 8782 u32 sip, u32 dip) 8783 { 8784 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8785 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8786 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8787 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8788 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8789 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8790 } 8791 8792 static inline void 8793 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8794 const char *smac, 8795 struct in6_addr sip, struct in6_addr dip) 8796 { 8797 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8798 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8799 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8800 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8801 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8802 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8803 } 8804 8805 /* MPAR - Monitoring Port Analyzer Register 8806 * ---------------------------------------- 8807 * MPAR register is used to query and configure the port analyzer port mirroring 8808 * properties. 8809 */ 8810 #define MLXSW_REG_MPAR_ID 0x901B 8811 #define MLXSW_REG_MPAR_LEN 0x0C 8812 8813 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8814 8815 /* reg_mpar_local_port 8816 * The local port to mirror the packets from. 8817 * Access: Index 8818 */ 8819 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8820 8821 enum mlxsw_reg_mpar_i_e { 8822 MLXSW_REG_MPAR_TYPE_EGRESS, 8823 MLXSW_REG_MPAR_TYPE_INGRESS, 8824 }; 8825 8826 /* reg_mpar_i_e 8827 * Ingress/Egress 8828 * Access: Index 8829 */ 8830 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8831 8832 /* reg_mpar_enable 8833 * Enable mirroring 8834 * By default, port mirroring is disabled for all ports. 8835 * Access: RW 8836 */ 8837 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8838 8839 /* reg_mpar_pa_id 8840 * Port Analyzer ID. 8841 * Access: RW 8842 */ 8843 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8844 8845 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8846 enum mlxsw_reg_mpar_i_e i_e, 8847 bool enable, u8 pa_id) 8848 { 8849 MLXSW_REG_ZERO(mpar, payload); 8850 mlxsw_reg_mpar_local_port_set(payload, local_port); 8851 mlxsw_reg_mpar_enable_set(payload, enable); 8852 mlxsw_reg_mpar_i_e_set(payload, i_e); 8853 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8854 } 8855 8856 /* MGIR - Management General Information Register 8857 * ---------------------------------------------- 8858 * MGIR register allows software to query the hardware and firmware general 8859 * information. 8860 */ 8861 #define MLXSW_REG_MGIR_ID 0x9020 8862 #define MLXSW_REG_MGIR_LEN 0x9C 8863 8864 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 8865 8866 /* reg_mgir_hw_info_device_hw_revision 8867 * Access: RO 8868 */ 8869 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 8870 8871 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 8872 8873 /* reg_mgir_fw_info_psid 8874 * PSID (ASCII string). 8875 * Access: RO 8876 */ 8877 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 8878 8879 /* reg_mgir_fw_info_extended_major 8880 * Access: RO 8881 */ 8882 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 8883 8884 /* reg_mgir_fw_info_extended_minor 8885 * Access: RO 8886 */ 8887 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 8888 8889 /* reg_mgir_fw_info_extended_sub_minor 8890 * Access: RO 8891 */ 8892 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 8893 8894 static inline void mlxsw_reg_mgir_pack(char *payload) 8895 { 8896 MLXSW_REG_ZERO(mgir, payload); 8897 } 8898 8899 static inline void 8900 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 8901 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 8902 { 8903 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 8904 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 8905 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 8906 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 8907 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 8908 } 8909 8910 /* MRSR - Management Reset and Shutdown Register 8911 * --------------------------------------------- 8912 * MRSR register is used to reset or shutdown the switch or 8913 * the entire system (when applicable). 8914 */ 8915 #define MLXSW_REG_MRSR_ID 0x9023 8916 #define MLXSW_REG_MRSR_LEN 0x08 8917 8918 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8919 8920 /* reg_mrsr_command 8921 * Reset/shutdown command 8922 * 0 - do nothing 8923 * 1 - software reset 8924 * Access: WO 8925 */ 8926 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8927 8928 static inline void mlxsw_reg_mrsr_pack(char *payload) 8929 { 8930 MLXSW_REG_ZERO(mrsr, payload); 8931 mlxsw_reg_mrsr_command_set(payload, 1); 8932 } 8933 8934 /* MLCR - Management LED Control Register 8935 * -------------------------------------- 8936 * Controls the system LEDs. 8937 */ 8938 #define MLXSW_REG_MLCR_ID 0x902B 8939 #define MLXSW_REG_MLCR_LEN 0x0C 8940 8941 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8942 8943 /* reg_mlcr_local_port 8944 * Local port number. 8945 * Access: RW 8946 */ 8947 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8948 8949 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8950 8951 /* reg_mlcr_beacon_duration 8952 * Duration of the beacon to be active, in seconds. 8953 * 0x0 - Will turn off the beacon. 8954 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8955 * Access: RW 8956 */ 8957 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8958 8959 /* reg_mlcr_beacon_remain 8960 * Remaining duration of the beacon, in seconds. 8961 * 0xFFFF indicates an infinite amount of time. 8962 * Access: RO 8963 */ 8964 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8965 8966 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8967 bool active) 8968 { 8969 MLXSW_REG_ZERO(mlcr, payload); 8970 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8971 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8972 MLXSW_REG_MLCR_DURATION_MAX : 0); 8973 } 8974 8975 /* MTPPS - Management Pulse Per Second Register 8976 * -------------------------------------------- 8977 * This register provides the device PPS capabilities, configure the PPS in and 8978 * out modules and holds the PPS in time stamp. 8979 */ 8980 #define MLXSW_REG_MTPPS_ID 0x9053 8981 #define MLXSW_REG_MTPPS_LEN 0x3C 8982 8983 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 8984 8985 /* reg_mtpps_enable 8986 * Enables the PPS functionality the specific pin. 8987 * A boolean variable. 8988 * Access: RW 8989 */ 8990 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 8991 8992 enum mlxsw_reg_mtpps_pin_mode { 8993 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 8994 }; 8995 8996 /* reg_mtpps_pin_mode 8997 * Pin mode to be used. The mode must comply with the supported modes of the 8998 * requested pin. 8999 * Access: RW 9000 */ 9001 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9002 9003 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9004 9005 /* reg_mtpps_pin 9006 * Pin to be configured or queried out of the supported pins. 9007 * Access: Index 9008 */ 9009 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9010 9011 /* reg_mtpps_time_stamp 9012 * When pin_mode = pps_in, the latched device time when it was triggered from 9013 * the external GPIO pin. 9014 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9015 * time to generate next output signal. 9016 * Time is in units of device clock. 9017 * Access: RW 9018 */ 9019 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9020 9021 static inline void 9022 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9023 { 9024 MLXSW_REG_ZERO(mtpps, payload); 9025 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9026 mlxsw_reg_mtpps_pin_mode_set(payload, 9027 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9028 mlxsw_reg_mtpps_enable_set(payload, true); 9029 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9030 } 9031 9032 /* MTUTC - Management UTC Register 9033 * ------------------------------- 9034 * Configures the HW UTC counter. 9035 */ 9036 #define MLXSW_REG_MTUTC_ID 0x9055 9037 #define MLXSW_REG_MTUTC_LEN 0x1C 9038 9039 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9040 9041 enum mlxsw_reg_mtutc_operation { 9042 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9043 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9044 }; 9045 9046 /* reg_mtutc_operation 9047 * Operation. 9048 * Access: OP 9049 */ 9050 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9051 9052 /* reg_mtutc_freq_adjustment 9053 * Frequency adjustment: Every PPS the HW frequency will be 9054 * adjusted by this value. Units of HW clock, where HW counts 9055 * 10^9 HW clocks for 1 HW second. 9056 * Access: RW 9057 */ 9058 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9059 9060 /* reg_mtutc_utc_sec 9061 * UTC seconds. 9062 * Access: WO 9063 */ 9064 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9065 9066 static inline void 9067 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9068 u32 freq_adj, u32 utc_sec) 9069 { 9070 MLXSW_REG_ZERO(mtutc, payload); 9071 mlxsw_reg_mtutc_operation_set(payload, oper); 9072 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9073 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9074 } 9075 9076 /* MCQI - Management Component Query Information 9077 * --------------------------------------------- 9078 * This register allows querying information about firmware components. 9079 */ 9080 #define MLXSW_REG_MCQI_ID 0x9061 9081 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9082 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9083 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9084 9085 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9086 9087 /* reg_mcqi_component_index 9088 * Index of the accessed component. 9089 * Access: Index 9090 */ 9091 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9092 9093 enum mlxfw_reg_mcqi_info_type { 9094 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9095 }; 9096 9097 /* reg_mcqi_info_type 9098 * Component properties set. 9099 * Access: RW 9100 */ 9101 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9102 9103 /* reg_mcqi_offset 9104 * The requested/returned data offset from the section start, given in bytes. 9105 * Must be DWORD aligned. 9106 * Access: RW 9107 */ 9108 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9109 9110 /* reg_mcqi_data_size 9111 * The requested/returned data size, given in bytes. If data_size is not DWORD 9112 * aligned, the last bytes are zero padded. 9113 * Access: RW 9114 */ 9115 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9116 9117 /* reg_mcqi_cap_max_component_size 9118 * Maximum size for this component, given in bytes. 9119 * Access: RO 9120 */ 9121 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9122 9123 /* reg_mcqi_cap_log_mcda_word_size 9124 * Log 2 of the access word size in bytes. Read and write access must be aligned 9125 * to the word size. Write access must be done for an integer number of words. 9126 * Access: RO 9127 */ 9128 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9129 9130 /* reg_mcqi_cap_mcda_max_write_size 9131 * Maximal write size for MCDA register 9132 * Access: RO 9133 */ 9134 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9135 9136 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9137 { 9138 MLXSW_REG_ZERO(mcqi, payload); 9139 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9140 mlxsw_reg_mcqi_info_type_set(payload, 9141 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9142 mlxsw_reg_mcqi_offset_set(payload, 0); 9143 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9144 } 9145 9146 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9147 u32 *p_cap_max_component_size, 9148 u8 *p_cap_log_mcda_word_size, 9149 u16 *p_cap_mcda_max_write_size) 9150 { 9151 *p_cap_max_component_size = 9152 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9153 *p_cap_log_mcda_word_size = 9154 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9155 *p_cap_mcda_max_write_size = 9156 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9157 } 9158 9159 /* MCC - Management Component Control 9160 * ---------------------------------- 9161 * Controls the firmware component and updates the FSM. 9162 */ 9163 #define MLXSW_REG_MCC_ID 0x9062 9164 #define MLXSW_REG_MCC_LEN 0x1C 9165 9166 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9167 9168 enum mlxsw_reg_mcc_instruction { 9169 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9170 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9171 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9172 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9173 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9174 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9175 }; 9176 9177 /* reg_mcc_instruction 9178 * Command to be executed by the FSM. 9179 * Applicable for write operation only. 9180 * Access: RW 9181 */ 9182 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9183 9184 /* reg_mcc_component_index 9185 * Index of the accessed component. Applicable only for commands that 9186 * refer to components. Otherwise, this field is reserved. 9187 * Access: Index 9188 */ 9189 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9190 9191 /* reg_mcc_update_handle 9192 * Token representing the current flow executed by the FSM. 9193 * Access: WO 9194 */ 9195 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9196 9197 /* reg_mcc_error_code 9198 * Indicates the successful completion of the instruction, or the reason it 9199 * failed 9200 * Access: RO 9201 */ 9202 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9203 9204 /* reg_mcc_control_state 9205 * Current FSM state 9206 * Access: RO 9207 */ 9208 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9209 9210 /* reg_mcc_component_size 9211 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9212 * the size may shorten the update time. Value 0x0 means that size is 9213 * unspecified. 9214 * Access: WO 9215 */ 9216 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9217 9218 static inline void mlxsw_reg_mcc_pack(char *payload, 9219 enum mlxsw_reg_mcc_instruction instr, 9220 u16 component_index, u32 update_handle, 9221 u32 component_size) 9222 { 9223 MLXSW_REG_ZERO(mcc, payload); 9224 mlxsw_reg_mcc_instruction_set(payload, instr); 9225 mlxsw_reg_mcc_component_index_set(payload, component_index); 9226 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9227 mlxsw_reg_mcc_component_size_set(payload, component_size); 9228 } 9229 9230 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9231 u8 *p_error_code, u8 *p_control_state) 9232 { 9233 if (p_update_handle) 9234 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9235 if (p_error_code) 9236 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9237 if (p_control_state) 9238 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9239 } 9240 9241 /* MCDA - Management Component Data Access 9242 * --------------------------------------- 9243 * This register allows reading and writing a firmware component. 9244 */ 9245 #define MLXSW_REG_MCDA_ID 0x9063 9246 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9247 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9248 #define MLXSW_REG_MCDA_LEN \ 9249 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9250 9251 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9252 9253 /* reg_mcda_update_handle 9254 * Token representing the current flow executed by the FSM. 9255 * Access: RW 9256 */ 9257 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9258 9259 /* reg_mcda_offset 9260 * Offset of accessed address relative to component start. Accesses must be in 9261 * accordance to log_mcda_word_size in MCQI reg. 9262 * Access: RW 9263 */ 9264 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9265 9266 /* reg_mcda_size 9267 * Size of the data accessed, given in bytes. 9268 * Access: RW 9269 */ 9270 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9271 9272 /* reg_mcda_data 9273 * Data block accessed. 9274 * Access: RW 9275 */ 9276 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9277 9278 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9279 u32 offset, u16 size, u8 *data) 9280 { 9281 int i; 9282 9283 MLXSW_REG_ZERO(mcda, payload); 9284 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9285 mlxsw_reg_mcda_offset_set(payload, offset); 9286 mlxsw_reg_mcda_size_set(payload, size); 9287 9288 for (i = 0; i < size / 4; i++) 9289 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9290 } 9291 9292 /* MPSC - Monitoring Packet Sampling Configuration Register 9293 * -------------------------------------------------------- 9294 * MPSC Register is used to configure the Packet Sampling mechanism. 9295 */ 9296 #define MLXSW_REG_MPSC_ID 0x9080 9297 #define MLXSW_REG_MPSC_LEN 0x1C 9298 9299 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9300 9301 /* reg_mpsc_local_port 9302 * Local port number 9303 * Not supported for CPU port 9304 * Access: Index 9305 */ 9306 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9307 9308 /* reg_mpsc_e 9309 * Enable sampling on port local_port 9310 * Access: RW 9311 */ 9312 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9313 9314 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9315 9316 /* reg_mpsc_rate 9317 * Sampling rate = 1 out of rate packets (with randomization around 9318 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9319 * Access: RW 9320 */ 9321 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9322 9323 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9324 u32 rate) 9325 { 9326 MLXSW_REG_ZERO(mpsc, payload); 9327 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9328 mlxsw_reg_mpsc_e_set(payload, e); 9329 mlxsw_reg_mpsc_rate_set(payload, rate); 9330 } 9331 9332 /* MGPC - Monitoring General Purpose Counter Set Register 9333 * The MGPC register retrieves and sets the General Purpose Counter Set. 9334 */ 9335 #define MLXSW_REG_MGPC_ID 0x9081 9336 #define MLXSW_REG_MGPC_LEN 0x18 9337 9338 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9339 9340 /* reg_mgpc_counter_set_type 9341 * Counter set type. 9342 * Access: OP 9343 */ 9344 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9345 9346 /* reg_mgpc_counter_index 9347 * Counter index. 9348 * Access: Index 9349 */ 9350 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9351 9352 enum mlxsw_reg_mgpc_opcode { 9353 /* Nop */ 9354 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9355 /* Clear counters */ 9356 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9357 }; 9358 9359 /* reg_mgpc_opcode 9360 * Opcode. 9361 * Access: OP 9362 */ 9363 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9364 9365 /* reg_mgpc_byte_counter 9366 * Byte counter value. 9367 * Access: RW 9368 */ 9369 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9370 9371 /* reg_mgpc_packet_counter 9372 * Packet counter value. 9373 * Access: RW 9374 */ 9375 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9376 9377 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9378 enum mlxsw_reg_mgpc_opcode opcode, 9379 enum mlxsw_reg_flow_counter_set_type set_type) 9380 { 9381 MLXSW_REG_ZERO(mgpc, payload); 9382 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9383 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9384 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9385 } 9386 9387 /* MPRS - Monitoring Parsing State Register 9388 * ---------------------------------------- 9389 * The MPRS register is used for setting up the parsing for hash, 9390 * policy-engine and routing. 9391 */ 9392 #define MLXSW_REG_MPRS_ID 0x9083 9393 #define MLXSW_REG_MPRS_LEN 0x14 9394 9395 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9396 9397 /* reg_mprs_parsing_depth 9398 * Minimum parsing depth. 9399 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9400 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9401 * Access: RW 9402 */ 9403 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9404 9405 /* reg_mprs_parsing_en 9406 * Parsing enable. 9407 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9408 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9409 * Access: RW 9410 */ 9411 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9412 9413 /* reg_mprs_vxlan_udp_dport 9414 * VxLAN UDP destination port. 9415 * Used for identifying VxLAN packets and for dport field in 9416 * encapsulation. Default is 4789. 9417 * Access: RW 9418 */ 9419 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9420 9421 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9422 u16 vxlan_udp_dport) 9423 { 9424 MLXSW_REG_ZERO(mprs, payload); 9425 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9426 mlxsw_reg_mprs_parsing_en_set(payload, true); 9427 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9428 } 9429 9430 /* MOGCR - Monitoring Global Configuration Register 9431 * ------------------------------------------------ 9432 */ 9433 #define MLXSW_REG_MOGCR_ID 0x9086 9434 #define MLXSW_REG_MOGCR_LEN 0x20 9435 9436 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9437 9438 /* reg_mogcr_ptp_iftc 9439 * PTP Ingress FIFO Trap Clear 9440 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9441 * to this value. Default 0. 9442 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9443 * Access: RW 9444 */ 9445 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9446 9447 /* reg_mogcr_ptp_eftc 9448 * PTP Egress FIFO Trap Clear 9449 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9450 * to this value. Default 0. 9451 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9452 * Access: RW 9453 */ 9454 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9455 9456 /* MTPPPC - Time Precision Packet Port Configuration 9457 * ------------------------------------------------- 9458 * This register serves for configuration of which PTP messages should be 9459 * timestamped. This is a global configuration, despite the register name. 9460 * 9461 * Reserved when Spectrum-2. 9462 */ 9463 #define MLXSW_REG_MTPPPC_ID 0x9090 9464 #define MLXSW_REG_MTPPPC_LEN 0x28 9465 9466 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9467 9468 /* reg_mtpppc_ing_timestamp_message_type 9469 * Bitwise vector of PTP message types to timestamp at ingress. 9470 * MessageType field as defined by IEEE 1588 9471 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9472 * Default all 0 9473 * Access: RW 9474 */ 9475 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9476 9477 /* reg_mtpppc_egr_timestamp_message_type 9478 * Bitwise vector of PTP message types to timestamp at egress. 9479 * MessageType field as defined by IEEE 1588 9480 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9481 * Default all 0 9482 * Access: RW 9483 */ 9484 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9485 9486 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9487 { 9488 MLXSW_REG_ZERO(mtpppc, payload); 9489 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9490 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9491 } 9492 9493 /* MTPPTR - Time Precision Packet Timestamping Reading 9494 * --------------------------------------------------- 9495 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9496 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9497 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9498 * trapped. The sequence number is used to synchronize the timestamp FIFO 9499 * entries and the trapped packets. 9500 * Reserved when Spectrum-2. 9501 */ 9502 9503 #define MLXSW_REG_MTPPTR_ID 0x9091 9504 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9505 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9506 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9507 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9508 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9509 9510 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9511 9512 /* reg_mtpptr_local_port 9513 * Not supported for CPU port. 9514 * Access: Index 9515 */ 9516 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9517 9518 enum mlxsw_reg_mtpptr_dir { 9519 MLXSW_REG_MTPPTR_DIR_INGRESS, 9520 MLXSW_REG_MTPPTR_DIR_EGRESS, 9521 }; 9522 9523 /* reg_mtpptr_dir 9524 * Direction. 9525 * Access: Index 9526 */ 9527 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9528 9529 /* reg_mtpptr_clr 9530 * Clear the records. 9531 * Access: OP 9532 */ 9533 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9534 9535 /* reg_mtpptr_num_rec 9536 * Number of valid records in the response 9537 * Range 0.. cap_ptp_timestamp_fifo 9538 * Access: RO 9539 */ 9540 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9541 9542 /* reg_mtpptr_rec_message_type 9543 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9544 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9545 * Access: RO 9546 */ 9547 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9548 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9549 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9550 9551 /* reg_mtpptr_rec_domain_number 9552 * DomainNumber field as defined by IEEE 1588 9553 * Access: RO 9554 */ 9555 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9556 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9557 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9558 9559 /* reg_mtpptr_rec_sequence_id 9560 * SequenceId field as defined by IEEE 1588 9561 * Access: RO 9562 */ 9563 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9564 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9565 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9566 9567 /* reg_mtpptr_rec_timestamp_high 9568 * Timestamp of when the PTP packet has passed through the port Units of PLL 9569 * clock time. 9570 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9571 * Access: RO 9572 */ 9573 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9574 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9575 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9576 9577 /* reg_mtpptr_rec_timestamp_low 9578 * See rec_timestamp_high. 9579 * Access: RO 9580 */ 9581 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9582 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9583 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9584 9585 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9586 unsigned int rec, 9587 u8 *p_message_type, 9588 u8 *p_domain_number, 9589 u16 *p_sequence_id, 9590 u64 *p_timestamp) 9591 { 9592 u32 timestamp_high, timestamp_low; 9593 9594 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9595 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9596 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9597 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9598 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9599 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9600 } 9601 9602 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 9603 * --------------------------------------------------------- 9604 * This register is used for configuring under which trap to deliver PTP 9605 * packets depending on type of the packet. 9606 */ 9607 #define MLXSW_REG_MTPTPT_ID 0x9092 9608 #define MLXSW_REG_MTPTPT_LEN 0x08 9609 9610 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9611 9612 enum mlxsw_reg_mtptpt_trap_id { 9613 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9614 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9615 }; 9616 9617 /* reg_mtptpt_trap_id 9618 * Trap id. 9619 * Access: Index 9620 */ 9621 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9622 9623 /* reg_mtptpt_message_type 9624 * Bitwise vector of PTP message types to trap. This is a necessary but 9625 * non-sufficient condition since need to enable also per port. See MTPPPC. 9626 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9627 * Bit0: Sync, Bit1: Delay_Req) 9628 */ 9629 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9630 9631 static inline void mlxsw_reg_mtptptp_pack(char *payload, 9632 enum mlxsw_reg_mtptpt_trap_id trap_id, 9633 u16 message_type) 9634 { 9635 MLXSW_REG_ZERO(mtptpt, payload); 9636 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9637 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9638 } 9639 9640 /* MGPIR - Management General Peripheral Information Register 9641 * ---------------------------------------------------------- 9642 * MGPIR register allows software to query the hardware and 9643 * firmware general information of peripheral entities. 9644 */ 9645 #define MLXSW_REG_MGPIR_ID 0x9100 9646 #define MLXSW_REG_MGPIR_LEN 0xA0 9647 9648 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9649 9650 enum mlxsw_reg_mgpir_device_type { 9651 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9652 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9653 }; 9654 9655 /* device_type 9656 * Access: RO 9657 */ 9658 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9659 9660 /* devices_per_flash 9661 * Number of devices of device_type per flash (can be shared by few devices). 9662 * Access: RO 9663 */ 9664 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 9665 9666 /* num_of_devices 9667 * Number of devices of device_type. 9668 * Access: RO 9669 */ 9670 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 9671 9672 /* num_of_modules 9673 * Number of modules. 9674 * Access: RO 9675 */ 9676 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 9677 9678 static inline void mlxsw_reg_mgpir_pack(char *payload) 9679 { 9680 MLXSW_REG_ZERO(mgpir, payload); 9681 } 9682 9683 static inline void 9684 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 9685 enum mlxsw_reg_mgpir_device_type *device_type, 9686 u8 *devices_per_flash, u8 *num_of_modules) 9687 { 9688 if (num_of_devices) 9689 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 9690 if (device_type) 9691 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 9692 if (devices_per_flash) 9693 *devices_per_flash = 9694 mlxsw_reg_mgpir_devices_per_flash_get(payload); 9695 if (num_of_modules) 9696 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 9697 } 9698 9699 /* TNGCR - Tunneling NVE General Configuration Register 9700 * ---------------------------------------------------- 9701 * The TNGCR register is used for setting up the NVE Tunneling configuration. 9702 */ 9703 #define MLXSW_REG_TNGCR_ID 0xA001 9704 #define MLXSW_REG_TNGCR_LEN 0x44 9705 9706 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 9707 9708 enum mlxsw_reg_tngcr_type { 9709 MLXSW_REG_TNGCR_TYPE_VXLAN, 9710 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 9711 MLXSW_REG_TNGCR_TYPE_GENEVE, 9712 MLXSW_REG_TNGCR_TYPE_NVGRE, 9713 }; 9714 9715 /* reg_tngcr_type 9716 * Tunnel type for encapsulation and decapsulation. The types are mutually 9717 * exclusive. 9718 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 9719 * Access: RW 9720 */ 9721 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 9722 9723 /* reg_tngcr_nve_valid 9724 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 9725 * Access: RW 9726 */ 9727 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 9728 9729 /* reg_tngcr_nve_ttl_uc 9730 * The TTL for NVE tunnel encapsulation underlay unicast packets. 9731 * Access: RW 9732 */ 9733 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 9734 9735 /* reg_tngcr_nve_ttl_mc 9736 * The TTL for NVE tunnel encapsulation underlay multicast packets. 9737 * Access: RW 9738 */ 9739 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 9740 9741 enum { 9742 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9743 MLXSW_REG_TNGCR_FL_NO_COPY, 9744 /* Copy flow label from inner packet if packet is IPv6 and 9745 * encapsulation is by IPv6. Otherwise, calculate flow label using 9746 * nve_flh. 9747 */ 9748 MLXSW_REG_TNGCR_FL_COPY, 9749 }; 9750 9751 /* reg_tngcr_nve_flc 9752 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9753 * Access: RW 9754 */ 9755 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9756 9757 enum { 9758 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9759 * uses {nve_fl_prefix, nve_fl_suffix}. 9760 */ 9761 MLXSW_REG_TNGCR_FL_NO_HASH, 9762 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9763 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9764 */ 9765 MLXSW_REG_TNGCR_FL_HASH, 9766 }; 9767 9768 /* reg_tngcr_nve_flh 9769 * NVE flow label hash. 9770 * Access: RW 9771 */ 9772 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9773 9774 /* reg_tngcr_nve_fl_prefix 9775 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9776 * Access: RW 9777 */ 9778 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9779 9780 /* reg_tngcr_nve_fl_suffix 9781 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9782 * Reserved when nve_flh=1 and for Spectrum. 9783 * Access: RW 9784 */ 9785 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9786 9787 enum { 9788 /* Source UDP port is fixed (default '0') */ 9789 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9790 /* Source UDP port is calculated based on hash */ 9791 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9792 }; 9793 9794 /* reg_tngcr_nve_udp_sport_type 9795 * NVE UDP source port type. 9796 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9797 * When the source UDP port is calculated based on hash, then the 8 LSBs 9798 * are calculated from hash the 8 MSBs are configured by 9799 * nve_udp_sport_prefix. 9800 * Access: RW 9801 */ 9802 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9803 9804 /* reg_tngcr_nve_udp_sport_prefix 9805 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9806 * Reserved when NVE type is NVGRE. 9807 * Access: RW 9808 */ 9809 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 9810 9811 /* reg_tngcr_nve_group_size_mc 9812 * The amount of sequential linked lists of MC entries. The first linked 9813 * list is configured by SFD.underlay_mc_ptr. 9814 * Valid values: 1, 2, 4, 8, 16, 32, 64 9815 * The linked list are configured by TNUMT. 9816 * The hash is set by LAG hash. 9817 * Access: RW 9818 */ 9819 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9820 9821 /* reg_tngcr_nve_group_size_flood 9822 * The amount of sequential linked lists of flooding entries. The first 9823 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9824 * Valid values: 1, 2, 4, 8, 16, 32, 64 9825 * The linked list are configured by TNUMT. 9826 * The hash is set by LAG hash. 9827 * Access: RW 9828 */ 9829 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9830 9831 /* reg_tngcr_learn_enable 9832 * During decapsulation, whether to learn from NVE port. 9833 * Reserved when Spectrum-2. See TNPC. 9834 * Access: RW 9835 */ 9836 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9837 9838 /* reg_tngcr_underlay_virtual_router 9839 * Underlay virtual router. 9840 * Reserved when Spectrum-2. 9841 * Access: RW 9842 */ 9843 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9844 9845 /* reg_tngcr_underlay_rif 9846 * Underlay ingress router interface. RIF type should be loopback generic. 9847 * Reserved when Spectrum. 9848 * Access: RW 9849 */ 9850 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9851 9852 /* reg_tngcr_usipv4 9853 * Underlay source IPv4 address of the NVE. 9854 * Access: RW 9855 */ 9856 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9857 9858 /* reg_tngcr_usipv6 9859 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9860 * modified under traffic of NVE tunneling encapsulation. 9861 * Access: RW 9862 */ 9863 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9864 9865 static inline void mlxsw_reg_tngcr_pack(char *payload, 9866 enum mlxsw_reg_tngcr_type type, 9867 bool valid, u8 ttl) 9868 { 9869 MLXSW_REG_ZERO(tngcr, payload); 9870 mlxsw_reg_tngcr_type_set(payload, type); 9871 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9872 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9873 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9874 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9875 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9876 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9877 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9878 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9879 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9880 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9881 } 9882 9883 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9884 * ------------------------------------------------------- 9885 * The TNUMT register is for building the underlay MC table. It is used 9886 * for MC, flooding and BC traffic into the NVE tunnel. 9887 */ 9888 #define MLXSW_REG_TNUMT_ID 0xA003 9889 #define MLXSW_REG_TNUMT_LEN 0x20 9890 9891 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9892 9893 enum mlxsw_reg_tnumt_record_type { 9894 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9895 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9896 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9897 }; 9898 9899 /* reg_tnumt_record_type 9900 * Record type. 9901 * Access: RW 9902 */ 9903 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9904 9905 enum mlxsw_reg_tnumt_tunnel_port { 9906 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9907 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9908 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9909 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9910 }; 9911 9912 /* reg_tnumt_tunnel_port 9913 * Tunnel port. 9914 * Access: RW 9915 */ 9916 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9917 9918 /* reg_tnumt_underlay_mc_ptr 9919 * Index to the underlay multicast table. 9920 * For Spectrum the index is to the KVD linear. 9921 * Access: Index 9922 */ 9923 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9924 9925 /* reg_tnumt_vnext 9926 * The next_underlay_mc_ptr is valid. 9927 * Access: RW 9928 */ 9929 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9930 9931 /* reg_tnumt_next_underlay_mc_ptr 9932 * The next index to the underlay multicast table. 9933 * Access: RW 9934 */ 9935 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9936 9937 /* reg_tnumt_record_size 9938 * Number of IP addresses in the record. 9939 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9940 * Access: RW 9941 */ 9942 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9943 9944 /* reg_tnumt_udip 9945 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9946 * Access: RW 9947 */ 9948 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9949 9950 /* reg_tnumt_udip_ptr 9951 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9952 * i >= size. The IPv6 addresses are configured by RIPS. 9953 * Access: RW 9954 */ 9955 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9956 9957 static inline void mlxsw_reg_tnumt_pack(char *payload, 9958 enum mlxsw_reg_tnumt_record_type type, 9959 enum mlxsw_reg_tnumt_tunnel_port tport, 9960 u32 underlay_mc_ptr, bool vnext, 9961 u32 next_underlay_mc_ptr, 9962 u8 record_size) 9963 { 9964 MLXSW_REG_ZERO(tnumt, payload); 9965 mlxsw_reg_tnumt_record_type_set(payload, type); 9966 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9967 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9968 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9969 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9970 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9971 } 9972 9973 /* TNQCR - Tunneling NVE QoS Configuration Register 9974 * ------------------------------------------------ 9975 * The TNQCR register configures how QoS is set in encapsulation into the 9976 * underlay network. 9977 */ 9978 #define MLXSW_REG_TNQCR_ID 0xA010 9979 #define MLXSW_REG_TNQCR_LEN 0x0C 9980 9981 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9982 9983 /* reg_tnqcr_enc_set_dscp 9984 * For encapsulation: How to set DSCP field: 9985 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9986 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9987 * 1 - Set the DSCP field as TNQDR.dscp 9988 * Access: RW 9989 */ 9990 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9991 9992 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9993 { 9994 MLXSW_REG_ZERO(tnqcr, payload); 9995 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9996 } 9997 9998 /* TNQDR - Tunneling NVE QoS Default Register 9999 * ------------------------------------------ 10000 * The TNQDR register configures the default QoS settings for NVE 10001 * encapsulation. 10002 */ 10003 #define MLXSW_REG_TNQDR_ID 0xA011 10004 #define MLXSW_REG_TNQDR_LEN 0x08 10005 10006 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10007 10008 /* reg_tnqdr_local_port 10009 * Local port number (receive port). CPU port is supported. 10010 * Access: Index 10011 */ 10012 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10013 10014 /* reg_tnqdr_dscp 10015 * For encapsulation, the default DSCP. 10016 * Access: RW 10017 */ 10018 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10019 10020 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10021 { 10022 MLXSW_REG_ZERO(tnqdr, payload); 10023 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10024 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10025 } 10026 10027 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10028 * -------------------------------------------------------- 10029 * The TNEEM register maps ECN of the IP header at the ingress to the 10030 * encapsulation to the ECN of the underlay network. 10031 */ 10032 #define MLXSW_REG_TNEEM_ID 0xA012 10033 #define MLXSW_REG_TNEEM_LEN 0x0C 10034 10035 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10036 10037 /* reg_tneem_overlay_ecn 10038 * ECN of the IP header in the overlay network. 10039 * Access: Index 10040 */ 10041 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10042 10043 /* reg_tneem_underlay_ecn 10044 * ECN of the IP header in the underlay network. 10045 * Access: RW 10046 */ 10047 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10048 10049 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10050 u8 underlay_ecn) 10051 { 10052 MLXSW_REG_ZERO(tneem, payload); 10053 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10054 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10055 } 10056 10057 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10058 * -------------------------------------------------------- 10059 * The TNDEM register configures the actions that are done in the 10060 * decapsulation. 10061 */ 10062 #define MLXSW_REG_TNDEM_ID 0xA013 10063 #define MLXSW_REG_TNDEM_LEN 0x0C 10064 10065 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10066 10067 /* reg_tndem_underlay_ecn 10068 * ECN field of the IP header in the underlay network. 10069 * Access: Index 10070 */ 10071 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10072 10073 /* reg_tndem_overlay_ecn 10074 * ECN field of the IP header in the overlay network. 10075 * Access: Index 10076 */ 10077 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10078 10079 /* reg_tndem_eip_ecn 10080 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10081 * from the decapsulation. 10082 * Access: RW 10083 */ 10084 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10085 10086 /* reg_tndem_trap_en 10087 * Trap enable: 10088 * 0 - No trap due to decap ECN 10089 * 1 - Trap enable with trap_id 10090 * Access: RW 10091 */ 10092 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10093 10094 /* reg_tndem_trap_id 10095 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10096 * Reserved when trap_en is '0'. 10097 * Access: RW 10098 */ 10099 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10100 10101 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10102 u8 overlay_ecn, u8 ecn, bool trap_en, 10103 u16 trap_id) 10104 { 10105 MLXSW_REG_ZERO(tndem, payload); 10106 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10107 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10108 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10109 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10110 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10111 } 10112 10113 /* TNPC - Tunnel Port Configuration Register 10114 * ----------------------------------------- 10115 * The TNPC register is used for tunnel port configuration. 10116 * Reserved when Spectrum. 10117 */ 10118 #define MLXSW_REG_TNPC_ID 0xA020 10119 #define MLXSW_REG_TNPC_LEN 0x18 10120 10121 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10122 10123 enum mlxsw_reg_tnpc_tunnel_port { 10124 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10125 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10126 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10127 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10128 }; 10129 10130 /* reg_tnpc_tunnel_port 10131 * Tunnel port. 10132 * Access: Index 10133 */ 10134 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10135 10136 /* reg_tnpc_learn_enable_v6 10137 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10138 * Access: RW 10139 */ 10140 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10141 10142 /* reg_tnpc_learn_enable_v4 10143 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10144 * Access: RW 10145 */ 10146 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10147 10148 static inline void mlxsw_reg_tnpc_pack(char *payload, 10149 enum mlxsw_reg_tnpc_tunnel_port tport, 10150 bool learn_enable) 10151 { 10152 MLXSW_REG_ZERO(tnpc, payload); 10153 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10154 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10155 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10156 } 10157 10158 /* TIGCR - Tunneling IPinIP General Configuration Register 10159 * ------------------------------------------------------- 10160 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10161 */ 10162 #define MLXSW_REG_TIGCR_ID 0xA801 10163 #define MLXSW_REG_TIGCR_LEN 0x10 10164 10165 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10166 10167 /* reg_tigcr_ipip_ttlc 10168 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10169 * header. 10170 * Access: RW 10171 */ 10172 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10173 10174 /* reg_tigcr_ipip_ttl_uc 10175 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10176 * reg_tigcr_ipip_ttlc is unset. 10177 * Access: RW 10178 */ 10179 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10180 10181 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10182 { 10183 MLXSW_REG_ZERO(tigcr, payload); 10184 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10185 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10186 } 10187 10188 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10189 * ----------------------------------------------------------- 10190 * The TIEEM register maps ECN of the IP header at the ingress to the 10191 * encapsulation to the ECN of the underlay network. 10192 */ 10193 #define MLXSW_REG_TIEEM_ID 0xA812 10194 #define MLXSW_REG_TIEEM_LEN 0x0C 10195 10196 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10197 10198 /* reg_tieem_overlay_ecn 10199 * ECN of the IP header in the overlay network. 10200 * Access: Index 10201 */ 10202 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10203 10204 /* reg_tineem_underlay_ecn 10205 * ECN of the IP header in the underlay network. 10206 * Access: RW 10207 */ 10208 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10209 10210 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10211 u8 underlay_ecn) 10212 { 10213 MLXSW_REG_ZERO(tieem, payload); 10214 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10215 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10216 } 10217 10218 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10219 * ----------------------------------------------------------- 10220 * The TIDEM register configures the actions that are done in the 10221 * decapsulation. 10222 */ 10223 #define MLXSW_REG_TIDEM_ID 0xA813 10224 #define MLXSW_REG_TIDEM_LEN 0x0C 10225 10226 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10227 10228 /* reg_tidem_underlay_ecn 10229 * ECN field of the IP header in the underlay network. 10230 * Access: Index 10231 */ 10232 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10233 10234 /* reg_tidem_overlay_ecn 10235 * ECN field of the IP header in the overlay network. 10236 * Access: Index 10237 */ 10238 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10239 10240 /* reg_tidem_eip_ecn 10241 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10242 * from the decapsulation. 10243 * Access: RW 10244 */ 10245 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10246 10247 /* reg_tidem_trap_en 10248 * Trap enable: 10249 * 0 - No trap due to decap ECN 10250 * 1 - Trap enable with trap_id 10251 * Access: RW 10252 */ 10253 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10254 10255 /* reg_tidem_trap_id 10256 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10257 * Reserved when trap_en is '0'. 10258 * Access: RW 10259 */ 10260 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10261 10262 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10263 u8 overlay_ecn, u8 eip_ecn, 10264 bool trap_en, u16 trap_id) 10265 { 10266 MLXSW_REG_ZERO(tidem, payload); 10267 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10268 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10269 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10270 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10271 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10272 } 10273 10274 /* SBPR - Shared Buffer Pools Register 10275 * ----------------------------------- 10276 * The SBPR configures and retrieves the shared buffer pools and configuration. 10277 */ 10278 #define MLXSW_REG_SBPR_ID 0xB001 10279 #define MLXSW_REG_SBPR_LEN 0x14 10280 10281 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10282 10283 /* shared direstion enum for SBPR, SBCM, SBPM */ 10284 enum mlxsw_reg_sbxx_dir { 10285 MLXSW_REG_SBXX_DIR_INGRESS, 10286 MLXSW_REG_SBXX_DIR_EGRESS, 10287 }; 10288 10289 /* reg_sbpr_dir 10290 * Direction. 10291 * Access: Index 10292 */ 10293 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10294 10295 /* reg_sbpr_pool 10296 * Pool index. 10297 * Access: Index 10298 */ 10299 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10300 10301 /* reg_sbpr_infi_size 10302 * Size is infinite. 10303 * Access: RW 10304 */ 10305 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10306 10307 /* reg_sbpr_size 10308 * Pool size in buffer cells. 10309 * Reserved when infi_size = 1. 10310 * Access: RW 10311 */ 10312 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10313 10314 enum mlxsw_reg_sbpr_mode { 10315 MLXSW_REG_SBPR_MODE_STATIC, 10316 MLXSW_REG_SBPR_MODE_DYNAMIC, 10317 }; 10318 10319 /* reg_sbpr_mode 10320 * Pool quota calculation mode. 10321 * Access: RW 10322 */ 10323 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10324 10325 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10326 enum mlxsw_reg_sbxx_dir dir, 10327 enum mlxsw_reg_sbpr_mode mode, u32 size, 10328 bool infi_size) 10329 { 10330 MLXSW_REG_ZERO(sbpr, payload); 10331 mlxsw_reg_sbpr_pool_set(payload, pool); 10332 mlxsw_reg_sbpr_dir_set(payload, dir); 10333 mlxsw_reg_sbpr_mode_set(payload, mode); 10334 mlxsw_reg_sbpr_size_set(payload, size); 10335 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10336 } 10337 10338 /* SBCM - Shared Buffer Class Management Register 10339 * ---------------------------------------------- 10340 * The SBCM register configures and retrieves the shared buffer allocation 10341 * and configuration according to Port-PG, including the binding to pool 10342 * and definition of the associated quota. 10343 */ 10344 #define MLXSW_REG_SBCM_ID 0xB002 10345 #define MLXSW_REG_SBCM_LEN 0x28 10346 10347 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10348 10349 /* reg_sbcm_local_port 10350 * Local port number. 10351 * For Ingress: excludes CPU port and Router port 10352 * For Egress: excludes IP Router 10353 * Access: Index 10354 */ 10355 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10356 10357 /* reg_sbcm_pg_buff 10358 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10359 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10360 * For traffic class: range is 0..cap_max_tclass - 1 10361 * Note that when traffic class is in MC aware mode then the traffic 10362 * classes which are MC aware cannot be configured. 10363 * Access: Index 10364 */ 10365 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10366 10367 /* reg_sbcm_dir 10368 * Direction. 10369 * Access: Index 10370 */ 10371 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10372 10373 /* reg_sbcm_min_buff 10374 * Minimum buffer size for the limiter, in cells. 10375 * Access: RW 10376 */ 10377 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10378 10379 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10380 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10381 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10382 10383 /* reg_sbcm_infi_max 10384 * Max buffer is infinite. 10385 * Access: RW 10386 */ 10387 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10388 10389 /* reg_sbcm_max_buff 10390 * When the pool associated to the port-pg/tclass is configured to 10391 * static, Maximum buffer size for the limiter configured in cells. 10392 * When the pool associated to the port-pg/tclass is configured to 10393 * dynamic, the max_buff holds the "alpha" parameter, supporting 10394 * the following values: 10395 * 0: 0 10396 * i: (1/128)*2^(i-1), for i=1..14 10397 * 0xFF: Infinity 10398 * Reserved when infi_max = 1. 10399 * Access: RW 10400 */ 10401 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10402 10403 /* reg_sbcm_pool 10404 * Association of the port-priority to a pool. 10405 * Access: RW 10406 */ 10407 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10408 10409 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10410 enum mlxsw_reg_sbxx_dir dir, 10411 u32 min_buff, u32 max_buff, 10412 bool infi_max, u8 pool) 10413 { 10414 MLXSW_REG_ZERO(sbcm, payload); 10415 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10416 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10417 mlxsw_reg_sbcm_dir_set(payload, dir); 10418 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10419 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10420 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10421 mlxsw_reg_sbcm_pool_set(payload, pool); 10422 } 10423 10424 /* SBPM - Shared Buffer Port Management Register 10425 * --------------------------------------------- 10426 * The SBPM register configures and retrieves the shared buffer allocation 10427 * and configuration according to Port-Pool, including the definition 10428 * of the associated quota. 10429 */ 10430 #define MLXSW_REG_SBPM_ID 0xB003 10431 #define MLXSW_REG_SBPM_LEN 0x28 10432 10433 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10434 10435 /* reg_sbpm_local_port 10436 * Local port number. 10437 * For Ingress: excludes CPU port and Router port 10438 * For Egress: excludes IP Router 10439 * Access: Index 10440 */ 10441 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10442 10443 /* reg_sbpm_pool 10444 * The pool associated to quota counting on the local_port. 10445 * Access: Index 10446 */ 10447 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10448 10449 /* reg_sbpm_dir 10450 * Direction. 10451 * Access: Index 10452 */ 10453 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10454 10455 /* reg_sbpm_buff_occupancy 10456 * Current buffer occupancy in cells. 10457 * Access: RO 10458 */ 10459 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10460 10461 /* reg_sbpm_clr 10462 * Clear Max Buffer Occupancy 10463 * When this bit is set, max_buff_occupancy field is cleared (and a 10464 * new max value is tracked from the time the clear was performed). 10465 * Access: OP 10466 */ 10467 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10468 10469 /* reg_sbpm_max_buff_occupancy 10470 * Maximum value of buffer occupancy in cells monitored. Cleared by 10471 * writing to the clr field. 10472 * Access: RO 10473 */ 10474 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10475 10476 /* reg_sbpm_min_buff 10477 * Minimum buffer size for the limiter, in cells. 10478 * Access: RW 10479 */ 10480 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10481 10482 /* reg_sbpm_max_buff 10483 * When the pool associated to the port-pg/tclass is configured to 10484 * static, Maximum buffer size for the limiter configured in cells. 10485 * When the pool associated to the port-pg/tclass is configured to 10486 * dynamic, the max_buff holds the "alpha" parameter, supporting 10487 * the following values: 10488 * 0: 0 10489 * i: (1/128)*2^(i-1), for i=1..14 10490 * 0xFF: Infinity 10491 * Access: RW 10492 */ 10493 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10494 10495 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10496 enum mlxsw_reg_sbxx_dir dir, bool clr, 10497 u32 min_buff, u32 max_buff) 10498 { 10499 MLXSW_REG_ZERO(sbpm, payload); 10500 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10501 mlxsw_reg_sbpm_pool_set(payload, pool); 10502 mlxsw_reg_sbpm_dir_set(payload, dir); 10503 mlxsw_reg_sbpm_clr_set(payload, clr); 10504 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10505 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10506 } 10507 10508 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10509 u32 *p_max_buff_occupancy) 10510 { 10511 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10512 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10513 } 10514 10515 /* SBMM - Shared Buffer Multicast Management Register 10516 * -------------------------------------------------- 10517 * The SBMM register configures and retrieves the shared buffer allocation 10518 * and configuration for MC packets according to Switch-Priority, including 10519 * the binding to pool and definition of the associated quota. 10520 */ 10521 #define MLXSW_REG_SBMM_ID 0xB004 10522 #define MLXSW_REG_SBMM_LEN 0x28 10523 10524 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10525 10526 /* reg_sbmm_prio 10527 * Switch Priority. 10528 * Access: Index 10529 */ 10530 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10531 10532 /* reg_sbmm_min_buff 10533 * Minimum buffer size for the limiter, in cells. 10534 * Access: RW 10535 */ 10536 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10537 10538 /* reg_sbmm_max_buff 10539 * When the pool associated to the port-pg/tclass is configured to 10540 * static, Maximum buffer size for the limiter configured in cells. 10541 * When the pool associated to the port-pg/tclass is configured to 10542 * dynamic, the max_buff holds the "alpha" parameter, supporting 10543 * the following values: 10544 * 0: 0 10545 * i: (1/128)*2^(i-1), for i=1..14 10546 * 0xFF: Infinity 10547 * Access: RW 10548 */ 10549 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10550 10551 /* reg_sbmm_pool 10552 * Association of the port-priority to a pool. 10553 * Access: RW 10554 */ 10555 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10556 10557 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10558 u32 max_buff, u8 pool) 10559 { 10560 MLXSW_REG_ZERO(sbmm, payload); 10561 mlxsw_reg_sbmm_prio_set(payload, prio); 10562 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10563 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10564 mlxsw_reg_sbmm_pool_set(payload, pool); 10565 } 10566 10567 /* SBSR - Shared Buffer Status Register 10568 * ------------------------------------ 10569 * The SBSR register retrieves the shared buffer occupancy according to 10570 * Port-Pool. Note that this register enables reading a large amount of data. 10571 * It is the user's responsibility to limit the amount of data to ensure the 10572 * response can match the maximum transfer unit. In case the response exceeds 10573 * the maximum transport unit, it will be truncated with no special notice. 10574 */ 10575 #define MLXSW_REG_SBSR_ID 0xB005 10576 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10577 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10578 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10579 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10580 MLXSW_REG_SBSR_REC_LEN * \ 10581 MLXSW_REG_SBSR_REC_MAX_COUNT) 10582 10583 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10584 10585 /* reg_sbsr_clr 10586 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 10587 * field is cleared (and a new max value is tracked from the time the clear 10588 * was performed). 10589 * Access: OP 10590 */ 10591 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 10592 10593 /* reg_sbsr_ingress_port_mask 10594 * Bit vector for all ingress network ports. 10595 * Indicates which of the ports (for which the relevant bit is set) 10596 * are affected by the set operation. Configuration of any other port 10597 * does not change. 10598 * Access: Index 10599 */ 10600 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 10601 10602 /* reg_sbsr_pg_buff_mask 10603 * Bit vector for all switch priority groups. 10604 * Indicates which of the priorities (for which the relevant bit is set) 10605 * are affected by the set operation. Configuration of any other priority 10606 * does not change. 10607 * Range is 0..cap_max_pg_buffers - 1 10608 * Access: Index 10609 */ 10610 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 10611 10612 /* reg_sbsr_egress_port_mask 10613 * Bit vector for all egress network ports. 10614 * Indicates which of the ports (for which the relevant bit is set) 10615 * are affected by the set operation. Configuration of any other port 10616 * does not change. 10617 * Access: Index 10618 */ 10619 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 10620 10621 /* reg_sbsr_tclass_mask 10622 * Bit vector for all traffic classes. 10623 * Indicates which of the traffic classes (for which the relevant bit is 10624 * set) are affected by the set operation. Configuration of any other 10625 * traffic class does not change. 10626 * Range is 0..cap_max_tclass - 1 10627 * Access: Index 10628 */ 10629 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 10630 10631 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 10632 { 10633 MLXSW_REG_ZERO(sbsr, payload); 10634 mlxsw_reg_sbsr_clr_set(payload, clr); 10635 } 10636 10637 /* reg_sbsr_rec_buff_occupancy 10638 * Current buffer occupancy in cells. 10639 * Access: RO 10640 */ 10641 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10642 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 10643 10644 /* reg_sbsr_rec_max_buff_occupancy 10645 * Maximum value of buffer occupancy in cells monitored. Cleared by 10646 * writing to the clr field. 10647 * Access: RO 10648 */ 10649 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10650 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 10651 10652 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 10653 u32 *p_buff_occupancy, 10654 u32 *p_max_buff_occupancy) 10655 { 10656 *p_buff_occupancy = 10657 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 10658 *p_max_buff_occupancy = 10659 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 10660 } 10661 10662 /* SBIB - Shared Buffer Internal Buffer Register 10663 * --------------------------------------------- 10664 * The SBIB register configures per port buffers for internal use. The internal 10665 * buffers consume memory on the port buffers (note that the port buffers are 10666 * used also by PBMC). 10667 * 10668 * For Spectrum this is used for egress mirroring. 10669 */ 10670 #define MLXSW_REG_SBIB_ID 0xB006 10671 #define MLXSW_REG_SBIB_LEN 0x10 10672 10673 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 10674 10675 /* reg_sbib_local_port 10676 * Local port number 10677 * Not supported for CPU port and router port 10678 * Access: Index 10679 */ 10680 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 10681 10682 /* reg_sbib_buff_size 10683 * Units represented in cells 10684 * Allowed range is 0 to (cap_max_headroom_size - 1) 10685 * Default is 0 10686 * Access: RW 10687 */ 10688 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 10689 10690 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 10691 u32 buff_size) 10692 { 10693 MLXSW_REG_ZERO(sbib, payload); 10694 mlxsw_reg_sbib_local_port_set(payload, local_port); 10695 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 10696 } 10697 10698 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 10699 MLXSW_REG(sgcr), 10700 MLXSW_REG(spad), 10701 MLXSW_REG(smid), 10702 MLXSW_REG(sspr), 10703 MLXSW_REG(sfdat), 10704 MLXSW_REG(sfd), 10705 MLXSW_REG(sfn), 10706 MLXSW_REG(spms), 10707 MLXSW_REG(spvid), 10708 MLXSW_REG(spvm), 10709 MLXSW_REG(spaft), 10710 MLXSW_REG(sfgc), 10711 MLXSW_REG(sftr), 10712 MLXSW_REG(sfdf), 10713 MLXSW_REG(sldr), 10714 MLXSW_REG(slcr), 10715 MLXSW_REG(slcor), 10716 MLXSW_REG(spmlr), 10717 MLXSW_REG(svfa), 10718 MLXSW_REG(svpe), 10719 MLXSW_REG(sfmr), 10720 MLXSW_REG(spvmlr), 10721 MLXSW_REG(cwtp), 10722 MLXSW_REG(cwtpm), 10723 MLXSW_REG(pgcr), 10724 MLXSW_REG(ppbt), 10725 MLXSW_REG(pacl), 10726 MLXSW_REG(pagt), 10727 MLXSW_REG(ptar), 10728 MLXSW_REG(ppbs), 10729 MLXSW_REG(prcr), 10730 MLXSW_REG(pefa), 10731 MLXSW_REG(pemrbt), 10732 MLXSW_REG(ptce2), 10733 MLXSW_REG(perpt), 10734 MLXSW_REG(peabfe), 10735 MLXSW_REG(perar), 10736 MLXSW_REG(ptce3), 10737 MLXSW_REG(percr), 10738 MLXSW_REG(pererp), 10739 MLXSW_REG(iedr), 10740 MLXSW_REG(qpts), 10741 MLXSW_REG(qpcr), 10742 MLXSW_REG(qtct), 10743 MLXSW_REG(qeec), 10744 MLXSW_REG(qrwe), 10745 MLXSW_REG(qpdsm), 10746 MLXSW_REG(qpdp), 10747 MLXSW_REG(qpdpm), 10748 MLXSW_REG(qtctm), 10749 MLXSW_REG(qpsc), 10750 MLXSW_REG(pmlp), 10751 MLXSW_REG(pmtu), 10752 MLXSW_REG(ptys), 10753 MLXSW_REG(ppad), 10754 MLXSW_REG(paos), 10755 MLXSW_REG(pfcc), 10756 MLXSW_REG(ppcnt), 10757 MLXSW_REG(plib), 10758 MLXSW_REG(pptb), 10759 MLXSW_REG(pbmc), 10760 MLXSW_REG(pspa), 10761 MLXSW_REG(pplr), 10762 MLXSW_REG(pmtm), 10763 MLXSW_REG(htgt), 10764 MLXSW_REG(hpkt), 10765 MLXSW_REG(rgcr), 10766 MLXSW_REG(ritr), 10767 MLXSW_REG(rtar), 10768 MLXSW_REG(ratr), 10769 MLXSW_REG(rtdp), 10770 MLXSW_REG(rdpm), 10771 MLXSW_REG(ricnt), 10772 MLXSW_REG(rrcr), 10773 MLXSW_REG(ralta), 10774 MLXSW_REG(ralst), 10775 MLXSW_REG(raltb), 10776 MLXSW_REG(ralue), 10777 MLXSW_REG(rauht), 10778 MLXSW_REG(raleu), 10779 MLXSW_REG(rauhtd), 10780 MLXSW_REG(rigr2), 10781 MLXSW_REG(recr2), 10782 MLXSW_REG(rmft2), 10783 MLXSW_REG(mfcr), 10784 MLXSW_REG(mfsc), 10785 MLXSW_REG(mfsm), 10786 MLXSW_REG(mfsl), 10787 MLXSW_REG(fore), 10788 MLXSW_REG(mtcap), 10789 MLXSW_REG(mtmp), 10790 MLXSW_REG(mtbr), 10791 MLXSW_REG(mcia), 10792 MLXSW_REG(mpat), 10793 MLXSW_REG(mpar), 10794 MLXSW_REG(mgir), 10795 MLXSW_REG(mrsr), 10796 MLXSW_REG(mlcr), 10797 MLXSW_REG(mtpps), 10798 MLXSW_REG(mtutc), 10799 MLXSW_REG(mpsc), 10800 MLXSW_REG(mcqi), 10801 MLXSW_REG(mcc), 10802 MLXSW_REG(mcda), 10803 MLXSW_REG(mgpc), 10804 MLXSW_REG(mprs), 10805 MLXSW_REG(mogcr), 10806 MLXSW_REG(mtpppc), 10807 MLXSW_REG(mtpptr), 10808 MLXSW_REG(mtptpt), 10809 MLXSW_REG(mgpir), 10810 MLXSW_REG(tngcr), 10811 MLXSW_REG(tnumt), 10812 MLXSW_REG(tnqcr), 10813 MLXSW_REG(tnqdr), 10814 MLXSW_REG(tneem), 10815 MLXSW_REG(tndem), 10816 MLXSW_REG(tnpc), 10817 MLXSW_REG(tigcr), 10818 MLXSW_REG(tieem), 10819 MLXSW_REG(tidem), 10820 MLXSW_REG(sbpr), 10821 MLXSW_REG(sbcm), 10822 MLXSW_REG(sbpm), 10823 MLXSW_REG(sbmm), 10824 MLXSW_REG(sbsr), 10825 MLXSW_REG(sbib), 10826 }; 10827 10828 static inline const char *mlxsw_reg_id_str(u16 reg_id) 10829 { 10830 const struct mlxsw_reg_info *reg_info; 10831 int i; 10832 10833 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 10834 reg_info = mlxsw_reg_infos[i]; 10835 if (reg_info->id == reg_id) 10836 return reg_info->name; 10837 } 10838 return "*UNKNOWN*"; 10839 } 10840 10841 /* PUDE - Port Up / Down Event 10842 * --------------------------- 10843 * Reports the operational state change of a port. 10844 */ 10845 #define MLXSW_REG_PUDE_LEN 0x10 10846 10847 /* reg_pude_swid 10848 * Switch partition ID with which to associate the port. 10849 * Access: Index 10850 */ 10851 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 10852 10853 /* reg_pude_local_port 10854 * Local port number. 10855 * Access: Index 10856 */ 10857 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 10858 10859 /* reg_pude_admin_status 10860 * Port administrative state (the desired state). 10861 * 1 - Up. 10862 * 2 - Down. 10863 * 3 - Up once. This means that in case of link failure, the port won't go 10864 * into polling mode, but will wait to be re-enabled by software. 10865 * 4 - Disabled by system. Can only be set by hardware. 10866 * Access: RO 10867 */ 10868 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 10869 10870 /* reg_pude_oper_status 10871 * Port operatioanl state. 10872 * 1 - Up. 10873 * 2 - Down. 10874 * 3 - Down by port failure. This means that the device will not let the 10875 * port up again until explicitly specified by software. 10876 * Access: RO 10877 */ 10878 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 10879 10880 #endif 10881