1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "dr_types.h" 5 #include "dr_ste.h" 6 7 enum dr_action_domain { 8 DR_ACTION_DOMAIN_NIC_INGRESS, 9 DR_ACTION_DOMAIN_NIC_EGRESS, 10 DR_ACTION_DOMAIN_FDB_INGRESS, 11 DR_ACTION_DOMAIN_FDB_EGRESS, 12 DR_ACTION_DOMAIN_MAX, 13 }; 14 15 enum dr_action_valid_state { 16 DR_ACTION_STATE_ERR, 17 DR_ACTION_STATE_NO_ACTION, 18 DR_ACTION_STATE_ENCAP, 19 DR_ACTION_STATE_DECAP, 20 DR_ACTION_STATE_MODIFY_HDR, 21 DR_ACTION_STATE_POP_VLAN, 22 DR_ACTION_STATE_PUSH_VLAN, 23 DR_ACTION_STATE_NON_TERM, 24 DR_ACTION_STATE_TERM, 25 DR_ACTION_STATE_ASO, 26 DR_ACTION_STATE_MAX, 27 }; 28 29 static const char * const action_type_to_str[] = { 30 [DR_ACTION_TYP_TNL_L2_TO_L2] = "DR_ACTION_TYP_TNL_L2_TO_L2", 31 [DR_ACTION_TYP_L2_TO_TNL_L2] = "DR_ACTION_TYP_L2_TO_TNL_L2", 32 [DR_ACTION_TYP_TNL_L3_TO_L2] = "DR_ACTION_TYP_TNL_L3_TO_L2", 33 [DR_ACTION_TYP_L2_TO_TNL_L3] = "DR_ACTION_TYP_L2_TO_TNL_L3", 34 [DR_ACTION_TYP_DROP] = "DR_ACTION_TYP_DROP", 35 [DR_ACTION_TYP_QP] = "DR_ACTION_TYP_QP", 36 [DR_ACTION_TYP_FT] = "DR_ACTION_TYP_FT", 37 [DR_ACTION_TYP_CTR] = "DR_ACTION_TYP_CTR", 38 [DR_ACTION_TYP_TAG] = "DR_ACTION_TYP_TAG", 39 [DR_ACTION_TYP_MODIFY_HDR] = "DR_ACTION_TYP_MODIFY_HDR", 40 [DR_ACTION_TYP_VPORT] = "DR_ACTION_TYP_VPORT", 41 [DR_ACTION_TYP_POP_VLAN] = "DR_ACTION_TYP_POP_VLAN", 42 [DR_ACTION_TYP_PUSH_VLAN] = "DR_ACTION_TYP_PUSH_VLAN", 43 [DR_ACTION_TYP_SAMPLER] = "DR_ACTION_TYP_SAMPLER", 44 [DR_ACTION_TYP_INSERT_HDR] = "DR_ACTION_TYP_INSERT_HDR", 45 [DR_ACTION_TYP_REMOVE_HDR] = "DR_ACTION_TYP_REMOVE_HDR", 46 [DR_ACTION_TYP_ASO_FLOW_METER] = "DR_ACTION_TYP_ASO_FLOW_METER", 47 [DR_ACTION_TYP_RANGE] = "DR_ACTION_TYP_RANGE", 48 [DR_ACTION_TYP_MAX] = "DR_ACTION_UNKNOWN", 49 }; 50 51 static const char *dr_action_id_to_str(enum mlx5dr_action_type action_id) 52 { 53 if (action_id > DR_ACTION_TYP_MAX) 54 action_id = DR_ACTION_TYP_MAX; 55 return action_type_to_str[action_id]; 56 } 57 58 static bool mlx5dr_action_supp_fwd_fdb_multi_ft(struct mlx5_core_dev *dev) 59 { 60 return (MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_any_table_limit_regc) || 61 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_any_table)); 62 } 63 64 static const enum dr_action_valid_state 65 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = { 66 [DR_ACTION_DOMAIN_NIC_INGRESS] = { 67 [DR_ACTION_STATE_NO_ACTION] = { 68 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 69 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 70 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 71 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 72 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 73 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 74 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 75 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 76 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 77 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 78 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 79 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 80 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 81 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 82 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 83 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 84 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 85 }, 86 [DR_ACTION_STATE_DECAP] = { 87 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 88 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 89 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 90 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 91 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 92 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_DECAP, 93 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 94 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 95 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 96 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 97 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 98 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 99 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 100 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 101 }, 102 [DR_ACTION_STATE_ENCAP] = { 103 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 104 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 105 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 106 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 107 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 108 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_ENCAP, 109 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 110 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 111 }, 112 [DR_ACTION_STATE_MODIFY_HDR] = { 113 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 114 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 115 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 116 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 117 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 118 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_MODIFY_HDR, 119 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 120 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 121 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 122 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 123 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 124 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 125 }, 126 [DR_ACTION_STATE_POP_VLAN] = { 127 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 128 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 129 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 130 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 131 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 132 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_POP_VLAN, 133 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 134 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 135 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 136 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 137 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 138 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 139 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 140 }, 141 [DR_ACTION_STATE_PUSH_VLAN] = { 142 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 143 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 144 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 145 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 146 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_PUSH_VLAN, 147 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 148 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 149 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 150 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 151 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 152 }, 153 [DR_ACTION_STATE_NON_TERM] = { 154 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 155 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 156 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 157 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 158 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 159 [DR_ACTION_TYP_TAG] = DR_ACTION_STATE_NON_TERM, 160 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 161 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 162 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 163 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 164 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 165 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 166 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 167 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 168 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 169 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 170 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 171 }, 172 [DR_ACTION_STATE_ASO] = { 173 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 174 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 175 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 176 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 177 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 178 }, 179 [DR_ACTION_STATE_TERM] = { 180 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 181 }, 182 }, 183 [DR_ACTION_DOMAIN_NIC_EGRESS] = { 184 [DR_ACTION_STATE_NO_ACTION] = { 185 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 186 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 187 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 188 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 189 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 190 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 191 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 192 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 193 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 194 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 195 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 196 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 197 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 198 }, 199 [DR_ACTION_STATE_DECAP] = { 200 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 201 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 202 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 203 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 204 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 205 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 206 }, 207 [DR_ACTION_STATE_ENCAP] = { 208 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 209 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 210 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 211 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 212 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 213 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 214 }, 215 [DR_ACTION_STATE_MODIFY_HDR] = { 216 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 217 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 218 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 219 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 220 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 221 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 222 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 223 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 224 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 225 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 226 }, 227 [DR_ACTION_STATE_POP_VLAN] = { 228 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 229 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 230 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 231 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 232 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 233 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 234 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 235 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 236 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 237 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 238 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 239 }, 240 [DR_ACTION_STATE_PUSH_VLAN] = { 241 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 242 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 243 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 244 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 245 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 246 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 247 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 248 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 249 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 250 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 251 }, 252 [DR_ACTION_STATE_NON_TERM] = { 253 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 254 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 255 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 256 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 257 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 258 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 259 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 260 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 261 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 262 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 263 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 264 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 265 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 266 }, 267 [DR_ACTION_STATE_ASO] = { 268 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 269 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 270 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 271 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 272 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 273 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 274 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 275 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 276 }, 277 [DR_ACTION_STATE_TERM] = { 278 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 279 }, 280 }, 281 [DR_ACTION_DOMAIN_FDB_INGRESS] = { 282 [DR_ACTION_STATE_NO_ACTION] = { 283 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 284 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 285 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 286 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 287 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 288 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 289 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 290 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 291 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 292 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 293 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 294 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 295 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 296 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 297 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 298 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 299 }, 300 [DR_ACTION_STATE_DECAP] = { 301 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 302 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 303 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 304 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 305 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 306 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 307 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 308 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 309 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 310 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 311 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 312 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 313 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 314 }, 315 [DR_ACTION_STATE_ENCAP] = { 316 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 317 [DR_ACTION_TYP_QP] = DR_ACTION_STATE_TERM, 318 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 319 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 320 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 321 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 322 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 323 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 324 }, 325 [DR_ACTION_STATE_MODIFY_HDR] = { 326 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 327 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 328 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 329 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 330 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 331 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 332 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 333 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 334 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 335 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 336 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 337 }, 338 [DR_ACTION_STATE_POP_VLAN] = { 339 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 340 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 341 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 342 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 343 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 344 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 345 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 346 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 347 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 348 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 349 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 350 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 351 }, 352 [DR_ACTION_STATE_PUSH_VLAN] = { 353 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 354 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 355 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 356 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 357 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 358 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 359 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 360 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 361 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 362 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 363 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 364 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 365 }, 366 [DR_ACTION_STATE_NON_TERM] = { 367 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 368 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 369 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 370 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 371 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 372 [DR_ACTION_TYP_TNL_L2_TO_L2] = DR_ACTION_STATE_DECAP, 373 [DR_ACTION_TYP_TNL_L3_TO_L2] = DR_ACTION_STATE_DECAP, 374 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 375 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 376 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 377 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 378 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 379 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 380 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 381 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 382 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 383 }, 384 [DR_ACTION_STATE_ASO] = { 385 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 386 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 387 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 388 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 389 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 390 }, 391 [DR_ACTION_STATE_TERM] = { 392 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 393 }, 394 }, 395 [DR_ACTION_DOMAIN_FDB_EGRESS] = { 396 [DR_ACTION_STATE_NO_ACTION] = { 397 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 398 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 399 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 400 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 401 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 402 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 403 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 404 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 405 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 406 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 407 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 408 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 409 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 410 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 411 }, 412 [DR_ACTION_STATE_DECAP] = { 413 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 414 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 415 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 416 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_DECAP, 417 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 418 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 419 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 420 }, 421 [DR_ACTION_STATE_ENCAP] = { 422 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 423 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 424 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 425 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ENCAP, 426 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 427 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 428 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 429 }, 430 [DR_ACTION_STATE_MODIFY_HDR] = { 431 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 432 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 433 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 434 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 435 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_MODIFY_HDR, 436 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 437 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 438 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 439 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 440 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 441 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 442 }, 443 [DR_ACTION_STATE_POP_VLAN] = { 444 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 445 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 446 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 447 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_POP_VLAN, 448 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 449 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 450 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 451 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 452 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 453 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 454 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 455 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 456 }, 457 [DR_ACTION_STATE_PUSH_VLAN] = { 458 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 459 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 460 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 461 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 462 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 463 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_PUSH_VLAN, 464 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 465 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 466 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 467 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 468 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 469 }, 470 [DR_ACTION_STATE_NON_TERM] = { 471 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 472 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 473 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 474 [DR_ACTION_TYP_SAMPLER] = DR_ACTION_STATE_TERM, 475 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_NON_TERM, 476 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 477 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 478 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 479 [DR_ACTION_TYP_INSERT_HDR] = DR_ACTION_STATE_ENCAP, 480 [DR_ACTION_TYP_REMOVE_HDR] = DR_ACTION_STATE_DECAP, 481 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 482 [DR_ACTION_TYP_POP_VLAN] = DR_ACTION_STATE_POP_VLAN, 483 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 484 [DR_ACTION_TYP_ASO_FLOW_METER] = DR_ACTION_STATE_ASO, 485 }, 486 [DR_ACTION_STATE_ASO] = { 487 [DR_ACTION_TYP_L2_TO_TNL_L2] = DR_ACTION_STATE_ENCAP, 488 [DR_ACTION_TYP_L2_TO_TNL_L3] = DR_ACTION_STATE_ENCAP, 489 [DR_ACTION_TYP_MODIFY_HDR] = DR_ACTION_STATE_MODIFY_HDR, 490 [DR_ACTION_TYP_PUSH_VLAN] = DR_ACTION_STATE_PUSH_VLAN, 491 [DR_ACTION_TYP_DROP] = DR_ACTION_STATE_TERM, 492 [DR_ACTION_TYP_FT] = DR_ACTION_STATE_TERM, 493 [DR_ACTION_TYP_RANGE] = DR_ACTION_STATE_TERM, 494 [DR_ACTION_TYP_VPORT] = DR_ACTION_STATE_TERM, 495 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_ASO, 496 }, 497 [DR_ACTION_STATE_TERM] = { 498 [DR_ACTION_TYP_CTR] = DR_ACTION_STATE_TERM, 499 }, 500 }, 501 }; 502 503 static int 504 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type, 505 enum mlx5dr_action_type *action_type) 506 { 507 switch (reformat_type) { 508 case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2: 509 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2; 510 break; 511 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2: 512 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2; 513 break; 514 case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2: 515 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2; 516 break; 517 case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3: 518 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3; 519 break; 520 case DR_ACTION_REFORMAT_TYP_INSERT_HDR: 521 *action_type = DR_ACTION_TYP_INSERT_HDR; 522 break; 523 case DR_ACTION_REFORMAT_TYP_REMOVE_HDR: 524 *action_type = DR_ACTION_TYP_REMOVE_HDR; 525 break; 526 default: 527 return -EINVAL; 528 } 529 530 return 0; 531 } 532 533 /* Apply the actions on the rule STE array starting from the last_ste. 534 * Actions might require more than one STE, new_num_stes will return 535 * the new size of the STEs array, rule with actions. 536 */ 537 static void dr_actions_apply(struct mlx5dr_domain *dmn, 538 enum mlx5dr_domain_nic_type nic_type, 539 u8 *action_type_set, 540 u8 *last_ste, 541 struct mlx5dr_ste_actions_attr *attr, 542 u32 *new_num_stes) 543 { 544 struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; 545 u32 added_stes = 0; 546 547 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 548 mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, 549 last_ste, attr, &added_stes); 550 else 551 mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, 552 last_ste, attr, &added_stes); 553 554 *new_num_stes += added_stes; 555 } 556 557 static enum dr_action_domain 558 dr_action_get_action_domain(enum mlx5dr_domain_type domain, 559 enum mlx5dr_domain_nic_type nic_type) 560 { 561 switch (domain) { 562 case MLX5DR_DOMAIN_TYPE_NIC_RX: 563 return DR_ACTION_DOMAIN_NIC_INGRESS; 564 case MLX5DR_DOMAIN_TYPE_NIC_TX: 565 return DR_ACTION_DOMAIN_NIC_EGRESS; 566 case MLX5DR_DOMAIN_TYPE_FDB: 567 if (nic_type == DR_DOMAIN_NIC_TYPE_RX) 568 return DR_ACTION_DOMAIN_FDB_INGRESS; 569 return DR_ACTION_DOMAIN_FDB_EGRESS; 570 default: 571 WARN_ON(true); 572 return DR_ACTION_DOMAIN_MAX; 573 } 574 } 575 576 static 577 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain, 578 u32 action_type, 579 u32 *state) 580 { 581 u32 cur_state = *state; 582 583 /* Check action state machine is valid */ 584 *state = next_action_state[action_domain][cur_state][action_type]; 585 586 if (*state == DR_ACTION_STATE_ERR) 587 return -EOPNOTSUPP; 588 589 return 0; 590 } 591 592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn, 593 struct mlx5dr_action *dest_action, 594 u64 *final_icm_addr) 595 { 596 int ret; 597 598 switch (dest_action->action_type) { 599 case DR_ACTION_TYP_FT: 600 /* Allow destination flow table only if table is a terminating 601 * table, since there is an *assumption* that in such case FW 602 * will recalculate the CS. 603 */ 604 if (dest_action->dest_tbl->is_fw_tbl) { 605 *final_icm_addr = dest_action->dest_tbl->fw_tbl.rx_icm_addr; 606 } else { 607 mlx5dr_dbg(dmn, 608 "Destination FT should be terminating when modify TTL is used\n"); 609 return -EINVAL; 610 } 611 break; 612 613 case DR_ACTION_TYP_VPORT: 614 /* If destination is vport we will get the FW flow table 615 * that recalculates the CS and forwards to the vport. 616 */ 617 ret = mlx5dr_domain_get_recalc_cs_ft_addr(dest_action->vport->dmn, 618 dest_action->vport->caps->num, 619 final_icm_addr); 620 if (ret) { 621 mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n"); 622 return ret; 623 } 624 break; 625 626 default: 627 break; 628 } 629 630 return 0; 631 } 632 633 static void dr_action_modify_ttl_adjust(struct mlx5dr_domain *dmn, 634 struct mlx5dr_ste_actions_attr *attr, 635 bool rx_rule, 636 bool *recalc_cs_required) 637 { 638 *recalc_cs_required = false; 639 640 /* if device supports csum recalculation - no adjustment needed */ 641 if (mlx5dr_ste_supp_ttl_cs_recalc(&dmn->info.caps)) 642 return; 643 644 /* no adjustment needed on TX rules */ 645 if (!rx_rule) 646 return; 647 648 if (!MLX5_CAP_ESW_FLOWTABLE(dmn->mdev, fdb_ipv4_ttl_modify)) { 649 /* Ignore the modify TTL action. 650 * It is always kept as last HW action. 651 */ 652 attr->modify_actions--; 653 return; 654 } 655 656 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 657 /* Due to a HW bug on some devices, modifying TTL on RX flows 658 * will cause an incorrect checksum calculation. In such cases 659 * we will use a FW table to recalculate the checksum. 660 */ 661 *recalc_cs_required = true; 662 } 663 664 static void dr_action_print_sequence(struct mlx5dr_domain *dmn, 665 struct mlx5dr_action *actions[], 666 int last_idx) 667 { 668 int i; 669 670 for (i = 0; i <= last_idx; i++) 671 mlx5dr_err(dmn, "< %s (%d) > ", 672 dr_action_id_to_str(actions[i]->action_type), 673 actions[i]->action_type); 674 } 675 676 static int dr_action_get_dest_fw_tbl_addr(struct mlx5dr_matcher *matcher, 677 struct mlx5dr_action_dest_tbl *dest_tbl, 678 bool is_rx_rule, 679 u64 *final_icm_addr) 680 { 681 struct mlx5dr_cmd_query_flow_table_details output; 682 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 683 int ret; 684 685 if (!dest_tbl->fw_tbl.rx_icm_addr) { 686 ret = mlx5dr_cmd_query_flow_table(dmn->mdev, 687 dest_tbl->fw_tbl.type, 688 dest_tbl->fw_tbl.id, 689 &output); 690 if (ret) { 691 mlx5dr_err(dmn, 692 "Failed mlx5_cmd_query_flow_table ret: %d\n", 693 ret); 694 return ret; 695 } 696 697 dest_tbl->fw_tbl.tx_icm_addr = output.sw_owner_icm_root_1; 698 dest_tbl->fw_tbl.rx_icm_addr = output.sw_owner_icm_root_0; 699 } 700 701 *final_icm_addr = is_rx_rule ? dest_tbl->fw_tbl.rx_icm_addr : 702 dest_tbl->fw_tbl.tx_icm_addr; 703 return 0; 704 } 705 706 static int dr_action_get_dest_sw_tbl_addr(struct mlx5dr_matcher *matcher, 707 struct mlx5dr_action_dest_tbl *dest_tbl, 708 bool is_rx_rule, 709 u64 *final_icm_addr) 710 { 711 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 712 struct mlx5dr_icm_chunk *chunk; 713 714 if (dest_tbl->tbl->dmn != dmn) { 715 mlx5dr_err(dmn, 716 "Destination table belongs to a different domain\n"); 717 return -EINVAL; 718 } 719 720 if (dest_tbl->tbl->level <= matcher->tbl->level) { 721 mlx5_core_dbg_once(dmn->mdev, 722 "Connecting table to a lower/same level destination table\n"); 723 mlx5dr_dbg(dmn, 724 "Connecting table at level %d to a destination table at level %d\n", 725 matcher->tbl->level, 726 dest_tbl->tbl->level); 727 } 728 729 chunk = is_rx_rule ? dest_tbl->tbl->rx.s_anchor->chunk : 730 dest_tbl->tbl->tx.s_anchor->chunk; 731 732 *final_icm_addr = mlx5dr_icm_pool_get_chunk_icm_addr(chunk); 733 return 0; 734 } 735 736 static int dr_action_get_dest_tbl_addr(struct mlx5dr_matcher *matcher, 737 struct mlx5dr_action_dest_tbl *dest_tbl, 738 bool is_rx_rule, 739 u64 *final_icm_addr) 740 { 741 if (dest_tbl->is_fw_tbl) 742 return dr_action_get_dest_fw_tbl_addr(matcher, 743 dest_tbl, 744 is_rx_rule, 745 final_icm_addr); 746 747 return dr_action_get_dest_sw_tbl_addr(matcher, 748 dest_tbl, 749 is_rx_rule, 750 final_icm_addr); 751 } 752 753 #define WITH_VLAN_NUM_HW_ACTIONS 6 754 755 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher, 756 struct mlx5dr_matcher_rx_tx *nic_matcher, 757 struct mlx5dr_action *actions[], 758 u32 num_actions, 759 u8 *ste_arr, 760 u32 *new_hw_ste_arr_sz) 761 { 762 struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn; 763 bool rx_rule = nic_dmn->type == DR_DOMAIN_NIC_TYPE_RX; 764 struct mlx5dr_domain *dmn = matcher->tbl->dmn; 765 u8 action_type_set[DR_ACTION_TYP_MAX] = {}; 766 struct mlx5dr_ste_actions_attr attr = {}; 767 struct mlx5dr_action *dest_action = NULL; 768 u32 state = DR_ACTION_STATE_NO_ACTION; 769 enum dr_action_domain action_domain; 770 bool recalc_cs_required = false; 771 u8 *last_ste; 772 int i, ret; 773 774 attr.gvmi = dmn->info.caps.gvmi; 775 attr.hit_gvmi = dmn->info.caps.gvmi; 776 attr.final_icm_addr = nic_dmn->default_icm_addr; 777 action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->type); 778 779 for (i = 0; i < num_actions; i++) { 780 struct mlx5dr_action *action; 781 int max_actions_type = 1; 782 u32 action_type; 783 784 action = actions[i]; 785 action_type = action->action_type; 786 787 switch (action_type) { 788 case DR_ACTION_TYP_DROP: 789 attr.final_icm_addr = nic_dmn->drop_icm_addr; 790 break; 791 case DR_ACTION_TYP_FT: 792 dest_action = action; 793 ret = dr_action_get_dest_tbl_addr(matcher, action->dest_tbl, 794 rx_rule, &attr.final_icm_addr); 795 if (ret) 796 return ret; 797 break; 798 case DR_ACTION_TYP_RANGE: 799 ret = dr_action_get_dest_tbl_addr(matcher, 800 action->range->hit_tbl_action->dest_tbl, 801 rx_rule, &attr.final_icm_addr); 802 if (ret) 803 return ret; 804 805 ret = dr_action_get_dest_tbl_addr(matcher, 806 action->range->miss_tbl_action->dest_tbl, 807 rx_rule, &attr.range.miss_icm_addr); 808 if (ret) 809 return ret; 810 811 attr.range.definer_id = action->range->definer_id; 812 attr.range.min = action->range->min; 813 attr.range.max = action->range->max; 814 break; 815 case DR_ACTION_TYP_QP: 816 mlx5dr_info(dmn, "Domain doesn't support QP\n"); 817 return -EOPNOTSUPP; 818 case DR_ACTION_TYP_CTR: 819 attr.ctr_id = action->ctr->ctr_id + 820 action->ctr->offset; 821 break; 822 case DR_ACTION_TYP_TAG: 823 attr.flow_tag = action->flow_tag->flow_tag; 824 break; 825 case DR_ACTION_TYP_TNL_L2_TO_L2: 826 break; 827 case DR_ACTION_TYP_TNL_L3_TO_L2: 828 if (action->rewrite->ptrn && action->rewrite->arg) { 829 attr.decap_index = mlx5dr_arg_get_obj_id(action->rewrite->arg); 830 attr.decap_actions = action->rewrite->ptrn->num_of_actions; 831 attr.decap_pat_idx = action->rewrite->ptrn->index; 832 } else { 833 attr.decap_index = action->rewrite->index; 834 attr.decap_actions = action->rewrite->num_of_actions; 835 attr.decap_with_vlan = 836 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS; 837 attr.decap_pat_idx = MLX5DR_INVALID_PATTERN_INDEX; 838 } 839 break; 840 case DR_ACTION_TYP_MODIFY_HDR: 841 if (action->rewrite->single_action_opt) { 842 attr.modify_actions = action->rewrite->num_of_actions; 843 attr.single_modify_action = action->rewrite->data; 844 } else { 845 if (action->rewrite->ptrn && action->rewrite->arg) { 846 attr.modify_index = 847 mlx5dr_arg_get_obj_id(action->rewrite->arg); 848 attr.modify_actions = action->rewrite->ptrn->num_of_actions; 849 attr.modify_pat_idx = action->rewrite->ptrn->index; 850 } else { 851 attr.modify_index = action->rewrite->index; 852 attr.modify_actions = action->rewrite->num_of_actions; 853 attr.modify_pat_idx = MLX5DR_INVALID_PATTERN_INDEX; 854 } 855 } 856 if (action->rewrite->modify_ttl) 857 dr_action_modify_ttl_adjust(dmn, &attr, rx_rule, 858 &recalc_cs_required); 859 break; 860 case DR_ACTION_TYP_L2_TO_TNL_L2: 861 case DR_ACTION_TYP_L2_TO_TNL_L3: 862 if (rx_rule && 863 !(dmn->ste_ctx->actions_caps & DR_STE_CTX_ACTION_CAP_RX_ENCAP)) { 864 mlx5dr_info(dmn, "Device doesn't support Encap on RX\n"); 865 return -EOPNOTSUPP; 866 } 867 attr.reformat.size = action->reformat->size; 868 attr.reformat.id = action->reformat->id; 869 break; 870 case DR_ACTION_TYP_SAMPLER: 871 attr.final_icm_addr = rx_rule ? action->sampler->rx_icm_addr : 872 action->sampler->tx_icm_addr; 873 break; 874 case DR_ACTION_TYP_VPORT: 875 attr.hit_gvmi = action->vport->caps->vhca_gvmi; 876 dest_action = action; 877 attr.final_icm_addr = rx_rule ? 878 action->vport->caps->icm_address_rx : 879 action->vport->caps->icm_address_tx; 880 break; 881 case DR_ACTION_TYP_POP_VLAN: 882 if (!rx_rule && !(dmn->ste_ctx->actions_caps & 883 DR_STE_CTX_ACTION_CAP_TX_POP)) { 884 mlx5dr_dbg(dmn, "Device doesn't support POP VLAN action on TX\n"); 885 return -EOPNOTSUPP; 886 } 887 888 max_actions_type = MLX5DR_MAX_VLANS; 889 attr.vlans.count++; 890 break; 891 case DR_ACTION_TYP_PUSH_VLAN: 892 if (rx_rule && !(dmn->ste_ctx->actions_caps & 893 DR_STE_CTX_ACTION_CAP_RX_PUSH)) { 894 mlx5dr_dbg(dmn, "Device doesn't support PUSH VLAN action on RX\n"); 895 return -EOPNOTSUPP; 896 } 897 898 max_actions_type = MLX5DR_MAX_VLANS; 899 if (attr.vlans.count == MLX5DR_MAX_VLANS) { 900 mlx5dr_dbg(dmn, "Max VLAN push/pop count exceeded\n"); 901 return -EINVAL; 902 } 903 904 attr.vlans.headers[attr.vlans.count++] = action->push_vlan->vlan_hdr; 905 break; 906 case DR_ACTION_TYP_INSERT_HDR: 907 case DR_ACTION_TYP_REMOVE_HDR: 908 attr.reformat.size = action->reformat->size; 909 attr.reformat.id = action->reformat->id; 910 attr.reformat.param_0 = action->reformat->param_0; 911 attr.reformat.param_1 = action->reformat->param_1; 912 break; 913 case DR_ACTION_TYP_ASO_FLOW_METER: 914 attr.aso_flow_meter.obj_id = action->aso->obj_id; 915 attr.aso_flow_meter.offset = action->aso->offset; 916 attr.aso_flow_meter.dest_reg_id = action->aso->dest_reg_id; 917 attr.aso_flow_meter.init_color = action->aso->init_color; 918 break; 919 default: 920 mlx5dr_err(dmn, "Unsupported action type %d\n", action_type); 921 return -EINVAL; 922 } 923 924 /* Check action duplication */ 925 if (++action_type_set[action_type] > max_actions_type) { 926 mlx5dr_err(dmn, "Action type %d supports only max %d time(s)\n", 927 action_type, max_actions_type); 928 return -EINVAL; 929 } 930 931 /* Check action state machine is valid */ 932 if (dr_action_validate_and_get_next_state(action_domain, 933 action_type, 934 &state)) { 935 mlx5dr_err(dmn, "Invalid action (gvmi: %d, is_rx: %d) sequence provided:", 936 attr.gvmi, rx_rule); 937 dr_action_print_sequence(dmn, actions, i); 938 return -EOPNOTSUPP; 939 } 940 } 941 942 *new_hw_ste_arr_sz = nic_matcher->num_of_builders; 943 last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1); 944 945 if (recalc_cs_required && dest_action) { 946 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr); 947 if (ret) { 948 mlx5dr_err(dmn, 949 "Failed to handle checksum recalculation err %d\n", 950 ret); 951 return ret; 952 } 953 } 954 955 dr_actions_apply(dmn, 956 nic_dmn->type, 957 action_type_set, 958 last_ste, 959 &attr, 960 new_hw_ste_arr_sz); 961 962 return 0; 963 } 964 965 static unsigned int action_size[DR_ACTION_TYP_MAX] = { 966 [DR_ACTION_TYP_TNL_L2_TO_L2] = sizeof(struct mlx5dr_action_reformat), 967 [DR_ACTION_TYP_L2_TO_TNL_L2] = sizeof(struct mlx5dr_action_reformat), 968 [DR_ACTION_TYP_TNL_L3_TO_L2] = sizeof(struct mlx5dr_action_rewrite), 969 [DR_ACTION_TYP_L2_TO_TNL_L3] = sizeof(struct mlx5dr_action_reformat), 970 [DR_ACTION_TYP_FT] = sizeof(struct mlx5dr_action_dest_tbl), 971 [DR_ACTION_TYP_CTR] = sizeof(struct mlx5dr_action_ctr), 972 [DR_ACTION_TYP_TAG] = sizeof(struct mlx5dr_action_flow_tag), 973 [DR_ACTION_TYP_MODIFY_HDR] = sizeof(struct mlx5dr_action_rewrite), 974 [DR_ACTION_TYP_VPORT] = sizeof(struct mlx5dr_action_vport), 975 [DR_ACTION_TYP_PUSH_VLAN] = sizeof(struct mlx5dr_action_push_vlan), 976 [DR_ACTION_TYP_INSERT_HDR] = sizeof(struct mlx5dr_action_reformat), 977 [DR_ACTION_TYP_REMOVE_HDR] = sizeof(struct mlx5dr_action_reformat), 978 [DR_ACTION_TYP_SAMPLER] = sizeof(struct mlx5dr_action_sampler), 979 [DR_ACTION_TYP_ASO_FLOW_METER] = sizeof(struct mlx5dr_action_aso_flow_meter), 980 [DR_ACTION_TYP_RANGE] = sizeof(struct mlx5dr_action_range), 981 }; 982 983 static struct mlx5dr_action * 984 dr_action_create_generic(enum mlx5dr_action_type action_type) 985 { 986 struct mlx5dr_action *action; 987 int extra_size; 988 989 if (action_type < DR_ACTION_TYP_MAX) 990 extra_size = action_size[action_type]; 991 else 992 return NULL; 993 994 action = kzalloc(sizeof(*action) + extra_size, GFP_KERNEL); 995 if (!action) 996 return NULL; 997 998 action->action_type = action_type; 999 refcount_set(&action->refcount, 1); 1000 action->data = action + 1; 1001 1002 return action; 1003 } 1004 1005 struct mlx5dr_action *mlx5dr_action_create_drop(void) 1006 { 1007 return dr_action_create_generic(DR_ACTION_TYP_DROP); 1008 } 1009 1010 struct mlx5dr_action * 1011 mlx5dr_action_create_dest_table_num(struct mlx5dr_domain *dmn, u32 table_num) 1012 { 1013 struct mlx5dr_action *action; 1014 1015 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1016 if (!action) 1017 return NULL; 1018 1019 action->dest_tbl->is_fw_tbl = true; 1020 action->dest_tbl->fw_tbl.dmn = dmn; 1021 action->dest_tbl->fw_tbl.id = table_num; 1022 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1023 refcount_inc(&dmn->refcount); 1024 1025 return action; 1026 } 1027 1028 struct mlx5dr_action * 1029 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl) 1030 { 1031 struct mlx5dr_action *action; 1032 1033 refcount_inc(&tbl->refcount); 1034 1035 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1036 if (!action) 1037 goto dec_ref; 1038 1039 action->dest_tbl->tbl = tbl; 1040 1041 return action; 1042 1043 dec_ref: 1044 refcount_dec(&tbl->refcount); 1045 return NULL; 1046 } 1047 1048 static void dr_action_range_definer_fill(u16 *format_id, 1049 u8 *dw_selectors, 1050 u8 *byte_selectors, 1051 u8 *match_mask) 1052 { 1053 int i; 1054 1055 *format_id = MLX5_IFC_DEFINER_FORMAT_ID_SELECT; 1056 1057 dw_selectors[0] = MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN / 4; 1058 1059 for (i = 1; i < MLX5_IFC_DEFINER_DW_SELECTORS_NUM; i++) 1060 dw_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1061 1062 for (i = 0; i < MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM; i++) 1063 byte_selectors[i] = MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED; 1064 1065 MLX5_SET(match_definer_match_mask, match_mask, 1066 match_dw_0, 0xffffUL << 16); 1067 } 1068 1069 static int dr_action_create_range_definer(struct mlx5dr_action *action) 1070 { 1071 u8 match_mask[MLX5_FLD_SZ_BYTES(match_definer, match_mask)] = {}; 1072 u8 byte_selectors[MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM] = {}; 1073 u8 dw_selectors[MLX5_IFC_DEFINER_DW_SELECTORS_NUM] = {}; 1074 struct mlx5dr_domain *dmn = action->range->dmn; 1075 u32 definer_id; 1076 u16 format_id; 1077 int ret; 1078 1079 dr_action_range_definer_fill(&format_id, 1080 dw_selectors, 1081 byte_selectors, 1082 match_mask); 1083 1084 ret = mlx5dr_definer_get(dmn, format_id, 1085 dw_selectors, byte_selectors, 1086 match_mask, &definer_id); 1087 if (ret) 1088 return ret; 1089 1090 action->range->definer_id = definer_id; 1091 return 0; 1092 } 1093 1094 static void dr_action_destroy_range_definer(struct mlx5dr_action *action) 1095 { 1096 mlx5dr_definer_put(action->range->dmn, action->range->definer_id); 1097 } 1098 1099 struct mlx5dr_action * 1100 mlx5dr_action_create_dest_match_range(struct mlx5dr_domain *dmn, 1101 u32 field, 1102 struct mlx5_flow_table *hit_ft, 1103 struct mlx5_flow_table *miss_ft, 1104 u32 min, 1105 u32 max) 1106 { 1107 struct mlx5dr_action *action; 1108 int ret; 1109 1110 if (!mlx5dr_supp_match_ranges(dmn->mdev)) { 1111 mlx5dr_dbg(dmn, "SELECT definer support is needed for match range\n"); 1112 return NULL; 1113 } 1114 1115 if (field != MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN || 1116 min > 0xffff || max > 0xffff) { 1117 mlx5dr_err(dmn, "Invalid match range parameters\n"); 1118 return NULL; 1119 } 1120 1121 action = dr_action_create_generic(DR_ACTION_TYP_RANGE); 1122 if (!action) 1123 return NULL; 1124 1125 action->range->hit_tbl_action = 1126 mlx5dr_is_fw_table(hit_ft) ? 1127 mlx5dr_action_create_dest_flow_fw_table(dmn, hit_ft) : 1128 mlx5dr_action_create_dest_table(hit_ft->fs_dr_table.dr_table); 1129 1130 if (!action->range->hit_tbl_action) 1131 goto free_action; 1132 1133 action->range->miss_tbl_action = 1134 mlx5dr_is_fw_table(miss_ft) ? 1135 mlx5dr_action_create_dest_flow_fw_table(dmn, miss_ft) : 1136 mlx5dr_action_create_dest_table(miss_ft->fs_dr_table.dr_table); 1137 1138 if (!action->range->miss_tbl_action) 1139 goto free_hit_tbl_action; 1140 1141 action->range->min = min; 1142 action->range->max = max; 1143 action->range->dmn = dmn; 1144 1145 ret = dr_action_create_range_definer(action); 1146 if (ret) 1147 goto free_miss_tbl_action; 1148 1149 /* No need to increase refcount on domain for this action, 1150 * the hit/miss table actions will do it internally. 1151 */ 1152 1153 return action; 1154 1155 free_miss_tbl_action: 1156 mlx5dr_action_destroy(action->range->miss_tbl_action); 1157 free_hit_tbl_action: 1158 mlx5dr_action_destroy(action->range->hit_tbl_action); 1159 free_action: 1160 kfree(action); 1161 1162 return NULL; 1163 } 1164 1165 struct mlx5dr_action * 1166 mlx5dr_action_create_mult_dest_tbl(struct mlx5dr_domain *dmn, 1167 struct mlx5dr_action_dest *dests, 1168 u32 num_of_dests, 1169 bool ignore_flow_level, 1170 u32 flow_source) 1171 { 1172 struct mlx5dr_cmd_flow_destination_hw_info tmp_hw_dest; 1173 struct mlx5dr_cmd_flow_destination_hw_info *hw_dests; 1174 struct mlx5dr_action **ref_actions; 1175 struct mlx5dr_action *action; 1176 bool reformat_req = false; 1177 bool is_ft_wire = false; 1178 u16 num_dst_ft = 0; 1179 u32 num_of_ref = 0; 1180 u32 ref_act_cnt; 1181 u16 last_dest; 1182 int ret; 1183 int i; 1184 1185 if (dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 1186 mlx5dr_err(dmn, "Multiple destination support is for FDB only\n"); 1187 return NULL; 1188 } 1189 1190 hw_dests = kcalloc(num_of_dests, sizeof(*hw_dests), GFP_KERNEL); 1191 if (!hw_dests) 1192 return NULL; 1193 1194 if (unlikely(check_mul_overflow(num_of_dests, 2u, &ref_act_cnt))) 1195 goto free_hw_dests; 1196 1197 ref_actions = kcalloc(ref_act_cnt, sizeof(*ref_actions), GFP_KERNEL); 1198 if (!ref_actions) 1199 goto free_hw_dests; 1200 1201 for (i = 0; i < num_of_dests; i++) { 1202 struct mlx5dr_action *reformat_action = dests[i].reformat; 1203 struct mlx5dr_action *dest_action = dests[i].dest; 1204 1205 ref_actions[num_of_ref++] = dest_action; 1206 1207 switch (dest_action->action_type) { 1208 case DR_ACTION_TYP_VPORT: 1209 hw_dests[i].vport.flags = MLX5_FLOW_DEST_VPORT_VHCA_ID; 1210 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; 1211 hw_dests[i].vport.num = dest_action->vport->caps->num; 1212 hw_dests[i].vport.vhca_id = dest_action->vport->caps->vhca_gvmi; 1213 if (reformat_action) { 1214 reformat_req = true; 1215 hw_dests[i].vport.reformat_id = 1216 reformat_action->reformat->id; 1217 ref_actions[num_of_ref++] = reformat_action; 1218 hw_dests[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; 1219 } 1220 break; 1221 1222 case DR_ACTION_TYP_FT: 1223 if (num_dst_ft && 1224 !mlx5dr_action_supp_fwd_fdb_multi_ft(dmn->mdev)) { 1225 mlx5dr_dbg(dmn, "multiple FT destinations not supported\n"); 1226 goto free_ref_actions; 1227 } 1228 num_dst_ft++; 1229 hw_dests[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; 1230 if (dest_action->dest_tbl->is_fw_tbl) { 1231 hw_dests[i].ft_id = dest_action->dest_tbl->fw_tbl.id; 1232 } else { 1233 hw_dests[i].ft_id = dest_action->dest_tbl->tbl->table_id; 1234 if (dest_action->dest_tbl->is_wire_ft) { 1235 is_ft_wire = true; 1236 last_dest = i; 1237 } 1238 } 1239 break; 1240 1241 default: 1242 mlx5dr_dbg(dmn, "Invalid multiple destinations action\n"); 1243 goto free_ref_actions; 1244 } 1245 } 1246 1247 /* In multidest, the FW does the iterator in the RX except of the last 1248 * one that done in the TX. 1249 * So, if one of the ft target is wire, put it at the end of the dest list. 1250 */ 1251 if (is_ft_wire && num_dst_ft > 1) { 1252 tmp_hw_dest = hw_dests[last_dest]; 1253 hw_dests[last_dest] = hw_dests[num_of_dests - 1]; 1254 hw_dests[num_of_dests - 1] = tmp_hw_dest; 1255 } 1256 1257 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1258 if (!action) 1259 goto free_ref_actions; 1260 1261 ret = mlx5dr_fw_create_md_tbl(dmn, 1262 hw_dests, 1263 num_of_dests, 1264 reformat_req, 1265 &action->dest_tbl->fw_tbl.id, 1266 &action->dest_tbl->fw_tbl.group_id, 1267 ignore_flow_level, 1268 flow_source); 1269 if (ret) 1270 goto free_action; 1271 1272 refcount_inc(&dmn->refcount); 1273 1274 for (i = 0; i < num_of_ref; i++) 1275 refcount_inc(&ref_actions[i]->refcount); 1276 1277 action->dest_tbl->is_fw_tbl = true; 1278 action->dest_tbl->fw_tbl.dmn = dmn; 1279 action->dest_tbl->fw_tbl.type = FS_FT_FDB; 1280 action->dest_tbl->fw_tbl.ref_actions = ref_actions; 1281 action->dest_tbl->fw_tbl.num_of_ref_actions = num_of_ref; 1282 1283 kfree(hw_dests); 1284 1285 return action; 1286 1287 free_action: 1288 kfree(action); 1289 free_ref_actions: 1290 kfree(ref_actions); 1291 free_hw_dests: 1292 kfree(hw_dests); 1293 return NULL; 1294 } 1295 1296 struct mlx5dr_action * 1297 mlx5dr_action_create_dest_flow_fw_table(struct mlx5dr_domain *dmn, 1298 struct mlx5_flow_table *ft) 1299 { 1300 struct mlx5dr_action *action; 1301 1302 action = dr_action_create_generic(DR_ACTION_TYP_FT); 1303 if (!action) 1304 return NULL; 1305 1306 action->dest_tbl->is_fw_tbl = 1; 1307 action->dest_tbl->fw_tbl.type = ft->type; 1308 action->dest_tbl->fw_tbl.id = ft->id; 1309 action->dest_tbl->fw_tbl.dmn = dmn; 1310 1311 refcount_inc(&dmn->refcount); 1312 1313 return action; 1314 } 1315 1316 struct mlx5dr_action * 1317 mlx5dr_action_create_flow_counter(u32 counter_id) 1318 { 1319 struct mlx5dr_action *action; 1320 1321 action = dr_action_create_generic(DR_ACTION_TYP_CTR); 1322 if (!action) 1323 return NULL; 1324 1325 action->ctr->ctr_id = counter_id; 1326 1327 return action; 1328 } 1329 1330 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value) 1331 { 1332 struct mlx5dr_action *action; 1333 1334 action = dr_action_create_generic(DR_ACTION_TYP_TAG); 1335 if (!action) 1336 return NULL; 1337 1338 action->flow_tag->flow_tag = tag_value & 0xffffff; 1339 1340 return action; 1341 } 1342 1343 struct mlx5dr_action * 1344 mlx5dr_action_create_flow_sampler(struct mlx5dr_domain *dmn, u32 sampler_id) 1345 { 1346 struct mlx5dr_action *action; 1347 u64 icm_rx, icm_tx; 1348 int ret; 1349 1350 ret = mlx5dr_cmd_query_flow_sampler(dmn->mdev, sampler_id, 1351 &icm_rx, &icm_tx); 1352 if (ret) 1353 return NULL; 1354 1355 action = dr_action_create_generic(DR_ACTION_TYP_SAMPLER); 1356 if (!action) 1357 return NULL; 1358 1359 action->sampler->dmn = dmn; 1360 action->sampler->sampler_id = sampler_id; 1361 action->sampler->rx_icm_addr = icm_rx; 1362 action->sampler->tx_icm_addr = icm_tx; 1363 1364 refcount_inc(&dmn->refcount); 1365 return action; 1366 } 1367 1368 static int 1369 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type, 1370 struct mlx5dr_domain *dmn, 1371 u8 reformat_param_0, 1372 u8 reformat_param_1, 1373 size_t data_sz, 1374 void *data) 1375 { 1376 if (reformat_type == DR_ACTION_TYP_INSERT_HDR) { 1377 if ((!data && data_sz) || (data && !data_sz) || 1378 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_size) < data_sz || 1379 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_insert_offset) < reformat_param_1) { 1380 mlx5dr_dbg(dmn, "Invalid reformat parameters for INSERT_HDR\n"); 1381 goto out_err; 1382 } 1383 } else if (reformat_type == DR_ACTION_TYP_REMOVE_HDR) { 1384 if (data || 1385 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_size) < data_sz || 1386 MLX5_CAP_GEN_2(dmn->mdev, max_reformat_remove_offset) < reformat_param_1) { 1387 mlx5dr_dbg(dmn, "Invalid reformat parameters for REMOVE_HDR\n"); 1388 goto out_err; 1389 } 1390 } else if (reformat_param_0 || reformat_param_1 || 1391 reformat_type > DR_ACTION_TYP_REMOVE_HDR) { 1392 mlx5dr_dbg(dmn, "Invalid reformat parameters\n"); 1393 goto out_err; 1394 } 1395 1396 if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB) 1397 return 0; 1398 1399 if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) { 1400 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 && 1401 reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) { 1402 mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n"); 1403 goto out_err; 1404 } 1405 } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) { 1406 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 && 1407 reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) { 1408 mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n"); 1409 goto out_err; 1410 } 1411 } 1412 1413 return 0; 1414 1415 out_err: 1416 return -EINVAL; 1417 } 1418 1419 static int 1420 dr_action_create_reformat_action(struct mlx5dr_domain *dmn, 1421 u8 reformat_param_0, u8 reformat_param_1, 1422 size_t data_sz, void *data, 1423 struct mlx5dr_action *action) 1424 { 1425 u32 reformat_id; 1426 int ret; 1427 1428 switch (action->action_type) { 1429 case DR_ACTION_TYP_L2_TO_TNL_L2: 1430 case DR_ACTION_TYP_L2_TO_TNL_L3: 1431 { 1432 enum mlx5_reformat_ctx_type rt; 1433 1434 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2) 1435 rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL; 1436 else 1437 rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL; 1438 1439 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, 0, 0, 1440 data_sz, data, 1441 &reformat_id); 1442 if (ret) 1443 return ret; 1444 1445 action->reformat->id = reformat_id; 1446 action->reformat->size = data_sz; 1447 return 0; 1448 } 1449 case DR_ACTION_TYP_TNL_L2_TO_L2: 1450 { 1451 return 0; 1452 } 1453 case DR_ACTION_TYP_TNL_L3_TO_L2: 1454 { 1455 u8 *hw_actions; 1456 1457 hw_actions = kzalloc(DR_ACTION_CACHE_LINE_SIZE, GFP_KERNEL); 1458 if (!hw_actions) 1459 return -ENOMEM; 1460 1461 ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, 1462 data, data_sz, 1463 hw_actions, 1464 DR_ACTION_CACHE_LINE_SIZE, 1465 &action->rewrite->num_of_actions); 1466 if (ret) { 1467 mlx5dr_dbg(dmn, "Failed creating decap l3 action list\n"); 1468 kfree(hw_actions); 1469 return ret; 1470 } 1471 1472 action->rewrite->data = hw_actions; 1473 action->rewrite->dmn = dmn; 1474 1475 ret = mlx5dr_ste_alloc_modify_hdr(action); 1476 if (ret) { 1477 mlx5dr_dbg(dmn, "Failed preparing reformat data\n"); 1478 kfree(hw_actions); 1479 return ret; 1480 } 1481 return 0; 1482 } 1483 case DR_ACTION_TYP_INSERT_HDR: 1484 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, 1485 MLX5_REFORMAT_TYPE_INSERT_HDR, 1486 reformat_param_0, 1487 reformat_param_1, 1488 data_sz, data, 1489 &reformat_id); 1490 if (ret) 1491 return ret; 1492 1493 action->reformat->id = reformat_id; 1494 action->reformat->size = data_sz; 1495 action->reformat->param_0 = reformat_param_0; 1496 action->reformat->param_1 = reformat_param_1; 1497 return 0; 1498 case DR_ACTION_TYP_REMOVE_HDR: 1499 action->reformat->id = 0; 1500 action->reformat->size = data_sz; 1501 action->reformat->param_0 = reformat_param_0; 1502 action->reformat->param_1 = reformat_param_1; 1503 return 0; 1504 default: 1505 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type); 1506 return -EINVAL; 1507 } 1508 } 1509 1510 #define CVLAN_ETHERTYPE 0x8100 1511 #define SVLAN_ETHERTYPE 0x88a8 1512 1513 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void) 1514 { 1515 return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN); 1516 } 1517 1518 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn, 1519 __be32 vlan_hdr) 1520 { 1521 u32 vlan_hdr_h = ntohl(vlan_hdr); 1522 u16 ethertype = vlan_hdr_h >> 16; 1523 struct mlx5dr_action *action; 1524 1525 if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) { 1526 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n"); 1527 return NULL; 1528 } 1529 1530 action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN); 1531 if (!action) 1532 return NULL; 1533 1534 action->push_vlan->vlan_hdr = vlan_hdr_h; 1535 return action; 1536 } 1537 1538 struct mlx5dr_action * 1539 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn, 1540 enum mlx5dr_action_reformat_type reformat_type, 1541 u8 reformat_param_0, 1542 u8 reformat_param_1, 1543 size_t data_sz, 1544 void *data) 1545 { 1546 enum mlx5dr_action_type action_type; 1547 struct mlx5dr_action *action; 1548 int ret; 1549 1550 refcount_inc(&dmn->refcount); 1551 1552 /* General checks */ 1553 ret = dr_action_reformat_to_action_type(reformat_type, &action_type); 1554 if (ret) { 1555 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n"); 1556 goto dec_ref; 1557 } 1558 1559 ret = dr_action_verify_reformat_params(action_type, dmn, 1560 reformat_param_0, reformat_param_1, 1561 data_sz, data); 1562 if (ret) 1563 goto dec_ref; 1564 1565 action = dr_action_create_generic(action_type); 1566 if (!action) 1567 goto dec_ref; 1568 1569 action->reformat->dmn = dmn; 1570 1571 ret = dr_action_create_reformat_action(dmn, 1572 reformat_param_0, 1573 reformat_param_1, 1574 data_sz, 1575 data, 1576 action); 1577 if (ret) { 1578 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret); 1579 goto free_action; 1580 } 1581 1582 return action; 1583 1584 free_action: 1585 kfree(action); 1586 dec_ref: 1587 refcount_dec(&dmn->refcount); 1588 return NULL; 1589 } 1590 1591 static int 1592 dr_action_modify_sw_to_hw_add(struct mlx5dr_domain *dmn, 1593 __be64 *sw_action, 1594 __be64 *hw_action, 1595 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1596 { 1597 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1598 u8 max_length; 1599 u16 sw_field; 1600 u32 data; 1601 1602 /* Get SW modify action data */ 1603 sw_field = MLX5_GET(set_action_in, sw_action, field); 1604 data = MLX5_GET(set_action_in, sw_action, data); 1605 1606 /* Convert SW data to HW modify action format */ 1607 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1608 if (!hw_action_info) { 1609 mlx5dr_dbg(dmn, "Modify add action invalid field given\n"); 1610 return -EINVAL; 1611 } 1612 1613 max_length = hw_action_info->end - hw_action_info->start + 1; 1614 1615 mlx5dr_ste_set_action_add(dmn->ste_ctx, 1616 hw_action, 1617 hw_action_info->hw_field, 1618 hw_action_info->start, 1619 max_length, 1620 data); 1621 1622 *ret_hw_info = hw_action_info; 1623 1624 return 0; 1625 } 1626 1627 static int 1628 dr_action_modify_sw_to_hw_set(struct mlx5dr_domain *dmn, 1629 __be64 *sw_action, 1630 __be64 *hw_action, 1631 const struct mlx5dr_ste_action_modify_field **ret_hw_info) 1632 { 1633 const struct mlx5dr_ste_action_modify_field *hw_action_info; 1634 u8 offset, length, max_length; 1635 u16 sw_field; 1636 u32 data; 1637 1638 /* Get SW modify action data */ 1639 length = MLX5_GET(set_action_in, sw_action, length); 1640 offset = MLX5_GET(set_action_in, sw_action, offset); 1641 sw_field = MLX5_GET(set_action_in, sw_action, field); 1642 data = MLX5_GET(set_action_in, sw_action, data); 1643 1644 /* Convert SW data to HW modify action format */ 1645 hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); 1646 if (!hw_action_info) { 1647 mlx5dr_dbg(dmn, "Modify set action invalid field given\n"); 1648 return -EINVAL; 1649 } 1650 1651 /* PRM defines that length zero specific length of 32bits */ 1652 length = length ? length : 32; 1653 1654 max_length = hw_action_info->end - hw_action_info->start + 1; 1655 1656 if (length + offset > max_length) { 1657 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1658 return -EINVAL; 1659 } 1660 1661 mlx5dr_ste_set_action_set(dmn->ste_ctx, 1662 hw_action, 1663 hw_action_info->hw_field, 1664 hw_action_info->start + offset, 1665 length, 1666 data); 1667 1668 *ret_hw_info = hw_action_info; 1669 1670 return 0; 1671 } 1672 1673 static int 1674 dr_action_modify_sw_to_hw_copy(struct mlx5dr_domain *dmn, 1675 __be64 *sw_action, 1676 __be64 *hw_action, 1677 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1678 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1679 { 1680 u8 src_offset, dst_offset, src_max_length, dst_max_length, length; 1681 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1682 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1683 u16 src_field, dst_field; 1684 1685 /* Get SW modify action data */ 1686 src_field = MLX5_GET(copy_action_in, sw_action, src_field); 1687 dst_field = MLX5_GET(copy_action_in, sw_action, dst_field); 1688 src_offset = MLX5_GET(copy_action_in, sw_action, src_offset); 1689 dst_offset = MLX5_GET(copy_action_in, sw_action, dst_offset); 1690 length = MLX5_GET(copy_action_in, sw_action, length); 1691 1692 /* Convert SW data to HW modify action format */ 1693 hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); 1694 hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); 1695 if (!hw_src_action_info || !hw_dst_action_info) { 1696 mlx5dr_dbg(dmn, "Modify copy action invalid field given\n"); 1697 return -EINVAL; 1698 } 1699 1700 /* PRM defines that length zero specific length of 32bits */ 1701 length = length ? length : 32; 1702 1703 src_max_length = hw_src_action_info->end - 1704 hw_src_action_info->start + 1; 1705 dst_max_length = hw_dst_action_info->end - 1706 hw_dst_action_info->start + 1; 1707 1708 if (length + src_offset > src_max_length || 1709 length + dst_offset > dst_max_length) { 1710 mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n"); 1711 return -EINVAL; 1712 } 1713 1714 mlx5dr_ste_set_action_copy(dmn->ste_ctx, 1715 hw_action, 1716 hw_dst_action_info->hw_field, 1717 hw_dst_action_info->start + dst_offset, 1718 length, 1719 hw_src_action_info->hw_field, 1720 hw_src_action_info->start + src_offset); 1721 1722 *ret_dst_hw_info = hw_dst_action_info; 1723 *ret_src_hw_info = hw_src_action_info; 1724 1725 return 0; 1726 } 1727 1728 static int 1729 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn, 1730 __be64 *sw_action, 1731 __be64 *hw_action, 1732 const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, 1733 const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) 1734 { 1735 u8 action; 1736 int ret; 1737 1738 *hw_action = 0; 1739 *ret_src_hw_info = NULL; 1740 1741 /* Get SW modify action type */ 1742 action = MLX5_GET(set_action_in, sw_action, action_type); 1743 1744 switch (action) { 1745 case MLX5_ACTION_TYPE_SET: 1746 ret = dr_action_modify_sw_to_hw_set(dmn, sw_action, 1747 hw_action, 1748 ret_dst_hw_info); 1749 break; 1750 1751 case MLX5_ACTION_TYPE_ADD: 1752 ret = dr_action_modify_sw_to_hw_add(dmn, sw_action, 1753 hw_action, 1754 ret_dst_hw_info); 1755 break; 1756 1757 case MLX5_ACTION_TYPE_COPY: 1758 ret = dr_action_modify_sw_to_hw_copy(dmn, sw_action, 1759 hw_action, 1760 ret_dst_hw_info, 1761 ret_src_hw_info); 1762 break; 1763 1764 default: 1765 mlx5dr_info(dmn, "Unsupported action_type for modify action\n"); 1766 ret = -EOPNOTSUPP; 1767 } 1768 1769 return ret; 1770 } 1771 1772 static int 1773 dr_action_modify_check_set_field_limitation(struct mlx5dr_action *action, 1774 const __be64 *sw_action) 1775 { 1776 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1777 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1778 1779 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1780 action->rewrite->allow_rx = 0; 1781 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1782 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1783 sw_field); 1784 return -EINVAL; 1785 } 1786 } else if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1787 action->rewrite->allow_tx = 0; 1788 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1789 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1790 sw_field); 1791 return -EINVAL; 1792 } 1793 } 1794 1795 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1796 mlx5dr_dbg(dmn, "Modify SET actions not supported on both RX and TX\n"); 1797 return -EINVAL; 1798 } 1799 1800 return 0; 1801 } 1802 1803 static int 1804 dr_action_modify_check_add_field_limitation(struct mlx5dr_action *action, 1805 const __be64 *sw_action) 1806 { 1807 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1808 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1809 1810 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL && 1811 sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT && 1812 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM && 1813 sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) { 1814 mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", 1815 sw_field); 1816 return -EINVAL; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int 1823 dr_action_modify_check_copy_field_limitation(struct mlx5dr_action *action, 1824 const __be64 *sw_action) 1825 { 1826 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1827 u16 sw_fields[2]; 1828 int i; 1829 1830 sw_fields[0] = MLX5_GET(copy_action_in, sw_action, src_field); 1831 sw_fields[1] = MLX5_GET(copy_action_in, sw_action, dst_field); 1832 1833 for (i = 0; i < 2; i++) { 1834 if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_A) { 1835 action->rewrite->allow_rx = 0; 1836 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) { 1837 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n", 1838 sw_fields[i]); 1839 return -EINVAL; 1840 } 1841 } else if (sw_fields[i] == MLX5_ACTION_IN_FIELD_METADATA_REG_B) { 1842 action->rewrite->allow_tx = 0; 1843 if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) { 1844 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n", 1845 sw_fields[i]); 1846 return -EINVAL; 1847 } 1848 } 1849 } 1850 1851 if (!action->rewrite->allow_rx && !action->rewrite->allow_tx) { 1852 mlx5dr_dbg(dmn, "Modify copy actions not supported on both RX and TX\n"); 1853 return -EINVAL; 1854 } 1855 1856 return 0; 1857 } 1858 1859 static int 1860 dr_action_modify_check_field_limitation(struct mlx5dr_action *action, 1861 const __be64 *sw_action) 1862 { 1863 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1864 u8 action_type; 1865 int ret; 1866 1867 action_type = MLX5_GET(set_action_in, sw_action, action_type); 1868 1869 switch (action_type) { 1870 case MLX5_ACTION_TYPE_SET: 1871 ret = dr_action_modify_check_set_field_limitation(action, 1872 sw_action); 1873 break; 1874 1875 case MLX5_ACTION_TYPE_ADD: 1876 ret = dr_action_modify_check_add_field_limitation(action, 1877 sw_action); 1878 break; 1879 1880 case MLX5_ACTION_TYPE_COPY: 1881 ret = dr_action_modify_check_copy_field_limitation(action, 1882 sw_action); 1883 break; 1884 1885 default: 1886 mlx5dr_info(dmn, "Unsupported action %d modify action\n", 1887 action_type); 1888 ret = -EOPNOTSUPP; 1889 } 1890 1891 return ret; 1892 } 1893 1894 static bool 1895 dr_action_modify_check_is_ttl_modify(const void *sw_action) 1896 { 1897 u16 sw_field = MLX5_GET(set_action_in, sw_action, field); 1898 1899 return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL; 1900 } 1901 1902 static int dr_actions_convert_modify_header(struct mlx5dr_action *action, 1903 u32 max_hw_actions, 1904 u32 num_sw_actions, 1905 __be64 sw_actions[], 1906 __be64 hw_actions[], 1907 u32 *num_hw_actions, 1908 bool *modify_ttl) 1909 { 1910 const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; 1911 const struct mlx5dr_ste_action_modify_field *hw_src_action_info; 1912 struct mlx5dr_domain *dmn = action->rewrite->dmn; 1913 __be64 *modify_ttl_sw_action = NULL; 1914 int ret, i, hw_idx = 0; 1915 __be64 *sw_action; 1916 __be64 hw_action; 1917 u16 hw_field = 0; 1918 u32 l3_type = 0; 1919 u32 l4_type = 0; 1920 1921 *modify_ttl = false; 1922 1923 action->rewrite->allow_rx = 1; 1924 action->rewrite->allow_tx = 1; 1925 1926 for (i = 0; i < num_sw_actions || modify_ttl_sw_action; i++) { 1927 /* modify TTL is handled separately, as a last action */ 1928 if (i == num_sw_actions) { 1929 sw_action = modify_ttl_sw_action; 1930 modify_ttl_sw_action = NULL; 1931 } else { 1932 sw_action = &sw_actions[i]; 1933 } 1934 1935 ret = dr_action_modify_check_field_limitation(action, 1936 sw_action); 1937 if (ret) 1938 return ret; 1939 1940 if (!(*modify_ttl) && 1941 dr_action_modify_check_is_ttl_modify(sw_action)) { 1942 modify_ttl_sw_action = sw_action; 1943 *modify_ttl = true; 1944 continue; 1945 } 1946 1947 /* Convert SW action to HW action */ 1948 ret = dr_action_modify_sw_to_hw(dmn, 1949 sw_action, 1950 &hw_action, 1951 &hw_dst_action_info, 1952 &hw_src_action_info); 1953 if (ret) 1954 return ret; 1955 1956 /* Due to a HW limitation we cannot modify 2 different L3 types */ 1957 if (l3_type && hw_dst_action_info->l3_type && 1958 hw_dst_action_info->l3_type != l3_type) { 1959 mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n"); 1960 return -EINVAL; 1961 } 1962 if (hw_dst_action_info->l3_type) 1963 l3_type = hw_dst_action_info->l3_type; 1964 1965 /* Due to a HW limitation we cannot modify two different L4 types */ 1966 if (l4_type && hw_dst_action_info->l4_type && 1967 hw_dst_action_info->l4_type != l4_type) { 1968 mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n"); 1969 return -EINVAL; 1970 } 1971 if (hw_dst_action_info->l4_type) 1972 l4_type = hw_dst_action_info->l4_type; 1973 1974 /* HW reads and executes two actions at once this means we 1975 * need to create a gap if two actions access the same field 1976 */ 1977 if ((hw_idx % 2) && (hw_field == hw_dst_action_info->hw_field || 1978 (hw_src_action_info && 1979 hw_field == hw_src_action_info->hw_field))) { 1980 /* Check if after gap insertion the total number of HW 1981 * modify actions doesn't exceeds the limit 1982 */ 1983 hw_idx++; 1984 if (hw_idx >= max_hw_actions) { 1985 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n"); 1986 return -EINVAL; 1987 } 1988 } 1989 hw_field = hw_dst_action_info->hw_field; 1990 1991 hw_actions[hw_idx] = hw_action; 1992 hw_idx++; 1993 } 1994 1995 /* if the resulting HW actions list is empty, add NOP action */ 1996 if (!hw_idx) 1997 hw_idx++; 1998 1999 *num_hw_actions = hw_idx; 2000 2001 return 0; 2002 } 2003 2004 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn, 2005 size_t actions_sz, 2006 __be64 actions[], 2007 struct mlx5dr_action *action) 2008 { 2009 u32 max_hw_actions; 2010 u32 num_hw_actions; 2011 u32 num_sw_actions; 2012 __be64 *hw_actions; 2013 bool modify_ttl; 2014 int ret; 2015 2016 num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE; 2017 max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16); 2018 2019 if (num_sw_actions > max_hw_actions) { 2020 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n", 2021 num_sw_actions, max_hw_actions); 2022 return -EINVAL; 2023 } 2024 2025 hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL); 2026 if (!hw_actions) 2027 return -ENOMEM; 2028 2029 ret = dr_actions_convert_modify_header(action, 2030 max_hw_actions, 2031 num_sw_actions, 2032 actions, 2033 hw_actions, 2034 &num_hw_actions, 2035 &modify_ttl); 2036 if (ret) 2037 goto free_hw_actions; 2038 2039 action->rewrite->modify_ttl = modify_ttl; 2040 action->rewrite->data = (u8 *)hw_actions; 2041 action->rewrite->num_of_actions = num_hw_actions; 2042 2043 if (num_hw_actions == 1 && 2044 dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) { 2045 action->rewrite->single_action_opt = true; 2046 } else { 2047 action->rewrite->single_action_opt = false; 2048 ret = mlx5dr_ste_alloc_modify_hdr(action); 2049 if (ret) 2050 goto free_hw_actions; 2051 } 2052 2053 return 0; 2054 2055 free_hw_actions: 2056 kfree(hw_actions); 2057 return ret; 2058 } 2059 2060 struct mlx5dr_action * 2061 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn, 2062 u32 flags, 2063 size_t actions_sz, 2064 __be64 actions[]) 2065 { 2066 struct mlx5dr_action *action; 2067 int ret = 0; 2068 2069 refcount_inc(&dmn->refcount); 2070 2071 if (actions_sz % DR_MODIFY_ACTION_SIZE) { 2072 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n"); 2073 goto dec_ref; 2074 } 2075 2076 action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR); 2077 if (!action) 2078 goto dec_ref; 2079 2080 action->rewrite->dmn = dmn; 2081 2082 ret = dr_action_create_modify_action(dmn, 2083 actions_sz, 2084 actions, 2085 action); 2086 if (ret) { 2087 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret); 2088 goto free_action; 2089 } 2090 2091 return action; 2092 2093 free_action: 2094 kfree(action); 2095 dec_ref: 2096 refcount_dec(&dmn->refcount); 2097 return NULL; 2098 } 2099 2100 struct mlx5dr_action * 2101 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn, 2102 u16 vport, u8 vhca_id_valid, 2103 u16 vhca_id) 2104 { 2105 struct mlx5dr_cmd_vport_cap *vport_cap; 2106 struct mlx5dr_domain *vport_dmn; 2107 struct mlx5dr_action *action; 2108 u8 peer_vport; 2109 2110 peer_vport = vhca_id_valid && mlx5_core_is_pf(dmn->mdev) && 2111 (vhca_id != dmn->info.caps.gvmi); 2112 vport_dmn = peer_vport ? xa_load(&dmn->peer_dmn_xa, vhca_id) : dmn; 2113 if (!vport_dmn) { 2114 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n"); 2115 return NULL; 2116 } 2117 2118 if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) { 2119 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n"); 2120 return NULL; 2121 } 2122 2123 vport_cap = mlx5dr_domain_get_vport_cap(vport_dmn, vport); 2124 if (!vport_cap) { 2125 mlx5dr_err(dmn, 2126 "Failed to get vport 0x%x caps - vport is disabled or invalid\n", 2127 vport); 2128 return NULL; 2129 } 2130 2131 action = dr_action_create_generic(DR_ACTION_TYP_VPORT); 2132 if (!action) 2133 return NULL; 2134 2135 action->vport->dmn = vport_dmn; 2136 action->vport->caps = vport_cap; 2137 2138 return action; 2139 } 2140 2141 struct mlx5dr_action * 2142 mlx5dr_action_create_aso(struct mlx5dr_domain *dmn, u32 obj_id, 2143 u8 dest_reg_id, u8 aso_type, 2144 u8 init_color, u8 meter_id) 2145 { 2146 struct mlx5dr_action *action; 2147 2148 if (aso_type != MLX5_EXE_ASO_FLOW_METER) 2149 return NULL; 2150 2151 if (init_color > MLX5_FLOW_METER_COLOR_UNDEFINED) 2152 return NULL; 2153 2154 action = dr_action_create_generic(DR_ACTION_TYP_ASO_FLOW_METER); 2155 if (!action) 2156 return NULL; 2157 2158 action->aso->obj_id = obj_id; 2159 action->aso->offset = meter_id; 2160 action->aso->dest_reg_id = dest_reg_id; 2161 action->aso->init_color = init_color; 2162 action->aso->dmn = dmn; 2163 2164 refcount_inc(&dmn->refcount); 2165 2166 return action; 2167 } 2168 2169 u32 mlx5dr_action_get_pkt_reformat_id(struct mlx5dr_action *action) 2170 { 2171 return action->reformat->id; 2172 } 2173 2174 int mlx5dr_action_destroy(struct mlx5dr_action *action) 2175 { 2176 if (WARN_ON_ONCE(refcount_read(&action->refcount) > 1)) 2177 return -EBUSY; 2178 2179 switch (action->action_type) { 2180 case DR_ACTION_TYP_FT: 2181 if (action->dest_tbl->is_fw_tbl) 2182 refcount_dec(&action->dest_tbl->fw_tbl.dmn->refcount); 2183 else 2184 refcount_dec(&action->dest_tbl->tbl->refcount); 2185 2186 if (action->dest_tbl->is_fw_tbl && 2187 action->dest_tbl->fw_tbl.num_of_ref_actions) { 2188 struct mlx5dr_action **ref_actions; 2189 int i; 2190 2191 ref_actions = action->dest_tbl->fw_tbl.ref_actions; 2192 for (i = 0; i < action->dest_tbl->fw_tbl.num_of_ref_actions; i++) 2193 refcount_dec(&ref_actions[i]->refcount); 2194 2195 kfree(ref_actions); 2196 2197 mlx5dr_fw_destroy_md_tbl(action->dest_tbl->fw_tbl.dmn, 2198 action->dest_tbl->fw_tbl.id, 2199 action->dest_tbl->fw_tbl.group_id); 2200 } 2201 break; 2202 case DR_ACTION_TYP_TNL_L2_TO_L2: 2203 case DR_ACTION_TYP_REMOVE_HDR: 2204 refcount_dec(&action->reformat->dmn->refcount); 2205 break; 2206 case DR_ACTION_TYP_TNL_L3_TO_L2: 2207 mlx5dr_ste_free_modify_hdr(action); 2208 kfree(action->rewrite->data); 2209 refcount_dec(&action->rewrite->dmn->refcount); 2210 break; 2211 case DR_ACTION_TYP_L2_TO_TNL_L2: 2212 case DR_ACTION_TYP_L2_TO_TNL_L3: 2213 case DR_ACTION_TYP_INSERT_HDR: 2214 mlx5dr_cmd_destroy_reformat_ctx((action->reformat->dmn)->mdev, 2215 action->reformat->id); 2216 refcount_dec(&action->reformat->dmn->refcount); 2217 break; 2218 case DR_ACTION_TYP_MODIFY_HDR: 2219 if (!action->rewrite->single_action_opt) 2220 mlx5dr_ste_free_modify_hdr(action); 2221 kfree(action->rewrite->data); 2222 refcount_dec(&action->rewrite->dmn->refcount); 2223 break; 2224 case DR_ACTION_TYP_SAMPLER: 2225 refcount_dec(&action->sampler->dmn->refcount); 2226 break; 2227 case DR_ACTION_TYP_ASO_FLOW_METER: 2228 refcount_dec(&action->aso->dmn->refcount); 2229 break; 2230 case DR_ACTION_TYP_RANGE: 2231 dr_action_destroy_range_definer(action); 2232 mlx5dr_action_destroy(action->range->miss_tbl_action); 2233 mlx5dr_action_destroy(action->range->hit_tbl_action); 2234 break; 2235 default: 2236 break; 2237 } 2238 2239 kfree(action); 2240 return 0; 2241 } 2242