1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/init.h> 36 #include <linux/errno.h> 37 #include <linux/pci.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/slab.h> 40 #include <linux/io-mapping.h> 41 #include <linux/interrupt.h> 42 #include <linux/delay.h> 43 #include <linux/mlx5/driver.h> 44 #include <linux/mlx5/cq.h> 45 #include <linux/mlx5/qp.h> 46 #include <linux/debugfs.h> 47 #include <linux/kmod.h> 48 #include <linux/mlx5/mlx5_ifc.h> 49 #include <linux/mlx5/vport.h> 50 #ifdef CONFIG_RFS_ACCEL 51 #include <linux/cpu_rmap.h> 52 #endif 53 #include <linux/version.h> 54 #include <net/devlink.h> 55 #include "mlx5_core.h" 56 #include "lib/eq.h" 57 #include "fs_core.h" 58 #include "lib/mpfs.h" 59 #include "eswitch.h" 60 #include "devlink.h" 61 #include "fw_reset.h" 62 #include "lib/mlx5.h" 63 #include "fpga/core.h" 64 #include "fpga/ipsec.h" 65 #include "accel/ipsec.h" 66 #include "accel/tls.h" 67 #include "lib/clock.h" 68 #include "lib/vxlan.h" 69 #include "lib/geneve.h" 70 #include "lib/devcom.h" 71 #include "lib/pci_vsc.h" 72 #include "diag/fw_tracer.h" 73 #include "ecpf.h" 74 #include "lib/hv_vhca.h" 75 #include "diag/rsc_dump.h" 76 #include "sf/vhca_event.h" 77 #include "sf/dev/dev.h" 78 #include "sf/sf.h" 79 80 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 81 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); 82 MODULE_LICENSE("Dual BSD/GPL"); 83 84 unsigned int mlx5_core_debug_mask; 85 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); 86 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 87 88 static unsigned int prof_sel = MLX5_DEFAULT_PROF; 89 module_param_named(prof_sel, prof_sel, uint, 0444); 90 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); 91 92 static u32 sw_owner_id[4]; 93 94 enum { 95 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97 }; 98 99 static struct mlx5_profile profile[] = { 100 [0] = { 101 .mask = 0, 102 }, 103 [1] = { 104 .mask = MLX5_PROF_MASK_QP_SIZE, 105 .log_max_qp = 12, 106 }, 107 [2] = { 108 .mask = MLX5_PROF_MASK_QP_SIZE | 109 MLX5_PROF_MASK_MR_CACHE, 110 .log_max_qp = 18, 111 .mr_cache[0] = { 112 .size = 500, 113 .limit = 250 114 }, 115 .mr_cache[1] = { 116 .size = 500, 117 .limit = 250 118 }, 119 .mr_cache[2] = { 120 .size = 500, 121 .limit = 250 122 }, 123 .mr_cache[3] = { 124 .size = 500, 125 .limit = 250 126 }, 127 .mr_cache[4] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[5] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[6] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[7] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[8] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[9] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[10] = { 152 .size = 500, 153 .limit = 250 154 }, 155 .mr_cache[11] = { 156 .size = 500, 157 .limit = 250 158 }, 159 .mr_cache[12] = { 160 .size = 64, 161 .limit = 32 162 }, 163 .mr_cache[13] = { 164 .size = 32, 165 .limit = 16 166 }, 167 .mr_cache[14] = { 168 .size = 16, 169 .limit = 8 170 }, 171 .mr_cache[15] = { 172 .size = 8, 173 .limit = 4 174 }, 175 }, 176 }; 177 178 #define FW_INIT_TIMEOUT_MILI 2000 179 #define FW_INIT_WAIT_MS 2 180 #define FW_PRE_INIT_TIMEOUT_MILI 120000 181 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 182 183 static int fw_initializing(struct mlx5_core_dev *dev) 184 { 185 return ioread32be(&dev->iseg->initializing) >> 31; 186 } 187 188 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 189 u32 warn_time_mili) 190 { 191 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); 192 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); 193 int err = 0; 194 195 BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); 196 197 while (fw_initializing(dev)) { 198 if (time_after(jiffies, end)) { 199 err = -EBUSY; 200 break; 201 } 202 if (warn_time_mili && time_after(jiffies, warn)) { 203 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", 204 jiffies_to_msecs(end - warn) / 1000); 205 warn = jiffies + msecs_to_jiffies(warn_time_mili); 206 } 207 msleep(FW_INIT_WAIT_MS); 208 } 209 210 return err; 211 } 212 213 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 214 { 215 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, 216 driver_version); 217 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 218 int remaining_size = driver_ver_sz; 219 char *string; 220 221 if (!MLX5_CAP_GEN(dev, driver_version)) 222 return; 223 224 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 225 226 strncpy(string, "Linux", remaining_size); 227 228 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 229 strncat(string, ",", remaining_size); 230 231 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 232 strncat(string, KBUILD_MODNAME, remaining_size); 233 234 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 235 strncat(string, ",", remaining_size); 236 237 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); 238 239 snprintf(string + strlen(string), remaining_size, "%u.%u.%u", 240 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, 241 LINUX_VERSION_SUBLEVEL); 242 243 /*Send the command*/ 244 MLX5_SET(set_driver_version_in, in, opcode, 245 MLX5_CMD_OP_SET_DRIVER_VERSION); 246 247 mlx5_cmd_exec_in(dev, set_driver_version, in); 248 } 249 250 static int set_dma_caps(struct pci_dev *pdev) 251 { 252 int err; 253 254 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 255 if (err) { 256 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 257 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 258 if (err) { 259 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 260 return err; 261 } 262 } 263 264 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 265 if (err) { 266 dev_warn(&pdev->dev, 267 "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); 268 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 269 if (err) { 270 dev_err(&pdev->dev, 271 "Can't set consistent PCI DMA mask, aborting\n"); 272 return err; 273 } 274 } 275 276 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 277 return err; 278 } 279 280 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 281 { 282 struct pci_dev *pdev = dev->pdev; 283 int err = 0; 284 285 mutex_lock(&dev->pci_status_mutex); 286 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 287 err = pci_enable_device(pdev); 288 if (!err) 289 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 290 } 291 mutex_unlock(&dev->pci_status_mutex); 292 293 return err; 294 } 295 296 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 297 { 298 struct pci_dev *pdev = dev->pdev; 299 300 mutex_lock(&dev->pci_status_mutex); 301 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 302 pci_disable_device(pdev); 303 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 304 } 305 mutex_unlock(&dev->pci_status_mutex); 306 } 307 308 static int request_bar(struct pci_dev *pdev) 309 { 310 int err = 0; 311 312 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 313 dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); 314 return -ENODEV; 315 } 316 317 err = pci_request_regions(pdev, KBUILD_MODNAME); 318 if (err) 319 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 320 321 return err; 322 } 323 324 static void release_bar(struct pci_dev *pdev) 325 { 326 pci_release_regions(pdev); 327 } 328 329 struct mlx5_reg_host_endianness { 330 u8 he; 331 u8 rsvd[15]; 332 }; 333 334 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 335 336 enum { 337 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 338 MLX5_DEV_CAP_FLAG_DCT, 339 }; 340 341 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 342 { 343 switch (size) { 344 case 128: 345 return 0; 346 case 256: 347 return 1; 348 case 512: 349 return 2; 350 case 1024: 351 return 3; 352 case 2048: 353 return 4; 354 case 4096: 355 return 5; 356 default: 357 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 358 return 0; 359 } 360 } 361 362 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 363 enum mlx5_cap_type cap_type, 364 enum mlx5_cap_mode cap_mode) 365 { 366 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 367 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 368 void *out, *hca_caps; 369 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 370 int err; 371 372 memset(in, 0, sizeof(in)); 373 out = kzalloc(out_sz, GFP_KERNEL); 374 if (!out) 375 return -ENOMEM; 376 377 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 378 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 379 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); 380 if (err) { 381 mlx5_core_warn(dev, 382 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 383 cap_type, cap_mode, err); 384 goto query_ex; 385 } 386 387 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 388 389 switch (cap_mode) { 390 case HCA_CAP_OPMOD_GET_MAX: 391 memcpy(dev->caps.hca_max[cap_type], hca_caps, 392 MLX5_UN_SZ_BYTES(hca_cap_union)); 393 break; 394 case HCA_CAP_OPMOD_GET_CUR: 395 memcpy(dev->caps.hca_cur[cap_type], hca_caps, 396 MLX5_UN_SZ_BYTES(hca_cap_union)); 397 break; 398 default: 399 mlx5_core_warn(dev, 400 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 401 cap_type, cap_mode); 402 err = -EINVAL; 403 break; 404 } 405 query_ex: 406 kfree(out); 407 return err; 408 } 409 410 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 411 { 412 int ret; 413 414 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 415 if (ret) 416 return ret; 417 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 418 } 419 420 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) 421 { 422 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 423 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); 424 return mlx5_cmd_exec_in(dev, set_hca_cap, in); 425 } 426 427 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) 428 { 429 void *set_hca_cap; 430 int req_endianness; 431 int err; 432 433 if (!MLX5_CAP_GEN(dev, atomic)) 434 return 0; 435 436 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 437 if (err) 438 return err; 439 440 req_endianness = 441 MLX5_CAP_ATOMIC(dev, 442 supported_atomic_req_8B_endianness_mode_1); 443 444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 445 return 0; 446 447 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 448 449 /* Set requestor to host endianness */ 450 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, 451 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 452 453 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); 454 } 455 456 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) 457 { 458 void *set_hca_cap; 459 bool do_set = false; 460 int err; 461 462 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || 463 !MLX5_CAP_GEN(dev, pg)) 464 return 0; 465 466 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 467 if (err) 468 return err; 469 470 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 471 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], 472 MLX5_ST_SZ_BYTES(odp_cap)); 473 474 #define ODP_CAP_SET_MAX(dev, field) \ 475 do { \ 476 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ 477 if (_res) { \ 478 do_set = true; \ 479 MLX5_SET(odp_cap, set_hca_cap, field, _res); \ 480 } \ 481 } while (0) 482 483 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); 484 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); 485 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); 486 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); 487 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); 488 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); 489 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); 490 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); 491 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); 492 ODP_CAP_SET_MAX(dev, dc_odp_caps.send); 493 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); 494 ODP_CAP_SET_MAX(dev, dc_odp_caps.write); 495 ODP_CAP_SET_MAX(dev, dc_odp_caps.read); 496 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); 497 498 if (!do_set) 499 return 0; 500 501 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); 502 } 503 504 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) 505 { 506 struct mlx5_profile *prof = dev->profile; 507 void *set_hca_cap; 508 int err; 509 510 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 511 if (err) 512 return err; 513 514 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 515 capability); 516 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], 517 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 518 519 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 520 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 521 128); 522 /* we limit the size of the pkey table to 128 entries for now */ 523 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 524 to_fw_pkey_sz(dev, 128)); 525 526 /* Check log_max_qp from HCA caps to set in current profile */ 527 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { 528 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", 529 profile[prof_sel].log_max_qp, 530 MLX5_CAP_GEN_MAX(dev, log_max_qp)); 531 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); 532 } 533 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 534 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 535 prof->log_max_qp); 536 537 /* disable cmdif checksum */ 538 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 539 540 /* Enable 4K UAR only when HCA supports it and page size is bigger 541 * than 4K. 542 */ 543 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 544 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 545 546 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 547 548 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) 549 MLX5_SET(cmd_hca_cap, 550 set_hca_cap, 551 cache_line_128byte, 552 cache_line_size() >= 128 ? 1 : 0); 553 554 if (MLX5_CAP_GEN_MAX(dev, dct)) 555 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); 556 557 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) 558 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); 559 560 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) 561 MLX5_SET(cmd_hca_cap, 562 set_hca_cap, 563 num_vhca_ports, 564 MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); 565 566 if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) 567 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); 568 569 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) 570 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); 571 572 mlx5_vhca_state_cap_handle(dev, set_hca_cap); 573 574 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); 575 } 576 577 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) 578 { 579 void *set_hca_cap; 580 int err; 581 582 if (!MLX5_CAP_GEN(dev, roce)) 583 return 0; 584 585 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 586 if (err) 587 return err; 588 589 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || 590 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) 591 return 0; 592 593 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 594 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], 595 MLX5_ST_SZ_BYTES(roce_cap)); 596 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); 597 598 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); 599 return err; 600 } 601 602 static int set_hca_cap(struct mlx5_core_dev *dev) 603 { 604 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 605 void *set_ctx; 606 int err; 607 608 set_ctx = kzalloc(set_sz, GFP_KERNEL); 609 if (!set_ctx) 610 return -ENOMEM; 611 612 err = handle_hca_cap(dev, set_ctx); 613 if (err) { 614 mlx5_core_err(dev, "handle_hca_cap failed\n"); 615 goto out; 616 } 617 618 memset(set_ctx, 0, set_sz); 619 err = handle_hca_cap_atomic(dev, set_ctx); 620 if (err) { 621 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 622 goto out; 623 } 624 625 memset(set_ctx, 0, set_sz); 626 err = handle_hca_cap_odp(dev, set_ctx); 627 if (err) { 628 mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); 629 goto out; 630 } 631 632 memset(set_ctx, 0, set_sz); 633 err = handle_hca_cap_roce(dev, set_ctx); 634 if (err) { 635 mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); 636 goto out; 637 } 638 639 out: 640 kfree(set_ctx); 641 return err; 642 } 643 644 static int set_hca_ctrl(struct mlx5_core_dev *dev) 645 { 646 struct mlx5_reg_host_endianness he_in; 647 struct mlx5_reg_host_endianness he_out; 648 int err; 649 650 if (!mlx5_core_is_pf(dev)) 651 return 0; 652 653 memset(&he_in, 0, sizeof(he_in)); 654 he_in.he = MLX5_SET_HOST_ENDIANNESS; 655 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 656 &he_out, sizeof(he_out), 657 MLX5_REG_HOST_ENDIANNESS, 0, 1); 658 return err; 659 } 660 661 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 662 { 663 int ret = 0; 664 665 /* Disable local_lb by default */ 666 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 667 ret = mlx5_nic_vport_update_local_lb(dev, false); 668 669 return ret; 670 } 671 672 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 673 { 674 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; 675 676 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 677 MLX5_SET(enable_hca_in, in, function_id, func_id); 678 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 679 dev->caps.embedded_cpu); 680 return mlx5_cmd_exec_in(dev, enable_hca, in); 681 } 682 683 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) 684 { 685 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; 686 687 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 688 MLX5_SET(disable_hca_in, in, function_id, func_id); 689 MLX5_SET(enable_hca_in, in, embedded_cpu_function, 690 dev->caps.embedded_cpu); 691 return mlx5_cmd_exec_in(dev, disable_hca, in); 692 } 693 694 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 695 { 696 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; 697 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; 698 u32 sup_issi; 699 int err; 700 701 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 702 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); 703 if (err) { 704 u32 syndrome; 705 u8 status; 706 707 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 708 if (!status || syndrome == MLX5_DRIVER_SYND) { 709 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", 710 err, status, syndrome); 711 return err; 712 } 713 714 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); 715 dev->issi = 0; 716 return 0; 717 } 718 719 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 720 721 if (sup_issi & (1 << 1)) { 722 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; 723 724 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 725 MLX5_SET(set_issi_in, set_in, current_issi, 1); 726 err = mlx5_cmd_exec_in(dev, set_issi, set_in); 727 if (err) { 728 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", 729 err); 730 return err; 731 } 732 733 dev->issi = 1; 734 735 return 0; 736 } else if (sup_issi & (1 << 0) || !sup_issi) { 737 return 0; 738 } 739 740 return -EOPNOTSUPP; 741 } 742 743 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, 744 const struct pci_device_id *id) 745 { 746 struct mlx5_priv *priv = &dev->priv; 747 int err = 0; 748 749 mutex_init(&dev->pci_status_mutex); 750 pci_set_drvdata(dev->pdev, dev); 751 752 dev->bar_addr = pci_resource_start(pdev, 0); 753 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); 754 755 err = mlx5_pci_enable_device(dev); 756 if (err) { 757 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 758 return err; 759 } 760 761 err = request_bar(pdev); 762 if (err) { 763 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 764 goto err_disable; 765 } 766 767 pci_set_master(pdev); 768 769 err = set_dma_caps(pdev); 770 if (err) { 771 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 772 goto err_clr_master; 773 } 774 775 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && 776 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && 777 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) 778 mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); 779 780 dev->iseg_base = dev->bar_addr; 781 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 782 if (!dev->iseg) { 783 err = -ENOMEM; 784 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 785 goto err_clr_master; 786 } 787 788 mlx5_pci_vsc_init(dev); 789 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); 790 return 0; 791 792 err_clr_master: 793 pci_clear_master(dev->pdev); 794 release_bar(dev->pdev); 795 err_disable: 796 mlx5_pci_disable_device(dev); 797 return err; 798 } 799 800 static void mlx5_pci_close(struct mlx5_core_dev *dev) 801 { 802 /* health work might still be active, and it needs pci bar in 803 * order to know the NIC state. Therefore, drain the health WQ 804 * before removing the pci bars 805 */ 806 mlx5_drain_health_wq(dev); 807 iounmap(dev->iseg); 808 pci_clear_master(dev->pdev); 809 release_bar(dev->pdev); 810 mlx5_pci_disable_device(dev); 811 } 812 813 static int mlx5_init_once(struct mlx5_core_dev *dev) 814 { 815 int err; 816 817 dev->priv.devcom = mlx5_devcom_register_device(dev); 818 if (IS_ERR(dev->priv.devcom)) 819 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", 820 dev->priv.devcom); 821 822 err = mlx5_query_board_id(dev); 823 if (err) { 824 mlx5_core_err(dev, "query board id failed\n"); 825 goto err_devcom; 826 } 827 828 err = mlx5_irq_table_init(dev); 829 if (err) { 830 mlx5_core_err(dev, "failed to initialize irq table\n"); 831 goto err_devcom; 832 } 833 834 err = mlx5_eq_table_init(dev); 835 if (err) { 836 mlx5_core_err(dev, "failed to initialize eq\n"); 837 goto err_irq_cleanup; 838 } 839 840 err = mlx5_events_init(dev); 841 if (err) { 842 mlx5_core_err(dev, "failed to initialize events\n"); 843 goto err_eq_cleanup; 844 } 845 846 err = mlx5_fw_reset_init(dev); 847 if (err) { 848 mlx5_core_err(dev, "failed to initialize fw reset events\n"); 849 goto err_events_cleanup; 850 } 851 852 mlx5_cq_debugfs_init(dev); 853 854 mlx5_init_reserved_gids(dev); 855 856 mlx5_init_clock(dev); 857 858 dev->vxlan = mlx5_vxlan_create(dev); 859 dev->geneve = mlx5_geneve_create(dev); 860 861 err = mlx5_init_rl_table(dev); 862 if (err) { 863 mlx5_core_err(dev, "Failed to init rate limiting\n"); 864 goto err_tables_cleanup; 865 } 866 867 err = mlx5_mpfs_init(dev); 868 if (err) { 869 mlx5_core_err(dev, "Failed to init l2 table %d\n", err); 870 goto err_rl_cleanup; 871 } 872 873 err = mlx5_sriov_init(dev); 874 if (err) { 875 mlx5_core_err(dev, "Failed to init sriov %d\n", err); 876 goto err_mpfs_cleanup; 877 } 878 879 err = mlx5_eswitch_init(dev); 880 if (err) { 881 mlx5_core_err(dev, "Failed to init eswitch %d\n", err); 882 goto err_sriov_cleanup; 883 } 884 885 err = mlx5_fpga_init(dev); 886 if (err) { 887 mlx5_core_err(dev, "Failed to init fpga device %d\n", err); 888 goto err_eswitch_cleanup; 889 } 890 891 err = mlx5_vhca_event_init(dev); 892 if (err) { 893 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); 894 goto err_fpga_cleanup; 895 } 896 897 err = mlx5_sf_hw_table_init(dev); 898 if (err) { 899 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); 900 goto err_sf_hw_table_cleanup; 901 } 902 903 err = mlx5_sf_table_init(dev); 904 if (err) { 905 mlx5_core_err(dev, "Failed to init SF table %d\n", err); 906 goto err_sf_table_cleanup; 907 } 908 909 dev->dm = mlx5_dm_create(dev); 910 if (IS_ERR(dev->dm)) 911 mlx5_core_warn(dev, "Failed to init device memory%d\n", err); 912 913 dev->tracer = mlx5_fw_tracer_create(dev); 914 dev->hv_vhca = mlx5_hv_vhca_create(dev); 915 dev->rsc_dump = mlx5_rsc_dump_create(dev); 916 917 return 0; 918 919 err_sf_table_cleanup: 920 mlx5_sf_hw_table_cleanup(dev); 921 err_sf_hw_table_cleanup: 922 mlx5_vhca_event_cleanup(dev); 923 err_fpga_cleanup: 924 mlx5_fpga_cleanup(dev); 925 err_eswitch_cleanup: 926 mlx5_eswitch_cleanup(dev->priv.eswitch); 927 err_sriov_cleanup: 928 mlx5_sriov_cleanup(dev); 929 err_mpfs_cleanup: 930 mlx5_mpfs_cleanup(dev); 931 err_rl_cleanup: 932 mlx5_cleanup_rl_table(dev); 933 err_tables_cleanup: 934 mlx5_geneve_destroy(dev->geneve); 935 mlx5_vxlan_destroy(dev->vxlan); 936 mlx5_cq_debugfs_cleanup(dev); 937 mlx5_fw_reset_cleanup(dev); 938 err_events_cleanup: 939 mlx5_events_cleanup(dev); 940 err_eq_cleanup: 941 mlx5_eq_table_cleanup(dev); 942 err_irq_cleanup: 943 mlx5_irq_table_cleanup(dev); 944 err_devcom: 945 mlx5_devcom_unregister_device(dev->priv.devcom); 946 947 return err; 948 } 949 950 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 951 { 952 mlx5_rsc_dump_destroy(dev); 953 mlx5_hv_vhca_destroy(dev->hv_vhca); 954 mlx5_fw_tracer_destroy(dev->tracer); 955 mlx5_dm_cleanup(dev); 956 mlx5_sf_table_cleanup(dev); 957 mlx5_sf_hw_table_cleanup(dev); 958 mlx5_vhca_event_cleanup(dev); 959 mlx5_fpga_cleanup(dev); 960 mlx5_eswitch_cleanup(dev->priv.eswitch); 961 mlx5_sriov_cleanup(dev); 962 mlx5_mpfs_cleanup(dev); 963 mlx5_cleanup_rl_table(dev); 964 mlx5_geneve_destroy(dev->geneve); 965 mlx5_vxlan_destroy(dev->vxlan); 966 mlx5_cleanup_clock(dev); 967 mlx5_cleanup_reserved_gids(dev); 968 mlx5_cq_debugfs_cleanup(dev); 969 mlx5_fw_reset_cleanup(dev); 970 mlx5_events_cleanup(dev); 971 mlx5_eq_table_cleanup(dev); 972 mlx5_irq_table_cleanup(dev); 973 mlx5_devcom_unregister_device(dev->priv.devcom); 974 } 975 976 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) 977 { 978 int err; 979 980 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), 981 fw_rev_min(dev), fw_rev_sub(dev)); 982 983 /* Only PFs hold the relevant PCIe information for this query */ 984 if (mlx5_core_is_pf(dev)) 985 pcie_print_link_status(dev->pdev); 986 987 /* wait for firmware to accept initialization segments configurations 988 */ 989 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); 990 if (err) { 991 mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", 992 FW_PRE_INIT_TIMEOUT_MILI); 993 return err; 994 } 995 996 err = mlx5_cmd_init(dev); 997 if (err) { 998 mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); 999 return err; 1000 } 1001 1002 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1003 if (err) { 1004 mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", 1005 FW_INIT_TIMEOUT_MILI); 1006 goto err_cmd_cleanup; 1007 } 1008 1009 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); 1010 1011 err = mlx5_core_enable_hca(dev, 0); 1012 if (err) { 1013 mlx5_core_err(dev, "enable hca failed\n"); 1014 goto err_cmd_cleanup; 1015 } 1016 1017 err = mlx5_core_set_issi(dev); 1018 if (err) { 1019 mlx5_core_err(dev, "failed to set issi\n"); 1020 goto err_disable_hca; 1021 } 1022 1023 err = mlx5_satisfy_startup_pages(dev, 1); 1024 if (err) { 1025 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1026 goto err_disable_hca; 1027 } 1028 1029 err = set_hca_ctrl(dev); 1030 if (err) { 1031 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1032 goto reclaim_boot_pages; 1033 } 1034 1035 err = set_hca_cap(dev); 1036 if (err) { 1037 mlx5_core_err(dev, "set_hca_cap failed\n"); 1038 goto reclaim_boot_pages; 1039 } 1040 1041 err = mlx5_satisfy_startup_pages(dev, 0); 1042 if (err) { 1043 mlx5_core_err(dev, "failed to allocate init pages\n"); 1044 goto reclaim_boot_pages; 1045 } 1046 1047 err = mlx5_cmd_init_hca(dev, sw_owner_id); 1048 if (err) { 1049 mlx5_core_err(dev, "init hca failed\n"); 1050 goto reclaim_boot_pages; 1051 } 1052 1053 mlx5_set_driver_version(dev); 1054 1055 mlx5_start_health_poll(dev); 1056 1057 err = mlx5_query_hca_caps(dev); 1058 if (err) { 1059 mlx5_core_err(dev, "query hca failed\n"); 1060 goto stop_health; 1061 } 1062 1063 return 0; 1064 1065 stop_health: 1066 mlx5_stop_health_poll(dev, boot); 1067 reclaim_boot_pages: 1068 mlx5_reclaim_startup_pages(dev); 1069 err_disable_hca: 1070 mlx5_core_disable_hca(dev, 0); 1071 err_cmd_cleanup: 1072 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1073 mlx5_cmd_cleanup(dev); 1074 1075 return err; 1076 } 1077 1078 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) 1079 { 1080 int err; 1081 1082 mlx5_stop_health_poll(dev, boot); 1083 err = mlx5_cmd_teardown_hca(dev); 1084 if (err) { 1085 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1086 return err; 1087 } 1088 mlx5_reclaim_startup_pages(dev); 1089 mlx5_core_disable_hca(dev, 0); 1090 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); 1091 mlx5_cmd_cleanup(dev); 1092 1093 return 0; 1094 } 1095 1096 static int mlx5_load(struct mlx5_core_dev *dev) 1097 { 1098 int err; 1099 1100 dev->priv.uar = mlx5_get_uars_page(dev); 1101 if (IS_ERR(dev->priv.uar)) { 1102 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1103 err = PTR_ERR(dev->priv.uar); 1104 return err; 1105 } 1106 1107 mlx5_events_start(dev); 1108 mlx5_pagealloc_start(dev); 1109 1110 err = mlx5_irq_table_create(dev); 1111 if (err) { 1112 mlx5_core_err(dev, "Failed to alloc IRQs\n"); 1113 goto err_irq_table; 1114 } 1115 1116 err = mlx5_eq_table_create(dev); 1117 if (err) { 1118 mlx5_core_err(dev, "Failed to create EQs\n"); 1119 goto err_eq_table; 1120 } 1121 1122 err = mlx5_fw_tracer_init(dev->tracer); 1123 if (err) { 1124 mlx5_core_err(dev, "Failed to init FW tracer\n"); 1125 goto err_fw_tracer; 1126 } 1127 1128 mlx5_fw_reset_events_start(dev); 1129 mlx5_hv_vhca_init(dev->hv_vhca); 1130 1131 err = mlx5_rsc_dump_init(dev); 1132 if (err) { 1133 mlx5_core_err(dev, "Failed to init Resource dump\n"); 1134 goto err_rsc_dump; 1135 } 1136 1137 err = mlx5_fpga_device_start(dev); 1138 if (err) { 1139 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1140 goto err_fpga_start; 1141 } 1142 1143 mlx5_accel_ipsec_init(dev); 1144 1145 err = mlx5_accel_tls_init(dev); 1146 if (err) { 1147 mlx5_core_err(dev, "TLS device start failed %d\n", err); 1148 goto err_tls_start; 1149 } 1150 1151 err = mlx5_init_fs(dev); 1152 if (err) { 1153 mlx5_core_err(dev, "Failed to init flow steering\n"); 1154 goto err_fs; 1155 } 1156 1157 err = mlx5_core_set_hca_defaults(dev); 1158 if (err) { 1159 mlx5_core_err(dev, "Failed to set hca defaults\n"); 1160 goto err_sriov; 1161 } 1162 1163 mlx5_vhca_event_start(dev); 1164 1165 err = mlx5_sf_hw_table_create(dev); 1166 if (err) { 1167 mlx5_core_err(dev, "sf table create failed %d\n", err); 1168 goto err_vhca; 1169 } 1170 1171 err = mlx5_ec_init(dev); 1172 if (err) { 1173 mlx5_core_err(dev, "Failed to init embedded CPU\n"); 1174 goto err_ec; 1175 } 1176 1177 err = mlx5_sriov_attach(dev); 1178 if (err) { 1179 mlx5_core_err(dev, "sriov init failed %d\n", err); 1180 goto err_sriov; 1181 } 1182 1183 mlx5_sf_dev_table_create(dev); 1184 1185 return 0; 1186 1187 err_sriov: 1188 mlx5_ec_cleanup(dev); 1189 err_ec: 1190 mlx5_sf_hw_table_destroy(dev); 1191 err_vhca: 1192 mlx5_vhca_event_stop(dev); 1193 mlx5_cleanup_fs(dev); 1194 err_fs: 1195 mlx5_accel_tls_cleanup(dev); 1196 err_tls_start: 1197 mlx5_accel_ipsec_cleanup(dev); 1198 mlx5_fpga_device_stop(dev); 1199 err_fpga_start: 1200 mlx5_rsc_dump_cleanup(dev); 1201 err_rsc_dump: 1202 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1203 mlx5_fw_reset_events_stop(dev); 1204 mlx5_fw_tracer_cleanup(dev->tracer); 1205 err_fw_tracer: 1206 mlx5_eq_table_destroy(dev); 1207 err_eq_table: 1208 mlx5_irq_table_destroy(dev); 1209 err_irq_table: 1210 mlx5_pagealloc_stop(dev); 1211 mlx5_events_stop(dev); 1212 mlx5_put_uars_page(dev, dev->priv.uar); 1213 return err; 1214 } 1215 1216 static void mlx5_unload(struct mlx5_core_dev *dev) 1217 { 1218 mlx5_sf_dev_table_destroy(dev); 1219 mlx5_sriov_detach(dev); 1220 mlx5_ec_cleanup(dev); 1221 mlx5_sf_hw_table_destroy(dev); 1222 mlx5_vhca_event_stop(dev); 1223 mlx5_cleanup_fs(dev); 1224 mlx5_accel_ipsec_cleanup(dev); 1225 mlx5_accel_tls_cleanup(dev); 1226 mlx5_fpga_device_stop(dev); 1227 mlx5_rsc_dump_cleanup(dev); 1228 mlx5_hv_vhca_cleanup(dev->hv_vhca); 1229 mlx5_fw_reset_events_stop(dev); 1230 mlx5_fw_tracer_cleanup(dev->tracer); 1231 mlx5_eq_table_destroy(dev); 1232 mlx5_irq_table_destroy(dev); 1233 mlx5_pagealloc_stop(dev); 1234 mlx5_events_stop(dev); 1235 mlx5_put_uars_page(dev, dev->priv.uar); 1236 } 1237 1238 int mlx5_init_one(struct mlx5_core_dev *dev) 1239 { 1240 int err = 0; 1241 1242 mutex_lock(&dev->intf_state_mutex); 1243 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1244 mlx5_core_warn(dev, "interface is up, NOP\n"); 1245 goto out; 1246 } 1247 /* remove any previous indication of internal error */ 1248 dev->state = MLX5_DEVICE_STATE_UP; 1249 1250 err = mlx5_function_setup(dev, true); 1251 if (err) 1252 goto err_function; 1253 1254 err = mlx5_init_once(dev); 1255 if (err) { 1256 mlx5_core_err(dev, "sw objs init failed\n"); 1257 goto function_teardown; 1258 } 1259 1260 err = mlx5_load(dev); 1261 if (err) 1262 goto err_load; 1263 1264 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1265 1266 err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); 1267 if (err) 1268 goto err_devlink_reg; 1269 1270 err = mlx5_register_device(dev); 1271 if (err) 1272 goto err_register; 1273 1274 mutex_unlock(&dev->intf_state_mutex); 1275 return 0; 1276 1277 err_register: 1278 mlx5_devlink_unregister(priv_to_devlink(dev)); 1279 err_devlink_reg: 1280 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1281 mlx5_unload(dev); 1282 err_load: 1283 mlx5_cleanup_once(dev); 1284 function_teardown: 1285 mlx5_function_teardown(dev, true); 1286 err_function: 1287 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1288 out: 1289 mutex_unlock(&dev->intf_state_mutex); 1290 return err; 1291 } 1292 1293 void mlx5_uninit_one(struct mlx5_core_dev *dev) 1294 { 1295 mutex_lock(&dev->intf_state_mutex); 1296 1297 mlx5_unregister_device(dev); 1298 mlx5_devlink_unregister(priv_to_devlink(dev)); 1299 1300 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1301 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1302 __func__); 1303 mlx5_cleanup_once(dev); 1304 goto out; 1305 } 1306 1307 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1308 mlx5_unload(dev); 1309 mlx5_cleanup_once(dev); 1310 mlx5_function_teardown(dev, true); 1311 out: 1312 mutex_unlock(&dev->intf_state_mutex); 1313 } 1314 1315 int mlx5_load_one(struct mlx5_core_dev *dev) 1316 { 1317 int err = 0; 1318 1319 mutex_lock(&dev->intf_state_mutex); 1320 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1321 mlx5_core_warn(dev, "interface is up, NOP\n"); 1322 goto out; 1323 } 1324 /* remove any previous indication of internal error */ 1325 dev->state = MLX5_DEVICE_STATE_UP; 1326 1327 err = mlx5_function_setup(dev, false); 1328 if (err) 1329 goto err_function; 1330 1331 err = mlx5_load(dev); 1332 if (err) 1333 goto err_load; 1334 1335 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1336 1337 err = mlx5_attach_device(dev); 1338 if (err) 1339 goto err_attach; 1340 1341 mutex_unlock(&dev->intf_state_mutex); 1342 return 0; 1343 1344 err_attach: 1345 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1346 mlx5_unload(dev); 1347 err_load: 1348 mlx5_function_teardown(dev, false); 1349 err_function: 1350 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1351 out: 1352 mutex_unlock(&dev->intf_state_mutex); 1353 return err; 1354 } 1355 1356 void mlx5_unload_one(struct mlx5_core_dev *dev) 1357 { 1358 mutex_lock(&dev->intf_state_mutex); 1359 1360 mlx5_detach_device(dev); 1361 1362 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1363 mlx5_core_warn(dev, "%s: interface is down, NOP\n", 1364 __func__); 1365 goto out; 1366 } 1367 1368 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1369 mlx5_unload(dev); 1370 mlx5_function_teardown(dev, false); 1371 out: 1372 mutex_unlock(&dev->intf_state_mutex); 1373 } 1374 1375 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) 1376 { 1377 struct mlx5_priv *priv = &dev->priv; 1378 int err; 1379 1380 dev->profile = &profile[profile_idx]; 1381 1382 INIT_LIST_HEAD(&priv->ctx_list); 1383 spin_lock_init(&priv->ctx_lock); 1384 mutex_init(&dev->intf_state_mutex); 1385 1386 mutex_init(&priv->bfregs.reg_head.lock); 1387 mutex_init(&priv->bfregs.wc_head.lock); 1388 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1389 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1390 1391 mutex_init(&priv->alloc_mutex); 1392 mutex_init(&priv->pgdir_mutex); 1393 INIT_LIST_HEAD(&priv->pgdir_list); 1394 1395 priv->dbg_root = debugfs_create_dir(dev_name(dev->device), 1396 mlx5_debugfs_root); 1397 INIT_LIST_HEAD(&priv->traps); 1398 1399 err = mlx5_health_init(dev); 1400 if (err) 1401 goto err_health_init; 1402 1403 err = mlx5_pagealloc_init(dev); 1404 if (err) 1405 goto err_pagealloc_init; 1406 1407 err = mlx5_adev_init(dev); 1408 if (err) 1409 goto err_adev_init; 1410 1411 return 0; 1412 1413 err_adev_init: 1414 mlx5_pagealloc_cleanup(dev); 1415 err_pagealloc_init: 1416 mlx5_health_cleanup(dev); 1417 err_health_init: 1418 debugfs_remove(dev->priv.dbg_root); 1419 mutex_destroy(&priv->pgdir_mutex); 1420 mutex_destroy(&priv->alloc_mutex); 1421 mutex_destroy(&priv->bfregs.wc_head.lock); 1422 mutex_destroy(&priv->bfregs.reg_head.lock); 1423 mutex_destroy(&dev->intf_state_mutex); 1424 return err; 1425 } 1426 1427 void mlx5_mdev_uninit(struct mlx5_core_dev *dev) 1428 { 1429 struct mlx5_priv *priv = &dev->priv; 1430 1431 mlx5_adev_cleanup(dev); 1432 mlx5_pagealloc_cleanup(dev); 1433 mlx5_health_cleanup(dev); 1434 debugfs_remove_recursive(dev->priv.dbg_root); 1435 mutex_destroy(&priv->pgdir_mutex); 1436 mutex_destroy(&priv->alloc_mutex); 1437 mutex_destroy(&priv->bfregs.wc_head.lock); 1438 mutex_destroy(&priv->bfregs.reg_head.lock); 1439 mutex_destroy(&dev->intf_state_mutex); 1440 } 1441 1442 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 1443 { 1444 struct mlx5_core_dev *dev; 1445 struct devlink *devlink; 1446 int err; 1447 1448 devlink = mlx5_devlink_alloc(); 1449 if (!devlink) { 1450 dev_err(&pdev->dev, "devlink alloc failed\n"); 1451 return -ENOMEM; 1452 } 1453 1454 dev = devlink_priv(devlink); 1455 dev->device = &pdev->dev; 1456 dev->pdev = pdev; 1457 1458 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? 1459 MLX5_COREDEV_VF : MLX5_COREDEV_PF; 1460 1461 dev->priv.adev_idx = mlx5_adev_idx_alloc(); 1462 if (dev->priv.adev_idx < 0) { 1463 err = dev->priv.adev_idx; 1464 goto adev_init_err; 1465 } 1466 1467 err = mlx5_mdev_init(dev, prof_sel); 1468 if (err) 1469 goto mdev_init_err; 1470 1471 err = mlx5_pci_init(dev, pdev, id); 1472 if (err) { 1473 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", 1474 err); 1475 goto pci_init_err; 1476 } 1477 1478 err = mlx5_init_one(dev); 1479 if (err) { 1480 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", 1481 err); 1482 goto err_init_one; 1483 } 1484 1485 err = mlx5_crdump_enable(dev); 1486 if (err) 1487 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); 1488 1489 pci_save_state(pdev); 1490 if (!mlx5_core_is_mp_slave(dev)) 1491 devlink_reload_enable(devlink); 1492 return 0; 1493 1494 err_init_one: 1495 mlx5_pci_close(dev); 1496 pci_init_err: 1497 mlx5_mdev_uninit(dev); 1498 mdev_init_err: 1499 mlx5_adev_idx_free(dev->priv.adev_idx); 1500 adev_init_err: 1501 mlx5_devlink_free(devlink); 1502 1503 return err; 1504 } 1505 1506 static void remove_one(struct pci_dev *pdev) 1507 { 1508 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1509 struct devlink *devlink = priv_to_devlink(dev); 1510 1511 devlink_reload_disable(devlink); 1512 mlx5_crdump_disable(dev); 1513 mlx5_drain_health_wq(dev); 1514 mlx5_uninit_one(dev); 1515 mlx5_pci_close(dev); 1516 mlx5_mdev_uninit(dev); 1517 mlx5_adev_idx_free(dev->priv.adev_idx); 1518 mlx5_devlink_free(devlink); 1519 } 1520 1521 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1522 pci_channel_state_t state) 1523 { 1524 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1525 1526 mlx5_core_info(dev, "%s was called\n", __func__); 1527 1528 mlx5_enter_error_state(dev, false); 1529 mlx5_error_sw_reset(dev); 1530 mlx5_unload_one(dev); 1531 mlx5_drain_health_wq(dev); 1532 mlx5_pci_disable_device(dev); 1533 1534 return state == pci_channel_io_perm_failure ? 1535 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1536 } 1537 1538 /* wait for the device to show vital signs by waiting 1539 * for the health counter to start counting. 1540 */ 1541 static int wait_vital(struct pci_dev *pdev) 1542 { 1543 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1544 struct mlx5_core_health *health = &dev->priv.health; 1545 const int niter = 100; 1546 u32 last_count = 0; 1547 u32 count; 1548 int i; 1549 1550 for (i = 0; i < niter; i++) { 1551 count = ioread32be(health->health_counter); 1552 if (count && count != 0xffffffff) { 1553 if (last_count && last_count != count) { 1554 mlx5_core_info(dev, 1555 "wait vital counter value 0x%x after %d iterations\n", 1556 count, i); 1557 return 0; 1558 } 1559 last_count = count; 1560 } 1561 msleep(50); 1562 } 1563 1564 return -ETIMEDOUT; 1565 } 1566 1567 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1568 { 1569 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1570 int err; 1571 1572 mlx5_core_info(dev, "%s was called\n", __func__); 1573 1574 err = mlx5_pci_enable_device(dev); 1575 if (err) { 1576 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", 1577 __func__, err); 1578 return PCI_ERS_RESULT_DISCONNECT; 1579 } 1580 1581 pci_set_master(pdev); 1582 pci_restore_state(pdev); 1583 pci_save_state(pdev); 1584 1585 if (wait_vital(pdev)) { 1586 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); 1587 return PCI_ERS_RESULT_DISCONNECT; 1588 } 1589 1590 return PCI_ERS_RESULT_RECOVERED; 1591 } 1592 1593 static void mlx5_pci_resume(struct pci_dev *pdev) 1594 { 1595 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1596 int err; 1597 1598 mlx5_core_info(dev, "%s was called\n", __func__); 1599 1600 err = mlx5_load_one(dev); 1601 if (err) 1602 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", 1603 __func__, err); 1604 else 1605 mlx5_core_info(dev, "%s: device recovered\n", __func__); 1606 } 1607 1608 static const struct pci_error_handlers mlx5_err_handler = { 1609 .error_detected = mlx5_pci_err_detected, 1610 .slot_reset = mlx5_pci_slot_reset, 1611 .resume = mlx5_pci_resume 1612 }; 1613 1614 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1615 { 1616 bool fast_teardown = false, force_teardown = false; 1617 int ret = 1; 1618 1619 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1620 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1621 1622 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1623 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1624 1625 if (!fast_teardown && !force_teardown) 1626 return -EOPNOTSUPP; 1627 1628 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1629 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1630 return -EAGAIN; 1631 } 1632 1633 /* Panic tear down fw command will stop the PCI bus communication 1634 * with the HCA, so the health polll is no longer needed. 1635 */ 1636 mlx5_drain_health_wq(dev); 1637 mlx5_stop_health_poll(dev, false); 1638 1639 ret = mlx5_cmd_fast_teardown_hca(dev); 1640 if (!ret) 1641 goto succeed; 1642 1643 ret = mlx5_cmd_force_teardown_hca(dev); 1644 if (!ret) 1645 goto succeed; 1646 1647 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); 1648 mlx5_start_health_poll(dev); 1649 return ret; 1650 1651 succeed: 1652 mlx5_enter_error_state(dev, true); 1653 1654 /* Some platforms requiring freeing the IRQ's in the shutdown 1655 * flow. If they aren't freed they can't be allocated after 1656 * kexec. There is no need to cleanup the mlx5_core software 1657 * contexts. 1658 */ 1659 mlx5_core_eq_free_irqs(dev); 1660 1661 return 0; 1662 } 1663 1664 static void shutdown(struct pci_dev *pdev) 1665 { 1666 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1667 int err; 1668 1669 mlx5_core_info(dev, "Shutdown was called\n"); 1670 err = mlx5_try_fast_unload(dev); 1671 if (err) 1672 mlx5_unload_one(dev); 1673 mlx5_pci_disable_device(dev); 1674 } 1675 1676 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) 1677 { 1678 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1679 1680 mlx5_unload_one(dev); 1681 1682 return 0; 1683 } 1684 1685 static int mlx5_resume(struct pci_dev *pdev) 1686 { 1687 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1688 1689 return mlx5_load_one(dev); 1690 } 1691 1692 static const struct pci_device_id mlx5_core_pci_table[] = { 1693 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, 1694 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ 1695 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, 1696 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ 1697 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, 1698 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ 1699 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ 1700 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ 1701 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ 1702 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ 1703 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ 1704 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ 1705 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ 1706 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ 1707 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ 1708 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ 1709 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 1710 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ 1711 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 1712 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 1713 { 0, } 1714 }; 1715 1716 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 1717 1718 void mlx5_disable_device(struct mlx5_core_dev *dev) 1719 { 1720 mlx5_error_sw_reset(dev); 1721 mlx5_unload_one(dev); 1722 } 1723 1724 int mlx5_recover_device(struct mlx5_core_dev *dev) 1725 { 1726 int ret = -EIO; 1727 1728 mlx5_pci_disable_device(dev); 1729 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 1730 ret = mlx5_load_one(dev); 1731 return ret; 1732 } 1733 1734 static struct pci_driver mlx5_core_driver = { 1735 .name = KBUILD_MODNAME, 1736 .id_table = mlx5_core_pci_table, 1737 .probe = probe_one, 1738 .remove = remove_one, 1739 .suspend = mlx5_suspend, 1740 .resume = mlx5_resume, 1741 .shutdown = shutdown, 1742 .err_handler = &mlx5_err_handler, 1743 .sriov_configure = mlx5_core_sriov_configure, 1744 }; 1745 1746 static void mlx5_core_verify_params(void) 1747 { 1748 if (prof_sel >= ARRAY_SIZE(profile)) { 1749 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", 1750 prof_sel, 1751 ARRAY_SIZE(profile) - 1, 1752 MLX5_DEFAULT_PROF); 1753 prof_sel = MLX5_DEFAULT_PROF; 1754 } 1755 } 1756 1757 static int __init init(void) 1758 { 1759 int err; 1760 1761 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), 1762 "mlx5_core name not in sync with kernel module name"); 1763 1764 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); 1765 1766 mlx5_core_verify_params(); 1767 mlx5_fpga_ipsec_build_fs_cmds(); 1768 mlx5_register_debugfs(); 1769 1770 err = pci_register_driver(&mlx5_core_driver); 1771 if (err) 1772 goto err_debug; 1773 1774 err = mlx5_sf_driver_register(); 1775 if (err) 1776 goto err_sf; 1777 1778 #ifdef CONFIG_MLX5_CORE_EN 1779 err = mlx5e_init(); 1780 if (err) { 1781 pci_unregister_driver(&mlx5_core_driver); 1782 goto err_debug; 1783 } 1784 #endif 1785 1786 return 0; 1787 1788 err_sf: 1789 pci_unregister_driver(&mlx5_core_driver); 1790 err_debug: 1791 mlx5_unregister_debugfs(); 1792 return err; 1793 } 1794 1795 static void __exit cleanup(void) 1796 { 1797 #ifdef CONFIG_MLX5_CORE_EN 1798 mlx5e_cleanup(); 1799 #endif 1800 mlx5_sf_driver_unregister(); 1801 pci_unregister_driver(&mlx5_core_driver); 1802 mlx5_unregister_debugfs(); 1803 } 1804 1805 module_init(init); 1806 module_exit(cleanup); 1807