1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/mlx5/driver.h> 34 #include <linux/mlx5/cmd.h> 35 #include <linux/module.h> 36 #include "mlx5_core.h" 37 #include "../../mlxfw/mlxfw.h" 38 39 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out, 40 int outlen) 41 { 42 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0}; 43 44 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 45 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 46 } 47 48 int mlx5_query_board_id(struct mlx5_core_dev *dev) 49 { 50 u32 *out; 51 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 52 int err; 53 54 out = kzalloc(outlen, GFP_KERNEL); 55 if (!out) 56 return -ENOMEM; 57 58 err = mlx5_cmd_query_adapter(dev, out, outlen); 59 if (err) 60 goto out; 61 62 memcpy(dev->board_id, 63 MLX5_ADDR_OF(query_adapter_out, out, 64 query_adapter_struct.vsd_contd_psid), 65 MLX5_FLD_SZ_BYTES(query_adapter_out, 66 query_adapter_struct.vsd_contd_psid)); 67 68 out: 69 kfree(out); 70 return err; 71 } 72 73 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id) 74 { 75 u32 *out; 76 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 77 int err; 78 79 out = kzalloc(outlen, GFP_KERNEL); 80 if (!out) 81 return -ENOMEM; 82 83 err = mlx5_cmd_query_adapter(mdev, out, outlen); 84 if (err) 85 goto out; 86 87 *vendor_id = MLX5_GET(query_adapter_out, out, 88 query_adapter_struct.ieee_vendor_id); 89 out: 90 kfree(out); 91 return err; 92 } 93 EXPORT_SYMBOL(mlx5_core_query_vendor_id); 94 95 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev) 96 { 97 return mlx5_query_pcam_reg(dev, dev->caps.pcam, 98 MLX5_PCAM_FEATURE_ENHANCED_FEATURES, 99 MLX5_PCAM_REGS_5000_TO_507F); 100 } 101 102 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) 103 { 104 return mlx5_query_mcam_reg(dev, dev->caps.mcam, 105 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, 106 MLX5_MCAM_REGS_FIRST_128); 107 } 108 109 int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 110 { 111 int err; 112 113 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 114 if (err) 115 return err; 116 117 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 118 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS); 119 if (err) 120 return err; 121 } 122 123 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 124 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS); 125 if (err) 126 return err; 127 } 128 129 if (MLX5_CAP_GEN(dev, pg)) { 130 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 131 if (err) 132 return err; 133 } 134 135 if (MLX5_CAP_GEN(dev, atomic)) { 136 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 137 if (err) 138 return err; 139 } 140 141 if (MLX5_CAP_GEN(dev, roce)) { 142 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 143 if (err) 144 return err; 145 } 146 147 if (MLX5_CAP_GEN(dev, nic_flow_table) || 148 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 149 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE); 150 if (err) 151 return err; 152 } 153 154 if (MLX5_CAP_GEN(dev, vport_group_manager) && 155 MLX5_CAP_GEN(dev, eswitch_flow_table)) { 156 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE); 157 if (err) 158 return err; 159 } 160 161 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) { 162 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH); 163 if (err) 164 return err; 165 } 166 167 if (MLX5_CAP_GEN(dev, vector_calc)) { 168 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC); 169 if (err) 170 return err; 171 } 172 173 if (MLX5_CAP_GEN(dev, qos)) { 174 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS); 175 if (err) 176 return err; 177 } 178 179 if (MLX5_CAP_GEN(dev, pcam_reg)) 180 mlx5_get_pcam_reg(dev); 181 182 if (MLX5_CAP_GEN(dev, mcam_reg)) 183 mlx5_get_mcam_reg(dev); 184 185 return 0; 186 } 187 188 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev) 189 { 190 u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0}; 191 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0}; 192 193 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); 194 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 195 } 196 197 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev) 198 { 199 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 200 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 201 202 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 203 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 204 } 205 206 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev) 207 { 208 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 209 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 210 int force_state; 211 int ret; 212 213 if (!MLX5_CAP_GEN(dev, force_teardown)) { 214 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 215 return -EOPNOTSUPP; 216 } 217 218 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 219 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE); 220 221 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out)); 222 if (ret) 223 return ret; 224 225 force_state = MLX5_GET(teardown_hca_out, out, force_state); 226 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 227 mlx5_core_err(dev, "teardown with force mode failed\n"); 228 return -EIO; 229 } 230 231 return 0; 232 } 233 234 enum mlxsw_reg_mcc_instruction { 235 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 236 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 237 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 238 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 239 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 240 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08, 241 }; 242 243 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev, 244 enum mlxsw_reg_mcc_instruction instr, 245 u16 component_index, u32 update_handle, 246 u32 component_size) 247 { 248 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 249 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 250 251 memset(in, 0, sizeof(in)); 252 253 MLX5_SET(mcc_reg, in, instruction, instr); 254 MLX5_SET(mcc_reg, in, component_index, component_index); 255 MLX5_SET(mcc_reg, in, update_handle, update_handle); 256 MLX5_SET(mcc_reg, in, component_size, component_size); 257 258 return mlx5_core_access_reg(dev, in, sizeof(in), out, 259 sizeof(out), MLX5_REG_MCC, 0, 1); 260 } 261 262 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev, 263 u32 *update_handle, u8 *error_code, 264 u8 *control_state) 265 { 266 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 267 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 268 int err; 269 270 memset(in, 0, sizeof(in)); 271 memset(out, 0, sizeof(out)); 272 MLX5_SET(mcc_reg, in, update_handle, *update_handle); 273 274 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 275 sizeof(out), MLX5_REG_MCC, 0, 0); 276 if (err) 277 goto out; 278 279 *update_handle = MLX5_GET(mcc_reg, out, update_handle); 280 *error_code = MLX5_GET(mcc_reg, out, error_code); 281 *control_state = MLX5_GET(mcc_reg, out, control_state); 282 283 out: 284 return err; 285 } 286 287 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev, 288 u32 update_handle, 289 u32 offset, u16 size, 290 u8 *data) 291 { 292 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size; 293 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; 294 int i, j, dw_size = size >> 2; 295 __be32 data_element; 296 u32 *in; 297 298 in = kzalloc(in_size, GFP_KERNEL); 299 if (!in) 300 return -ENOMEM; 301 302 MLX5_SET(mcda_reg, in, update_handle, update_handle); 303 MLX5_SET(mcda_reg, in, offset, offset); 304 MLX5_SET(mcda_reg, in, size, size); 305 306 for (i = 0; i < dw_size; i++) { 307 j = i * 4; 308 data_element = htonl(*(u32 *)&data[j]); 309 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4); 310 } 311 312 err = mlx5_core_access_reg(dev, in, in_size, out, 313 sizeof(out), MLX5_REG_MCDA, 0, 1); 314 kfree(in); 315 return err; 316 } 317 318 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev, 319 u16 component_index, 320 u32 *max_component_size, 321 u8 *log_mcda_word_size, 322 u16 *mcda_max_write_size) 323 { 324 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)]; 325 int offset = MLX5_ST_SZ_DW(mcqi_reg); 326 u32 in[MLX5_ST_SZ_DW(mcqi_reg)]; 327 int err; 328 329 memset(in, 0, sizeof(in)); 330 memset(out, 0, sizeof(out)); 331 332 MLX5_SET(mcqi_reg, in, component_index, component_index); 333 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap)); 334 335 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 336 sizeof(out), MLX5_REG_MCQI, 0, 0); 337 if (err) 338 goto out; 339 340 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size); 341 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size); 342 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size); 343 344 out: 345 return err; 346 } 347 348 struct mlx5_mlxfw_dev { 349 struct mlxfw_dev mlxfw_dev; 350 struct mlx5_core_dev *mlx5_core_dev; 351 }; 352 353 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev, 354 u16 component_index, u32 *p_max_size, 355 u8 *p_align_bits, u16 *p_max_write_size) 356 { 357 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 358 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 359 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 360 361 return mlx5_reg_mcqi_query(dev, component_index, p_max_size, 362 p_align_bits, p_max_write_size); 363 } 364 365 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 366 { 367 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 368 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 369 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 370 u8 control_state, error_code; 371 int err; 372 373 *fwhandle = 0; 374 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state); 375 if (err) 376 return err; 377 378 if (control_state != MLXFW_FSM_STATE_IDLE) 379 return -EBUSY; 380 381 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 382 0, *fwhandle, 0); 383 } 384 385 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 386 u16 component_index, u32 component_size) 387 { 388 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 389 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 390 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 391 392 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 393 component_index, fwhandle, component_size); 394 } 395 396 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 397 u8 *data, u16 size, u32 offset) 398 { 399 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 400 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 401 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 402 403 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data); 404 } 405 406 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 407 u16 component_index) 408 { 409 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 410 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 411 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 412 413 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 414 component_index, fwhandle, 0); 415 } 416 417 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 418 { 419 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 420 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 421 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 422 423 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0, 424 fwhandle, 0); 425 } 426 427 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 428 enum mlxfw_fsm_state *fsm_state, 429 enum mlxfw_fsm_state_err *fsm_state_err) 430 { 431 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 432 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 433 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 434 u8 control_state, error_code; 435 int err; 436 437 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state); 438 if (err) 439 return err; 440 441 *fsm_state = control_state; 442 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 443 MLXFW_FSM_STATE_ERR_MAX); 444 return 0; 445 } 446 447 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 448 { 449 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 450 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 451 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 452 453 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 454 } 455 456 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 457 { 458 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 459 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 460 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 461 462 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 463 fwhandle, 0); 464 } 465 466 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = { 467 .component_query = mlx5_component_query, 468 .fsm_lock = mlx5_fsm_lock, 469 .fsm_component_update = mlx5_fsm_component_update, 470 .fsm_block_download = mlx5_fsm_block_download, 471 .fsm_component_verify = mlx5_fsm_component_verify, 472 .fsm_activate = mlx5_fsm_activate, 473 .fsm_query_state = mlx5_fsm_query_state, 474 .fsm_cancel = mlx5_fsm_cancel, 475 .fsm_release = mlx5_fsm_release 476 }; 477 478 int mlx5_firmware_flash(struct mlx5_core_dev *dev, 479 const struct firmware *firmware) 480 { 481 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = { 482 .mlxfw_dev = { 483 .ops = &mlx5_mlxfw_dev_ops, 484 .psid = dev->board_id, 485 .psid_size = strlen(dev->board_id), 486 }, 487 .mlx5_core_dev = dev 488 }; 489 490 if (!MLX5_CAP_GEN(dev, mcam_reg) || 491 !MLX5_CAP_MCAM_REG(dev, mcqi) || 492 !MLX5_CAP_MCAM_REG(dev, mcc) || 493 !MLX5_CAP_MCAM_REG(dev, mcda)) { 494 pr_info("%s flashing isn't supported by the running FW\n", __func__); 495 return -EOPNOTSUPP; 496 } 497 498 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware); 499 } 500